[tlul,rtl] Explicitly zero some integrity bits from tlul_adapter_reg

The existing behaviour of the tlul_rsp_intg_gen was to add rsp/data
integrity bits if their generation was enabled and pass through the
input integrity bits if not.

In some instantiations (in tlul_adapter_reg and tlul_adapter_dmi),
these bits are actually always zero. One consequence is missing
coverage in DV simulations. The problem is that e.g. the rsp_intg
signal is driven with a continuous assignment:

    assign rsp_intg = tl_i.d_user.rsp_intg;

But the right hand side is zero, so constant and the assignment is not
marked as covered.

This commit adds a UserInIsZero parameter. If this is true then we
know the input d_user signal is zero and thus can wire the variable
directly to zero.

This removes the cover point but will not change RTL behaviour at all.

Signed-off-by: Rupert Swarbrick <[email protected]>

hw/ip/tlul/rtl/tlul_adapter_dmi.sv

@@ -115,7 +115,8 @@ module tlul_adapter_dmi
   // outgoing integrity generation
   tlul_rsp_intg_gen #(
     .EnableRspIntgGen(EnableRspIntgGen),
-    .EnableDataIntgGen(EnableDataIntgGen)
+    .EnableDataIntgGen(EnableDataIntgGen),
+    .UserInIsZero(1'b1)
   ) u_rsp_intg_gen (
     .tl_i(tl_d2h_o_pre),
     .tl_o(tl_d2h_o)

hw/ip/tlul/rtl/tlul_adapter_reg.sv

@@ -166,7 +166,8 @@ module tlul_adapter_reg
   // outgoing integrity generation
   tlul_rsp_intg_gen #(
     .EnableRspIntgGen(EnableRspIntgGen),
-    .EnableDataIntgGen(EnableDataIntgGen)
+    .EnableDataIntgGen(EnableDataIntgGen),
+    .UserInIsZero(1'b1)
   ) u_rsp_intg_gen (
     .tl_i(tl_o_pre),
     .tl_o(tl_o)

hw/ip/tlul/rtl/tlul_rsp_intg_gen.sv

@@ -4,13 +4,27 @@
 
 `include "prim_assert.sv"
 
-/**
- * Tile-Link UL response integrity generator
- */
+/*
+
+ Tile-Link UL response integrity generator
+
+ This generates integrity bits that get stored in the rsp_intg and data_intg fields of tl_o.d_user.
+
+ If EnableRspIntgGen is true then the rsp_intg field is generated from the opcode, d_size and
+ d_error fields of the response (extracted with tlul_pkg::extract_d2h_rsp_intg). If it is false then
+ the rsp_intg field either comes from the same field in the tl_i input (if UserInIsZero is false) or
+ is wired to zero (if UserInIsZero is true).
+
+ If EnableDataIntgGen is true then the data_intg field is generated from the d_data field of the
+ response. If it is false then the rsp_intg field either comes from the same field in the tl_i input
+ (if UserInIsZero is false) or is wired to zero (if UserInIsZero is true).
+
+*/
 
 module tlul_rsp_intg_gen import tlul_pkg::*; #(
   parameter bit EnableRspIntgGen = 1'b1,
-  parameter bit EnableDataIntgGen = 1'b1
+  parameter bit EnableDataIntgGen = 1'b1,
+  parameter bit UserInIsZero = 1'b0
 ) (
   // TL-UL interface
   input  tl_d2h_t tl_i,
@@ -28,6 +42,8 @@ module tlul_rsp_intg_gen import tlul_pkg::*; #(
       .data_i(D2HRspMaxWidth'(rsp)),
       .data_o({rsp_intg, unused_payload})
     );
+  end else if (UserInIsZero) begin : gen_zero_rsp_intg
+    assign rsp_intg = 0;
   end else begin : gen_passthrough_rsp_intg
     assign rsp_intg = tl_i.d_user.rsp_intg;
   end
@@ -39,6 +55,8 @@ module tlul_rsp_intg_gen import tlul_pkg::*; #(
       .data_i(DataMaxWidth'(tl_i.d_data)),
       .data_intg_o({data_intg, unused_data})
     );
+  end else if (UserInIsZero) begin : gen_zero_data_intg
+    assign data_intg = 0;
   end else begin : gen_passthrough_data_intg
     assign data_intg = tl_i.d_user.data_intg;
   end