From 6e7d267b5cef0750e2ff133645da4e829bf23ea1 Mon Sep 17 00:00:00 2001 From: Alexander Williams Date: Sat, 4 Jan 2025 05:23:22 +0000 Subject: [PATCH] [top] Adjust VLNVs for top-level lint and sim targets Uniquify the VLNVs for top-level lint and sim targets. Use the direct VLNVs for dependencies to top-specific cores. Add a special core for earlgrey's AST to bring in the direct VLNVs required to guarantee simulation against earlgrey parameters. Adjust lint and simulation configs to map to these adjusted VLNVs. Co-authored-by: Andreas Kurth Signed-off-by: Alexander Williams --- .../lint/top_darjeeling_dv_lint_cfgs.hjson | 2 +- .../lint/top_darjeeling_lint_cfgs.hjson | 4 +-- hw/top_earlgrey/dv/chip_sim.core | 13 ++++--- hw/top_earlgrey/dv/chip_sim_cfg.hjson | 2 +- hw/top_earlgrey/dv/env/chip_env.core | 9 +++-- hw/top_earlgrey/dv/tests/chip_test.core | 5 ++- hw/top_earlgrey/dv/verilator/chip_sim.core | 5 ++- .../formal/top_earlgrey_fpv_ip_cfgs.hjson | 2 +- .../ip/ast/top_earlgrey_ast_top.core | 34 +++++++++++++++++++ .../lint/top_earlgrey_dv_lint_cfgs.hjson | 10 +++--- .../lint/top_earlgrey_fpv_lint_cfgs.hjson | 2 +- .../lint/top_earlgrey_lint_cfgs.hjson | 6 ++-- 12 files changed, 70 insertions(+), 24 deletions(-) create mode 100644 hw/top_earlgrey/ip/ast/top_earlgrey_ast_top.core diff --git a/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson b/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson index c458a21a1a6799..cb2b6f6fb67630 100644 --- a/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson +++ b/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson @@ -206,7 +206,7 @@ // rel_path: "hw/top_darjeeling/ip/xbar_mbx/dv/lint/{tool}" // }, // { name: chip - // fusesoc_core: lowrisc:dv:chip_sim + // fusesoc_core: lowrisc:dv:top_darjeeling_chip_sim // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] // rel_path: "hw/top_darjeeling/dv/lint/{tool}" // overrides: [ diff --git a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson index 4c21ae64a661fa..ab9df523c9f629 100644 --- a/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson +++ b/hw/top_darjeeling/lint/top_darjeeling_lint_cfgs.hjson @@ -53,7 +53,7 @@ rel_path: "hw/ip/aon_timer/lint/{tool}" }, { name: ast - fusesoc_core: lowrisc:systems:ast + fusesoc_core: lowrisc:systems:top_darjeeling_ast import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_darjeeling/ip/ast/lint/{tool}" overrides: [ @@ -293,7 +293,7 @@ rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}" }, { name: sensor_ctrl - fusesoc_core: lowrisc:systems:sensor_ctrl + fusesoc_core: lowrisc:systems:top_darjeeling_sensor_ctrl import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_darjeeling/ip/sensor_ctrl/lint/{tool}" }, diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core index 5fbc9320503c73..56cd717c045131 100644 --- a/hw/top_earlgrey/dv/chip_sim.core +++ b/hw/top_earlgrey/dv/chip_sim.core @@ -2,8 +2,11 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:chip_sim:0.1" +name: "lowrisc:dv:top_earlgrey_chip_sim:0.1" description: "Earlgrey chip DV sim target" +virtual: + - lowrisc:dv:chip_sim + filesets: files_rtl: depend: @@ -19,10 +22,10 @@ filesets: - lowrisc:opentitan:top_earlgrey_alert_handler_reg - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:ip:tlul - - lowrisc:dv:chip_test - - lowrisc:dv:clkmgr_sva - - lowrisc:dv:pwrmgr_sva - - lowrisc:dv:rstmgr_sva + - lowrisc:dv:top_earlgrey_chip_test + - lowrisc:opentitan:top_earlgrey_clkmgr_sva + - lowrisc:opentitan:top_earlgrey_pwrmgr_sva + - lowrisc:opentitan:top_earlgrey_rstmgr_sva - lowrisc:dv:top_earlgrey_sva - lowrisc:dv:top_earlgrey_xbar_main_bind - lowrisc:dv:top_earlgrey_xbar_peri_bind diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson index 9f53798d59cefb..ecee7eaa3a8b4a 100644 --- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson +++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson @@ -15,7 +15,7 @@ tool: vcs // Fusesoc core file used for building the file list. - fusesoc_core: lowrisc:dv:chip_sim:0.1 + fusesoc_core: lowrisc:dv:top_earlgrey_chip_sim:0.1 // Testplan hjson file, excluding the connectivity tests. testplan: "{proj_root}/hw/top_earlgrey/data/chip_testplan.hjson:-conn:-no_dv" diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core index 2700ff84fb9d84..d67e749c998b5b 100644 --- a/hw/top_earlgrey/dv/env/chip_env.core +++ b/hw/top_earlgrey/dv/env/chip_env.core @@ -2,8 +2,11 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:chip_env:0.1" +name: "lowrisc:dv:top_earlgrey_chip_env:0.1" description: "CHIP DV UVM environmnt" +virtual: + - lowrisc:dv:chip_env + filesets: files_dv: depend: @@ -34,8 +37,8 @@ filesets: - lowrisc:ip:otp_ctrl_pkg - lowrisc:ip_interfaces:pwrmgr_pkg - lowrisc:dv:lc_ctrl_dv_utils - - "!fileset_partner ? (lowrisc:systems:ast_pkg)" - - "fileset_partner ? (partner:systems:ast_pkg)" + - "!fileset_partner ? (lowrisc:systems:top_earlgrey_ast_pkg)" + - "fileset_partner ? (partner:systems:top_earlgrey_ast_pkg)" files: - chip_common_pkg.sv - chip_if.sv diff --git a/hw/top_earlgrey/dv/tests/chip_test.core b/hw/top_earlgrey/dv/tests/chip_test.core index c0196dbe8b2081..2c04dd6e6e6f40 100644 --- a/hw/top_earlgrey/dv/tests/chip_test.core +++ b/hw/top_earlgrey/dv/tests/chip_test.core @@ -2,8 +2,11 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:chip_test:0.1" +name: "lowrisc:dv:top_earlgrey_chip_test:0.1" description: "CHIP DV UVM test" +virtual: + - lowrisc:dv:chip_test + filesets: files_dv: depend: diff --git a/hw/top_earlgrey/dv/verilator/chip_sim.core b/hw/top_earlgrey/dv/verilator/chip_sim.core index a5b58502a030fc..e43ee8cc33044b 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim.core +++ b/hw/top_earlgrey/dv/verilator/chip_sim.core @@ -2,8 +2,11 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:dv:chip_verilator_sim:0.1" +name: "lowrisc:dv:top_earlgrey_chip_verilator_sim:0.1" description: "Earl Grey toplevel for simulation with Verilator" +virtual: + - lowrisc:dv:chip_verilator_sim + filesets: files_sim_verilator: depend: diff --git a/hw/top_earlgrey/formal/top_earlgrey_fpv_ip_cfgs.hjson b/hw/top_earlgrey/formal/top_earlgrey_fpv_ip_cfgs.hjson index 9068702fbf6e71..5492553ad39abe 100644 --- a/hw/top_earlgrey/formal/top_earlgrey_fpv_ip_cfgs.hjson +++ b/hw/top_earlgrey/formal/top_earlgrey_fpv_ip_cfgs.hjson @@ -23,7 +23,7 @@ { name: pinmux_fpv dut: pinmux_tb - fusesoc_core: lowrisc:fpv:pinmux_fpv + fusesoc_core: lowrisc:opentitan:top_earlgrey_pinmux_fpv import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/pinmux/{sub_flow}/{tool}" defines: "FPV_ALERT_NO_SIGINT_ERR" diff --git a/hw/top_earlgrey/ip/ast/top_earlgrey_ast_top.core b/hw/top_earlgrey/ip/ast/top_earlgrey_ast_top.core new file mode 100644 index 00000000000000..f7c80f8fbfbd2a --- /dev/null +++ b/hw/top_earlgrey/ip/ast/top_earlgrey_ast_top.core @@ -0,0 +1,34 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:top_earlgrey_ast_top:0.1" +description: "Pseudo top-level for Earl Grey's ast" +filesets: + files_rtl: + depend: + - lowrisc:opentitan:top_earlgrey_alert_handler_pkg + - lowrisc:opentitan:top_earlgrey_clkmgr_pkg + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg + - lowrisc:opentitan:top_earlgrey_rstmgr_pkg + - lowrisc:opentitan:top_earlgrey_pinmux_pkg + - lowrisc:systems:top_earlgrey_ast + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + lint: + toplevel: ast + filesets: + - files_rtl + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson index d249a511c6a1eb..c18ef11f80c21c 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson @@ -34,7 +34,7 @@ rel_path: "hw/top_earlgrey/ip/aon_timer/dv/lint/{tool}" }, { name: clkmgr - fusesoc_core: lowrisc:dv:clkmgr_sim + fusesoc_core: lowrisc:opentitan:top_earlgrey_clkmgr_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/clkmgr/dv/lint/{tool}" }, @@ -59,7 +59,7 @@ rel_path: "hw/ip/edn/dv/lint/{tool}" }, { name: flash_ctrl - fusesoc_core: lowrisc:dv:flash_ctrl_sim + fusesoc_core: lowrisc:opentitan:top_earlgrey_flash_ctrl_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/dv/lint/{tool}" }, @@ -131,7 +131,7 @@ rel_path: "hw/ip/prim/dv/prim_prince/lint/{tool}" }, { name: pwrmgr - fusesoc_core: lowrisc:dv:pwrmgr_sim + fusesoc_core: lowrisc:opentitan:top_earlgrey_pwrmgr_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/pwrmgr/dv/lint/{tool}" }, @@ -141,7 +141,7 @@ rel_path: "hw/ip/rom_ctrl/dv/lint/{tool}" }, { name: rstmgr - fusesoc_core: lowrisc:dv:rstmgr_sim + fusesoc_core: lowrisc:opentitan:top_earlgrey_rstmgr_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/rstmgr/dv/lint/{tool}" }, @@ -196,7 +196,7 @@ rel_path: "hw/top_earlgrey/ip/xbar_peri/dv/lint/{tool}" }, { name: chip - fusesoc_core: lowrisc:dv:chip_sim + fusesoc_core: lowrisc:dv:top_earlgrey_chip_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/dv/lint/{tool}" overrides: [ diff --git a/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson index 7eb897f22ee100..b37e3b91d7e852 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_fpv_lint_cfgs.hjson @@ -133,7 +133,7 @@ } { name: pinmux_fpv - fusesoc_core: lowrisc:fpv:pinmux_fpv + fusesoc_core: lowrisc:opentitan:top_earlgrey_pinmux_fpv import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/pinmux/fpv/lint/{tool}" } diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index dc74dba688f697..756393f4b0f1d0 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -48,7 +48,7 @@ rel_path: "hw/ip/ascon/lint/{tool}" }, { name: ast - fusesoc_core: lowrisc:systems:ast + fusesoc_core: lowrisc:dv:top_earlgrey_ast_top import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip/ast/lint/{tool}" overrides: [ @@ -158,7 +158,7 @@ ] }, { name: pinmux - fusesoc_core: lowrisc:ip_interfaces:pinmux + fusesoc_core: lowrisc:opentitan:top_earlgrey_pinmux import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip_autogen/pinmux/lint/{tool}" overrides: [ @@ -283,7 +283,7 @@ rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}" }, { name: sensor_ctrl - fusesoc_core: lowrisc:systems:sensor_ctrl + fusesoc_core: lowrisc:systems:top_earlgrey_sensor_ctrl import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/top_earlgrey/ip/sensor_ctrl/lint/{tool}" },