diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core b/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core index 8e8dc085bd528..c74c91756816e 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core @@ -12,6 +12,8 @@ filesets: - lowrisc:prim:mubi - lowrisc:prim:all - lowrisc:systems:top_racl_pkg + - lowrisc:prim:edge_detector + - lowrisc:prim:onehot files: - rtl/ac_range_check_reg_pkg.sv - rtl/ac_range_check_reg_top.sv diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson b/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson deleted file mode 100644 index d3b8ffd87ff59..0000000000000 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson +++ /dev/null @@ -1,86 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -{ - name: "dma" - import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", - "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", - "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", - "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"] - testpoints: [ - { - name: ac_range_check_smoke - desc: ''' - Smoke test in which we configure a randomized number of ranges to allow a transfer - and perform transfers. - - Stimulus: - - Assert range_check_overwrite_i to MuBi8::False - - Configure a random number of ranges: - * Randomize the RANGE_BASE and RANGE_LIMIT register (RANGE_LIMIT > RANGE_BASE) - * Randomize the RANGE_PERM register and set the RANGE_PERM.enable bit to 1 - * Set RANGE_RACL_POLICY_SHADOWED.read_perm and - RANGE_RACL_POLICY_SHADOWED.write_perm to 0xFFFF (disables RACL checks) - - Perform random TLUL requests where at least 1 RACL role bit is set in the TLUL - user bit vector. - - Checking: - - If a request falls outside of any configured range, the request is denied and TLUL - error is returned. Read requests return all zero as data. - - If the request falls in any of the configured range, and the TLUL request matches - the (R/W/X) permissions of the configured range, the request should be allowed. - * Write transfer goes through - * Read and Execute request return the expected data - ''' - stage: V1 - tests: ["ac_range_check_smoke"] - } - { - name: ac_range_lock_range - desc: ''' - Test the range lock functionality - - Stimulus: - - Configure a range's RANGE_BASE, RANGE_LIMIT, RANGE_PERM, RANGE_RACL_POLICY_SHADOWED - register - - Clear RANGE_REGWEN to MuBi4::False in a randomized way - - Try to reconfigure the range with different values - - Checking: - - If RANGE_REGWEN was cleared to MuBi4::False, the reconfigured register values - The original configuration should remain in the registers. If RANGE_REGWEN was not - cleared, the reconfigured values should have replaced the original ones. - ''' - stage: V2 - tests: ["ac_range_lock_range"] - } - { - name: ac_range_bypass_enable - desc: ''' - Test the bypass functionality for enabled ranges. - - Stimulus: - - Assert range_check_overwrite_i to Mubi8::True - - Configure the AC range check to block certain address ranges - * Randomize type of denial (R/W/X, RACL policies) - - Perform random TLUL requests that fall within blocked ranges and outside with: - * Random request type (R/W/X) and random RACL role - - Checking: - - Check if all transfers are allowed - - LOG_STATUS.deny_cnt must stay 0 - ''' - stage: V2 - tests: ["ac_range_check_bypass"] - } - ] - covergroups: [ - { - name: ac_range_check_log_status_cg - desc: ''' - Cover all status fields of the LOG_STATUS. - (deny_cnt and deny_range_index are not part of this). - ''' - } - ] - } diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/doc/checklist.md b/hw/top_darjeeling/ip_autogen/ac_range_check/doc/checklist.md new file mode 100644 index 0000000000000..f663bc000f973 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/doc/checklist.md @@ -0,0 +1,275 @@ +--- +title: "AC_RANGE_CHECK Checklist" +--- + + +This checklist is for [Hardware Stage](/doc/project_governance/development_stages.md) transitions for the [AC_RANGE_CHECK peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](/doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Not Started | [AC_RANGE_CHECK Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Not Started | +RTL | [CLKRST_CONNECTED][] | Not Started | +RTL | [IP_TOP][] | Not Started | +RTL | [IP_INSTANTIABLE][] | Not Started | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started | +RTL | [FUNC_IMPLEMENTED][] | Not Started | +RTL | [ASSERT_KNOWN_ADDED][] | Not Started | +Code Quality | [LINT_SETUP][] | Not Started | +Security | [SEC_CM_SCOPED][] | Not Started | + +[SPEC_COMPLETE]: /doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: /doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: /doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: /doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: /doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: /doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: /doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: /doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: /doc/project_governance/checklist/README.md#lint_setup +[SEC_CM_SCOPED]: /doc/project_governance/checklist/README.md#sec_cm_scoped + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [BLOCK_DIAGRAM][] | Not Started | +Documentation | [DOC_INTERFACE][] | Not Started | +Documentation | [DOC_INTEGRATION_GUIDE][] | Not Started | +Documentation | [MISSING_FUNC][] | Not Started | +Documentation | [FEATURE_FROZEN][] | Not Started | +RTL | [FEATURE_COMPLETE][] | Not Started | +RTL | [PORT_FROZEN][] | Not Started | +RTL | [ARCHITECTURE_FROZEN][] | Not Started | +RTL | [REVIEW_TODO][] | Not Started | +RTL | [STYLE_X][] | Not Started | +RTL | [CDC_SYNCMACRO][] | Not Started | +Code Quality | [LINT_PASS][] | Not Started | +Code Quality | [CDC_SETUP][] | Not Started | +Code Quality | [RDC_SETUP][] | Not Started | +Code Quality | [AREA_CHECK][] | Not Started | +Code Quality | [TIMING_CHECK][] | Not Started | +Security | [SEC_CM_DOCUMENTED][] | Not Started | + +[NEW_FEATURES]: /doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: /doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: /doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: /doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: /doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: /doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: /doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: /doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: /doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: /doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: /doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: /doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: /doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: /doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: /doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: /doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: /doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: /doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Not Started | +Security | [SEC_CM_IMPLEMENTED][] | Not Started | +Security | [SEC_CM_RND_CNST][] | Not Started | +Security | [SEC_CM_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_CM_SHADOW_REGS][] | Not Started | +Security | [SEC_CM_RTL_REVIEWED][] | Not Started | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started | + +[SEC_CM_ASSETS_LISTED]: /doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: /doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: /doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: /doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: /doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[NEW_FEATURES_D3]: /doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: /doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: /doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: /doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: /doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: /doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: /doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: /doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: /doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [AC_RANGE_CHECK DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Not Started | [AC_RANGE_CHECK Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Not Started | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | +Testbench | [SIM_TB_ENV_CREATED][] | Not Started | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | +Testbench | [TB_GEN_AUTOMATED][] | Not Started | +Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Code Quality | [TB_LINT_SETUP][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?) +Review | [V2_CHECKLIST_SCOPED][] | Not Started | + +[DV_DOC_DRAFT_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: /doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: /doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: /doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: /doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: /doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: /doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: /doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: /doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: /doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: /doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | +Documentation | [DV_DOC_COMPLETED][] | Not Started | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started | +Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | +Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | +Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | +Tests | [SIM_FW_SIMULATED][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | +Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | +Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Not Started | + +[DESIGN_DELTAS_CAPTURED_V2]: /doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: /doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: /doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: /doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: /doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: /doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: /doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: /doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: /doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:/doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started | +Tests | [FPV_SEC_CM_VERIFIED][] | Not Started | +Tests | [SIM_SEC_CM_VERIFIED][] | Not Started | +Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started | +Review | [SEC_CM_DV_REVIEWED][] | Not Started | + +[SEC_CM_TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: /doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: /doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: /doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: /doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: /doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:/doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: /doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: /doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: /doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/README.md b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/README.md new file mode 100644 index 0000000000000..3f18cdfe262c4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/README.md @@ -0,0 +1,129 @@ +# AC_RANGE_CHECK DV document + +## Goals +* **DV** + * Verify all AC_RANGE_CHECK IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/ac_range_check/dv/latest/report.html) + +## Design features +For detailed information on `ac_range_check` design features, please see the [`ac_range_check` HWIP technical specification](../README.md). + +## Testbench architecture +The `ac_range_check` UVM DV testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv`. +It instantiates the `ac_range_check` DUT module `hw/ip/ac_range_check/rtl/ac_range_check.sv`. +In addition, the testbench instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [Reset shadowed interface](../../../../dv/sv/common_ifs/README.md) // TODO add something in this doc about this interface. +* [TileLink host interface for the CSRs](../../../../dv/sv/tl_agent/README.md) +* [TileLink host interface for the Unfiltered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* [TileLink device interface for the Filtered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Compile-time configurations +[list compile time configurations, if any and what are they used for] + +### Global types & methods +All common types and methods defined at the package level can be found in `ac_range_check_env_pkg`. +Some of them in use are: +```systemverilog +[list a few parameters, types & methods; no need to mention all] +``` + +### TL_agent +* `ac_range_check` UVM environment instantiates a (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into `ac_range_check` device, to access to the CSRs (Control/Status Registers). +* Host interface to the Unfiltered CTN accesses. +* Device interface to the Filtered CTN accesses. + +The `tl_agent` monitor supplies partial TileLink request packets as well as completed TileLink response packets over the TLM analysis port for further processing within the `ac_range_check` scoreboard. + +### Alert_agent +`ac_range_check` testbench instantiates (already handled in CIP base env) [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +[list alert names]. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in AC_RANGE_CHECK device. + +### UVM RAL Model +The `ac_range_check` RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +#### Sequence cfg +An efficient way to develop test sequences is by providing some random variables that are used to configure the DUT / drive stimulus. +The random variables are constrained using weights and knobs that can be controlled. +These weights and knobs take on a "default" value that will result in the widest exploration of the design state space, when the test sequence is randomized and run as-is. +To steer the randomization towards a particular distribution or to achieve interesting combinations of the random variables, the test sequence can be extended to create a specialized variant. +In this extended sequence, nothing would need to be done, other than setting those weights and knobs appropriately. +This helps increase the likelihood of hitting the design corners that would otherwise be difficult to achieve, while maximizing reuse. + +This object aims to provide such run-time controls. + +#### Env cfg +The `ac_range_check_env_cfg`, environment configuration object provides access to the following elements: +* Build-time controls to configure the UVM environment composition during the `build_phase` +* Downstream agent configuration objects for ease of lookup from any environment component + * This includes the `tl_agent_cfg` objects for both TL interfaces +* All virtual interfaces that connect to the DUT listed above (retrieved from the `uvm_config_db`) +* Sequence configuration object described above + +All environment components contain a handle to an instance of this class (that was created in the test class via the parent `dv_base_test`). +By housing all of the above, all pertinent information is more easily shared with all environment components. + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib`. +The `ac_range_check_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `ac_range_check_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: From `hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq/ac_range_check_base_vseq.sv`, +* task 1: +* task 2: + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* cg1: +* cg2: + +### Self-checking strategy +#### Scoreboard +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* analysis port1: +* analysis port2: + + +#### Assertions +* TLUL assertions: The `hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* assert prop 1: +* assert prop 2: + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ cd $REPO_TOP +$ ./util/dvsim/dvsim.py hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_smoke +``` + +## Testplan +[Testplan](../data/ac_range_check_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core new file mode 100644 index 0000000000000..d71b1bc3feb72 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_sim:0.1 +description: "AC_RANGE_CHECK DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:opentitan:top_darjeeling_ac_range_check:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:opentitan:top_darjeeling_ac_range_check_test + - lowrisc:opentitan:top_darjeeling_ac_range_check_sva + files: + - tb/tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson new file mode 100644 index 0000000000000..7ec5eee0e92f0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: ac_range_check + + // Top level dut name (sv module). + dut: ac_range_check + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: xcelium + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:opentitan:top_darjeeling_ac_range_check_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/ac_range_check_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", // TODO MVy needed? + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["ac_range_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: ac_range_check_base_test + uvm_test_seq: ac_range_check_base_vseq + + // List of test specifications. + tests: [ + { + name: ac_range_check_smoke + uvm_test_seq: ac_range_check_smoke_vseq + } + + // TODO: add more tests here + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["ac_range_check_smoke"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core new file mode 100644 index 0000000000000..b4c7a2580e21f --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core @@ -0,0 +1,39 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_env:0.1 +description: "AC_RANGE_CHECK DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:dv_base_reg + - lowrisc:dv:dv_lib + files: + - ac_range_check_env_pkg.sv + - ac_range_check_env_cfg.sv: {is_include_file: true} + - ac_range_check_env_cov.sv: {is_include_file: true} + - ac_range_check_virtual_sequencer.sv: {is_include_file: true} + - ac_range_check_scoreboard.sv: {is_include_file: true} + - ac_range_check_env.sv: {is_include_file: true} + - seq_lib/ac_range_check_vseq_list.sv: {is_include_file: true} + - seq_lib/ac_range_check_base_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_common_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_smoke_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: ac_range_check + ip_hjson: ../../data/ac_range_check.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv new file mode 100644 index 0000000000000..ab3fc70d125d2 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env extends cip_base_env #( + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T(ac_range_check_virtual_sequencer), + .SCOREBOARD_T (ac_range_check_scoreboard) + ); + `uvm_component_utils(ac_range_check_env) + + tl_agent tl_csr_agt; + tl_agent tl_unfilt_agt; + tl_agent tl_filt_agt; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); +endclass : ac_range_check_env + + +function ac_range_check_env::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_env::build_phase(uvm_phase phase); + super.build_phase(phase); + + // Create CSR TL agent + tl_csr_agt = tl_agent::type_id::create("tl_csr_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_csr_agt*", "cfg", cfg.tl_csr_agt_cfg); + cfg.tl_csr_agt_cfg.en_cov = cfg.en_cov; + + // Create Unfiltered TL agent + tl_unfilt_agt = tl_agent::type_id::create("tl_unfilt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agt*", "cfg", cfg.tl_unfilt_agt_cfg); + cfg.tl_unfilt_agt_cfg.en_cov = cfg.en_cov; + + // Create Fltered TL agent + tl_filt_agt = tl_agent::type_id::create("tl_filt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_filt_agt*", "cfg", cfg.tl_filt_agt_cfg); + cfg.tl_filt_agt_cfg.en_cov = cfg.en_cov; +endfunction : build_phase + +function void ac_range_check_env::connect_phase(uvm_phase phase); + super.connect_phase(phase); + if (cfg.en_scb) begin + tl_csr_agt.monitor.analysis_port.connect(scoreboard.tl_csr_fifo.analysis_export); + tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export); + tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export); + end + if (cfg.is_active && cfg.tl_csr_agt_cfg.is_active) begin + virtual_sequencer.tl_csr_sqr = tl_csr_agt.sequencer; + end + if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin + virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer; + end + if (cfg.is_active && cfg.tl_filt_agt_cfg.is_active) begin + virtual_sequencer.tl_filt_sqr = tl_filt_agt.sequencer; + end +endfunction : connect_phase diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv new file mode 100644 index 0000000000000..b4e1f6a6872bb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv @@ -0,0 +1,47 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block)); + + // External component config objects + rand tl_agent_cfg tl_csr_agt_cfg; + rand tl_agent_cfg tl_unfilt_agt_cfg; + rand tl_agent_cfg tl_filt_agt_cfg; + + `uvm_object_utils_begin(ac_range_check_env_cfg) + `uvm_field_object(tl_csr_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT) + `uvm_object_utils_end + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern function void initialize(bit [31:0] csr_base_addr = '1); +endclass : ac_range_check_env_cfg + + +function ac_range_check_env_cfg::new(string name=""); + super.new(name); +endfunction : new + +function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + // Create tl_csr agent config obj + tl_csr_agt_cfg = tl_agent_cfg::type_id::create("tl_csr_agt_cfg"); + // Create tl_unfilt agent config obj + tl_unfilt_agt_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agt_cfg"); + // Create tl_filt agent config obj + tl_filt_agt_cfg = tl_agent_cfg::type_id::create("tl_filt_agt_cfg"); + + // Set num_interrupts + begin + uvm_reg rg = ral.get_reg_by_name("intr_state"); + if (rg != null) begin + num_interrupts = ral.intr_state.get_n_used_bits(); + end + end +endfunction : initialize diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv new file mode 100644 index 0000000000000..c5068f7a7da75 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class ac_range_check_env_cov extends cip_base_env_cov #(.CFG_T(ac_range_check_env_cfg)); + `uvm_component_utils(ac_range_check_env_cov) + + // The base class provides the following handles for use: + // ac_range_check_env_cfg: cfg + + // Covergroups + // TODO MVy [add covergroups here] + + // Standard SV/UVM methods + extern function new(string name, uvm_component parent); + extern function void build_phase(uvm_phase phase); +endclass : ac_range_check_env_cov + + +function ac_range_check_env_cov::new(string name, uvm_component parent); + super.new(name, parent); + // TODO MVy [instantiate covergroups here] +endfunction : new + +function void ac_range_check_env_cov::build_phase(uvm_phase phase); + super.build_phase(phase); + // TODO MVy [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details +endfunction : build_phase diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv new file mode 100644 index 0000000000000..3a8c0bbd88d0a --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv @@ -0,0 +1,39 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_env_pkg; + // Dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import tl_agent_pkg::*; + import dv_lib_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import ac_range_check_ral_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Parameters + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[] = {"recov_ctrl_update_err", "fatal_fault"}; + + // Types + typedef enum int { + DenyCntReached = 0 + } ac_range_check_intr_e; + + // Functions + + // Package sources + `include "ac_range_check_env_cfg.sv" + `include "ac_range_check_env_cov.sv" + `include "ac_range_check_virtual_sequencer.sv" + `include "ac_range_check_scoreboard.sv" + `include "ac_range_check_env.sv" + `include "ac_range_check_vseq_list.sv" +endpackage : ac_range_check_env_pkg diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv new file mode 100644 index 0000000000000..b2bd178e1a487 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv @@ -0,0 +1,171 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_scoreboard extends cip_base_scoreboard #( + .CFG_T(ac_range_check_env_cfg), + .RAL_T(ac_range_check_reg_block), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_scoreboard) + + // Local variables + + // TLM agent fifos + uvm_tlm_analysis_fifo #(tl_seq_item) tl_csr_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo; + + // Local queues to hold incoming packets pending comparison + tl_seq_item tl_csr_q[$]; + tl_seq_item tl_unfilt_q[$]; + tl_seq_item tl_filt_q[$]; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern function void check_phase(uvm_phase phase); + + // Class specific methods + extern task process_tl_csr_fifo(); + extern task process_tl_unfilt_fifo(); + extern task process_tl_filt_fifo(); + extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + extern function void reset(string kind = "HARD"); +endclass : ac_range_check_scoreboard + + +function ac_range_check_scoreboard::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_scoreboard::build_phase(uvm_phase phase); + super.build_phase(phase); + tl_csr_fifo = new("tl_csr_fifo", this); + tl_unfilt_fifo = new("tl_unfilt_fifo", this); + tl_filt_fifo = new("tl_filt_fifo", this); + // TODO: remove once support alert checking + do_alert_check = 0; +endfunction : build_phase + +function void ac_range_check_scoreboard::connect_phase(uvm_phase phase); + super.connect_phase(phase); +endfunction : connect_phase + +task ac_range_check_scoreboard::run_phase(uvm_phase phase); + super.run_phase(phase); + wait(cfg.under_reset); + forever begin + wait(!cfg.under_reset); + // This isolation fork is needed to ensure that "disable fork" call won't kill any other + // processes at the same level from the parent classes + fork begin : isolation_fork + fork + begin : main_thread + fork + process_tl_csr_fifo(); + process_tl_unfilt_fifo(); + process_tl_filt_fifo(); + join + wait fork; // To ensure it will be killed only when the reset will occur + end + begin : reset_thread + wait(cfg.under_reset); + end + join_any + disable fork; // Terminates all descendants and sub-descendants of isolation_fork + end join + end +endtask : run_phase + +task ac_range_check_scoreboard::process_tl_csr_fifo(); + tl_seq_item item; + forever begin + tl_csr_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_csr item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_csr_fifo + +task ac_range_check_scoreboard::process_tl_unfilt_fifo(); + tl_seq_item item; + forever begin + tl_unfilt_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_unfilt item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_unfilt_fifo + +task ac_range_check_scoreboard::process_tl_filt_fifo(); + tl_seq_item item; + forever begin + tl_filt_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_filt item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_filt_fifo + +task ac_range_check_scoreboard::process_tl_access(tl_seq_item item, + tl_channels_e channel, + string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = ( write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = ( write && channel == DataChannel); + + // If access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // Process the csr req: + // - for write, update local variable and fifo at address phase + // - for read, update predication at address phase and compare at data phase + case (csr.get_name()) + // Add individual case item for each csr + "intr_state": begin + // FIXME TODO MVy + do_read_check = 1'b0; + end + "intr_enable": begin + // FIXME TODO MVy + end + "intr_test": begin + // FIXME TODO MVy + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end +endtask : process_tl_access + +function void ac_range_check_scoreboard::reset(string kind = "HARD"); + super.reset(kind); + // Reset local fifos queues and variables +endfunction : reset + +function void ac_range_check_scoreboard::check_phase(uvm_phase phase); + super.check_phase(phase); + // Post test checks - ensure that all local fifos and queues are empty +endfunction : check_phase diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv new file mode 100644 index 0000000000000..2f022b0c6debe --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(ac_range_check_env_cfg), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_virtual_sequencer) + + tl_sequencer tl_csr_sqr; + tl_sequencer tl_unfilt_sqr; + tl_sequencer tl_filt_sqr; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_virtual_sequencer + +function ac_range_check_virtual_sequencer::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv new file mode 100644 index 0000000000000..2a3dbb5072c73 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_vseq extends cip_base_vseq #( + .RAL_T (ac_range_check_reg_block), + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T (ac_range_check_virtual_sequencer) + ); + `uvm_object_utils(ac_range_check_base_vseq) + + // Various knobs to enable certain routines + bit do_ac_range_check_init = 1'b1; + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern task dut_init(string reset_kind = "HARD"); + extern task ac_range_check_init(); +endclass : ac_range_check_base_vseq + + +function ac_range_check_base_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_base_vseq::dut_init(string reset_kind = "HARD"); + super.dut_init(); + if (do_ac_range_check_init) begin + ac_range_check_init(); + end +endtask : dut_init + +task ac_range_check_base_vseq::ac_range_check_init(); + `uvm_error(`gfn, "FIXME") +endtask : ac_range_check_init diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv new file mode 100644 index 0000000000000..de14ef600afd1 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence is mainly used to run the CSR tests, there is no need to run multiple transactions +// in this sequence. Hence, the constraint is set to run only one transaction. +class ac_range_check_common_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_common_vseq) + + // Constraints + extern constraint num_trans_c; + + // Standard SV/UVM methods + extern function new(string name=""); + extern task pre_start(); + extern task body(); +endclass : ac_range_check_common_vseq + + +constraint ac_range_check_common_vseq::num_trans_c { + num_trans == 1; +} + +function ac_range_check_common_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_common_vseq::pre_start(); + do_ac_range_check_init = 1'b0; + super.pre_start(); +endtask : pre_start + +task ac_range_check_common_vseq::body(); + run_common_vseq_wrapper(num_trans); +endtask : body diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv new file mode 100644 index 0000000000000..c6c70a470ab6b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_smoke_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_smoke_vseq) + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_smoke_vseq + + +function ac_range_check_smoke_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_smoke_vseq::body(); + `uvm_error(`gfn, "FIXME") +endtask : body diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv new file mode 100644 index 0000000000000..5e7b497a396c3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "ac_range_check_base_vseq.sv" +`include "ac_range_check_smoke_vseq.sv" +`include "ac_range_check_common_vseq.sv" diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv new file mode 100644 index 0000000000000..87cc1a4fb823c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ac_range_check_bind; + + bind ac_range_check tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind ac_range_check ac_range_check_csr_assert_fpv ac_range_check_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core new file mode 100644 index 0000000000000..a2a24d67fe8a3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_sva:0.1 +description: "AC_RANGE_CHECK assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - ac_range_check_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:opentitan:top_darjeeling_ac_range_check + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/ac_range_check.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: ac_range_check diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv new file mode 100644 index 0000000000000..2fbd85cfe43dd --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv @@ -0,0 +1,86 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // Dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import ac_range_check_env_pkg::*; + import ac_range_check_test_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk; + wire rst_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire rst_shadowed_n; + wire top_racl_pkg::racl_policy_vec_t racl_policies; + wire racl_error; + wire top_racl_pkg::racl_error_log_t racl_error_log; + wire intr_deny_cnt_reached; + wire prim_mubi_pkg::mubi8_t range_check_overwrite; + + // Interfaces + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + clk_rst_if clk_rst_if (.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shad_if (.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + tl_if tl_csr_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_unfilt_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_filt_if (.clk(clk), .rst_n(rst_n)); + + `DV_ALERT_IF_CONNECT() + + // DUT + ac_range_check dut ( + .clk_i (clk ), + .rst_ni (rst_n ), + .rst_shadowed_ni (rst_shadowed_n ), + // Alerts + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // RACL interface + .racl_policies_i (racl_policies ), + .racl_error_o (racl_error ), + .racl_error_log_o (racl_error_log ), + // Access range check interrupts + .intr_deny_cnt_reached_o (intr_deny_cnt_reached ), + // Bus interface + .tl_i (tl_csr_if.h2d ), + .tl_o (tl_csr_if.d2h ), + // Inter module signals + .range_check_overwrite_i (range_check_overwrite ), + // Incoming TLUL interface + .ctn_tl_h2d_i (tl_unfilt_if.h2d ), + .ctn_tl_d2h_o (tl_unfilt_if.d2h ), + // Filtered outgoing TLUL interface to the target if request is not squashed + .ctn_filtered_tl_h2d_o (tl_filt_if.h2d ), + .ctn_filtered_tl_d2h_i (tl_filt_if.d2h ) + ); + + // Manage inputs + // TODO should be driven dynamically by an io_agent (to be created TODO MVy) + assign range_check_overwrite = prim_mubi_pkg::MuBi8False; + assign racl_policies = top_racl_pkg::RACL_POLICY_VEC_DEFAULT; + + // Manage outputs + assign interrupts[DenyCntReached] = intr_deny_cnt_reached; + // TODO should be monitored dynamically by an io_agent (to be created TODO MVy) + // assign io_if.racl_error = racl_error; + // assign io_if.racl_error_log = racl_error_log; + + initial begin + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_csr_agt*", "tl_csr_vif", tl_csr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "tl_unfilt_vif", tl_unfilt_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "tl_filt_vif", tl_filt_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv new file mode 100644 index 0000000000000..e732a5b5661d0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_test extends cip_base_test #( + .CFG_T(ac_range_check_env_cfg), + .ENV_T(ac_range_check_env) + ); + + `uvm_component_utils(ac_range_check_base_test) + + // The base class dv_base_test creates the following instances: + // - ac_range_check_env_cfg: cfg + // - ac_range_check_env: env + + // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in the run_phase. + // As such, nothing more needs to be done + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_base_test + + +function ac_range_check_base_test::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core new file mode 100644 index 0000000000000..4919631b32638 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_test:0.1 +description: "AC_RANGE_CHECK DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:opentitan:top_darjeeling_ac_range_check_env + files: + - ac_range_check_test_pkg.sv + - ac_range_check_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv new file mode 100644 index 0000000000000..a409d852dcd5d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_test_pkg; + // Dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import ac_range_check_env_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Local types + + // Functions + + // Package sources + `include "ac_range_check_base_test.sv" + +endpackage