diff --git a/hw/ip/prim/prim_mubi.core b/hw/ip/prim/prim_mubi.core index 45aa85f7aec6ce..f8d8cdd0b604f9 100644 --- a/hw/ip/prim/prim_mubi.core +++ b/hw/ip/prim/prim_mubi.core @@ -16,8 +16,8 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:buf - lowrisc:prim:flop + - lowrisc:prim:mubi_pkg files: - - rtl/prim_mubi_pkg.sv - rtl/prim_mubi4_sender.sv - rtl/prim_mubi4_sync.sv - rtl/prim_mubi4_dec.sv diff --git a/hw/ip/prim/prim_mubi_pkg.core b/hw/ip/prim/prim_mubi_pkg.core new file mode 100644 index 00000000000000..57a1f61a2eebe2 --- /dev/null +++ b/hw/ip/prim/prim_mubi_pkg.core @@ -0,0 +1,45 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# +# util/design/gen-mubi.py +# +name: "lowrisc:prim:mubi_pkg:0.1" +description: "Multibit types and functions" +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + files: + - rtl/prim_mubi_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/prim_mubi.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index 736caad5944fd1..fcb0c00176a02e 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core @@ -8,7 +8,7 @@ description: "prim" filesets: files_rtl: depend: - - lowrisc:ip:tlul + - lowrisc:tlul:headers - lowrisc:prim:ram_1p - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" diff --git a/hw/ip/tlul/headers.core b/hw/ip/tlul/headers.core index 3da0e1c75e2ef7..2f2e722535b3f8 100644 --- a/hw/ip/tlul/headers.core +++ b/hw/ip/tlul/headers.core @@ -10,7 +10,7 @@ filesets: depend: - lowrisc:constants:top_pkg - lowrisc:prim:secded - - lowrisc:prim:mubi + - lowrisc:prim:mubi_pkg files: - rtl/tlul_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl index ff456a51e7e09e..b334f683b1f8b1 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr.core.tpl @@ -12,6 +12,7 @@ filesets: depend: - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg:0.1")} - ${instance_vlnv("lowrisc:ip:pwrmgr_reg:0.1")} + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl index cdf252d74038f2..8f848f9b665ff1 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr_pkg.core.tpl @@ -9,12 +9,12 @@ virtual: filesets: files_rtl: - depend: - - ${instance_vlnv("lowrisc:ip:pwrmgr_reg")} % if wait_for_external_reset: + depend: - lowrisc:ip:rom_ctrl_pkg % endif files: + - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl index 886a9c9fc6fb6d..e4de42ba0cad3a 100644 --- a/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl +++ b/hw/ip_templates/pwrmgr/pwrmgr_reg.core.tpl @@ -10,11 +10,11 @@ virtual: filesets: files_rtl: depend: - - lowrisc:tlul:headers - lowrisc:ip:tlul + - ${instance_vlnv("lowrisc:ip:pwrmgr_pkg")} - lowrisc:prim:subreg + - lowrisc:tlul:headers files: - - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_reg_top.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core index bd571df415d598..b11f1e915c6efb 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr.core @@ -12,6 +12,7 @@ filesets: depend: - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg:0.1 - lowrisc:opentitan:top_darjeeling_pwrmgr_reg:0.1 + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core index 997acbf90f7376..444c46d7404353 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -10,9 +10,9 @@ virtual: filesets: files_rtl: depend: - - lowrisc:opentitan:top_darjeeling_pwrmgr_reg - lowrisc:ip:rom_ctrl_pkg files: + - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core index 4734a823dc51e0..aaa19bc65a59f8 100644 --- a/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_darjeeling/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -10,11 +10,11 @@ virtual: filesets: files_rtl: depend: - - lowrisc:tlul:headers - lowrisc:ip:tlul + - lowrisc:opentitan:top_darjeeling_pwrmgr_pkg - lowrisc:prim:subreg + - lowrisc:tlul:headers files: - - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_reg_top.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core index e02527dbc422db..6c666f9c2ace7c 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr.core @@ -12,6 +12,7 @@ filesets: depend: - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg:0.1 - lowrisc:opentitan:top_earlgrey_pwrmgr_reg:0.1 + - lowrisc:ip:rom_ctrl_pkg - lowrisc:ip:rv_core_ibex_pkg - lowrisc:ip:pwrmgr_component file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core index 443110c717e337..12116d09ff13f5 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -9,9 +9,8 @@ virtual: filesets: files_rtl: - depend: - - lowrisc:opentitan:top_earlgrey_pwrmgr_reg files: + - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_pkg.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core index 37d80d19168bc1..10aeb6362523dd 100644 --- a/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core +++ b/hw/top_earlgrey/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -10,11 +10,11 @@ virtual: filesets: files_rtl: depend: - - lowrisc:tlul:headers - lowrisc:ip:tlul + - lowrisc:opentitan:top_earlgrey_pwrmgr_pkg - lowrisc:prim:subreg + - lowrisc:tlul:headers files: - - rtl/pwrmgr_reg_pkg.sv - rtl/pwrmgr_reg_top.sv file_type: systemVerilogSource diff --git a/util/design/data/prim_mubi.core.tpl b/util/design/data/prim_mubi.core.tpl index 29fd2528ebefbf..b82d7edcf914f3 100644 --- a/util/design/data/prim_mubi.core.tpl +++ b/util/design/data/prim_mubi.core.tpl @@ -16,8 +16,8 @@ filesets: - lowrisc:prim:assert - lowrisc:prim:buf - lowrisc:prim:flop + - lowrisc:prim:mubi_pkg files: - - rtl/prim_mubi_pkg.sv % for n in range(1, n_max_nibbles+1): - rtl/prim_mubi${4*n}_sender.sv - rtl/prim_mubi${4*n}_sync.sv diff --git a/util/design/data/prim_mubi_pkg.core.tpl b/util/design/data/prim_mubi_pkg.core.tpl new file mode 100644 index 00000000000000..57a1f61a2eebe2 --- /dev/null +++ b/util/design/data/prim_mubi_pkg.core.tpl @@ -0,0 +1,45 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# +# util/design/gen-mubi.py +# +name: "lowrisc:prim:mubi_pkg:0.1" +description: "Multibit types and functions" +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + files: + - rtl/prim_mubi_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/prim_mubi.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/util/design/mubi/prim_mubi.py b/util/design/mubi/prim_mubi.py index 3737a2a03bf270..d634f226c787db 100755 --- a/util/design/mubi/prim_mubi.py +++ b/util/design/mubi/prim_mubi.py @@ -7,6 +7,7 @@ from mako.template import Template # type: ignore MUBI_PKG_TPL_PATH = "util/design/data/prim_mubi_pkg.sv.tpl" +MUBI_PKG_CORE_TPL_PATH = "util/design/data/prim_mubi_pkg.core.tpl" MUBI_CORE_TPL_PATH = "util/design/data/prim_mubi.core.tpl" MUBI_SENDER_TPL_PATH = "util/design/data/prim_mubi_sender.sv.tpl" MUBI_SYNC_TPL_PATH = "util/design/data/prim_mubi_sync.sv.tpl" @@ -15,6 +16,7 @@ MUBI_SW_ASM_TPL_PATH = "util/design/data/multibits_asm.h.tpl" MUBI_PKG_OUT_PATH = "hw/ip/prim/rtl/prim_mubi_pkg.sv" +MUBI_PKG_CORE_OUT_PATH = "hw/ip/prim/prim_mubi_pkg.core" MUBI_CORE_OUT_PATH = "hw/ip/prim/prim_mubi.core" MUBI_SENDER_OUT_PATH = "hw/ip/prim/rtl/prim_mubi{}_sender.sv" MUBI_SYNC_OUT_PATH = "hw/ip/prim/rtl/prim_mubi{}_sync.sv" @@ -60,6 +62,7 @@ def gen() -> None: tpls = [ (MUBI_PKG_TPL_PATH, MUBI_PKG_OUT_PATH), + (MUBI_PKG_CORE_TPL_PATH, MUBI_PKG_CORE_OUT_PATH), (MUBI_CORE_TPL_PATH, MUBI_CORE_OUT_PATH), (MUBI_SW_TPL_PATH, MUBI_SW_OUT_PATH), (MUBI_SW_ASM_TPL_PATH, MUBI_SW_ASM_OUT_PATH),