diff --git a/hw/ip/aon_timer/dv/cov/aon_timer_unr_manually_excluded_excl.el b/hw/ip/aon_timer/dv/cov/aon_timer_unr_manually_excluded_excl.el
new file mode 100644
index 00000000000000..5de5a6eb07d74e
--- /dev/null
+++ b/hw/ip/aon_timer/dv/cov/aon_timer_unr_manually_excluded_excl.el
@@ -0,0 +1,186 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+//==================================================
+// This file contains the Excluded objects
+// Generated By User: antonio
+// Format Version: 2
+// Date: Wed Dec 18 17:15:12 2024
+// ExclMode: default
+//==================================================
+CHECKSUM: "1706182284 132761700"
+INSTANCE: tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
+ANNOTATION: "tl_i.d_user is hardcoded to 0x0 "
+Block 1 "461445014" "assign rsp_intg = tl_i.d_user.rsp_intg;"
+ANNOTATION: "tl_i.d_user is hardcoded to 0x0"
+Block 2 "2643129081" "assign data_intg = tl_i.d_user.data_intg;"
+CHECKSUM: "2815520955 1214062232"
+INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Block 43 "3846199569" "gen_wr_req.state_d = StIdle;"
+CHECKSUM: "2815520955 1214062232"
+INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Block 43 "3846199569" "gen_wr_req.state_d = StIdle;"
+CHECKSUM: "2815520955 1214062232"
+INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Block 43 "3846199569" "gen_wr_req.state_d = StIdle;"
+CHECKSUM: "2815520955 1214062232"
+INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Block 43 "3846199569" "gen_wr_req.state_d = StIdle;"
+CHECKSUM: "2815520955 4051034043"
+INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-"
+CHECKSUM: "2815520955 4051034043"
+INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-"
+CHECKSUM: "2815520955 4051034043"
+INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-"
+CHECKSUM: "2815520955 4051034043"
+INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb
+ANNOTATION: "Default statement can't be hit unless some wrong value is forced in the `state_d` signal"
+Branch 4 "3547459906" "gen_wr_req.state_q" (6) "gen_wr_req.state_q default,-,-,-,-"
+CHECKSUM: "530940107 4102526809"
+INSTANCE: tb.dut
+ANNOTATION: "intr_test_flds_we[0/1] is asserted at the same time whenever the intr_test register is written, so the combination of only one Qe being set is not possible."
+Condition 4 "594611319" "(reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe) 1 -1" (3 "10")
+Condition 4 "594611319" "(reg2hw.intr_test.wkup_timer_expired.qe | reg2hw.intr_test.wdog_timer_bark.qe) 1 -1" (2 "01")
+CHECKSUM: "1125143680 279071062"
+INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 4 "937119686" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 279071062"
+INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 4 "937119686" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 279071062"
+INSTANCE: tb.dut.u_reg.u_wdog_count_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 4 "937119686" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 3293469597"
+INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 5 "937119686" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 1408670975"
+INSTANCE: tb.dut.u_reg.u_wkup_ctrl_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 3 "86646938" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 1408670975"
+INSTANCE: tb.dut.u_reg.u_wkup_thold_hi_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 3 "86646938" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 1408670975"
+INSTANCE: tb.dut.u_reg.u_wkup_thold_lo_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 3 "86646938" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 1408670975"
+INSTANCE: tb.dut.u_reg.u_wdog_bark_thold_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 3 "86646938" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 1408670975"
+INSTANCE: tb.dut.u_reg.u_wdog_bite_thold_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 3 "86646938" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "1125143680 1408670975"
+INSTANCE: tb.dut.u_reg.u_wdog_ctrl_cdc
+ANNOTATION: "src_ack is only 1 cycle pulse, and is an acknowledgment to a request from a read/write.
+src_busy_q feeds of the request, so by the time src_ack is high src_busy_q should also be high.
+See assertion SrcAckBusyChk_A for more details"
+Condition 3 "86646938" "(src_busy_q && src_ack) 1 -1" (1 "01")
+CHECKSUM: "2815520955 4109606122"
+INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb
+ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req"
+Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01")
+ANNOTATION: "It would need dst_req_i=1, dst_req_q=1, busy=1. However, that's not possible.
+
+The FSM stays in IDLE until there's a request, and  then stays in StWait 1-cycle. During StWait, dst_req_q is set to 0x1, but we are also transitioning back to StIdle where busy will be set to 0x0 making the missing condition coverage unhittable.
+"
+Condition 2 "1682497780" "(dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy) 1 -1" (2 "101")
+CHECKSUM: "2815520955 4109606122"
+INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb
+ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req"
+Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01")
+ANNOTATION: "It can't be hit because the case where dst_req=1 and dst_lat_d=1 is covered in the branch above."
+Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01")
+ANNOTATION: "It would need dst_req_i=1, dst_req_q=1, busy=1. However, that's not possible.
+
+The FSM stays in IDLE until there's a request, and  then stays in StWait 1-cycle. During StWait, dst_req_q is set to 0x1, but we are also transitioning back to StIdle where busy will be set to 0x0 making the missing condition coverage unhittable.
+"
+Condition 2 "1682497780" "(dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy) 1 -1" (2 "101")
+CHECKSUM: "2815520955 4109606122"
+INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb
+ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req"
+Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01")
+ANNOTATION: "It can't be hit because the case where dst_req=1 and dst_lat_d=1 is covered in the branch above."
+Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01")
+ANNOTATION: "It would need dst_req_i=1, dst_req_q=1, busy=1. However, that's not possible.
+
+The FSM stays in IDLE until there's a request, and  then stays in StWait 1-cycle. During StWait, dst_req_q is set to 0x1, but we are also transitioning back to StIdle where busy will be set to 0x0 making the missing condition coverage unhittable.
+"
+Condition 2 "1682497780" "(dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy) 1 -1" (2 "101")
+CHECKSUM: "2815520955 4109606122"
+INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb
+ANNOTATION: "It can't be hit because dst_update_ack won't be set prior to dst_update_req"
+Condition 3 "3080886878" "(gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack) 1 -1" (1 "01")
+ANNOTATION: "It can't be hit because the case where dst_req=1 and dst_lat_d=1 is covered in the branch above."
+Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01")
+ANNOTATION: "It would need dst_req_i=1, dst_req_q=1, busy=1. However, that's not possible.
+
+The FSM stays in IDLE until there's a request, and  then stays in StWait 1-cycle. During StWait, dst_req_q is set to 0x1, but we are also transitioning back to StIdle where busy will be set to 0x0 making the missing condition coverage unhittable.
+"
+Condition 2 "1682497780" "(dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy) 1 -1" (2 "101")
+CHECKSUM: "3643792208 1147758610"
+INSTANCE: tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10")
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01")
+ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable"
+Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" (1 "01")
+CHECKSUM: "3643792208 1147758610"
+INSTANCE: tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10")
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01")
+ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable"
+Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" (1 "01")
+CHECKSUM: "3643792208 1147758610"
+INSTANCE: tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10")
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01")
+ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable"
+Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1" (1 "01")
+CHECKSUM: "3643792208 1147758610"
+INSTANCE: tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync
+ANNOTATION: "src_ack becomes one 1-cycle after dst_ack goes high. Since dst_ack_i is wired to dst_req_o, it means src_ack_o can't be set until after src_req_i is set."
+Condition 1 "1414883863" "(src_req_i & src_ack_o) 1 -1"
+ANNOTATION: "Output and input are connected to the same signal, hence the missing coverage is not reachable"
+Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1"