diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll index a2526d9f5591a..c2aab35194831 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll @@ -31,7 +31,7 @@ define void @broadcast() #0{ ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector undef, undef, zeroinitializer ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector undef, undef, zeroinitializer ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector undef, undef, zeroinitializer -; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void %zero = shufflevector undef, undef, zeroinitializer %1 = shufflevector undef, undef, zeroinitializer diff --git a/llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll b/llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll index a214451bfd3fd..f0a5e9045c3b2 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll @@ -293,7 +293,7 @@ define i32 @store_with_pointer_phi_incoming_phi(ptr %A, ptr %B, ptr %C, i1 %c.0, ; CHECK-EMPTY: ; CHECK-NEXT: Expressions re-written: ; -; CHECK-EMPTY +; CHECK-EMPTY: entry: br label %loop.header @@ -376,7 +376,7 @@ define i32 @store_with_pointer_phi_incoming_phi_irreducible_cycle(ptr %A, ptr %B ; CHECK-EMPTY: ; CHECK-NEXT: Expressions re-written: ; -; CHECK-EMPTY +; CHECK-EMPTY: entry: br label %loop.header diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll index 7fd8ac40e4bec..500fcc41dc40c 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/branch-outside.ll @@ -1,6 +1,6 @@ ; RUN: opt %s -mtriple amdgcn-- -passes='print' -disable-output 2>&1 | FileCheck %s -; CHECK=LABEL: UniformityInfo for function 'basic': +; CHECK-LABEL: UniformityInfo for function 'basic': ; CHECK: CYCLES ASSSUMED DIVERGENT: ; CHECK: depth=1: entries(P T) Q define amdgpu_kernel void @basic(i32 %a, i32 %b, i32 %c) { @@ -37,7 +37,7 @@ exit: ret void } -; CHECK=LABEL: UniformityInfo for function 'nested': +; CHECK-LABEL: UniformityInfo for function 'nested': ; CHECK: CYCLES ASSSUMED DIVERGENT: ; CHECK: depth=1: entries(P T) Q A C B define amdgpu_kernel void @nested(i32 %a, i32 %b, i32 %c) { diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll index 2a3ff4166213d..4b6fced1d58dd 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/exit-divergence.ll @@ -1,6 +1,6 @@ ; RUN: opt %s -mtriple amdgcn-- -passes='print' -disable-output 2>&1 | FileCheck %s -; CHECK=LABEL: UniformityInfo for function 'basic': +; CHECK-LABEL: UniformityInfo for function 'basic': ; CHECK-NOT: CYCLES ASSSUMED DIVERGENT: ; CHECK: CYCLES WITH DIVERGENT EXIT: ; CHECK: depth=1: entries(P T) Q diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll index feb29497f80c9..6edd6384db7d1 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/reducible-headers.ll @@ -31,7 +31,7 @@ ; at P should not be marked divergent. define amdgpu_kernel void @nested_irreducible(i32 %a, i32 %b, i32 %c) { -; CHECK=LABEL: UniformityInfo for function 'nested_irreducible': +; CHECK-LABEL: UniformityInfo for function 'nested_irreducible': ; CHECK-NOT: CYCLES ASSSUMED DIVERGENT: ; CHECK: CYCLES WITH DIVERGENT EXIT: ; CHECK-DAG: depth=2: entries(P T) R Q @@ -118,7 +118,7 @@ exit: ; Thus, any PHI at P should not be marked divergent. define amdgpu_kernel void @header_label_1(i32 %a, i32 %b, i32 %c) { -; CHECK=LABEL: UniformityInfo for function 'header_label_1': +; CHECK-LABEL: UniformityInfo for function 'header_label_1': ; CHECK-NOT: CYCLES ASSSUMED DIVERGENT: ; CHECK: CYCLES WITH DIVERGENT EXIT: ; CHECK: depth=1: entries(H) Q P U T R diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/temporal_diverge.ll b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/temporal_diverge.ll index 395d7125e3c8d..3015e1326a406 100644 --- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/temporal_diverge.ll +++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/temporal_diverge.ll @@ -169,7 +169,7 @@ X: br label %G G: -; C HECK: DIVERGENT: %div.user = +; CHECK: DIVERGENT: %div.user = %div.user = add i32 %uni.inc, 5 br i1 %uni.cond, label %G, label %Y ; CHECK: DIVERGENT: %div.user = diff --git a/llvm/test/Assembler/bfloat.ll b/llvm/test/Assembler/bfloat.ll index 3a3b4c2b277db..6f935c5dac154 100644 --- a/llvm/test/Assembler/bfloat.ll +++ b/llvm/test/Assembler/bfloat.ll @@ -37,25 +37,25 @@ define float @check_bfloat_convert() { ret float %tmp } -; ASSEM-DISASS-LABEL @snan_bfloat +; ASSEM-DISASS-LABEL: @snan_bfloat define bfloat @snan_bfloat() { ; ASSEM-DISASS: ret bfloat 0xR7F81 ret bfloat 0xR7F81 } -; ASSEM-DISASS-LABEL @qnan_bfloat +; ASSEM-DISASS-LABEL: @qnan_bfloat define bfloat @qnan_bfloat() { ; ASSEM-DISASS: ret bfloat 0xR7FC0 ret bfloat 0xR7FC0 } -; ASSEM-DISASS-LABEL @pos_inf_bfloat +; ASSEM-DISASS-LABEL: @pos_inf_bfloat define bfloat @pos_inf_bfloat() { ; ASSEM-DISASS: ret bfloat 0xR7F80 ret bfloat 0xR7F80 } -; ASSEM-DISASS-LABEL @neg_inf_bfloat +; ASSEM-DISASS-LABEL: @neg_inf_bfloat define bfloat @neg_inf_bfloat() { ; ASSEM-DISASS: ret bfloat 0xRFF80 ret bfloat 0xRFF80 diff --git a/llvm/test/Bitcode/convergence-control.ll b/llvm/test/Bitcode/convergence-control.ll index 7ba5609b6a7cc..6988ab029f42a 100644 --- a/llvm/test/Bitcode/convergence-control.ll +++ b/llvm/test/Bitcode/convergence-control.ll @@ -18,7 +18,7 @@ B: C: ; CHECK-LABEL: C: ; CHECK: [[C:%.*]] = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token [[B]]) ] - ; CHEC K: call void @f() [ "convergencectrl"(token [[C]]) ] + ; CHECK: call void @f() [ "convergencectrl"(token [[C]]) ] ; %c = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %b) ] call void @f() [ "convergencectrl"(token %c) ] diff --git a/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll b/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll index b2643dc8f9dcb..44071a113a4a0 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll @@ -320,8 +320,8 @@ declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld3lane. define %struct.bfloat16x8x3_t @test_vld3q_lane_bf16(ptr %ptr, [3 x <8 x bfloat>] %src.coerce) local_unnamed_addr nounwind { ; CHECK-LABEL: test_vld3q_lane_bf16: ; CHECK: // %bb.0: // %entry -; CHECKT: ld3 { v0.h, v1.h, v2.h }[7], [x0] -; CHECKT: ret +; CHECK: ld3 { v0.h, v1.h, v2.h }[7], [x0] +; CHECK: ret entry: %src.coerce.fca.0.extract = extractvalue [3 x <8 x bfloat>] %src.coerce, 0 %src.coerce.fca.1.extract = extractvalue [3 x <8 x bfloat>] %src.coerce, 1 diff --git a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll index e11ae9a251590..aa4f374d5d7e7 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD ; RUN: llc -mtriple=aarch64 -aarch64-enable-sink-fold=true -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI -; CHECK_GI: warning: Instruction selection used fallback path for mulv_v3i64 +; CHECK-GI: warning: Instruction selection used fallback path for mulv_v3i64 declare i8 @llvm.vector.reduce.mul.v2i8(<2 x i8>) declare i8 @llvm.vector.reduce.mul.v3i8(<3 x i8>) diff --git a/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll b/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll index 6bcd2f04849b2..d999959bba46f 100644 --- a/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll +++ b/llvm/test/CodeGen/AArch64/arm64-addr-mode-folding.ll @@ -8,7 +8,7 @@ define i32 @fct(i32 %i1, i32 %i2) { ; Sign extension is used more than once, thus it should not be folded. ; CodeGenPrepare is not sharing sext across uses, thus this is folded because ; of that. -; _CHECK-NOT: , sxtw] +; CHECK-NOT: , sxtw] entry: %idxprom = sext i32 %i1 to i64 %0 = load ptr, ptr @block, align 8 diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll index 0000262e833da..19b9205dc1786 100644 --- a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll +++ b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll @@ -2,70 +2,70 @@ ; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS define i8 @test_load_8(ptr %addr) { -; CHECK-LABAL: test_load_8: +; CHECK-LABEL: test_load_8: ; CHECK: ldarb w0, [x0] %val = load atomic i8, ptr %addr seq_cst, align 1 ret i8 %val } define i16 @test_load_16(ptr %addr) { -; CHECK-LABAL: test_load_16: +; CHECK-LABEL: test_load_16: ; CHECK: ldarh w0, [x0] %val = load atomic i16, ptr %addr acquire, align 2 ret i16 %val } define i32 @test_load_32(ptr %addr) { -; CHECK-LABAL: test_load_32: +; CHECK-LABEL: test_load_32: ; CHECK: ldar w0, [x0] %val = load atomic i32, ptr %addr seq_cst, align 4 ret i32 %val } define i64 @test_load_64(ptr %addr) { -; CHECK-LABAL: test_load_64: +; CHECK-LABEL: test_load_64: ; CHECK: ldar x0, [x0] %val = load atomic i64, ptr %addr seq_cst, align 8 ret i64 %val } define ptr @test_load_ptr(ptr %addr) { -; CHECK-LABAL: test_load_ptr: +; CHECK-LABEL: test_load_ptr: ; CHECK: ldar w0, [x0] %val = load atomic ptr, ptr %addr seq_cst, align 8 ret ptr %val } define void @test_store_8(ptr %addr) { -; CHECK-LABAL: test_store_8: +; CHECK-LABEL: test_store_8: ; CHECK: stlrb wzr, [x0] store atomic i8 0, ptr %addr seq_cst, align 1 ret void } define void @test_store_16(ptr %addr) { -; CHECK-LABAL: test_store_16: +; CHECK-LABEL: test_store_16: ; CHECK: stlrh wzr, [x0] store atomic i16 0, ptr %addr seq_cst, align 2 ret void } define void @test_store_32(ptr %addr) { -; CHECK-LABAL: test_store_32: +; CHECK-LABEL: test_store_32: ; CHECK: stlr wzr, [x0] store atomic i32 0, ptr %addr seq_cst, align 4 ret void } define void @test_store_64(ptr %addr) { -; CHECK-LABAL: test_store_64: +; CHECK-LABEL: test_store_64: ; CHECK: stlr xzr, [x0] store atomic i64 0, ptr %addr seq_cst, align 8 ret void } define void @test_store_ptr(ptr %addr) { -; CHECK-LABAL: test_store_ptr: +; CHECK-LABEL: test_store_ptr: ; CHECK: stlr wzr, [x0] store atomic ptr null, ptr %addr seq_cst, align 8 ret void diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll index e9556b9d5cbee..c550a24754c96 100644 --- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll +++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s define void @no_op() nounwind { -; CHECK-LABEL .def $ientry_thunk$cdecl$v$v; +; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v; ; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v ; CHECK: // %bb.0: ; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill diff --git a/llvm/test/CodeGen/AArch64/cxx-tlscc.ll b/llvm/test/CodeGen/AArch64/cxx-tlscc.ll index 21367aaa8b07f..5a2be8e0e47a9 100644 --- a/llvm/test/CodeGen/AArch64/cxx-tlscc.ll +++ b/llvm/test/CodeGen/AArch64/cxx-tlscc.ll @@ -46,7 +46,7 @@ __tls_init.exit: ; CHECK-NOT: stp x20, x19 ; FIXME: The splitting logic in the register allocator fails to split along ; control flow here, we used to get this right by accident before... -; CHECK-NOTXX: stp x14, x13 +; COM: CHECK-NOT: stp x14, x13 ; CHECK-NOT: stp x12, x11 ; CHECK-NOT: stp x10, x9 ; CHECK-NOT: stp x8, x7 @@ -65,7 +65,7 @@ __tls_init.exit: ; CHECK-NOT: ldp x8, x7 ; CHECK-NOT: ldp x10, x9 ; CHECK-NOT: ldp x12, x11 -; CHECK-NOTXX: ldp x14, x13 +; COM: CHECK-NOT: ldp x14, x13 ; CHECK-NOT: ldp x20, x19 ; CHECK-NOT: ldp d1, d0 ; CHECK-NOT: ldp d3, d2 diff --git a/llvm/test/CodeGen/AArch64/fp16-fmla.ll b/llvm/test/CodeGen/AArch64/fp16-fmla.ll index a81721afb8453..916fbeb94dcf8 100644 --- a/llvm/test/CodeGen/AArch64/fp16-fmla.ll +++ b/llvm/test/CodeGen/AArch64/fp16-fmla.ll @@ -84,11 +84,11 @@ entry: define <4 x half> @test_FMLAv4i16_indexed_OP1(<4 x half> %a, <4 x i16> %b, <4 x i16> %c) { ; CHECK-LABEL: test_FMLAv4i16_indexed_OP1: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fadd -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %mul = mul <4 x i16> %c, %b %m = bitcast <4 x i16> %mul to <4 x half> @@ -98,11 +98,11 @@ entry: define <4 x half> @test_FMLAv4i16_indexed_OP2(<4 x half> %a, <4 x i16> %b, <4 x i16> %c) { ; CHECK-LABEL: test_FMLAv4i16_indexed_OP2: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fadd -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fmla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %mul = mul <4 x i16> %c, %b %m = bitcast <4 x i16> %mul to <4 x half> @@ -112,11 +112,11 @@ entry: define <8 x half> @test_FMLAv8i16_indexed_OP1(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) { ; CHECK-LABEL: test_FMLAv8i16_indexed_OP1: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fadd -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %mul = mul <8 x i16> %c, %b %m = bitcast <8 x i16> %mul to <8 x half> @@ -126,11 +126,11 @@ entry: define <8 x half> @test_FMLAv8i16_indexed_OP2(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) { ; CHECK-LABEL: test_FMLAv8i16_indexed_OP2: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fadd -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %mul = mul <8 x i16> %c, %b %m = bitcast <8 x i16> %mul to <8 x half> @@ -178,11 +178,11 @@ entry: define <4 x half> @test_FMLSv4i16_indexed_OP2(<4 x half> %a, <4 x i16> %b, <4 x i16> %c) { ; CHECK-LABEL: test_FMLSv4i16_indexed_OP2: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fsub -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fmls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fmls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %mul = mul <4 x i16> %c, %b %m = bitcast <4 x i16> %mul to <4 x half> @@ -192,12 +192,12 @@ entry: define <8 x half> @test_FMLSv8i16_indexed_OP1(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) { ; CHECK-LABEL: test_FMLSv8i16_indexed_OP1: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fsub -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fneg {{v[0-9]+}}.8h, {{v[0-9]+}}.8h -; CHECK-FIXME: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fneg {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +; COM: CHECK: fmla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %mul = mul <8 x i16> %c, %b %m = bitcast <8 x i16> %mul to <8 x half> @@ -207,11 +207,11 @@ entry: define <8 x half> @test_FMLSv8i16_indexed_OP2(<8 x half> %a, <8 x i16> %b, <8 x i16> %c) { ; CHECK-LABEL: test_FMLSv8i16_indexed_OP2: -; CHECK-FIXME: Currently LLVM produces inefficient code: +; FIXME: Currently LLVM produces inefficient code: ; CHECK: mul ; CHECK: fsub -; CHECK-FIXME: It should instead produce the following instruction: -; CHECK-FIXME: fmls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h +; FIXME: It should instead produce the following instruction: +; COM: CHECK: fmls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %mul = mul <8 x i16> %c, %b %m = bitcast <8 x i16> %mul to <8 x half> diff --git a/llvm/test/CodeGen/AArch64/fpimm.ll b/llvm/test/CodeGen/AArch64/fpimm.ll index b92bb4245c7f3..e2944243338f5 100644 --- a/llvm/test/CodeGen/AArch64/fpimm.ll +++ b/llvm/test/CodeGen/AArch64/fpimm.ll @@ -38,7 +38,7 @@ define void @check_double() { ; 64-bit ORR followed by MOVK. ; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844 ; CHECK-DAG: movk [[XFP0]], #64764, lsl #16 -; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]] +; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]] %newval3 = fadd double %val, 0xFCFCFC00FC store volatile double %newval3, ptr @varf64 diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll index a5757a70843a9..fa63df35ac857 100644 --- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll +++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll @@ -28,7 +28,7 @@ define void @a() "sign-return-address"="all" { } define void @b() "sign-return-address"="non-leaf" { -; CHECK-LABE: b: // @b +; CHECK-LABEL: b: // @b ; V8A-NOT: hint #25 ; V83A-NOT: paciasp ; CHECK-NOT: .cfi_negate_ra_state diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll index fedbb642a3620..c589d356e6937 100644 --- a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll +++ b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll @@ -83,11 +83,11 @@ entry: ret double 0x400921FB54442D18 ; CHECK-LABEL: litf: -; CHECK-DONT: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]] -; CHECK-DONT-NEXT: ldr {{d[0-9]+}}, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}} -; CHECK-FUSE: mov [[R:x[0-9]+]], #11544 -; CHECK-FUSE: movk [[R]], #21572, lsl #16 -; CHECK-FUSE: movk [[R]], #8699, lsl #32 -; CHECK-FUSE: movk [[R]], #16393, lsl #48 -; CHECK-FUSE: fmov {{d[0-9]+}}, [[R]] +; CHECKDONT: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]] +; CHECKDONT-NEXT: ldr {{d[0-9]+}}, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}} +; CHECKFUSE: mov [[R:x[0-9]+]], #11544 +; CHECKFUSE: movk [[R]], #21572, lsl #16 +; CHECKFUSE: movk [[R]], #8699, lsl #32 +; CHECKFUSE: movk [[R]], #16393, lsl #48 +; CHECKFUSE: fmov {{d[0-9]+}}, [[R]] } diff --git a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll index f380b2d05d863..078c2b91af67b 100644 --- a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll +++ b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll @@ -96,7 +96,7 @@ entry: ; CHECK-NEXT: {{^[ \t]+b }} ; CHECK-NEXT: //NO_APP ; For direct branches, no mitigation is needed. -; ISDDSB-NOT: dsb sy +; ISBDSB-NOT: dsb sy ; SB-NOT: {{ sb$}} asm.fallthrough: ; preds = %entry @@ -192,7 +192,7 @@ entry: ; CHECK: .Lfunc_end } -; HARDEN-label: __llvm_slsblr_thunk_x0: +; HARDEN-LABEL: __llvm_slsblr_thunk_x0: ; HARDEN: mov x16, x0 ; HARDEN: br x16 ; ISBDSB-NEXT: dsb sy @@ -208,7 +208,7 @@ entry: ; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19 ; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19 ; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19,@function -; HARDEN-label: __llvm_slsblr_thunk_x19: +; HARDEN-LABEL: __llvm_slsblr_thunk_x19: ; HARDEN: mov x16, x19 ; HARDEN: br x16 ; ISBDSB-NEXT: dsb sy diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir index 66d2067b531a3..bfdb1763776b4 100644 --- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir +++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir @@ -12,7 +12,7 @@ # This test also checks that pairwise store STP is generated. -# CHECK-LABLE: test +# CHECK-LABEL: test # CHECK: bb.0: # CHECK-NEXT: liveins: $x0, $x17, $x18 # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64) diff --git a/llvm/test/CodeGen/AArch64/sve-calling-convention.ll b/llvm/test/CodeGen/AArch64/sve-calling-convention.ll index bfb750517cbf9..fd8258d9b718e 100644 --- a/llvm/test/CodeGen/AArch64/sve-calling-convention.ll +++ b/llvm/test/CodeGen/AArch64/sve-calling-convention.ll @@ -149,7 +149,7 @@ define [2 x ] @sve_signature_pred_2xv4i1([2 x } ; Test that a scalable predicate argument in [1 x ] type is assigned to two P registers. -; CHECK-LABLE: name: sve_signature_pred_1xv32i1 +; CHECK-LABEL: name: sve_signature_pred_1xv32i1 ; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p3 ; CHECK: [[RES0:%[0-9]+]]:ppr = COPY $p2 ; CHECK: $p0 = COPY [[RES0]] @@ -160,7 +160,7 @@ define [1 x ] @sve_signature_pred_1xv32i1([1 x ] type is assigned to four P registers. -; CHECK-LABLE: name: sve_signature_pred_2xv32i1 +; CHECK-LABEL: name: sve_signature_pred_2xv32i1 ; CHECK: [[RES3:%[0-9]+]]:ppr = COPY $p3 ; CHECK: [[RES2:%[0-9]+]]:ppr = COPY $p2 ; CHECK: [[RES1:%[0-9]+]]:ppr = COPY $p1 diff --git a/llvm/test/CodeGen/AArch64/swift-error.ll b/llvm/test/CodeGen/AArch64/swift-error.ll index 19671ce5a1d9b..b2ccfd2cc7f94 100644 --- a/llvm/test/CodeGen/AArch64/swift-error.ll +++ b/llvm/test/CodeGen/AArch64/swift-error.ll @@ -10,7 +10,7 @@ entry: ret void } -; CHEECK-LABEL: g +; CHECK-LABEL: g ; CHECK: str x30, [sp, #-16]! ; CHECK: bl f ; CHECK: ldr x30, [sp], #16 diff --git a/llvm/test/CodeGen/AMDGPU/and.ll b/llvm/test/CodeGen/AMDGPU/and.ll index d6137597293f6..b1a74f4693325 100644 --- a/llvm/test/CodeGen/AMDGPU/and.ll +++ b/llvm/test/CodeGen/AMDGPU/and.ll @@ -198,9 +198,9 @@ define amdgpu_kernel void @s_and_constant_i64(ptr addrspace(1) %out, i64 %a) { } ; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64: -; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}} -; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}} -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[KLO]]:[[KHI]]] +; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}} +; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}} +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[KLO]]:[[KHI]]] define amdgpu_kernel void @s_and_multi_use_constant_i64(ptr addrspace(1) %out, i64 %a, i64 %b) { %and0 = and i64 %a, 549756338176 %and1 = and i64 %b, 549756338176 @@ -398,7 +398,7 @@ define amdgpu_kernel void @s_and_inline_imm_1_i64(ptr addrspace(1) %out, ptr add } ; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64 -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 ; SI: s_load_dword ; SI: s_load_dwordx2 @@ -413,7 +413,7 @@ define amdgpu_kernel void @s_and_inline_imm_1.0_i64(ptr addrspace(1) %out, ptr a } ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64 -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 ; SI: s_load_dword ; SI: s_load_dwordx2 @@ -428,7 +428,7 @@ define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(ptr addrspace(1) %out, p } ; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64 -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 ; SI: s_load_dword ; SI: s_load_dwordx2 @@ -443,7 +443,7 @@ define amdgpu_kernel void @s_and_inline_imm_0.5_i64(ptr addrspace(1) %out, ptr a } ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64: -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 ; SI: s_load_dword ; SI: s_load_dwordx2 @@ -484,7 +484,7 @@ define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(ptr addrspace(1) %out, p } ; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64: -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 ; SI: s_load_dword ; SI: s_load_dwordx2 @@ -499,7 +499,7 @@ define amdgpu_kernel void @s_and_inline_imm_4.0_i64(ptr addrspace(1) %out, ptr a } ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64: -; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 +; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 ; SI: s_load_dword ; SI: s_load_dwordx2 diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll index ed045107d354d..0b64d25426035 100644 --- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll +++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll @@ -49,7 +49,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 { ; features when the number of registers is frozen), this ends up using ; more than expected. -; XALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs: +; ALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs: ; XTOSGPR: SGPRBlocks: 1 ; XTOSGPR: NumSGPRsForWavesPerEU: 16 @@ -87,13 +87,13 @@ define amdgpu_kernel void @max_10_sgprs() #0 { ;} ; The following test is commented out for now; http://llvm.org/PR31230 -; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}} +; COM: ALL-LABEL: max_12_sgprs_12_input_sgprs{{$}} ; ; Make sure copies for input buffer are not clobbered. This requires ; ; swapping the order the registers are copied from what normally ; ; happens. -; XALL: SGPRBlocks: 2 -; XALL: NumSGPRsForWavesPerEU: 18 +; COM: ALL: SGPRBlocks: 2 +; COM: ALL: NumSGPRsForWavesPerEU: 18 ;define amdgpu_kernel void @max_12_sgprs_12_input_sgprs(ptr addrspace(1) %out1, ; ptr addrspace(1) %out2, ; ptr addrspace(1) %out3, diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll index 5e6f377da28e1..53a4a998c0178 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll @@ -557,16 +557,16 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 } ; GCN-LABEL: {{^}}func_call_too_many_args_use_workitem_id_x_byval: -; FIXED-ABI-NOT: v31 +; FIXEDABI-NOT: v31 ; FIXEDABI: v_mov_b32_e32 [[K0:v[0-9]+]], 0x3e7{{$}} ; FIXEDABI: buffer_store_dword [[K0]], off, s[0:3], s33{{$}} ; FIXEDABI: v_mov_b32_e32 [[K1:v[0-9]+]], 0x140{{$}} ; FIXEDABI: buffer_store_dword [[K1]], off, s[0:3], s32{{$}} ; FIXEDABI: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s33{{$}} -; FIXED-ABI-NOT: v31 +; FIXEDABI-NOT: v31 ; FIXEDABI: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}} -; FIXED-ABI-NOT: v31 +; FIXEDABI-NOT: v31 ; FIXEDABI: s_swappc_b64 define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { %alloca = alloca i32, align 4, addrspace(5) diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll index 15ebdd70ae881..5ba9569943a77 100644 --- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll +++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll @@ -41,8 +41,8 @@ entry: } ; FIXME: This is treated like a kernel -; XGCN-LABEL: {{^}}func: -; XGCN: s_endpgm +; COM: GCN-LABEL: {{^}}func: +; COM: GCN: s_endpgm ; define spir_func void @func(ptr addrspace(1) %out) { ; entry: ; store i32 0, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll index 49f9f695409b1..d0ab8b3db42d8 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll @@ -632,7 +632,7 @@ done: ; OPT-LABEL: @test_sink_global_small_min_scratch_global_offset( ; OPT-SICIVI: %in.gep = getelementptr i8, ptr addrspace(1) %in, i64 -4096 -; OPT-SICIV: br +; OPT-SICIVI: br ; OPT-SICIVI: %tmp1 = load i8, ptr addrspace(1) %in.gep ; OPT-GFX9: br diff --git a/llvm/test/CodeGen/AMDGPU/commute-compares.ll b/llvm/test/CodeGen/AMDGPU/commute-compares.ll index d94e75c8c8e22..a72856ec7efa1 100644 --- a/llvm/test/CodeGen/AMDGPU/commute-compares.ll +++ b/llvm/test/CodeGen/AMDGPU/commute-compares.ll @@ -697,7 +697,7 @@ define amdgpu_kernel void @commute_uno_2.0_f64(ptr addrspace(1) %out, ptr addrsp ; SIShrinkInstructions, this was using the VOP3 compare. ; GCN-LABEL: {{^}}commute_frameindex: -; XGCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} +; COM: GCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}} ; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]] diff --git a/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll b/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll index d4bafa12af129..9aa00fb058335 100644 --- a/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll +++ b/llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll @@ -32,7 +32,7 @@ define amdgpu_kernel void @cvt_rpi_i32_f32_fabs(ptr addrspace(1) %out, float %x) ; FIXME: This doesn't work because it forms fsub 0.5, x ; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg: -; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}} +; COM: SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}} ; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}} ; SI-SAFE-NOT: v_cvt_flr_i32_f32 ; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]] @@ -49,7 +49,7 @@ define amdgpu_kernel void @cvt_rpi_i32_f32_fneg(ptr addrspace(1) %out, float %x) ; FIXME: This doesn't work for same reason as above ; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg: ; SI-SAFE-NOT: v_cvt_rpi_i32_f32 -; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}| +; COM: SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}| ; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}| ; SI-SAFE-NOT: v_cvt_flr_i32_f32 diff --git a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll index 49486adda6f2e..d67af1a89b679 100644 --- a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll +++ b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll @@ -28,7 +28,7 @@ define amdgpu_kernel void @test_f64_denormals(ptr addrspace(1) %out0, ptr addrsp } ; GCN-LABEL: {{^}}test_f32_denormals: -; GCNL: FloatMode: 48 +; GCN: FloatMode: 48 ; GCN: IeeeMode: 1 define amdgpu_kernel void @test_f32_denormals(ptr addrspace(1) %out0, ptr addrspace(1) %out1) #3 { store float 0.0, ptr addrspace(1) %out0 diff --git a/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll b/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll index 2ac5891773d73..eeafdae481e3a 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll @@ -114,7 +114,7 @@ define amdgpu_ps float @select_fneg_a_or_q_cmp_ogt_a_neg1(float %a, float %b) #0 ; VI-SAFE: v_cmp_gt_f32_e32 vcc, -1.0, v0 ; VI-SAFE-NEXT: v_cndmask_b32_e64 v0, 1.0, -v0, vcc -; VI-NANN: v_max_f32_e64 v0, -v0, 1.0 +; VI-NNAN: v_max_f32_e64 v0, -v0, 1.0 define amdgpu_ps float @select_fneg_a_or_q_cmp_olt_a_neg1(float %a, float %b) #0 { %fneg.a = fneg float %a %cmp.a = fcmp olt float %a, -1.0 diff --git a/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll b/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll index 945973b277289..1ed8ef31ae683 100644 --- a/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll @@ -455,7 +455,7 @@ define amdgpu_kernel void @mad_sub_fabs_f32(ptr addrspace(1) noalias nocapture % ; GCN: {{buffer|flat|global}}_load_dword [[REGB:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_dword [[REGC:v[0-9]+]] ; GCN-FLUSH-MAD: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| -; GCN-FLUSH-FMA: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| +; GCN-FLUSH-FMAC:v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| ; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| diff --git a/llvm/test/CodeGen/AMDGPU/internalize.ll b/llvm/test/CodeGen/AMDGPU/internalize.ll index 6b2a4d5fc328b..f7d9c4c32ad33 100644 --- a/llvm/test/CodeGen/AMDGPU/internalize.ll +++ b/llvm/test/CodeGen/AMDGPU/internalize.ll @@ -11,7 +11,7 @@ @gvar_used = addrspace(1) global i32 undef, align 4 ; OPT: define internal fastcc void @func_used_noinline( -; OPT-NONE: define fastcc void @func_used_noinline( +; OPTNONE: define fastcc void @func_used_noinline( define fastcc void @func_used_noinline(ptr addrspace(1) %out, i32 %tid) #1 { entry: store volatile i32 %tid, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll index 27fb4e5f965c9..edff0a16bd813 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll @@ -303,7 +303,7 @@ define amdgpu_kernel void @v_test_class_full_mask_f64(ptr addrspace(1) %out, ptr } ; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f64: -; XSI: v_cmp_class_f64_e32 vcc, 1.0, +; SI: v_cmp_class_f64_e32 vcc, 1.0, ; SI: v_cmp_class_f64_e32 vcc, ; SI: s_endpgm define amdgpu_kernel void @test_class_inline_imm_constant_dynamic_mask_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll index fb44d11bc30c0..547e92651c211 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll @@ -30,7 +30,7 @@ entry: ; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_no_clamp ; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GFX10: v_dot4c_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}} -; GF11: v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}} neg_lo:[1,1,0]{{$}} +; GFX11: v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}} neg_lo:[1,1,0]{{$}} define amdgpu_kernel void @test_llvm_amdgcn_sdot4_no_clamp( ptr addrspace(1) %r, ptr addrspace(1) %a, diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll index 6ed99f7074b64..958cc06c6c881 100644 --- a/llvm/test/CodeGen/AMDGPU/load-global-i8.ll +++ b/llvm/test/CodeGen/AMDGPU/load-global-i8.ll @@ -728,7 +728,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out ret void } -; XFUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i64: +; FUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i64: ; define amdgpu_kernel void @global_zextload_v64i8_to_v64i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(1) %in ; %ext = zext <64 x i8> %load to <64 x i64> @@ -736,7 +736,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i64(ptr addrspace(1) %out ; ret void ; } -; XFUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i64: +; FUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i64: ; define amdgpu_kernel void @global_sextload_v64i8_to_v64i64(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(1) %in ; %ext = sext <64 x i8> %load to <64 x i64> @@ -960,7 +960,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i16(ptr addrspace(1) %out ret void } -; XFUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i16: +; FUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i16: ; define amdgpu_kernel void @global_zextload_v64i8_to_v64i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(1) %in ; %ext = zext <64 x i8> %load to <64 x i16> @@ -968,7 +968,7 @@ define amdgpu_kernel void @global_sextload_v32i8_to_v32i16(ptr addrspace(1) %out ; ret void ; } -; XFUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i16: +; FUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i16: ; define amdgpu_kernel void @global_sextload_v64i8_to_v64i16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(1) %in ; %ext = sext <64 x i8> %load to <64 x i16> diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll index 1dd08c561b2ab..37fee453c4aa4 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i16.ll @@ -931,7 +931,7 @@ define amdgpu_kernel void @local_sextload_v32i16_to_v32i64(ptr addrspace(3) %out ret void } -; ; XFUNC-LABEL: {{^}}local_zextload_v64i16_to_v64i64: +; FUNC-LABEL: {{^}}local_zextload_v64i16_to_v64i64: ; define amdgpu_kernel void @local_zextload_v64i16_to_v64i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 { ; %load = load <64 x i16>, ptr addrspace(3) %in ; %ext = zext <64 x i16> %load to <64 x i64> @@ -939,7 +939,7 @@ define amdgpu_kernel void @local_sextload_v32i16_to_v32i64(ptr addrspace(3) %out ; ret void ; } -; ; XFUNC-LABEL: {{^}}local_sextload_v64i16_to_v64i64: +; FUNC-LABEL: {{^}}local_sextload_v64i16_to_v64i64: ; define amdgpu_kernel void @local_sextload_v64i16_to_v64i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 { ; %load = load <64 x i16>, ptr addrspace(3) %in ; %ext = sext <64 x i16> %load to <64 x i64> diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i8.ll b/llvm/test/CodeGen/AMDGPU/load-local-i8.ll index a2e55ce06b525..6205544c6c57f 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i8.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i8.ll @@ -670,7 +670,7 @@ define amdgpu_kernel void @local_sextload_v32i8_to_v32i64(ptr addrspace(3) %out, ret void } -; XFUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i64: +; FUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i64: ; define amdgpu_kernel void @local_zextload_v64i8_to_v64i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(3) %in ; %ext = zext <64 x i8> %load to <64 x i64> @@ -678,7 +678,7 @@ define amdgpu_kernel void @local_sextload_v32i8_to_v32i64(ptr addrspace(3) %out, ; ret void ; } -; XFUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i64: +; FUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i64: ; define amdgpu_kernel void @local_sextload_v64i8_to_v64i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(3) %in ; %ext = sext <64 x i8> %load to <64 x i64> @@ -1010,7 +1010,7 @@ define amdgpu_kernel void @local_sextload_v32i8_to_v32i16(ptr addrspace(3) %out, ret void } -; XFUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i16: +; FUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i16: ; define amdgpu_kernel void @local_zextload_v64i8_to_v64i16(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(3) %in ; %ext = zext <64 x i8> %load to <64 x i16> @@ -1018,7 +1018,7 @@ define amdgpu_kernel void @local_sextload_v32i8_to_v32i16(ptr addrspace(3) %out, ; ret void ; } -; XFUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i16: +; FUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i16: ; define amdgpu_kernel void @local_sextload_v64i8_to_v64i16(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 { ; %load = load <64 x i8>, ptr addrspace(3) %in ; %ext = sext <64 x i8> %load to <64 x i16> diff --git a/llvm/test/CodeGen/AMDGPU/local-atomics.ll b/llvm/test/CodeGen/AMDGPU/local-atomics.ll index b5f81f088fe7a..8a0b9a294c621 100644 --- a/llvm/test/CodeGen/AMDGPU/local-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/local-atomics.ll @@ -291,7 +291,7 @@ define amdgpu_kernel void @lds_atomic_xor_ret_i32_offset(ptr addrspace(1) %out, } ; FIXME: There is no atomic nand instr -; XFUNC-LABEL: {{^}}lds_atomic_nand_ret_i32:uction, so we somehow need to expand this. +; COM: FUNC-LABEL: {{^}}lds_atomic_nand_ret_i32:uction, so we somehow need to expand this. ; define amdgpu_kernel void @lds_atomic_nand_ret_i32(ptr addrspace(1) %out, ptr addrspace(3) %ptr) nounwind { ; %result = atomicrmw nand ptr addrspace(3) %ptr, i32 4 seq_cst ; store i32 %result, ptr addrspace(1) %out, align 4 @@ -631,7 +631,7 @@ define amdgpu_kernel void @lds_atomic_xor_noret_i32_offset(ptr addrspace(3) %ptr } ; FIXME: There is no atomic nand instr -; XFUNC-LABEL: {{^}}lds_atomic_nand_noret_i32:uction, so we somehow need to expand this. +; COM: FUNC-LABEL: {{^}}lds_atomic_nand_noret_i32:uction, so we somehow need to expand this. ; define amdgpu_kernel void @lds_atomic_nand_noret_i32(ptr addrspace(3) %ptr) nounwind { ; %result = atomicrmw nand ptr addrspace(3) %ptr, i32 4 seq_cst ; ret void diff --git a/llvm/test/CodeGen/AMDGPU/local-atomics64.ll b/llvm/test/CodeGen/AMDGPU/local-atomics64.ll index e6ce93986b0a4..a1f8a43cb4a5e 100644 --- a/llvm/test/CodeGen/AMDGPU/local-atomics64.ll +++ b/llvm/test/CodeGen/AMDGPU/local-atomics64.ll @@ -241,7 +241,7 @@ define amdgpu_kernel void @lds_atomic_xor_ret_i64_offset(ptr addrspace(1) %out, } ; FIXME: There is no atomic nand instr -; XGCN-LABEL: {{^}}lds_atomic_nand_ret_i64:uction, so we somehow need to expand this. +; COM: GCN-LABEL: {{^}}lds_atomic_nand_ret_i64:uction, so we somehow need to expand this. ; define amdgpu_kernel void @lds_atomic_nand_ret_i64(ptr addrspace(1) %out, ptr addrspace(3) %ptr) nounwind { ; %result = atomicrmw nand ptr addrspace(3) %ptr, i32 4 seq_cst ; store i64 %result, ptr addrspace(1) %out, align 8 @@ -542,7 +542,7 @@ define amdgpu_kernel void @lds_atomic_xor_noret_i64_offset(ptr addrspace(3) %ptr } ; FIXME: There is no atomic nand instr -; XGCN-LABEL: {{^}}lds_atomic_nand_noret_i64:uction, so we somehow need to expand this. +; COM: GCN-LABEL: {{^}}lds_atomic_nand_noret_i64:uction, so we somehow need to expand this. ; define amdgpu_kernel void @lds_atomic_nand_noret_i64(ptr addrspace(3) %ptr) nounwind { ; %result = atomicrmw nand ptr addrspace(3) %ptr, i32 4 seq_cst ; ret void diff --git a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll index e7855a1137a4a..0707f845f8e00 100644 --- a/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll +++ b/llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.ll @@ -8,8 +8,8 @@ ; to follow a base one. ; GCN-LABEL: {{^}}out_of_order_merge: -; GCN-COUNT2: ds_read2_b64 -; GCN-COUNT3: ds_write_b64 +; GCN-COUNT-2: ds_read2_b64 +; GCN-COUNT-3: ds_write_b64 define amdgpu_kernel void @out_of_order_merge() { entry: %gep2 = getelementptr inbounds [96 x double], ptr addrspace(3) @Ldisp, i32 0, i32 1 diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll index d5aeff7e819dd..95c993b534f40 100644 --- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll @@ -116,100 +116,100 @@ exit: ; Check that we do not use 32 temp vgprs, but rotate 3 vgprs only. ; 3 vgprs are needed to avoid wait states between writes. -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x42f80000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x42fa0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x42fc0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x42fe0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43000000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43010000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43020000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43030000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43040000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43050000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43060000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43070000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43080000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43090000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x430a0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x430b0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x430c0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x430d0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x430e0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x430f0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43100000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43110000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43120000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43130000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43140000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43150000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43160000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43170000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43180000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x43190000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 -; GFX-908: v_mov_b32_e32 v0, 0x431a0000 -; GFX-908: s_nop 1 -; GFX-908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x42f80000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x42fa0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x42fc0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x42fe0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43000000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43010000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43020000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43030000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43040000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43050000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43060000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43070000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43080000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43090000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x430a0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x430b0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x430c0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x430d0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x430e0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x430f0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43100000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43110000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43120000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43130000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43140000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43150000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43160000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43170000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43180000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x43190000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 +; GFX908: v_mov_b32_e32 v0, 0x431a0000 +; GFX908: s_nop 1 +; GFX908: v_accvgpr_write_b32 {{[0-9]+}}, v0 ; FIXME: Constant is now in VGPR instead of SGPR. diff --git a/llvm/test/CodeGen/AMDGPU/reduction.ll b/llvm/test/CodeGen/AMDGPU/reduction.ll index 53a036b617725..ec2c9b370dc9e 100644 --- a/llvm/test/CodeGen/AMDGPU/reduction.ll +++ b/llvm/test/CodeGen/AMDGPU/reduction.ll @@ -488,14 +488,14 @@ entry: ; directly from the IR to avoid unnecessary quieting. ; GCN-LABEL: {{^}}reduction_fast_max_pattern_v4f16: -; XGFX9: v_pk_max_f16 [[MAX:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}} -; XGFX9-NEXT: v_max_f16_sdwa v{{[0-9]+}}, [[MAX]], [[MAX]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; COM: GFX9: v_pk_max_f16 [[MAX:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}} +; COM: GFX9-NEXT: v_max_f16_sdwa v{{[0-9]+}}, [[MAX]], [[MAX]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; XVI: s_waitcnt -; XVI-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; XVI-NEXT: v_max_f16_e32 v0, v0, v1 -; XVI-NEXT: v_max_f16_e32 v0, v0, v2 -; XVI-NEXT: s_setpc_b64 +; COM: VI: s_waitcnt +; COM: VI-NEXT: v_max_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; COM: VI-NEXT: v_max_f16_e32 v0, v0, v1 +; COM: VI-NEXT: v_max_f16_e32 v0, v0, v2 +; COM: VI-NEXT: s_setpc_b64 ; GFX9: s_waitcnt ; GFX9-NEXT: v_pk_max_f16 [[CANON1:v[0-9]+]], v1, v1 @@ -527,14 +527,14 @@ entry: ; directly from the IR to avoid unnecessary quieting. ; GCN-LABEL: {{^}}reduction_fast_min_pattern_v4f16: -; XGFX9: v_pk_min_f16 [[MIN:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}} -; XGFX9-NEXT: v_min_f16_sdwa v{{[0-9]+}}, [[MIN]], [[MIN]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 - -; XVI: s_waitcnt -; XVI-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; XVI-NEXT: v_min_f16_e32 v0, v0, v1 -; XVI-NEXT: v_min_f16_e32 v0, v0, v2 -; XVI-NEXT: s_setpc_b64 +; COM: GFX9: v_pk_min_f16 [[MIN:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}{{$}} +; COM: GFX9-NEXT: v_min_f16_sdwa v{{[0-9]+}}, [[MIN]], [[MIN]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 + +; COM: VI: s_waitcnt +; COM: VI-NEXT: v_min_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; COM: VI-NEXT: v_min_f16_e32 v0, v0, v1 +; COM: VI-NEXT: v_min_f16_e32 v0, v0, v2 +; COM: VI-NEXT: s_setpc_b64 ; GFX9: s_waitcnt ; GFX9-NEXT: v_pk_max_f16 [[CANON1:v[0-9]+]], v1, v1 diff --git a/llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll b/llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll index a0380c82d9aaf..05532431f495b 100644 --- a/llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll +++ b/llvm/test/CodeGen/AMDGPU/remove-incompatible-functions.ll @@ -375,13 +375,13 @@ define void @caller(ptr %out, ptr %in, i64 %a, i64 %b, i64 %c) { ; GFX8: call void null( ; GFX9: call void @needs_gfx9_insts( ; GFX10: call void @needs_gfx9_insts( - ; GFX111: call void @needs_gfx9_insts(c + ; GFX11: call void @needs_gfx9_insts(c call void @needs_gfx9_insts(ptr %out, ptr %in, i64 %a, i64 %b, i64 %c) ; GFX7: call void null( ; GFX8: call void null( ; GFX9: call void null( ; GFX10: call void @needs_gfx10_insts( - ; GFX111: call void @needs_gfx10_insts( + ; GFX11: call void @needs_gfx10_insts( call void @needs_gfx10_insts(ptr %out, ptr %in, i64 %a, i64 %b, i64 %c) ; GFX7: call void null( ; GFX8: call void null( diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll b/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll index ffa808b459226..e95aee2492dcc 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/complex_dot_prod.ll @@ -45,7 +45,7 @@ define dso_local arm_aapcscc void @complex_dot_prod(ptr nocapture readonly %pSrc ; CHECK-LLC-NEXT: str r7, [r2] ; CHECK-LLC-NEXT: str r0, [r3] ; CHECK-LLC-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} -; CHECK-LCC: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} +; CHECK-LLC: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} ; ; CHECK-OPT-LABEL: @complex_dot_prod( ; CHECK-OPT-NEXT: entry: diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll index 9570c70676dbb..374bd4d1e0e8e 100644 --- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll +++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll @@ -5,7 +5,7 @@ %struct.float16x8x2_t = type { [2 x <8 x half>] } define dso_local <4 x half> @test_vabs_f16(<4 x half> %a) { -; CHECKLABEL: test_vabs_f16: +; CHECK-LABEL: test_vabs_f16: ; CHECK-LABEL: test_vabs_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vabs.f16 d0, d0 @@ -16,7 +16,7 @@ entry: } define dso_local <8 x half> @test_vabsq_f16(<8 x half> %a) { -; CHECKLABEL: test_vabsq_f16: +; CHECK-LABEL: test_vabsq_f16: ; CHECK-LABEL: test_vabsq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vabs.f16 q0, q0 @@ -27,7 +27,7 @@ entry: } define dso_local <4 x i16> @test_vceqz_f16(<4 x half> %a) { -; CHECKLABEL: test_vceqz_f16: +; CHECK-LABEL: test_vceqz_f16: ; CHECK-LABEL: test_vceqz_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vceq.f16 d0, d0, #0 @@ -39,7 +39,7 @@ entry: } define dso_local <8 x i16> @test_vceqzq_f16(<8 x half> %a) { -; CHECKLABEL: test_vceqzq_f16: +; CHECK-LABEL: test_vceqzq_f16: ; CHECK-LABEL: test_vceqzq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vceq.f16 q0, q0, #0 @@ -51,7 +51,7 @@ entry: } define dso_local <4 x i16> @test_vcgez_f16(<4 x half> %a) { -; CHECKLABEL: test_vcgez_f16: +; CHECK-LABEL: test_vcgez_f16: ; CHECK-LABEL: test_vcgez_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcge.f16 d0, d0, #0 @@ -63,7 +63,7 @@ entry: } define dso_local <8 x i16> @test_vcgezq_f16(<8 x half> %a) { -; CHECKLABEL: test_vcgezq_f16: +; CHECK-LABEL: test_vcgezq_f16: ; CHECK-LABEL: test_vcgezq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcge.f16 q0, q0, #0 @@ -75,7 +75,7 @@ entry: } define dso_local <4 x i16> @test_vcgtz_f16(<4 x half> %a) { -; CHECKLABEL: test_vcgtz_f16: +; CHECK-LABEL: test_vcgtz_f16: ; CHECK-LABEL: test_vcgtz_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcgt.f16 d0, d0, #0 @@ -87,7 +87,7 @@ entry: } define dso_local <8 x i16> @test_vcgtzq_f16(<8 x half> %a) { -; CHECKLABEL: test_vcgtzq_f16: +; CHECK-LABEL: test_vcgtzq_f16: ; CHECK-LABEL: test_vcgtzq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcgt.f16 q0, q0, #0 @@ -99,7 +99,7 @@ entry: } define dso_local <4 x i16> @test_vclez_f16(<4 x half> %a) { -; CHECKLABEL: test_vclez_f16: +; CHECK-LABEL: test_vclez_f16: ; CHECK-LABEL: test_vclez_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcle.f16 d0, d0, #0 @@ -111,7 +111,7 @@ entry: } define dso_local <8 x i16> @test_vclezq_f16(<8 x half> %a) { -; CHECKLABEL: test_vclezq_f16: +; CHECK-LABEL: test_vclezq_f16: ; CHECK-LABEL: test_vclezq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcle.f16 q0, q0, #0 @@ -123,7 +123,7 @@ entry: } define dso_local <4 x i16> @test_vcltz_f16(<4 x half> %a) { -; CHECKLABEL: test_vcltz_f16: +; CHECK-LABEL: test_vcltz_f16: ; CHECK-LABEL: test_vcltz_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vclt.f16 d0, d0, #0 @@ -135,7 +135,7 @@ entry: } define dso_local <8 x i16> @test_vcltzq_f16(<8 x half> %a) { -; CHECKLABEL: test_vcltzq_f16: +; CHECK-LABEL: test_vcltzq_f16: ; CHECK-LABEL: test_vcltzq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vclt.f16 q0, q0, #0 @@ -377,7 +377,7 @@ entry: } define dso_local <4 x half> @test_vneg_f16(<4 x half> %a) { -; CHECKLABEL: test_vneg_f16: +; CHECK-LABEL: test_vneg_f16: ; CHECK-LABEL: test_vneg_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vneg.f16 d0, d0 @@ -388,7 +388,7 @@ entry: } define dso_local <8 x half> @test_vnegq_f16(<8 x half> %a) { -; CHECKLABEL: test_vnegq_f16: +; CHECK-LABEL: test_vnegq_f16: ; CHECK-LABEL: test_vnegq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vneg.f16 q0, q0 @@ -399,7 +399,7 @@ entry: } define dso_local <4 x half> @test_vrecpe_f16(<4 x half> %a) { -; CHECKLABEL: test_vrecpe_f16: +; CHECK-LABEL: test_vrecpe_f16: ; CHECK-LABEL: test_vrecpe_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrecpe.f16 d0, d0 @@ -410,7 +410,7 @@ entry: } define dso_local <8 x half> @test_vrecpeq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrecpeq_f16: +; CHECK-LABEL: test_vrecpeq_f16: ; CHECK-LABEL: test_vrecpeq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrecpe.f16 q0, q0 @@ -421,7 +421,7 @@ entry: } define dso_local <4 x half> @test_vrnd_f16(<4 x half> %a) { -; CHECKLABEL: test_vrnd_f16: +; CHECK-LABEL: test_vrnd_f16: ; CHECK-LABEL: test_vrnd_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintz.f16 d0, d0 @@ -432,7 +432,7 @@ entry: } define dso_local <8 x half> @test_vrndq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrndq_f16: +; CHECK-LABEL: test_vrndq_f16: ; CHECK-LABEL: test_vrndq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintz.f16 q0, q0 @@ -443,7 +443,7 @@ entry: } define dso_local <4 x half> @test_vrnda_f16(<4 x half> %a) { -; CHECKLABEL: test_vrnda_f16: +; CHECK-LABEL: test_vrnda_f16: ; CHECK-LABEL: test_vrnda_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrinta.f16 d0, d0 @@ -454,7 +454,7 @@ entry: } define dso_local <8 x half> @test_vrndaq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrndaq_f16: +; CHECK-LABEL: test_vrndaq_f16: ; CHECK-LABEL: test_vrndaq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrinta.f16 q0, q0 @@ -465,7 +465,7 @@ entry: } define dso_local <4 x half> @test_vrndm_f16(<4 x half> %a) { -; CHECKLABEL: test_vrndm_f16: +; CHECK-LABEL: test_vrndm_f16: ; CHECK-LABEL: test_vrndm_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintm.f16 d0, d0 @@ -476,7 +476,7 @@ entry: } define dso_local <8 x half> @test_vrndmq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrndmq_f16: +; CHECK-LABEL: test_vrndmq_f16: ; CHECK-LABEL: test_vrndmq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintm.f16 q0, q0 @@ -487,7 +487,7 @@ entry: } define dso_local <4 x half> @test_vrndn_f16(<4 x half> %a) { -; CHECKLABEL: test_vrndn_f16: +; CHECK-LABEL: test_vrndn_f16: ; CHECK-LABEL: test_vrndn_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintn.f16 d0, d0 @@ -498,7 +498,7 @@ entry: } define dso_local <8 x half> @test_vrndnq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrndnq_f16: +; CHECK-LABEL: test_vrndnq_f16: ; CHECK-LABEL: test_vrndnq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintn.f16 q0, q0 @@ -509,7 +509,7 @@ entry: } define dso_local <4 x half> @test_vrndp_f16(<4 x half> %a) { -; CHECKLABEL: test_vrndp_f16: +; CHECK-LABEL: test_vrndp_f16: ; CHECK-LABEL: test_vrndp_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintp.f16 d0, d0 @@ -520,7 +520,7 @@ entry: } define dso_local <8 x half> @test_vrndpq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrndpq_f16: +; CHECK-LABEL: test_vrndpq_f16: ; CHECK-LABEL: test_vrndpq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintp.f16 q0, q0 @@ -531,7 +531,7 @@ entry: } define dso_local <4 x half> @test_vrndx_f16(<4 x half> %a) { -; CHECKLABEL: test_vrndx_f16: +; CHECK-LABEL: test_vrndx_f16: ; CHECK-LABEL: test_vrndx_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintx.f16 d0, d0 @@ -542,7 +542,7 @@ entry: } define dso_local <8 x half> @test_vrndxq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrndxq_f16: +; CHECK-LABEL: test_vrndxq_f16: ; CHECK-LABEL: test_vrndxq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrintx.f16 q0, q0 @@ -553,7 +553,7 @@ entry: } define dso_local <4 x half> @test_vrsqrte_f16(<4 x half> %a) { -; CHECKLABEL: test_vrsqrte_f16: +; CHECK-LABEL: test_vrsqrte_f16: ; CHECK-LABEL: test_vrsqrte_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrsqrte.f16 d0, d0 @@ -564,7 +564,7 @@ entry: } define dso_local <8 x half> @test_vrsqrteq_f16(<8 x half> %a) { -; CHECKLABEL: test_vrsqrteq_f16: +; CHECK-LABEL: test_vrsqrteq_f16: ; CHECK-LABEL: test_vrsqrteq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrsqrte.f16 q0, q0 @@ -575,7 +575,7 @@ entry: } define dso_local <4 x half> @test_vadd_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vadd_f16: +; CHECK-LABEL: test_vadd_f16: ; CHECK-LABEL: test_vadd_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vadd.f16 d0, d0, d1 @@ -586,7 +586,7 @@ entry: } define dso_local <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vaddq_f16: +; CHECK-LABEL: test_vaddq_f16: ; CHECK-LABEL: test_vaddq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vadd.f16 q0, q0, q1 @@ -597,7 +597,7 @@ entry: } define dso_local <4 x half> @test_vabd_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vabd_f16: +; CHECK-LABEL: test_vabd_f16: ; CHECK-LABEL: test_vabd_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vabd.f16 d0, d0, d1 @@ -608,7 +608,7 @@ entry: } define dso_local <8 x half> @test_vabdq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vabdq_f16: +; CHECK-LABEL: test_vabdq_f16: ; CHECK-LABEL: test_vabdq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vabd.f16 q0, q0, q1 @@ -619,7 +619,7 @@ entry: } define dso_local <4 x i16> @test_vcage_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vcage_f16: +; CHECK-LABEL: test_vcage_f16: ; CHECK-LABEL: test_vcage_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vacge.f16 d0, d0, d1 @@ -630,7 +630,7 @@ entry: } define dso_local <8 x i16> @test_vcageq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vcageq_f16: +; CHECK-LABEL: test_vcageq_f16: ; CHECK-LABEL: test_vcageq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vacge.f16 q0, q0, q1 @@ -661,7 +661,7 @@ entry: } define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vcale_f16: +; CHECK-LABEL: test_vcale_f16: ; CHECK-LABEL: test_vcale_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vacge.f16 d0, d1, d0 @@ -672,7 +672,7 @@ entry: } define dso_local <8 x i16> @test_vcaleq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vcaleq_f16: +; CHECK-LABEL: test_vcaleq_f16: ; CHECK-LABEL: test_vcaleq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vacge.f16 q0, q1, q0 @@ -683,7 +683,7 @@ entry: } define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vceq_f16: +; CHECK-LABEL: test_vceq_f16: ; CHECK-LABEL: test_vceq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vceq.f16 d0, d0, d1 @@ -695,7 +695,7 @@ entry: } define dso_local <8 x i16> @test_vceqq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vceqq_f16: +; CHECK-LABEL: test_vceqq_f16: ; CHECK-LABEL: test_vceqq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vceq.f16 q0, q0, q1 @@ -707,7 +707,7 @@ entry: } define dso_local <4 x i16> @test_vcge_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vcge_f16: +; CHECK-LABEL: test_vcge_f16: ; CHECK-LABEL: test_vcge_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcge.f16 d0, d0, d1 @@ -719,7 +719,7 @@ entry: } define dso_local <8 x i16> @test_vcgeq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vcgeq_f16: +; CHECK-LABEL: test_vcgeq_f16: ; CHECK-LABEL: test_vcgeq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcge.f16 q0, q0, q1 @@ -731,7 +731,7 @@ entry: } define dso_local <4 x i16> @test_vcgt_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vcgt_f16: +; CHECK-LABEL: test_vcgt_f16: ; CHECK-LABEL: test_vcgt_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcgt.f16 d0, d0, d1 @@ -743,7 +743,7 @@ entry: } define dso_local <8 x i16> @test_vcgtq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vcgtq_f16: +; CHECK-LABEL: test_vcgtq_f16: ; CHECK-LABEL: test_vcgtq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcgt.f16 q0, q0, q1 @@ -755,7 +755,7 @@ entry: } define dso_local <4 x i16> @test_vcle_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vcle_f16: +; CHECK-LABEL: test_vcle_f16: ; CHECK-LABEL: test_vcle_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcge.f16 d0, d1, d0 @@ -767,7 +767,7 @@ entry: } define dso_local <8 x i16> @test_vcleq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vcleq_f16: +; CHECK-LABEL: test_vcleq_f16: ; CHECK-LABEL: test_vcleq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcge.f16 q0, q1, q0 @@ -779,7 +779,7 @@ entry: } define dso_local <4 x i16> @test_vclt_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vclt_f16: +; CHECK-LABEL: test_vclt_f16: ; CHECK-LABEL: test_vclt_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcgt.f16 d0, d1, d0 @@ -791,7 +791,7 @@ entry: } define dso_local <8 x i16> @test_vcltq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vcltq_f16: +; CHECK-LABEL: test_vcltq_f16: ; CHECK-LABEL: test_vcltq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcgt.f16 q0, q1, q0 @@ -803,7 +803,7 @@ entry: } define dso_local <4 x half> @test_vcvt_n_f16_s16(<4 x i16> %a) { -; CHECKLABEL: test_vcvt_n_f16_s16: +; CHECK-LABEL: test_vcvt_n_f16_s16: ; CHECK-LABEL: test_vcvt_n_f16_s16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.f16.s16 d0, d0, #2 @@ -816,7 +816,7 @@ entry: declare <4 x half> @llvm.arm.neon.vcvtfxs2fp.v4f16.v4i16(<4 x i16>, i32) #2 define dso_local <8 x half> @test_vcvtq_n_f16_s16(<8 x i16> %a) { -; CHECKLABEL: test_vcvtq_n_f16_s16: +; CHECK-LABEL: test_vcvtq_n_f16_s16: ; CHECK-LABEL: test_vcvtq_n_f16_s16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.f16.s16 q0, q0, #2 @@ -829,7 +829,7 @@ entry: declare <8 x half> @llvm.arm.neon.vcvtfxs2fp.v8f16.v8i16(<8 x i16>, i32) #2 define dso_local <4 x half> @test_vcvt_n_f16_u16(<4 x i16> %a) { -; CHECKLABEL: test_vcvt_n_f16_u16: +; CHECK-LABEL: test_vcvt_n_f16_u16: ; CHECK-LABEL: test_vcvt_n_f16_u16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.f16.u16 d0, d0, #2 @@ -842,7 +842,7 @@ entry: declare <4 x half> @llvm.arm.neon.vcvtfxu2fp.v4f16.v4i16(<4 x i16>, i32) #2 define dso_local <8 x half> @test_vcvtq_n_f16_u16(<8 x i16> %a) { -; CHECKLABEL: test_vcvtq_n_f16_u16: +; CHECK-LABEL: test_vcvtq_n_f16_u16: ; CHECK-LABEL: test_vcvtq_n_f16_u16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.f16.u16 q0, q0, #2 @@ -855,7 +855,7 @@ entry: declare <8 x half> @llvm.arm.neon.vcvtfxu2fp.v8f16.v8i16(<8 x i16>, i32) #2 define dso_local <4 x i16> @test_vcvt_n_s16_f16(<4 x half> %a) { -; CHECKLABEL: test_vcvt_n_s16_f16: +; CHECK-LABEL: test_vcvt_n_s16_f16: ; CHECK-LABEL: test_vcvt_n_s16_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.s16.f16 d0, d0, #2 @@ -868,7 +868,7 @@ entry: declare <4 x i16> @llvm.arm.neon.vcvtfp2fxs.v4i16.v4f16(<4 x half>, i32) #2 define dso_local <8 x i16> @test_vcvtq_n_s16_f16(<8 x half> %a) { -; CHECKLABEL: test_vcvtq_n_s16_f16: +; CHECK-LABEL: test_vcvtq_n_s16_f16: ; CHECK-LABEL: test_vcvtq_n_s16_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.s16.f16 q0, q0, #2 @@ -881,7 +881,7 @@ entry: declare <8 x i16> @llvm.arm.neon.vcvtfp2fxs.v8i16.v8f16(<8 x half>, i32) #2 define dso_local <4 x i16> @test_vcvt_n_u16_f16(<4 x half> %a) { -; CHECKLABEL: test_vcvt_n_u16_f16: +; CHECK-LABEL: test_vcvt_n_u16_f16: ; CHECK-LABEL: test_vcvt_n_u16_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.u16.f16 d0, d0, #2 @@ -894,7 +894,7 @@ entry: declare <4 x i16> @llvm.arm.neon.vcvtfp2fxu.v4i16.v4f16(<4 x half>, i32) #2 define dso_local <8 x i16> @test_vcvtq_n_u16_f16(<8 x half> %a) { -; CHECKLABEL: test_vcvtq_n_u16_f16: +; CHECK-LABEL: test_vcvtq_n_u16_f16: ; CHECK-LABEL: test_vcvtq_n_u16_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vcvt.u16.f16 q0, q0, #2 @@ -907,7 +907,7 @@ entry: declare <8 x i16> @llvm.arm.neon.vcvtfp2fxu.v8i16.v8f16(<8 x half>, i32) #2 define dso_local <4 x half> @test_vmax_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vmax_f16: +; CHECK-LABEL: test_vmax_f16: ; CHECK-LABEL: test_vmax_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmax.f16 d0, d0, d1 @@ -918,7 +918,7 @@ entry: } define dso_local <8 x half> @test_vmaxq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vmaxq_f16: +; CHECK-LABEL: test_vmaxq_f16: ; CHECK-LABEL: test_vmaxq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmax.f16 q0, q0, q1 @@ -989,7 +989,7 @@ entry: } define dso_local <4 x half> @test_vmul_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vmul_f16: +; CHECK-LABEL: test_vmul_f16: ; CHECK-LABEL: test_vmul_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmul.f16 d0, d0, d1 @@ -1000,7 +1000,7 @@ entry: } define dso_local <8 x half> @test_vmulq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vmulq_f16: +; CHECK-LABEL: test_vmulq_f16: ; CHECK-LABEL: test_vmulq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmul.f16 q0, q0, q1 @@ -1011,7 +1011,7 @@ entry: } define dso_local <4 x half> @test_vpadd_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vpadd_f16: +; CHECK-LABEL: test_vpadd_f16: ; CHECK-LABEL: test_vpadd_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vpadd.f16 d0, d0, d1 @@ -1022,7 +1022,7 @@ entry: } define dso_local <4 x half> @test_vpmax_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vpmax_f16: +; CHECK-LABEL: test_vpmax_f16: ; CHECK-LABEL: test_vpmax_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vpmax.f16 d0, d0, d1 @@ -1033,7 +1033,7 @@ entry: } define dso_local <4 x half> @test_vpmin_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vpmin_f16: +; CHECK-LABEL: test_vpmin_f16: ; CHECK-LABEL: test_vpmin_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vpmin.f16 d0, d0, d1 @@ -1044,7 +1044,7 @@ entry: } define dso_local <4 x half> @test_vrecps_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vrecps_f16: +; CHECK-LABEL: test_vrecps_f16: ; CHECK-LABEL: test_vrecps_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrecps.f16 d0, d0, d1 @@ -1055,7 +1055,7 @@ entry: } define dso_local <8 x half> @test_vrecpsq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vrecpsq_f16: +; CHECK-LABEL: test_vrecpsq_f16: ; CHECK-LABEL: test_vrecpsq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrecps.f16 q0, q0, q1 @@ -1066,7 +1066,7 @@ entry: } define dso_local <4 x half> @test_vrsqrts_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vrsqrts_f16: +; CHECK-LABEL: test_vrsqrts_f16: ; CHECK-LABEL: test_vrsqrts_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrsqrts.f16 d0, d0, d1 @@ -1077,7 +1077,7 @@ entry: } define dso_local <8 x half> @test_vrsqrtsq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vrsqrtsq_f16: +; CHECK-LABEL: test_vrsqrtsq_f16: ; CHECK-LABEL: test_vrsqrtsq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vrsqrts.f16 q0, q0, q1 @@ -1088,7 +1088,7 @@ entry: } define dso_local <4 x half> @test_vsub_f16(<4 x half> %a, <4 x half> %b) { -; CHECKLABEL: test_vsub_f16: +; CHECK-LABEL: test_vsub_f16: ; CHECK-LABEL: test_vsub_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vsub.f16 d0, d0, d1 @@ -1099,7 +1099,7 @@ entry: } define dso_local <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) { -; CHECKLABEL: test_vsubq_f16: +; CHECK-LABEL: test_vsubq_f16: ; CHECK-LABEL: test_vsubq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vsub.f16 q0, q0, q1 @@ -1209,7 +1209,7 @@ entry: } define dso_local <4 x half> @test_vbsl_f16(<4 x i16> %a, <4 x half> %b, <4 x half> %c) { -; CHECKLABEL: test_vbsl_f16: +; CHECK-LABEL: test_vbsl_f16: ; CHECK-LABEL: test_vbsl_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vbsl d0, d1, d2 @@ -1224,7 +1224,7 @@ entry: } define dso_local <8 x half> @test_vbslq_f16(<8 x i16> %a, <8 x half> %b, <8 x half> %c) { -; CHECKLABEL: test_vbslq_f16: +; CHECK-LABEL: test_vbslq_f16: ; CHECK-LABEL: test_vbslq_f16: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vbsl q0, q1, q2 diff --git a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll index ad538e1b4c800..a8cc0ddee3ec3 100644 --- a/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll +++ b/llvm/test/CodeGen/ARM/debug-frame-large-stack.ll @@ -35,17 +35,16 @@ define void @test2() { ; CHECK-ARM: sub sp, sp, #4096 ; CHECK-ARM: .cfi_endproc -; FIXME: Misspelled CHECK-ARM-FP-ELIM -; CHECK-ARM-FP_ELIM-LABEL: test2: -; CHECK-ARM-FP_ELIM: .cfi_startproc -; CHECK-ARM-FP_ELIM: push {r4, r5} -; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 8 -; CHECK-ARM-FP_ELIM: .cfi_offset 54, -4 -; CHECK-ARM-FP_ELIM: .cfi_offset r4, -8 -; CHECK-ARM-FP_ELIM: sub sp, sp, #72 -; CHECK-ARM-FP_ELIM: sub sp, sp, #4096 -; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 4176 -; CHECK-ARM-FP_ELIM: .cfi_endproc +; CHECK-ARM-FP-ELIM-LABEL: test2: +; CHECK-ARM-FP-ELIM: .cfi_startproc +; CHECK-ARM-FP-ELIM: push {r4, r5} +; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 8 +; CHECK-ARM-FP-ELIM: .cfi_offset 54, -4 +; CHECK-ARM-FP-ELIM: .cfi_offset r4, -8 +; CHECK-ARM-FP-ELIM: sub sp, sp, #72 +; CHECK-ARM-FP-ELIM: sub sp, sp, #4096 +; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 4176 +; CHECK-ARM-FP-ELIM: .cfi_endproc define i32 @test3() { %retval = alloca i32, align 4 diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll index 9fb64471e9881..892e66aed4e5f 100644 --- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll +++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll @@ -22,7 +22,7 @@ ; CHECK-DEFAULT: ldr{{.*}}, #4] ; CHECK-DEFAULT: str{{.*}}, #4] ; CHECK-DEFAULT: ldr{{.*}}, #8]! -; CHECK-DEAFULT: ldr{{.*}}, #8]! +; CHECK-DEFAULT: ldr{{.*}}, #8]! ; CHECK-DEFAULT: str{{.*}}, #8]! ; CHECK-COMPLEX: ldr{{.*}}, #8]! diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index bf2e8aa911c64..00922b1bf2492 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) { ; CHECK-THUMB-NEXT: orrs r0, r1 ; CHECK-THUMB-NEXT: bx lr entry: -; CHECk-THUMB: orrs r0, r1 %mul = mul i32 %y, 63767 %or = or i32 %mul, %x ret i32 %or diff --git a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll index f25d73a12246f..e8bdff4d7c8d3 100644 --- a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll +++ b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll @@ -96,7 +96,7 @@ entry: ; CHECK-NEXT: {{^[ \t]+b }} ; CHECK-NEXT: @NO_APP ; For direct branches, no mitigation is needed. -; ISDDSB-NOT: dsb sy +; ISBDSB-NOT: dsb sy ; SB-NOT: {{ sb$}} asm.fallthrough: ; preds = %entry @@ -248,7 +248,7 @@ entry: ; HARDEN-COMDAT-OFF-NOT: .hidden {{__llvm_slsblr_thunk_(arm|thumb)_r5}} ; HARDEN-COMDAT-OFF-NOT: .weak {{__llvm_slsblr_thunk_(arm|thumb)_r5}} ; HARDEN-COMDAT-OFF: .type {{__llvm_slsblr_thunk_(arm|thumb)_r5}},%function -; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}: +; HARDEN-LABEL: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}: ; HARDEN: bx r5 ; ISBDSB-NEXT: dsb sy ; ISBDSB-NEXT: isb diff --git a/llvm/test/CodeGen/ARM/sxt_rot.ll b/llvm/test/CodeGen/ARM/sxt_rot.ll index e9649c7a7fd9a..775e45201105c 100644 --- a/llvm/test/CodeGen/ARM/sxt_rot.ll +++ b/llvm/test/CodeGen/ARM/sxt_rot.ll @@ -22,7 +22,6 @@ define signext i8 @test1(i32 %A) { ; CHECK-V7: @ %bb.0: ; CHECK-V7-NEXT: sbfx r0, r0, #8, #8 ; CHECK-V7-NEXT: bx lr -; CHECk-V7: sbfx r0, r0, #8, #8 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C diff --git a/llvm/test/CodeGen/Hexagon/inline-division.ll b/llvm/test/CodeGen/Hexagon/inline-division.ll index 7249a3f55e868..e241a4335a845 100644 --- a/llvm/test/CodeGen/Hexagon/inline-division.ll +++ b/llvm/test/CodeGen/Hexagon/inline-division.ll @@ -15,7 +15,7 @@ entry: ;CHECK-NOT: call __hexagon_divsf3 ;CHECK: sfrecipa ;CHECK: sffixupn -;CHEKC: and +;CHECK: and ;CHECK: sfmpy %div = fdiv float %a, %b ret float %div diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir index f4a623d74436f..2710979124959 100644 --- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir +++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir @@ -38,7 +38,7 @@ body: | # CHECK-SUB-NOT: Bad machine code # # CHECK-SUB: Bad machine code: Live range continues after dead def flag -# CHECK_SUB-NEXT: function: test_fail +# CHECK-SUB-NEXT: function: test_fail # CHECK-SUB: v. register: %0 # CHECK-SUB: lanemask: 0000000000000002 # diff --git a/llvm/test/CodeGen/Lanai/lshift64.ll b/llvm/test/CodeGen/Lanai/lshift64.ll index 6a55d235e0998..11b3f330cb123 100644 --- a/llvm/test/CodeGen/Lanai/lshift64.ll +++ b/llvm/test/CodeGen/Lanai/lshift64.ll @@ -3,7 +3,7 @@ ; Test left-shift i64 lowering does not result in call being inserted. ; CHECK-LABEL: shift -; CHECKT: bt __ashldi3 +; CHECK: bt __ashldi3 ; CHECK: or %r0, 0x0, %r[[T0:[0-9]+]] ; CHECK: mov 0x20, %r[[T1:[0-9]+]] ; CHECK: sub %r[[T1]], %r[[ShAmt:[0-9]+]], %r[[T1]] diff --git a/llvm/test/CodeGen/MIR/AArch64/function-info-noredzone-present.mir b/llvm/test/CodeGen/MIR/AArch64/function-info-noredzone-present.mir index 739538689f46d..e85cd1062cb26 100644 --- a/llvm/test/CodeGen/MIR/AArch64/function-info-noredzone-present.mir +++ b/llvm/test/CodeGen/MIR/AArch64/function-info-noredzone-present.mir @@ -3,7 +3,7 @@ # This test checks for persistence of the hasRedZone attribute through a # llc transformation that shouldn't do anything -# CHECK-NAME: name: foo +# CHECK-LABEL: name: foo # CHECK-LABEL: machineFunctionInfo: {} --- diff --git a/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll index 69e54ba5cdb4f..d3786be482aa9 100644 --- a/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll +++ b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll @@ -2,7 +2,7 @@ define i16 @unnamed_stack() { entry: - ; CHECK-NAME: unnamed_stack + ; CHECK-LABEL: unnamed_stack ; CHECK: stack: ; CHECK-NEXT: - { id: 0, name: '', ; CHECK: %0:_(p0) = G_FRAME_INDEX %stack.0 @@ -13,7 +13,7 @@ entry: define i16 @named_stack() { entry: - ; CHECK-NAME: named_stack + ; CHECK-LABEL: named_stack ; CHECK: stack: ; CHECK-NEXT: - { id: 0, name: ptr, ; CHECK: %0:_(p0) = G_FRAME_INDEX %stack.0.ptr diff --git a/llvm/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/llvm/test/CodeGen/Mips/2008-07-15-SmallSection.ll index f5a761cb644be..05b705f758785 100644 --- a/llvm/test/CodeGen/Mips/2008-07-15-SmallSection.ll +++ b/llvm/test/CodeGen/Mips/2008-07-15-SmallSection.ll @@ -31,8 +31,8 @@ ; BASIC: .type s0,@object ; BASIC-NEXT: .section .sdata,"aw",@progbits -; EMDATA: .type s0,@object -; EMDATA-NEXT: .section .rodata,"a",@progbits +; EMBDATA: .type s0,@object +; EMBDATA-NEXT: .section .rodata,"a",@progbits @s0 = constant [8 x i8] c"AAAAAAA\00", align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index 1957453f55068..13468e0097be2 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -29,7 +29,7 @@ entry: define void @d1() #0 { entry: store double 1.234567e+00, ptr @de, align 8 -; mip32r2: .ent d1 +; mips32r2: .ent d1 ; mips32r2: lui $[[REG1a:[0-9]+]], 16371 ; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 ; mips32r2: lui $[[REG1b:[0-9]+]], 21403 diff --git a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll index bf69adf6702f0..58920483e24bf 100644 --- a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll +++ b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll @@ -3,11 +3,11 @@ ; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64 define i32 @shl_32(i32 %a, i32 %b) { -; MIPS32-LABLE: shl_32: +; MIPS32-LABEL: shl_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: sllv $2, $4, $5 -; MIPS64-LABLE: shl_32: +; MIPS64-LABEL: shl_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) { } define i32 @lshr_32(i32 %a, i32 %b) { -; MIPS32-LABLE: lshr_32: +; MIPS32-LABEL: lshr_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: srlv $2, $4, $5 -; MIPS64-LABLE: lshr_32: +; MIPS64-LABEL: lshr_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) { } define i32 @ashr_32(i32 %a, i32 %b) { -; MIPS32-LABLE: ashr_32: +; MIPS32-LABEL: ashr_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: srav $2, $4, $5 -; MIPS64-LABLE: ashr_32: +; MIPS64-LABEL: ashr_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) { } define i64 @shl_64(i64 %a, i64 %b) { -; MIPS64-LABLE: shl_64: +; MIPS64-LABEL: shl_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra @@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) { } define i64 @lshr_64(i64 %a, i64 %b) { -; MIPS64-LABLE: lshr_64: +; MIPS64-LABEL: lshr_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra @@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) { } define i64 @ashr_64(i64 %a, i64 %b) { -; MIPS64-LABLE: ashr_64: +; MIPS64-LABEL: ashr_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll index 3b200780b9f59..fb0a82684fbad 100644 --- a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll @@ -101,7 +101,7 @@ entry: ; PIC32R6: jalr $25 ; PIC32MM: jalr $25 ; STATIC32: jal -; SATATIC32MMR6: jal +; STATIC32MMR6: jal ; PIC64: jalr $25 ; STATIC64: jal ; N64R6: jalr $25 diff --git a/llvm/test/CodeGen/NVPTX/idioms.ll b/llvm/test/CodeGen/NVPTX/idioms.ll index e8fe47c303f92..f199ac339f41b 100644 --- a/llvm/test/CodeGen/NVPTX/idioms.ll +++ b/llvm/test/CodeGen/NVPTX/idioms.ll @@ -42,7 +42,7 @@ define %struct.S16 @i32_to_2xi16(i32 noundef %in) { %high = trunc i32 %high32 to i16 ; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_param_0]; ; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]]; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; %s1 = insertvalue %struct.S16 poison, i16 %low, 0 %s = insertvalue %struct.S16 %s1, i16 %high, 1 ret %struct.S16 %s @@ -56,7 +56,7 @@ define %struct.S16 @i32_to_2xi16_lh(i32 noundef %in) { %low = trunc i32 %in to i16 ; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_lh_param_0]; ; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]]; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; %s1 = insertvalue %struct.S16 poison, i16 %low, 0 %s = insertvalue %struct.S16 %s1, i16 %high, 1 ret %struct.S16 %s @@ -84,7 +84,7 @@ define %struct.S32 @i64_to_2xi32(i64 noundef %in) { %high = trunc i64 %high64 to i32 ; CHECK: ld.param.u64 %[[R64:rd[0-9]+]], [i64_to_2xi32_param_0]; ; CHECK-DAG: cvt.u32.u64 %r{{[0-9+]}}, %[[R64]]; -; CHECK-DAG mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]]; +; CHECK-DAG: mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]]; %s1 = insertvalue %struct.S32 poison, i32 %low, 0 %s = insertvalue %struct.S32 %s1, i32 %high, 1 ret %struct.S32 %s @@ -114,8 +114,8 @@ define %struct.S16 @i32_to_2xi16_shr(i32 noundef %i){ %h = trunc i32 %h32 to i16 ; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_shr_param_0]; ; CHECK: shr.s32 %[[R32H:r[0-9]+]], %[[R32]], 16; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]]; %s0 = insertvalue %struct.S16 poison, i16 %l, 0 %s1 = insertvalue %struct.S16 %s0, i16 %h, 1 ret %struct.S16 %s1 diff --git a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir index 2432f4245b46d..4188b47777a27 100644 --- a/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir +++ b/llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir @@ -67,7 +67,7 @@ body: | ... --- name: killFlagSameBlock -#CHECK : name : killFlagSameBlock +#CHECK: name : killFlagSameBlock tracksRegLiveness: true body: | bb.0.entry: @@ -82,7 +82,7 @@ body: | ... --- name: killFlagDifferentBlocks -#CHECK : name : killFlagDifferentBlocks +#CHECK: name : killFlagDifferentBlocks tracksRegLiveness: true body: | bb.0.entry: diff --git a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir index 66a266e89a9f7..1c588755b0477 100644 --- a/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir +++ b/llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir @@ -3,7 +3,7 @@ --- name: test -#CHECK : name : test +#CHECK: name : test tracksRegLiveness: true body: | bb.0.entry: @@ -21,7 +21,7 @@ body: | ... --- name: test2 -#CHECK : name : test2 +#CHECK: name : test2 tracksRegLiveness: true body: | bb.0.entry: diff --git a/llvm/test/CodeGen/PowerPC/livevars-crash1.mir b/llvm/test/CodeGen/PowerPC/livevars-crash1.mir index 6ddc2b022e9b5..9d68f0d82b3bd 100644 --- a/llvm/test/CodeGen/PowerPC/livevars-crash1.mir +++ b/llvm/test/CodeGen/PowerPC/livevars-crash1.mir @@ -97,7 +97,7 @@ body: | ; CHECK: %1:g8rc_and_g8rc_nox0 = COPY killed %12 ; CHECK: %5:gprc = LBZ 0, %1 :: (load (s8) from %ir.0) ; CHECK: %6:crrc = CMPWI killed %5, 0 - ; CHEXK: %7:crbitrc = COPY killed %6.sub_eq + ; CHECK: %7:crbitrc = COPY killed %6.sub_eq ; CHECK: %2:g8rc = nuw ADDI8 %1, 1 ; CHECK: STD %2, 0, %4 :: (store (s64) into %ir.p) ; CHECK: %8:gprc = LBZ 1, %1 :: (load (s8) from %ir.incdec.ptr) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll index 2ad068eb7dc3d..7a59682a3af1a 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll @@ -9,7 +9,7 @@ declare @llvm.riscv.vadd.nxv1i8.nxv1i8( , i64) -; FALLBACK_WITH_REPORT_ERR: :0:0: unable to translate instruction: call: +; FALLBACK-WITH-REPORT-ERR: :0:0: unable to translate instruction: call: ; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_arg define @scalable_arg( %0, %1, i64 %2) nounwind { entry: diff --git a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll index 4eeb1bf313858..b1f5c15b12a9a 100644 --- a/llvm/test/CodeGen/RISCV/patchable-function-entry.ll +++ b/llvm/test/CodeGen/RISCV/patchable-function-entry.ll @@ -22,10 +22,10 @@ define void @f1() "patchable-function-entry"="1" { ; RVC: c.nop ; RVC-NEXT: c.jr ra ; CHECK: .section __patchable_function_entries,"awo",@progbits,f1{{$}} -; 32: .p2align 2 -; 32-NEXT: .word .Lfunc_begin1 -; 64: .p2align 3 -; 64-NEXT: .quad .Lfunc_begin1 +; RV32: .p2align 2 +; RV32-NEXT: .word .Lfunc_begin1 +; RV64: .p2align 3 +; RV64-NEXT: .quad .Lfunc_begin1 ret void } diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll index 9817d7c6971f5..786e9f3eb1e13 100644 --- a/llvm/test/CodeGen/SPARC/inlineasm.ll +++ b/llvm/test/CodeGen/SPARC/inlineasm.ll @@ -144,7 +144,7 @@ entry: ret void } -; CHECK-label:test_twinword +; CHECK-LABEL:test_twinword ; CHECK: rd %asr5, %i1 ; CHECK: srlx %i1, 32, %i0 diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll index 449dd71954500..ebf200945b3eb 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll @@ -32,7 +32,7 @@ ; CHECK-DAG: %[[#Const42:]] = OpConstant %[[#DoubleTy:]] 42 ; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown" -; CHECK-NO: OpAsmTargetINTEL +; CHECK-NOT: OpAsmTargetINTEL ; CHECK: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "" ; CHECK: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" "" @@ -45,7 +45,7 @@ ; CHECK: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r" ; CHECK: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r" ; CHECK: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i" -; CHECK-NO: OpAsmINTEL +; CHECK-NOT: OpAsmINTEL ; CHECK: OpFunction ; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm1]] @@ -59,7 +59,7 @@ ; CHECK: OpAsmCallINTEL %[[#Int64Ty]] %[[#Asm9]] %[[#]] %[[#]] %[[#]] ; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm10]] %[[#Const123]] %[[#Const42]] ; CHECK: OpAsmCallINTEL %[[#VoidTy]] %[[#Asm11]] %[[#Const123]] %[[#Const42]] -; CHECK-NO: OpAsmCallINTEL +; CHECK-NOT: OpAsmCallINTEL define spir_kernel void @foo(ptr addrspace(1) %_arg_int, ptr addrspace(1) %_arg_float, ptr addrspace(1) %_arg_half, i64 %_lng) { %i1 = load i32, ptr addrspace(1) %_arg_int diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll index 986d88da41832..19c59236d7e59 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll @@ -5,8 +5,8 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-WITHOUT ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-: Capability USMStorageClassesINTEL -; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL +; CHECK-SPIRV: Capability USMStorageClassesINTEL +; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL ; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]] ; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]] ; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll index fe71ce862dfc3..f2c841ab95fd4 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse-subbyte.ll @@ -10,7 +10,7 @@ ; CHECK-SPIRV: OpCapability BitInstructions ; CHECK-SPIRV: OpExtension "SPV_KHR_bit_instructions" ; CHECK-SPIRV: %[[#CharTy:]] = OpTypeInt 8 0 -; CHECK-SPIRV-NO: %[[#CharTy:]] = OpTypeInt 8 0 +; CHECK-SPIRV-NOT: %[[#CharTy:]] = OpTypeInt 8 0 ; CHECK-SPIRV-COUNT-2: %[[#]] = OpBitReverse %[[#CharTy]] %[[#]] ; TODO: Add a check to ensure that there's no behavior change of bitreverse operation diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll index 1840ad5411f47..8a7dc7cd5dbeb 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpBitReverse_i2.ll @@ -10,7 +10,7 @@ ; CHECK-SPIRV: OpCapability BitInstructions ; CHECK-SPIRV: OpExtension "SPV_KHR_bit_instructions" ; CHECK-SPIRV: %[[#CharTy:]] = OpTypeInt 8 0 -; CHECK-SPIRV-NO: %[[#CharTy:]] = OpTypeInt 8 0 +; CHECK-SPIRV-NOT: %[[#CharTy:]] = OpTypeInt 8 0 ; CHECK-SPIRV: %[[#Arg:]] = OpFunctionParameter %[[#CharTy]] ; CHECK-SPIRV: %[[#Res:]] = OpBitReverse %[[#CharTy]] %[[#Arg]] ; CHECK-SPIRV: OpReturnValue %[[#Res]] diff --git a/llvm/test/CodeGen/SystemZ/prefetch-04.ll b/llvm/test/CodeGen/SystemZ/prefetch-04.ll index 61a2a1460c583..10755bdb66eb5 100644 --- a/llvm/test/CodeGen/SystemZ/prefetch-04.ll +++ b/llvm/test/CodeGen/SystemZ/prefetch-04.ll @@ -6,7 +6,7 @@ ; ; CHECK-LABEL: for.body ; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1 -; CHECK-not: call void @llvm.prefetch +; CHECK-NOT: call void @llvm.prefetch define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) { entry: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll index 165e73c2e8827..680d9e02a5c5c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll @@ -406,7 +406,7 @@ for.cond.cleanup: ; CHECK-MID: tB %bb.1 ; CHECK-MID: bb.1.while.body: ; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1 -; CHECk-MID: tB %bb.2 +; CHECK-MID: tB %bb.2 ; CHECK-MID: bb.2.while.end: define void @check_negated_xor_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { entry: @@ -440,7 +440,7 @@ while.end: ; CHECK-MID: tB %bb.1 ; CHECK-MID: bb.1.while.body: ; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1 -; CHECk-MID: tB %bb.2 +; CHECK-MID: tB %bb.2 ; CHECK-MID: bb.2.while.end: define void @check_negated_cmp_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { entry: @@ -474,7 +474,7 @@ while.end: ; CHECK-MID: tB %bb.1 ; CHECK-MID: bb.1.while.body: ; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1 -; CHECk-MID: tB %bb.2 +; CHECK-MID: tB %bb.2 ; CHECK-MID: bb.2.while.end: define void @check_negated_reordered_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { entry: diff --git a/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll b/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll index 70a5939865b7b..8337482d7b45a 100644 --- a/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll +++ b/llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll @@ -159,7 +159,7 @@ declare double @llvm.trunc.f64(double %Val) define double @trunc_d(double %a) { ; CHECK-LABEL: trunc_d: ; SOFT: {{(bl|b)}} trunc -; FFP4: b trunc +; VFP4: b trunc ; FP-ARMv8: vrintz.f64 %1 = call double @llvm.trunc.f64(double %a) ret double %1 @@ -224,8 +224,8 @@ define double @h_to_d(i16 %a) { ; NONE: bl __aeabi_f2d ; SP: vcvt{{[bt]}}.f32.f16 ; SP: bl __aeabi_f2d -; VFPv4: vcvt{{[bt]}}.f32.f16 -; VFPv4: vcvt.f64.f32 +; VFP4: vcvt{{[bt]}}.f32.f16 +; VFP4: vcvt.f64.f32 ; FP-ARMv8: vcvt{{[bt]}}.f64.f16 %1 = call double @llvm.convert.from.fp16.f64(i16 %a) ret double %1 diff --git a/llvm/test/CodeGen/Thumb2/float-ops.ll b/llvm/test/CodeGen/Thumb2/float-ops.ll index d2b1dd6f05a3f..6920b137f16cb 100644 --- a/llvm/test/CodeGen/Thumb2/float-ops.ll +++ b/llvm/test/CodeGen/Thumb2/float-ops.ll @@ -305,7 +305,7 @@ define double @select_d(double %a, double %b, i1 %c) { ; DP: lsls r0, r0, #31 ; VFP4-DP: vmovne.f64 d1, d0 ; VFP4-DP: vmov.f64 d0, d1 -; FP-ARMV8: vseleq.f64 d0, d1, d0 +; FP-ARMv8: vseleq.f64 d0, d1, d0 %1 = select i1 %c, double %a, double %b ret double %1 } diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll index 0b6d318348e3b..35a7d517c45ca 100644 --- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll +++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll @@ -141,6 +141,6 @@ attributes #0 = { minsize nofree norecurse nounwind optsize uwtable} ; UNWIND-NEXT: 0xB0 ; finish -; UNWINND-LABEL: 00000041 {{.*}} OUTLINED_FUNCTION_0 -; UNWINND-LABEL: 00000001 {{.*}} x -; UNWINND-LABEL: 00000021 {{.*}} y +; UNWIND-LABEL: 00000041 {{.*}} OUTLINED_FUNCTION_0 +; UNWIND-LABEL: 00000001 {{.*}} x +; UNWIND-LABEL: 00000021 {{.*}} y diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll index ffc29534df700..33451809fc367 100644 --- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll +++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll @@ -159,7 +159,7 @@ return: ; preds = %entry, %if.end ; CHECK-NEXT: bx lr -; CHEK-LABEL: OUTLINED_FUNCTION_0: +; CHECK-LABEL: OUTLINED_FUNCTION_0: ; CHECK-NOT: pac ; CHECK-NOT: aut ; CHECK: b _Z1hii @@ -203,6 +203,6 @@ attributes #2 = { noreturn } ; UNWIND-NEXT: 0xB0 ; finish ; UNWIND: 000000a9 {{.*}} OUTLINED_FUNCTION_0 -; UWNIND: 00000001 {{.*}} _Z1hii -; UWNIND: 0000003d {{.*}} _Z1fiiii -; UWNIND: 00000073 {{.*}} _Z1giiii +; UNWIND: 00000001 {{.*}} _Z1hii +; UNWIND: 0000003d {{.*}} _Z1fiiii +; UNWIND: 00000073 {{.*}} _Z1giiii diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index 03d4c7dd3281d..00e8ef20fb12b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -2060,7 +2060,6 @@ body: | ... --- name: test_fconstant -# ALL-LABEL: name: test_fconstant legalized: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/dynamic-regmask-preserve-all.ll b/llvm/test/CodeGen/X86/dynamic-regmask-preserve-all.ll index f92e22d14e22b..7d2b964baf0e9 100644 --- a/llvm/test/CodeGen/X86/dynamic-regmask-preserve-all.ll +++ b/llvm/test/CodeGen/X86/dynamic-regmask-preserve-all.ll @@ -56,7 +56,7 @@ define {i64, i64} @caller2(i64 %a0) nounwind { ret {i64, i64} %b1 } ; CHECK: name: caller2 -; CHECL: CALL64pcrel32 @callee2, CustomRegMask($bh,$bl,$bp,$bph,$bpl,$bx,$ch,$cl,$cx,$di,$dih,$dil,$ebp,$ebx,$ecx,$edi,$esi,$hbp,$hbx,$hcx,$hdi,$hsi,$rbp,$rbx,$rcx,$rdi,$rsi,$si,$sih,$sil,$r8,$r9,$r10,$r12,$r13,$r14,$r15,$xmm0,$xmm1,$xmm2,$xmm3,$xmm4,$xmm5,$xmm6,$xmm7,$xmm8,$xmm9,$xmm10,$xmm11,$xmm12,$xmm13,$xmm14,$xmm15,$r8b,$r9b,$r10b,$r12b,$r13b,$r14b,$r15b,$r8bh,$r9bh,$r10bh,$r12bh,$r13bh,$r14bh,$r15bh,$r8d,$r9d,$r10d,$r12d,$r13d,$r14d,$r15d,$r8w,$r9w,$r10w,$r12w,$r13w,$r14w,$r15w,$r8wh,$r9wh,$r10wh,$r12wh,$r13wh,$r14wh,$r15wh), implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $rdx +; CHECK: CALL64pcrel32 @callee2, CustomRegMask($bh,$bl,$bp,$bph,$bpl,$bx,$ch,$cl,$cx,$di,$dih,$dil,$ebp,$ebx,$ecx,$edi,$esi,$hbp,$hbx,$hcx,$hdi,$hsi,$rbp,$rbx,$rcx,$rdi,$rsi,$si,$sih,$sil,$r8,$r9,$r10,$r12,$r13,$r14,$r15,$xmm0,$xmm1,$xmm2,$xmm3,$xmm4,$xmm5,$xmm6,$xmm7,$xmm8,$xmm9,$xmm10,$xmm11,$xmm12,$xmm13,$xmm14,$xmm15,$r8b,$r9b,$r10b,$r12b,$r13b,$r14b,$r15b,$r8bh,$r9bh,$r10bh,$r12bh,$r13bh,$r14bh,$r15bh,$r8d,$r9d,$r10d,$r12d,$r13d,$r14d,$r15d,$r8w,$r9w,$r10w,$r12w,$r13w,$r14w,$r15w,$r8wh,$r9wh,$r10wh,$r12wh,$r13wh,$r14wh,$r15wh), implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $rdx ; CHECK: RET 0, $rax, $rdx diff --git a/llvm/test/CodeGen/X86/global-sections.ll b/llvm/test/CodeGen/X86/global-sections.ll index b300fc87e38ab..ebfb25fecae38 100644 --- a/llvm/test/CodeGen/X86/global-sections.ll +++ b/llvm/test/CodeGen/X86/global-sections.ll @@ -35,9 +35,9 @@ bb5: ret void } -; LINUX: .size F2, -; LINUX-NEX: .cfi_endproc -; LINUX-NEX: .section .rodata,"a",@progbits +; LINUX: .size F2, +; LINUX-NEXT: .cfi_endproc +; LINUX-NEXT: .section .rodata,"a",@progbits ; LINUX-SECTIONS: .section .text.F2,"ax",@progbits ; LINUX-SECTIONS: .size F2, diff --git a/llvm/test/CodeGen/X86/haddsub.ll b/llvm/test/CodeGen/X86/haddsub.ll index a0778195b5c73..b130f6b9be964 100644 --- a/llvm/test/CodeGen/X86/haddsub.ll +++ b/llvm/test/CodeGen/X86/haddsub.ll @@ -1709,23 +1709,23 @@ define double @fadd_reduce_v4f64(double %a0, <4 x double> %a1) { } define float @PR39936_v8f32(<8 x float>) { -; SSSE3-SLOW-LABEL: PR39936_v8f32: -; SSSE3-SLOW: # %bb.0: -; SSSE3-SLOW-NEXT: haddps %xmm1, %xmm0 -; SSSE3-SLOW-NEXT: movaps %xmm0, %xmm1 -; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3] -; SSSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3,2,3] -; SSSE3-SLOW-NEXT: addps %xmm1, %xmm0 -; SSSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] -; SSSE3-SLOW-NEXT: addss %xmm1, %xmm0 -; SSSE3-SLOW-NEXT: retq -; -; SSSE3-FAST-LABEL: PR39936_v8f32: -; SSSE3-FAST: # %bb.0: -; SSSE3-FAST-NEXT: haddps %xmm1, %xmm0 -; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 -; SSSE3-FAST-NEXT: haddps %xmm0, %xmm0 -; SSSE3-FAST-NEXT: retq +; SSE3-SLOW-LABEL: PR39936_v8f32: +; SSE3-SLOW: # %bb.0: +; SSE3-SLOW-NEXT: haddps %xmm1, %xmm0 +; SSE3-SLOW-NEXT: movaps %xmm0, %xmm1 +; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[2,3] +; SSE3-SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3,2,3] +; SSE3-SLOW-NEXT: addps %xmm1, %xmm0 +; SSE3-SLOW-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE3-SLOW-NEXT: addss %xmm1, %xmm0 +; SSE3-SLOW-NEXT: retq +; +; SSE3-FAST-LABEL: PR39936_v8f32: +; SSE3-FAST: # %bb.0: +; SSE3-FAST-NEXT: haddps %xmm1, %xmm0 +; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 +; SSE3-FAST-NEXT: haddps %xmm0, %xmm0 +; SSE3-FAST-NEXT: retq ; ; SSE3-SLOW-LABEL: PR39936_v8f32: ; SSE3-SLOW: # %bb.0: diff --git a/llvm/test/CodeGen/X86/sjlj.ll b/llvm/test/CodeGen/X86/sjlj.ll index 8fcaea8eb797d..977f278d00958 100644 --- a/llvm/test/CodeGen/X86/sjlj.ll +++ b/llvm/test/CodeGen/X86/sjlj.ll @@ -21,9 +21,9 @@ define i32 @sj0() nounwind { %r = tail call i32 @llvm.eh.sjlj.setjmp(ptr @buf) ret i32 %r ; X86: sj0 -; x86: movl %ebp, buf +; X86: movl %ebp, buf ; X86: movl %esp, buf+8 -; x86: movl ${{.*LBB.*}}, buf+4 +; X86: movl ${{.*LBB.*}}, buf+4 ; X86: ret ; PIC86: sj0 ; PIC86: movl %ebp, buf@GOTOFF(%[[GOT:.*]]) @@ -32,8 +32,8 @@ define i32 @sj0() nounwind { ; PIC86: movl %[[LREG]], buf@GOTOFF+4 ; PIC86: ret ; X64: sj0 -; x64: movq %rbp, buf(%rip) -; x64: movq ${{.*LBB.*}}, buf+8(%rip) +; X64: movq %rbp, buf(%rip) +; X64: movq ${{.*LBB.*}}, buf+8(%rip) ; X64: movq %rsp, buf+16(%rip) ; X64: ret ; PIC64: sj0 diff --git a/llvm/test/CodeGen/X86/tailregccpic.ll b/llvm/test/CodeGen/X86/tailregccpic.ll index f89c4ac4df599..a3a17d3b05397 100644 --- a/llvm/test/CodeGen/X86/tailregccpic.ll +++ b/llvm/test/CodeGen/X86/tailregccpic.ll @@ -13,12 +13,12 @@ entry: ret void } -;CHECK-LABLE: tail_call_regcall: +;CHECK-LABEL: tail_call_regcall: ;CHECK: # %bb.0: ;CHECK-NEXT: jmp __regcall3__func # TAILCALL ;CHECK-NEXT: .Lfunc_end0: -;CHECK-LABLE: __regcall3__func: +;CHECK-LABEL: __regcall3__func: ;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx ;CHECK-NEXT: movl a0@GOT(%ecx), %ecx ;CHECK-NEXT: movl %eax, (%ecx) diff --git a/llvm/test/DebugInfo/COFF/jump-table.ll b/llvm/test/DebugInfo/COFF/jump-table.ll index a8039809c8b77..355d9157f74c0 100644 --- a/llvm/test/DebugInfo/COFF/jump-table.ll +++ b/llvm/test/DebugInfo/COFF/jump-table.ll @@ -47,7 +47,7 @@ ; X64: .Ltmp4: ; X64-NEXT: jmpq *%{{.*}} ; A32: .LCPI0_0: -; A32-NEXT add pc, r{{.*}} +; A32-NEXT: add pc, r{{.*}} ; NOTE: thumbv7a places the jump tables just after the branch, so verify the other branch below ; A64: .Ltmp1: ; A64-NEXT: br x{{.*}} @@ -62,7 +62,7 @@ ; A64-NEXT: .byte (.LBB0_[[FIRSTBLOCK:[0-9]+]]-.LBB0_[[FIRSTBLOCK]])>>2 ; NOTE: thumbv7a places the jump tables just after the branch, so check for the other branch now ; A32: .LCPI0_1: -; A32-NEXT add pc, r{{.*}} +; A32-NEXT: add pc, r{{.*}} ; CHECK: {{\.?}}LJTI0_1: ; I686-NEXT: .long LBB0_[[#]] ; X64-NEXT: .long .LBB0_[[#]]-.LJTI0_1 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir index 0253c95cc1324..26c702f9334aa 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir @@ -172,7 +172,7 @@ body: | DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(1, 0), debug-location !7 ; CHECK: DBG_VALUE_LIST ![[VARNUM]], ; CHECK-SAME: !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_convert, 8, DW_ATE_signed, - ; CHECK-SAME : DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), $al + ; CHECK-SAME: : DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), $al MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0) ;; Clobber to force variable location onto stack. We should use a diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir index d4ed0fba2d7cd..2935293e40f8d 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir @@ -43,7 +43,7 @@ debugValueSubstitutions: body: | bb.0.entry: successors: %bb.1, %bb.2 - ; CHECK-LABE: bb.0.entry: + ; CHECK-LABEL: bb.0.entry: $rax = MOV64ri 1, debug-instr-number 1, debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17 @@ -69,8 +69,8 @@ body: | ;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17 ;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17 ;;; Test non-def operand - ;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0) - ;; check-next: DBG_VALUE_LIST {{.+}}, $noreg + ; COM: CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0) + ; COM: CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg $noreg = MOV32ri 1, debug-instr-number 5, debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir index 8f43a55b34001..3649b136d3900 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir @@ -55,11 +55,11 @@ ## to bb.3, but not into bb.4 because of the intervening out-of-scope block. ## Disabled actual testing of this because it's just for comparison purposes. # -# varloc-label: bb.1: +# varloc-LABEL: bb.1: # varloc: DBG_VALUE -# varloc-label: bb.2: +# varloc-LABEL: bb.2: ## No location here because it's out-of-scope. -# varloc-label: bb.3: +# varloc-LABEL: bb.3: # varloc: DBG_VALUE # ## Common tail for 'test2' -- this is checking that the assignment of undef or diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir index 47860f8f47118..588174619d795 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir @@ -20,7 +20,7 @@ debugInstrRef: true liveins: - { reg: '$rax' } # CHECK: debugValueSubstitutions: -# CHECK-NEXT - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 4 } +# CHECK-NEXT:- { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 4 } ## Subreg 4 -> sub_16bit body: | bb.0: @@ -41,7 +41,7 @@ debugInstrRef: true liveins: - { reg: '$rdi' } # CHECK: debugValueSubstitutions: -# CHECK-NEXT - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 4 } +# CHECK-NEXT:- { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 4 } ## Subreg 4 -> sub_16bit body: | bb.0: diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir index 5e088d3f46007..d506156bfab4e 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir @@ -4,7 +4,7 @@ # for corner cases that we can only hit with -mtriple=i386. --- name: test2add_32 -# CHECK: name: test2add_32 +# CHECK-LABEL: name: test2add_32 alignment: 16 tracksRegLiveness: true debugInstrRef: true @@ -12,7 +12,7 @@ liveins: - { reg: '$eax' } - { reg: '$ebp' } # CHECK: debugValueSubstitutions: -# CHECK-NAME: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } +# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 } body: | bb.0: liveins: $eax, $ebp diff --git a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir index 776335e5ddfd4..827095791b347 100644 --- a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir +++ b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir @@ -14,7 +14,7 @@ # CHECK: INLINEASM # CHECK-DAG: DBG_VALUE $esi, $noreg, !{{.*}}, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location {{.*}} # CHECK-DAG: DBG_VALUE $edx, $noreg, !{{.*}}, !DIExpression(DW_OP_LLVM_entry_value, 1), debug-location {{.*}} -# CHECK $eax = MOV32ri 123 +# CHECK:$eax = MOV32ri 123 --- | ; ModuleID = 'multiple-param-dbg-value-entry.ll' diff --git a/llvm/test/DebugInfo/MSP430/ranges_always.ll b/llvm/test/DebugInfo/MSP430/ranges_always.ll index 753c82b9cbd55..68504cf82c5d9 100644 --- a/llvm/test/DebugInfo/MSP430/ranges_always.ll +++ b/llvm/test/DebugInfo/MSP430/ranges_always.ll @@ -5,7 +5,7 @@ ; RUN: llc -O0 %s -mtriple=msp430 -filetype=obj -o - -minimize-addr-in-v5=Expressions \ ; RUN: | llvm-dwarfdump -debug-info -debug-addr -debug-rnglists -v - \ -; RUN: | FileCheck --check-prefix=CHECK --check-prefix=EXPRORFORM --check-prefix=EXPR\ +; RUN: | FileCheck --check-prefix=CHECK --check-prefix=EXPRORFORM --check-prefix=EXPR \ ; RUN: --implicit-check-not=DW_TAG --implicit-check-not=NULL --implicit-check-not=_pc %s ; RUN: llc -O0 %s -mtriple=msp430 -filetype=obj -o - -minimize-addr-in-v5=Form \ diff --git a/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test b/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test index cd285b8292408..cdad0fc44091c 100644 --- a/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test +++ b/llvm/test/DebugInfo/PDB/DIA/pdbdump-symbol-format.test @@ -10,7 +10,7 @@ ; The format is func [0x+ - 0x-] ; SYM_FORMAT_FPO: ---SYMBOLS--- ; SYM_FORMAT_FPO: symbolformat-fpo.obj -; SYM_FORMAT-FPO: func [{{.*}}] (FPO) unsigned int __cdecl fpo_func(unsigned int n) +; SYM_FORMAT_FPO: func [{{.*}}] (FPO) unsigned int __cdecl fpo_func(unsigned int n) ; SYM_FORMAT: ---SYMBOLS--- ; SYM_FORMAT: symbolformat.obj diff --git a/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll b/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll index 29f7d9353e0a3..1a575c21b93a0 100644 --- a/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll +++ b/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll @@ -142,9 +142,9 @@ entry: ; FASTISEL-INSTRREF-NEXT: - { srcinst: 3, srcop: 0, dstinst: 2, dstop: 0, subreg: 6 } ; FASTISEL-INSTRREF-NEXT: - { srcinst: 5, srcop: 0, dstinst: 4, dstop: 0, subreg: 6 } ; FASTISEL-INSTRREF-NEXT: - { srcinst: 6, srcop: 0, dstinst: 5, dstop: 0, subreg: 4 } -; FASTISEL-INSTRREF-NEXT - { srcinst: 8, srcop: 0, dstinst: 7, dstop: 0, subreg: 6 } -; FASTISEL-INSTRREF-NEXT - { srcinst: 9, srcop: 0, dstinst: 8, dstop: 0, subreg: 4 } -; FASTISEL-INSTRREF-NEXT - { srcinst: 10, srcop: 0, dstinst: 9, dstop: 0, subreg: 1 } +; FASTISEL-INSTRREF-NEXT: - { srcinst: 8, srcop: 0, dstinst: 7, dstop: 0, subreg: 6 } +; FASTISEL-INSTRREF-NEXT: - { srcinst: 9, srcop: 0, dstinst: 8, dstop: 0, subreg: 4 } +; FASTISEL-INSTRREF-NEXT: - { srcinst: 10, srcop: 0, dstinst: 9, dstop: 0, subreg: 1 } ;; Those substitutions are anchored against these DBG_PHIs: diff --git a/llvm/test/DebugInfo/X86/ranges_always.ll b/llvm/test/DebugInfo/X86/ranges_always.ll index 76f846e51d2fb..7220960a1e0e2 100644 --- a/llvm/test/DebugInfo/X86/ranges_always.ll +++ b/llvm/test/DebugInfo/X86/ranges_always.ll @@ -5,7 +5,7 @@ ; RUN: llc -O0 %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj -o - -minimize-addr-in-v5=Expressions \ ; RUN: | llvm-dwarfdump -debug-info -debug-addr -debug-rnglists -v - \ -; RUN: | FileCheck --check-prefix=CHECK --check-prefix=EXPRORFORM --check-prefix=EXPR\ +; RUN: | FileCheck --check-prefix=CHECK --check-prefix=EXPRORFORM --check-prefix=EXPR \ ; RUN: --implicit-check-not=DW_TAG --implicit-check-not=NULL --implicit-check-not=_pc %s ; RUN: llc -O0 %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj -o - -minimize-addr-in-v5=Form \ diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/dbg-phi-produces-undef.ll b/llvm/test/DebugInfo/assignment-tracking/X86/dbg-phi-produces-undef.ll index 2ab4e57f470af..2a9a3aadaa8df 100644 --- a/llvm/test/DebugInfo/assignment-tracking/X86/dbg-phi-produces-undef.ll +++ b/llvm/test/DebugInfo/assignment-tracking/X86/dbg-phi-produces-undef.ll @@ -30,7 +30,7 @@ ; CHECK: bb.0.entry: ; CHECK: DBG_VALUE %stack.0.c, $noreg, ![[var:[0-9]+]], !DIExpression(DW_OP_deref), debug-location ; CHECK-NEXT: MOV8mi %stack.0.c, 1, $noreg, 0, $noreg, 5, debug-location -; CHECL-NEXT: DBG_VALUE %stack.0.c, $noreg, ![[var]], !DIExpression(DW_OP_deref), debug-location +; CHECK-NEXT: DBG_VALUE %stack.0.c, $noreg, ![[var]], !DIExpression(DW_OP_deref), debug-location ; CHECK: bb.1.if.then: ; CHECK: MOV8mi %stack.0.c, 1, $noreg, 0, $noreg, 0 diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll index ba7d3f6a67e27..0d89c8260d5fe 100644 --- a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll +++ b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll @@ -144,7 +144,7 @@ entry4: ; Verify that we do not get a DBG_VALUE that maps foo5 to @S here. define i32 @test5() local_unnamed_addr #0 !dbg !47 { ; CHECK-LABEL: bb.0.entry5: -; cHECK-NEXT: DBG_VALUE $noreg, $noreg, ![[FOO5]], !DIExpression() +; CHECK-NEXT: DBG_VALUE $noreg, $noreg, ![[FOO5]], !DIExpression() ; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression() ; CHECK-NEXT: [[REG5:%[0-9]+]]:gr64 = LEA64r ; INSTRREF-SAME: debug-instr-number 1 diff --git a/llvm/test/DebugInfo/dwarfdump-dump-gdbindex-v8.test b/llvm/test/DebugInfo/dwarfdump-dump-gdbindex-v8.test index 3823c89606d81..8e9e2a9081ea9 100644 --- a/llvm/test/DebugInfo/dwarfdump-dump-gdbindex-v8.test +++ b/llvm/test/DebugInfo/dwarfdump-dump-gdbindex-v8.test @@ -39,7 +39,7 @@ RUN: llvm-dwarfdump -gdb-index %p/Inputs/dwarfdump-gdbindex-v8.elf-x86-64 | File ; CHECK: Types CU list offset = 0x38, has 2 entries: ; CHECK-NEXT: 0: offset = 0x00000000, type_offset = 0x0000001e, type_signature = 0x418503b8111e9a7b -; CHECK-NEXT; 1: offset = 0x00000044, type_offset = 0x0000001e, type_signature = 0x00f6cca4e3a15118 +; CHECK-NEXT: 1: offset = 0x00000044, type_offset = 0x0000001e, type_signature = 0x00f6cca4e3a15118 ; CHECK: Address area offset = 0x68, has 2 entries: ; CHECK-NEXT: Low/High address = [0x201180, 0x20118f) (Size: 0xf), CU id = 0 diff --git a/llvm/test/Feature/optnone-llc.ll b/llvm/test/Feature/optnone-llc.ll index 7e6678f9cdc42..ad51f18f1863f 100644 --- a/llvm/test/Feature/optnone-llc.ll +++ b/llvm/test/Feature/optnone-llc.ll @@ -1,3 +1,4 @@ +; RUN: llc -O0 -debug %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=LLC-O0 ; RUN: llc -O1 -debug %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=LLC-Ox ; RUN: llc -O2 -debug %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=LLC-Ox ; RUN: llc -O3 -debug %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=LLC-Ox diff --git a/llvm/test/Instrumentation/AddressSanitizer/aarch64be.ll b/llvm/test/Instrumentation/AddressSanitizer/aarch64be.ll index aeb1b0e8ebe77..5393420956e2b 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/aarch64be.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/aarch64be.ll @@ -12,7 +12,7 @@ entry: ; CHECK-AARCH64LE-NOT: ret ; Check for ASAN's Offset for AArch64 LE (1 << 36 or 68719476736) ; CHECK-AARCH64LE: lshr {{.*}} 3 -; CHECK-AARCH64Le-NEXT: {{68719476736}} +; CHECK-AARCH64LE-NEXT: {{68719476736}} ; CHECK-AARCH64LE: ret ; CHECK-AARCH64BE: @read_4_bytes diff --git a/llvm/test/Instrumentation/InstrProfiling/inline-data-var.ll b/llvm/test/Instrumentation/InstrProfiling/inline-data-var.ll index dcb97d0a9b976..7d9ae67610123 100644 --- a/llvm/test/Instrumentation/InstrProfiling/inline-data-var.ll +++ b/llvm/test/Instrumentation/InstrProfiling/inline-data-var.ll @@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK: @__profd_foobar = private global -; CHECK-NOT @__profd_foobar +; CHECK-NOT: @__profd_foobar declare void @llvm.instrprof.increment(ptr %0, i64 %1, i32 %2, i32 %3) @__profn_foobar = private constant [6 x i8] c"foobar" diff --git a/llvm/test/MC/AArch64/SME/feature.s b/llvm/test/MC/AArch64/SME/feature.s index f6193b1557b1b..87afb5b333eb5 100644 --- a/llvm/test/MC/AArch64/SME/feature.s +++ b/llvm/test/MC/AArch64/SME/feature.s @@ -8,4 +8,4 @@ tbx z0.b, z1.b, z2.b // Verify +sme flags imply +bf16 bfdot z0.s, z1.h, z2.h -// CHECK-INST: bfdot z0.s, z1.h, z2.h +// CHECK: bfdot z0.s, z1.h, z2.h diff --git a/llvm/test/MC/AArch64/armv8.7a-xs.s b/llvm/test/MC/AArch64/armv8.7a-xs.s index e3a1e12aae9a5..c41a6f8778263 100644 --- a/llvm/test/MC/AArch64/armv8.7a-xs.s +++ b/llvm/test/MC/AArch64/armv8.7a-xs.s @@ -99,39 +99,39 @@ // CHECK: tlbi vale3nxs, x1 // encoding: [0xa1,0x97,0x0e,0xd5] // CHECK: tlbi vmalls12e1nxs // encoding: [0xdf,0x97,0x0c,0xd5] // CHECK: tlbi vaale1nxs, x1 // encoding: [0xe1,0x97,0x08,0xd5] -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE2ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE3ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE2ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE3ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ASIDE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAAE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1ISnXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE2nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE3nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE2nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAE3nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ASIDE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAAE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI ALLE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VALE3nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1nXS requires: xs -// CHECK_NO_XS_ERR: [[@LINE-64]]:8: error: TLBI VAALE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE2ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE3ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE2ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE3ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ASIDE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAAE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE2ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE3ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAALE1ISnXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2E1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI IPAS2LE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE2nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE3nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE2nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAE3nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ASIDE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAAE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI ALLE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE2nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VALE3nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VMALLS12E1nXS requires: xs +// CHECK-NO-XS-ERR: [[@LINE-64]]:8: error: TLBI VAALE1nXS requires: xs tlbi vmalle1osnxs tlbi vae1osnxs, x1 @@ -225,49 +225,49 @@ // CHECK: tlbi rvale3isnxs, x1 // encoding: [0xa1,0x92,0x0e,0xd5] // CHECK: tlbi rvae3osnxs, x1 // encoding: [0x21,0x95,0x0e,0xd5] // CHECK: tlbi rvale3osnxs, x1 // encoding: [0xa1,0x95,0x0e,0xd5] -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: tlb-rmi, xs -// CHECK_NO_XS_ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VMALLE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ASIDE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAAE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VALE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAALE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI IPAS2E1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI IPAS2LE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAE2OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VALE2OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VMALLS12E1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VAE3OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI VALE3OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ALLE2OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ALLE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI ALLE3OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE1nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAAE1nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE1nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAALE1nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE1ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAAE1ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE1ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAALE1ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAAE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAALE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2E1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RIPAS2LE1OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE2nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE2nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE2ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE2ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE2OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE2OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE3nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE3nXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE3ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE3ISnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVAE3OSnXS requires: tlb-rmi, xs +// CHECK-NO-XS-ERR: [[@LINE-92]]:8: error: TLBI RVALE3OSnXS requires: tlb-rmi, xs diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s index 028700f4d11df..cf13c935ebc18 100644 --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -87,9 +87,9 @@ // CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w4, w5, #-4097 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-AARCH64-NEXT: add w5, w6, #0x1000 -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] +// CHECK-ERROR-ARM64-NEXT: add w5, w6, #0x1000 +// CHECK-ERROR-ARM64-NEXT: ^ // CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w4, w5, #-4096, lsl #12 // CHECK-ERROR-NEXT: ^ @@ -145,9 +145,9 @@ // Out of range immediate adds w0, w5, #0x10000 -// CHECK-ERROR-AARCH64: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-AARCH64-NEXT: adds w0, w5, #0x10000 -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64: error: expected compatible register, symbol or integer in range [0, 4095] +// CHECK-ERROR-ARM64-NEXT: adds w0, w5, #0x10000 +// CHECK-ERROR-ARM64-NEXT: ^ // Wn|WSP should be in second place adds w4, wzr, #0x123 @@ -846,15 +846,15 @@ sxtb x3, x2 sxth xzr, xzr sxtw x3, x5 -// CHECK-ERROR-AARCH64: error: invalid operand for instruction -// CHECK-ERROR-AARCH64-NEXT: sxtb x3, x2 -// CHECK-ERROR-AARCH64-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction -// CHECK-ERROR-AARCH64-NEXT: sxth xzr, xzr -// CHECK-ERROR-AARCH64-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction -// CHECK-ERROR-AARCH64-NEXT: sxtw x3, x5 -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64: error: invalid operand for instruction +// CHECK-ERROR-ARM64-NEXT: sxtb x3, x2 +// CHECK-ERROR-ARM64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-ARM64-NEXT: sxth xzr, xzr +// CHECK-ERROR-ARM64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-ARM64-NEXT: sxtw x3, x5 +// CHECK-ERROR-ARM64-NEXT: ^ uxtb x3, x12 uxth x5, x9 @@ -867,9 +867,9 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: uxth x5, x9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: invalid instruction -// CHECK-ERROR-AARCH64-NEXT: uxtw x3, x5 -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: invalid instruction +// CHECK-ERROR-ARM64-NEXT: uxtw x3, x5 +// CHECK-ERROR-ARM64-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: uxtb x2, sp // CHECK-ERROR-NEXT: ^ @@ -906,7 +906,7 @@ sbfiz x3, x5, #12, #53 sbfiz sp, x3, #7, #6 sbfiz w3, wsp, #10, #8 -// CHECK-ERROR-AARCH64: error: expected integer in range [, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [, 31] // CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: sbfiz w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ @@ -940,7 +940,7 @@ sbfx x3, x5, #12, #53 sbfx sp, x3, #7, #6 sbfx w3, wsp, #10, #8 -// CHECK-ERROR-AARCH64: error: expected integer in range [, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [, 31] // CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: sbfx w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ @@ -974,7 +974,7 @@ bfi x3, x5, #12, #53 bfi sp, x3, #7, #6 bfi w3, wsp, #10, #8 -// CHECK-ERROR-AARCH64: error: expected integer in range [, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [, 31] // CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: bfi w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ @@ -1008,7 +1008,7 @@ bfxil x3, x5, #12, #53 bfxil sp, x3, #7, #6 bfxil w3, wsp, #10, #8 -// CHECK-ERROR-AARCH64: error: expected integer in range [, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [, 31] // CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: bfxil w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ @@ -1042,7 +1042,7 @@ ubfiz x3, x5, #12, #53 ubfiz sp, x3, #7, #6 ubfiz w3, wsp, #10, #8 -// CHECK-ERROR-AARCH64: error: expected integer in range [, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [, 31] // CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: ubfiz w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ @@ -1076,7 +1076,7 @@ ubfx x3, x5, #12, #53 ubfx sp, x3, #7, #6 ubfx w3, wsp, #10, #8 -// CHECK-ERROR-AARCH64: error: expected integer in range [, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [, 31] // CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: ubfx w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ @@ -1553,7 +1553,7 @@ cbz w1, lsl //------------------------------------------------------------------------------ fcmp s3, d2 -// CHECK-ERROR-AARCH64: error: expected floating-point constant #0.0 +// CHECK-ERROR-ARM64: error: expected floating-point constant #0.0 // CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-NEXT: fcmp s3, d2 // CHECK-ERROR-NEXT: ^ @@ -1847,11 +1847,11 @@ cbz w1, lsl // CHECK-ERROR: error: expected lane specifier '[1]' // CHECK-ERROR-NEXT: fmov x3, v0.d[0] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-ARM64-NEXT: error: lane number incompatible with layout // CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: fmov v29.1d[1], x2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-ARM64-NEXT: error: lane number incompatible with layout // CHECK-ERROR-ARM64-NEXT: error: expected lane specifier '[1]' // CHECK-ERROR-NEXT: fmov x7, v0.d[2] // CHECK-ERROR-NEXT: ^ @@ -1898,7 +1898,7 @@ cbz w1, lsl stxrb w2, w3, [x4, #20] stlxrh w10, w11, [w2] -// CHECK-ERROR-AARCH64: error: expected '#0' +// CHECK-ERROR-ARM64: error: expected '#0' // CHECK-ERROR-ARM64: error: index must be absent or #0 // CHECK-ERROR-NEXT: stxrb w2, w3, [x4, #20] // CHECK-ERROR-NEXT: ^ @@ -2000,13 +2000,13 @@ cbz w1, lsl ldr x3, [x4, #25], #0 ldr x4, [x9, #0], #4 -// CHECK-ERROR-AARCH64: error: invalid operand for instruction +// CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr x3, [x4, #25], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected label or encodable integer pc offset -// CHECK-ERROR-AARCH64-NEXT: ldr x4, [x9, #0], #4 -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: expected label or encodable integer pc offset +// CHECK-ERROR-ARM64-NEXT: ldr x4, [x9, #0], #4 +// CHECK-ERROR-ARM64-NEXT: ^ strb w1, [x19], #256 strb w9, [sp], #-257 @@ -2438,15 +2438,15 @@ cbz w1, lsl ldr w0, [x0, #2] ldrsh w2, [x0, #123] str q0, [x0, #8] -// CHECK-ERROR-AARCH64: error: too few operands for instruction -// CHECK-ERROR-AARCH64-NEXT: ldr w0, [x0, #2] -// CHECK-ERROR-AARCH64-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction -// CHECK-ERROR-AARCH64-NEXT: ldrsh w2, [x0, #123] -// CHECK-ERROR-AARCH64-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction -// CHECK-ERROR-AARCH64-NEXT: str q0, [x0, #8] -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64: error: too few operands for instruction +// CHECK-ERROR-ARM64-NEXT: ldr w0, [x0, #2] +// CHECK-ERROR-ARM64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: too few operands for instruction +// CHECK-ERROR-ARM64-NEXT: ldrsh w2, [x0, #123] +// CHECK-ERROR-ARM64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: too few operands for instruction +// CHECK-ERROR-ARM64-NEXT: str q0, [x0, #8] +// CHECK-ERROR-ARM64-NEXT: ^ //// 32-bit addresses ldr w0, [w20] @@ -2466,12 +2466,12 @@ cbz w1, lsl // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: strb w0, [wsp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64: error: invalid operand for instruction -// CHECK-ERROR-AARCH64-NEXT: strh w31, [x23, #1] -// CHECK-ERROR-AARCH64-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction -// CHECK-ERROR-AARCH64-NEXT: str x5, [x22, #12] -// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-ARM64: error: invalid operand for instruction +// CHECK-ERROR-ARM64-NEXT: strh w31, [x23, #1] +// CHECK-ERROR-ARM64-NEXT: ^ +// CHECK-ERROR-ARM64-NEXT: error: too few operands for instruction +// CHECK-ERROR-ARM64-NEXT: str x5, [x22, #12] +// CHECK-ERROR-ARM64-NEXT: ^ // CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w7, [x12, #16384] // CHECK-ERROR-NEXT: ^ @@ -2481,18 +2481,18 @@ cbz w1, lsl prfm #32, [sp, #8] prfm pldl1strm, [w3, #8] prfm wibble, [sp] -// CHECK-ERROR-AARCH64: error: Invalid immediate for instruction +// CHECK-ERROR-ARM64: error: Invalid immediate for instruction // CHECK-ERROR-ARM64: error: prefetch operand out of range, [0,31] expected // CHECK-ERROR-NEXT: prfm #-1, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-ARM64-NEXT: error: Invalid immediate for instruction // CHECK-ERROR-ARM64-NEXT: error: prefetch operand out of range, [0,31] expected // CHECK-ERROR-NEXT: prfm #32, [sp, #8] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: prfm pldl1strm, [w3, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised +// CHECK-ERROR-ARM64-NEXT: error: operand specifier not recognised // CHECK-ERROR-ARM64-NEXT: error: prefetch hint expected // CHECK-ERROR-NEXT: prfm wibble, [sp] // CHECK-ERROR-NEXT: ^ @@ -2600,11 +2600,11 @@ cbz w1, lsl // CHECK-ERROR-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: ldr q5, [sp, x2, lsl #-1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-NEXT: ldr q10, [x20, w4, uxtw #2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-NEXT: str q21, [x20, w4, uxtw #5] // CHECK-ERROR-NEXT: ^ @@ -3189,11 +3189,11 @@ cbz w1, lsl // CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w4, #65536 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected relocated symbol or integer in range [0, 65535] // CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16 // CHECK-ERROR-NEXT: movn w1, #2, lsl #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: only 'lsl #+N' valid after immediate +// CHECK-ERROR-ARM64-NEXT: error: only 'lsl #+N' valid after immediate // CHECK-ERROR-ARM64-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: movk w3, #0, lsl #-1 // CHECK-ERROR-NEXT: ^ @@ -3203,11 +3203,11 @@ cbz w1, lsl // CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected relocated symbol or integer in range [0, 65535] // CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16 // CHECK-ERROR-NEXT: movk w3, #1, lsl #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected relocated symbol or integer in range [0, 65535] // CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0, 16, 32 or 48 // CHECK-ERROR-NEXT: movn x2, #12, lsl #64 // CHECK-ERROR-NEXT: ^ @@ -3429,7 +3429,7 @@ cbz w1, lsl // CHECK-ERROR-NEXT: error: specified {{IC|ic}} op does not use a register // CHECK-ERROR-NEXT: ic ialluis, x2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised +// CHECK-ERROR-ARM64-NEXT: error: operand specifier not recognised // CHECK-ERROR-ARM64-NEXT: error: invalid operand for IC instruction // CHECK-ERROR-NEXT: ic allu, x7 // CHECK-ERROR-NEXT: ^ diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s index 5225b5e656762..16993cf7a8588 100644 --- a/llvm/test/MC/ARM/coff-relocations.s +++ b/llvm/test/MC/ARM/coff-relocations.s @@ -25,7 +25,7 @@ branch24t_1: bl target @ CHECK-ENCODING-LABEL: : -@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0 +@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0 .thumb_func branch20t: diff --git a/llvm/test/MC/ARM/neon-complex.s b/llvm/test/MC/ARM/neon-complex.s index 6054a08dc82e8..50efb23f003f8 100644 --- a/llvm/test/MC/ARM/neon-complex.s +++ b/llvm/test/MC/ARM/neon-complex.s @@ -24,7 +24,7 @@ // FP16-THUMB: vcmla.f16 d0, d1, d2, #0 @ encoding: [0x21,0xfc,0x02,0x08] // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f16 q0, q1, q2, #0 // FP16-ARM: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x44,0x08,0x22,0xfc] // FP16-THUMB: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x22,0xfc,0x44,0x08] @@ -32,36 +32,36 @@ // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this: // V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: mve.fp // V82A: :[[@LINE-6]]:{{[0-9]*}}: note: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2, #0 // ARM: vcmla.f32 d0, d1, d2, #0 @ encoding: [0x02,0x08,0x31,0xfc] // THUMB: vcmla.f32 d0, d1, d2, #0 @ encoding: [0x31,0xfc,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 q0, q1, q2, #0 // ARM: vcmla.f32 q0, q1, q2, #0 @ encoding: [0x44,0x08,0x32,0xfc] // THUMB: vcmla.f32 q0, q1, q2, #0 @ encoding: [0x32,0xfc,0x44,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this: // V82A: :[[@LINE-4]]:{{[0-9]*}}: note: instruction requires: mve.fp // V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON // Valid rotations vcmla.f32 d0, d1, d2, #90 // ARM: vcmla.f32 d0, d1, d2, #90 @ encoding: [0x02,0x08,0xb1,0xfc] // THUMB: vcmla.f32 d0, d1, d2, #90 @ encoding: [0xb1,0xfc,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2, #180 // ARM: vcmla.f32 d0, d1, d2, #180 @ encoding: [0x02,0x08,0x31,0xfd] // THUMB: vcmla.f32 d0, d1, d2, #180 @ encoding: [0x31,0xfd,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2, #270 // ARM: vcmla.f32 d0, d1, d2, #270 @ encoding: [0x02,0x08,0xb1,0xfd] // THUMB: vcmla.f32 d0, d1, d2, #270 @ encoding: [0xb1,0xfd,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON // Invalid rotations vcmla.f32 d0, d1, d2, #-90 @@ -82,7 +82,7 @@ // FP16-THUMB: vcadd.f16 d0, d1, d2, #90 @ encoding: [0x81,0xfc,0x02,0x08] // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcadd.f16 q0, q1, q2, #90 // FP16-ARM: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x44,0x08,0x82,0xfc] // FP16-THUMB: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x82,0xfc,0x44,0x08] @@ -90,26 +90,26 @@ // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this: // V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: mve.fp // V82A: :[[@LINE-6]]:{{[0-9]*}}: note: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-7]]:{{[0-9]*}}: error: instruction requires: NEON vcadd.f32 d0, d1, d2, #90 // ARM: vcadd.f32 d0, d1, d2, #90 @ encoding: [0x02,0x08,0x91,0xfc] // THUMB: vcadd.f32 d0, d1, d2, #90 @ encoding: [0x91,0xfc,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON vcadd.f32 q0, q1, q2, #90 // ARM: vcadd.f32 q0, q1, q2, #90 @ encoding: [0x44,0x08,0x92,0xfc] // THUMB: vcadd.f32 q0, q1, q2, #90 @ encoding: [0x92,0xfc,0x44,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: invalid instruction, any one of the following would fix this: // V82A: :[[@LINE-4]]:{{[0-9]*}}: note: instruction requires: mve.fp // V82A: :[[@LINE-5]]:{{[0-9]*}}: note: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-6]]:{{[0-9]*}}: error: instruction requires: NEON // Valid rotations vcadd.f32 d0, d1, d2, #270 // ARM: vcadd.f32 d0, d1, d2, #270 @ encoding: [0x02,0x08,0x91,0xfd] // THUMB: vcadd.f32 d0, d1, d2, #270 @ encoding: [0x91,0xfd,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON // Invalid rotations vcadd.f32 d0, d1, d2, #0 @@ -137,40 +137,40 @@ // FP16-THUMB: vcmla.f16 d0, d1, d2[0], #0 @ encoding: [0x01,0xfe,0x02,0x08] // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f16 q0, q1, d2[0], #0 // FP16-ARM: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x02,0xfe] // FP16-THUMB: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x02,0xfe,0x42,0x08] // NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2[0], #0 // ARM: vcmla.f32 d0, d1, d2[0], #0 @ encoding: [0x02,0x08,0x81,0xfe] // THUMB: vcmla.f32 d0, d1, d2[0], #0 @ encoding: [0x81,0xfe,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 q0, q1, d2[0], #0 // ARM: vcmla.f32 q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x82,0xfe] // THUMB: vcmla.f32 q0, q1, d2[0], #0 @ encoding: [0x82,0xfe,0x42,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON // Valid rotations vcmla.f32 d0, d1, d2[0], #90 // ARM: vcmla.f32 d0, d1, d2[0], #90 @ encoding: [0x02,0x08,0x91,0xfe] // THUMB: vcmla.f32 d0, d1, d2[0], #90 @ encoding: [0x91,0xfe,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2[0], #180 // ARM: vcmla.f32 d0, d1, d2[0], #180 @ encoding: [0x02,0x08,0xa1,0xfe] // THUMB: vcmla.f32 d0, d1, d2[0], #180 @ encoding: [0xa1,0xfe,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2[0], #270 // ARM: vcmla.f32 d0, d1, d2[0], #270 @ encoding: [0x02,0x08,0xb1,0xfe] // THUMB: vcmla.f32 d0, d1, d2[0], #270 @ encoding: [0xb1,0xfe,0x02,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON // Invalid rotations vcmla.f32 d0, d1, d2[0], #-90 @@ -188,7 +188,7 @@ // FP16-ARM: vcmla.f16 d0, d1, d2[1], #0 @ encoding: [0x22,0x08,0x01,0xfe] // FP16-THUMB: vcmla.f16 d0, d1, d2[1], #0 @ encoding: [0x01,0xfe,0x22,0x08] // V82A: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: armv8.3a -// NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON +// NO-NEON-STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON // Invalid indices // The text of these errors vary depending on whether fullfp16 is present. diff --git a/llvm/test/MC/AsmParser/labels.s b/llvm/test/MC/AsmParser/labels.s index 599ce72c44eef..4d6653bfb7de4 100644 --- a/llvm/test/MC/AsmParser/labels.s +++ b/llvm/test/MC/AsmParser/labels.s @@ -29,7 +29,7 @@ foo: // CHECK: .long 11 .long "a 0" -// XXCHCK: .section "a 1,a 2" +// COM: CHECK: .section "a 1,a 2" //.section "a 1", "a 2" // CHECK: .globl "a 3" @@ -46,7 +46,7 @@ foo: // FIXME: We don't bother to support .lsym. -// CHECX: .lsym "a 8",1 +// COM: CHECK: .lsym "a 8",1 // .lsym "a 8", 1 // CHECK: .set "a 9", a-b diff --git a/llvm/test/MC/COFF/cv-inline-linetable.s b/llvm/test/MC/COFF/cv-inline-linetable.s index 2748fa71df75c..4cea3b1576896 100644 --- a/llvm/test/MC/COFF/cv-inline-linetable.s +++ b/llvm/test/MC/COFF/cv-inline-linetable.s @@ -76,9 +76,9 @@ Lfunc_end0: # PDB-NEXT: 0B26 code 0x1F (+0x6) line 2 (+1) # PDB-NEXT: 0B27 code 0x26 (+0x7) line 3 (+1) # PDB-NEXT: 0407 code end 0x2D (+0x7) -# PEB: S_INLINESITE_END -# PEB: S_INLINESITE_END -# PEB: S_PROC_ID_END +# PDB: S_INLINESITE_END +# PDB: S_INLINESITE_END +# PDB: S_PROC_ID_END .section .debug$T,"dr" .long 4 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt index 1d37bbcaf3865..ebaeeba50d10f 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt @@ -22,13 +22,13 @@ # CHECK: bfdot v2.4s, v3.8h, v4.2h[2] # CHECK: bfdot v2.4s, v3.8h, v4.2h[3] # NOBF16: warning: invalid instruction encoding -# NOBF-NEXT: [0x62,0xf0,0x44,0x4f] +# NOBF16-NEXT: [0x62,0xf0,0x44,0x4f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf0,0x64,0x4f] +# NOBF16-NEXT: [0x62,0xf0,0x64,0x4f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x44,0x4f] +# NOBF16-NEXT: [0x62,0xf8,0x44,0x4f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x64,0x4f] +# NOBF16-NEXT: [0x62,0xf8,0x64,0x4f] [0x62,0xf0,0x44,0x0f] @@ -40,13 +40,13 @@ # CHECK: bfdot v2.2s, v3.4h, v4.2h[2] # CHECK: bfdot v2.2s, v3.4h, v4.2h[3] # NOBF16: warning: invalid instruction encoding -# NOBF-NEXT: [0x62,0xf0,0x44,0x0f] +# NOBF16-NEXT: [0x62,0xf0,0x44,0x0f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf0,0x64,0x0f] +# NOBF16-NEXT: [0x62,0xf0,0x64,0x0f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x44,0x0f] +# NOBF16-NEXT: [0x62,0xf8,0x44,0x0f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x64,0x0f] +# NOBF16-NEXT: [0x62,0xf8,0x64,0x0f] [0x62,0xec,0x44,0x6e] diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt index ce09954f5f0f8..042cd5b9c89e7 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.7a-xs.txt @@ -89,38 +89,38 @@ # CHECK: tlbi vale3nxs, x1 # CHECK: tlbi vmalls12e1nxs # CHECK: tlbi vaale1nxs, x1 -# CHECK_NO_XS: sys #4, c9, c0, #1, x1 -# CHECK_NO_XS: sys #4, c9, c0, #5, x1 -# CHECK_NO_XS: sys #0, c9, c3, #0 -# CHECK_NO_XS: sys #4, c9, c3, #0 -# CHECK_NO_XS: sys #6, c9, c3, #0 -# CHECK_NO_XS: sys #0, c9, c3, #1, x1 -# CHECK_NO_XS: sys #4, c9, c3, #1, x1 -# CHECK_NO_XS: sys #6, c9, c3, #1, x1 -# CHECK_NO_XS: sys #0, c9, c3, #2, x1 -# CHECK_NO_XS: sys #0, c9, c3, #3, x1 -# CHECK_NO_XS: sys #4, c9, c3, #4 -# CHECK_NO_XS: sys #0, c9, c3, #5, x1 -# CHECK_NO_XS: sys #4, c9, c3, #5, x1 -# CHECK_NO_XS: sys #6, c9, c3, #5, x1 -# CHECK_NO_XS: sys #4, c9, c3, #6 -# CHECK_NO_XS: sys #0, c9, c3, #7, x1 -# CHECK_NO_XS: sys #4, c9, c4, #1, x1 -# CHECK_NO_XS: sys #4, c9, c4, #5, x1 -# CHECK_NO_XS: sys #0, c9, c7, #0 -# CHECK_NO_XS: sys #4, c9, c7, #0 -# CHECK_NO_XS: sys #6, c9, c7, #0 -# CHECK_NO_XS: sys #0, c9, c7, #1, x1 -# CHECK_NO_XS: sys #4, c9, c7, #1, x1 -# CHECK_NO_XS: sys #6, c9, c7, #1, x1 -# CHECK_NO_XS: sys #0, c9, c7, #2, x1 -# CHECK_NO_XS: sys #0, c9, c7, #3, x1 -# CHECK_NO_XS: sys #4, c9, c7, #4 -# CHECK_NO_XS: sys #0, c9, c7, #5, x1 -# CHECK_NO_XS: sys #4, c9, c7, #5, x1 -# CHECK_NO_XS: sys #6, c9, c7, #5, x1 -# CHECK_NO_XS: sys #4, c9, c7, #6 -# CHECK_NO_XS: sys #0, c9, c7, #7, x1 +# CHECK-NO-XS: sys #4, c9, c0, #1, x1 +# CHECK-NO-XS: sys #4, c9, c0, #5, x1 +# CHECK-NO-XS: sys #0, c9, c3, #0 +# CHECK-NO-XS: sys #4, c9, c3, #0 +# CHECK-NO-XS: sys #6, c9, c3, #0 +# CHECK-NO-XS: sys #0, c9, c3, #1, x1 +# CHECK-NO-XS: sys #4, c9, c3, #1, x1 +# CHECK-NO-XS: sys #6, c9, c3, #1, x1 +# CHECK-NO-XS: sys #0, c9, c3, #2, x1 +# CHECK-NO-XS: sys #0, c9, c3, #3, x1 +# CHECK-NO-XS: sys #4, c9, c3, #4 +# CHECK-NO-XS: sys #0, c9, c3, #5, x1 +# CHECK-NO-XS: sys #4, c9, c3, #5, x1 +# CHECK-NO-XS: sys #6, c9, c3, #5, x1 +# CHECK-NO-XS: sys #4, c9, c3, #6 +# CHECK-NO-XS: sys #0, c9, c3, #7, x1 +# CHECK-NO-XS: sys #4, c9, c4, #1, x1 +# CHECK-NO-XS: sys #4, c9, c4, #5, x1 +# CHECK-NO-XS: sys #0, c9, c7, #0 +# CHECK-NO-XS: sys #4, c9, c7, #0 +# CHECK-NO-XS: sys #6, c9, c7, #0 +# CHECK-NO-XS: sys #0, c9, c7, #1, x1 +# CHECK-NO-XS: sys #4, c9, c7, #1, x1 +# CHECK-NO-XS: sys #6, c9, c7, #1, x1 +# CHECK-NO-XS: sys #0, c9, c7, #2, x1 +# CHECK-NO-XS: sys #0, c9, c7, #3, x1 +# CHECK-NO-XS: sys #4, c9, c7, #4 +# CHECK-NO-XS: sys #0, c9, c7, #5, x1 +# CHECK-NO-XS: sys #4, c9, c7, #5, x1 +# CHECK-NO-XS: sys #6, c9, c7, #5, x1 +# CHECK-NO-XS: sys #4, c9, c7, #6 +# CHECK-NO-XS: sys #0, c9, c7, #7, x1 [0x1f,0x91,0x08,0xd5] [0x21,0x91,0x08,0xd5] @@ -214,51 +214,51 @@ # CHECK: tlbi rvale3isnxs, x1 # CHECK: tlbi rvae3osnxs, x1 # CHECK: tlbi rvale3osnxs, x1 -# CHECK_NO_XS: sys #0, c9, c1, #0 -# CHECK_NO_XS: sys #0, c9, c1, #1, x1 -# CHECK_NO_XS: sys #0, c9, c1, #2, x1 -# CHECK_NO_XS: sys #0, c9, c1, #3, x1 -# CHECK_NO_XS: sys #0, c9, c1, #5, x1 -# CHECK_NO_XS: sys #0, c9, c1, #7, x1 -# CHECK_NO_XS: sys #4, c9, c4, #0, x1 -# CHECK_NO_XS: sys #4, c9, c4, #4, x1 -# CHECK_NO_XS: sys #4, c9, c1, #1, x1 -# CHECK_NO_XS: sys #4, c9, c1, #5, x1 -# CHECK_NO_XS: sys #4, c9, c1, #6 -# CHECK_NO_XS: sys #6, c9, c1, #1, x1 -# CHECK_NO_XS: sys #6, c9, c1, #5, x1 -# CHECK_NO_XS: sys #4, c9, c1, #0 -# CHECK_NO_XS: sys #4, c9, c1, #4 -# CHECK_NO_XS: sys #6, c9, c1, #0 -# CHECK_NO_XS: sys #0, c9, c6, #1, x1 -# CHECK_NO_XS: sys #0, c9, c6, #3, x1 -# CHECK_NO_XS: sys #0, c9, c6, #5, x1 -# CHECK_NO_XS: sys #0, c9, c6, #7, x1 -# CHECK_NO_XS: sys #0, c9, c2, #1, x1 -# CHECK_NO_XS: sys #0, c9, c2, #3, x1 -# CHECK_NO_XS: sys #0, c9, c2, #5, x1 -# CHECK_NO_XS: sys #0, c9, c2, #7, x1 -# CHECK_NO_XS: sys #0, c9, c5, #1, x1 -# CHECK_NO_XS: sys #0, c9, c5, #3, x1 -# CHECK_NO_XS: sys #0, c9, c5, #5, x1 -# CHECK_NO_XS: sys #0, c9, c5, #7, x1 -# CHECK_NO_XS: sys #4, c9, c0, #2, x1 -# CHECK_NO_XS: sys #4, c9, c0, #6, x1 -# CHECK_NO_XS: sys #4, c9, c4, #2, x1 -# CHECK_NO_XS: sys #4, c9, c4, #6, x1 -# CHECK_NO_XS: sys #4, c9, c4, #3, x1 -# CHECK_NO_XS: sys #4, c9, c4, #7, x1 -# CHECK_NO_XS: sys #4, c9, c6, #1, x1 -# CHECK_NO_XS: sys #4, c9, c6, #5, x1 -# CHECK_NO_XS: sys #4, c9, c2, #1, x1 -# CHECK_NO_XS: sys #4, c9, c2, #5, x1 -# CHECK_NO_XS: sys #4, c9, c5, #1, x1 -# CHECK_NO_XS: sys #4, c9, c5, #5, x1 -# CHECK_NO_XS: sys #6, c9, c6, #1, x1 -# CHECK_NO_XS: sys #6, c9, c6, #5, x1 -# CHECK_NO_XS: sys #6, c9, c2, #1, x1 -# CHECK_NO_XS: sys #6, c9, c2, #5, x1 -# CHECK_NO_XS: sys #6, c9, c5, #1, x1 -# CHECK_NO_XS: sys #6, c9, c5, #5, x1 -# CHECK_NO_XS: sys #0, c9, c1, #0 -# CHECK_NO_XS: sys #4, c9, c0, #1, x1 +# CHECK-NO-XS: sys #0, c9, c1, #0 +# CHECK-NO-XS: sys #0, c9, c1, #1, x1 +# CHECK-NO-XS: sys #0, c9, c1, #2, x1 +# CHECK-NO-XS: sys #0, c9, c1, #3, x1 +# CHECK-NO-XS: sys #0, c9, c1, #5, x1 +# CHECK-NO-XS: sys #0, c9, c1, #7, x1 +# CHECK-NO-XS: sys #4, c9, c4, #0, x1 +# CHECK-NO-XS: sys #4, c9, c4, #4, x1 +# CHECK-NO-XS: sys #4, c9, c1, #1, x1 +# CHECK-NO-XS: sys #4, c9, c1, #5, x1 +# CHECK-NO-XS: sys #4, c9, c1, #6 +# CHECK-NO-XS: sys #6, c9, c1, #1, x1 +# CHECK-NO-XS: sys #6, c9, c1, #5, x1 +# CHECK-NO-XS: sys #4, c9, c1, #0 +# CHECK-NO-XS: sys #4, c9, c1, #4 +# CHECK-NO-XS: sys #6, c9, c1, #0 +# CHECK-NO-XS: sys #0, c9, c6, #1, x1 +# CHECK-NO-XS: sys #0, c9, c6, #3, x1 +# CHECK-NO-XS: sys #0, c9, c6, #5, x1 +# CHECK-NO-XS: sys #0, c9, c6, #7, x1 +# CHECK-NO-XS: sys #0, c9, c2, #1, x1 +# CHECK-NO-XS: sys #0, c9, c2, #3, x1 +# CHECK-NO-XS: sys #0, c9, c2, #5, x1 +# CHECK-NO-XS: sys #0, c9, c2, #7, x1 +# CHECK-NO-XS: sys #0, c9, c5, #1, x1 +# CHECK-NO-XS: sys #0, c9, c5, #3, x1 +# CHECK-NO-XS: sys #0, c9, c5, #5, x1 +# CHECK-NO-XS: sys #0, c9, c5, #7, x1 +# CHECK-NO-XS: sys #4, c9, c0, #2, x1 +# CHECK-NO-XS: sys #4, c9, c0, #6, x1 +# CHECK-NO-XS: sys #4, c9, c4, #2, x1 +# CHECK-NO-XS: sys #4, c9, c4, #6, x1 +# CHECK-NO-XS: sys #4, c9, c4, #3, x1 +# CHECK-NO-XS: sys #4, c9, c4, #7, x1 +# CHECK-NO-XS: sys #4, c9, c6, #1, x1 +# CHECK-NO-XS: sys #4, c9, c6, #5, x1 +# CHECK-NO-XS: sys #4, c9, c2, #1, x1 +# CHECK-NO-XS: sys #4, c9, c2, #5, x1 +# CHECK-NO-XS: sys #4, c9, c5, #1, x1 +# CHECK-NO-XS: sys #4, c9, c5, #5, x1 +# CHECK-NO-XS: sys #6, c9, c6, #1, x1 +# CHECK-NO-XS: sys #6, c9, c6, #5, x1 +# CHECK-NO-XS: sys #6, c9, c2, #1, x1 +# CHECK-NO-XS: sys #6, c9, c2, #5, x1 +# CHECK-NO-XS: sys #6, c9, c5, #1, x1 +# CHECK-NO-XS: sys #6, c9, c5, #5, x1 +# CHECK-NO-XS: sys #0, c9, c1, #0 +# CHECK-NO-XS: sys #4, c9, c0, #1, x1 diff --git a/llvm/test/MC/Disassembler/AArch64/tme.txt b/llvm/test/MC/Disassembler/AArch64/tme.txt index f250b33e0e1df..3c3d5c1f6ff9a 100644 --- a/llvm/test/MC/Disassembler/AArch64/tme.txt +++ b/llvm/test/MC/Disassembler/AArch64/tme.txt @@ -12,8 +12,8 @@ # CHECK: tcommit # CHECK: tcancel #0x1234 -# NOTEME: mrs -# NOTEME-NEXT: mrs -# NOTEME-NEXT: msr +# NOTME: mrs +# NOTME-NEXT: mrs +# NOTME-NEXT: msr # NOTME: warning: invalid instruction encoding # NOTME-NEXT: [0x80,0x46,0x62,0xd4] diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index 008bb1154e57f..fb999c3349c79 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -48,7 +48,7 @@ # FIXME: LDC encoding information is incorrect. Re-enable this along with more # robust testing for other values when we get it fleshed out and working # properly. -# CHECKx: ldclvc p5, cr15, [r8], #-0 +# COM: CHECK: ldclvc p5, cr15, [r8], #-0 #0x00 0xf5 0x78 0x7c # CHECK: ldc p13, c9, [r2, #0]! diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index e1ba009f3c4c8..9708821affae0 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -39,7 +39,7 @@ 0x04 0x11 0x14 0x9b # CHECK: bal 21104 # The encode/decode functions are not inverses of each other. 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 -0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 +0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 @@ -162,13 +162,13 @@ 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260 -0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20 +0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260 0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260 -0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20 +0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260 0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index 0030e51d6c238..28cd1619e80ad 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -56,7 +56,7 @@ 0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, 43981 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 -0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 +0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 @@ -181,13 +181,13 @@ 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260 -0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20 +0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260 0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260 -0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20 +0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260 0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt index 91831b64d4472..9ed3ac5a8fb9d 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt @@ -156,7 +156,7 @@ # CHECK: dcffixq. 12, 8 0xfd 0x80 0x46 0x45 -# CHECK : dcffixqq 18, 20 +# CHECK: dcffixqq 18, 20 0xfe 0x40 0xa7 0xc4 # CHECK: dctfix 8, 4 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt index 567c4fa5bd5ab..54bf5c4da43c0 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -325,7 +325,7 @@ # CHECK: subfeo 2, 3, 4 0x7c 0x43 0x25 0x10 -# CHECKE: subfeo. 2, 3, 4 +# CHECK: subfeo. 2, 3, 4 0x7c 0x43 0x25 0x11 # CHECK: addme 2, 3 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt index 15427e91a5b2a..269b561c91bf4 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt @@ -313,7 +313,7 @@ # CHECK: subfeo 2, 3, 4 0x10 0x25 0x43 0x7c -# CHECKE: subfeo. 2, 3, 4 +# CHECK: subfeo. 2, 3, 4 0x11 0x25 0x43 0x7c # CHECK: addme 2, 3 diff --git a/llvm/test/MC/Disassembler/X86/x86-16.txt b/llvm/test/MC/Disassembler/X86/x86-16.txt index 7de31411885ce..df91cd0d5bcd9 100644 --- a/llvm/test/MC/Disassembler/X86/x86-16.txt +++ b/llvm/test/MC/Disassembler/X86/x86-16.txt @@ -222,46 +222,46 @@ # CHECK: movw (%eax), %cs 0x67 0x8e 0x08 -# CHECKX: movl %cr0, %eax +# CHECK: movl %cr0, %eax 0x0f 0x20 0xc0 -# CHECKX: movl %cr1, %eax +# CHECK: movl %cr1, %eax 0x0f 0x20 0xc8 -# CHECKX: movl %cr2, %eax +# CHECK: movl %cr2, %eax 0x0f 0x20 0xd0 -# CHECKX: movl %cr3, %eax +# CHECK: movl %cr3, %eax 0x0f 0x20 0xd8 -# CHECKX: movl %cr4, %eax +# CHECK: movl %cr4, %eax 0x0f 0x20 0xe0 -# CHECKX: movl %dr0, %eax +# CHECK: movl %dr0, %eax 0x0f 0x21 0xc0 -# CHECKX: movl %dr1, %eax +# CHECK: movl %dr1, %eax 0x0f 0x21 0xc8 -# CHECKX: movl %dr1, %eax +# CHECK: movl %dr1, %eax 0x0f 0x21 0xc8 -# CHECKX: movl %dr2, %eax +# CHECK: movl %dr2, %eax 0x0f 0x21 0xd0 -# CHECKX: movl %dr3, %eax +# CHECK: movl %dr3, %eax 0x0f 0x21 0xd8 -# CHECKX: movl %dr4, %eax +# CHECK: movl %dr4, %eax 0x0f 0x21 0xe0 -# CHECKX: movl %dr5, %eax +# CHECK: movl %dr5, %eax 0x0f 0x21 0xe8 -# CHECKX: movl %dr6, %eax +# CHECK: movl %dr6, %eax 0x0f 0x21 0xf0 -# CHECKX: movl %dr7, %eax +# CHECK: movl %dr7, %eax 0x0f 0x21 0xf8 # CHECK: wait @@ -765,10 +765,10 @@ # CHECK: fsubp %st, %st(2) 0xde 0xe2 -# CHECKX: nop +# CHECK: nop 0x66 0x90 -# CHECKX: nop +# CHECK: nop 0x90 # CHECK: xchgl %ecx, %eax diff --git a/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s b/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s index a43c8084dbfa0..df05d136d7b97 100644 --- a/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s +++ b/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s @@ -34,4 +34,4 @@ r0 += add(r1, r2) } -# CHECK { r0 += add(r1,r2) } +# CHECK:{ r0 += add(r1,r2) } diff --git a/llvm/test/MC/LoongArch/Relocations/relax-align.s b/llvm/test/MC/LoongArch/Relocations/relax-align.s index 477d5ca24ec7d..3103a7b1055cb 100644 --- a/llvm/test/MC/LoongArch/Relocations/relax-align.s +++ b/llvm/test/MC/LoongArch/Relocations/relax-align.s @@ -58,7 +58,7 @@ break 6 # RELAX-INSTR-NEXT: nop ret -# INSNR-NEXT: ret +# INSTR-NEXT: ret ## Test the symbol index is different from .text. .section .text2, "ax" diff --git a/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s b/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s index af8ba714ef80a..90b3f4f4951df 100644 --- a/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s +++ b/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s @@ -17,33 +17,33 @@ fdadd.x %fp3, %fp4 fsub.x %fp1, %fp2 ; CHECK: fssub.x %fp3, %fp4 -; CHECK-SAME; encoding: [0xf2,0x00,0x0e,0x68] +; CHECK-SAME: encoding: [0xf2,0x00,0x0e,0x68] fssub.x %fp3, %fp4 ; CHECK: fdsub.x %fp5, %fp6 -; CHECK-SAME; encoding: [0xf2,0x00,0x17,0x6c] +; CHECK-SAME: encoding: [0xf2,0x00,0x17,0x6c] fdsub.x %fp5, %fp6 ; CHECK: fmul.x %fp2, %fp3 -; CHECK-SAME; encoding: [0xf2,0x00,0x09,0xa3] +; CHECK-SAME: encoding: [0xf2,0x00,0x09,0xa3] fmul.x %fp2, %fp3 ; CHECK: fsmul.x %fp4, %fp5 -; CHECK-SAME; encoding: [0xf2,0x00,0x12,0xe3] +; CHECK-SAME: encoding: [0xf2,0x00,0x12,0xe3] fsmul.x %fp4, %fp5 ; CHECK: fdmul.x %fp6, %fp7 -; CHECK-SAME; encoding: [0xf2,0x00,0x1b,0xe7] +; CHECK-SAME: encoding: [0xf2,0x00,0x1b,0xe7] fdmul.x %fp6, %fp7 ; CHECK: fdiv.x %fp3, %fp4 -; CHECK-SAME; encoding: [0xf2,0x00,0x0e,0x20] +; CHECK-SAME: encoding: [0xf2,0x00,0x0e,0x20] fdiv.x %fp3, %fp4 ; CHECK: fsdiv.x %fp5, %fp6 -; CHECK-SAME; encoding: [0xf2,0x00,0x17,0x60] +; CHECK-SAME: encoding: [0xf2,0x00,0x17,0x60] fsdiv.x %fp5, %fp6 ; CHECK: fddiv.x %fp7, %fp0 -; CHECK-SAME; encoding: [0xf2,0x00,0x1c,0x64] +; CHECK-SAME: encoding: [0xf2,0x00,0x1c,0x64] fddiv.x %fp7, %fp0 diff --git a/llvm/test/MC/MachO/lto-set-conditional.s b/llvm/test/MC/MachO/lto-set-conditional.s index 0007d4a259cbc..1ea26eaa231ec 100644 --- a/llvm/test/MC/MachO/lto-set-conditional.s +++ b/llvm/test/MC/MachO/lto-set-conditional.s @@ -57,14 +57,14 @@ a: # CHECK: Symbol { # CHECK-NEXT: Name: m # CHECK: Flags [ -# CHECK-NOT : NoDeadStrip +# CHECK-NOT: NoDeadStrip # CHECK: Value: 0x2 m: # CHECK: Symbol { # CHECK-NEXT: Name: h # CHECK: Flags [ -# CHECK-NOT : NoDeadStrip +# CHECK-NOT: NoDeadStrip # CHECK: Value: 0x2 .lto_set_conditional h, m diff --git a/llvm/test/MC/Mips/expansion-jal-sym-pic.s b/llvm/test/MC/Mips/expansion-jal-sym-pic.s index c7b5ccc1880bd..e843b4a2f4f1b 100644 --- a/llvm/test/MC/Mips/expansion-jal-sym-pic.s +++ b/llvm/test/MC/Mips/expansion-jal-sym-pic.s @@ -227,12 +227,12 @@ local_label: # XO32-NEXT: .reloc ($tmp1), R_MIPS_JALR, weak_label # ELF-XO32: 3c 19 00 00 lui $25, 0 -# ELF-XO32-MEXT: R_MIPS_CALL_HI16 weak_label -# ELF-XO32-MEXT: 03 3c c8 21 addu $25, $25, $gp -# ELF-XO32-MEXT: 8f 39 00 00 lw $25, 0($25) -# ELF-XO32-MEXT: R_MIPS_CALL_LO16 weak_label -# ELF-XO32-MEXT: 03 20 f8 09 jalr $25 -# ELF-XO32-MEXT: R_MIPS_JALR weak_label +# ELF-XO32-NEXT: R_MIPS_CALL_HI16 weak_label +# ELF-XO32-NEXT: 03 3c c8 21 addu $25, $25, $gp +# ELF-XO32-NEXT: 8f 39 00 00 lw $25, 0($25) +# ELF-XO32-NEXT: R_MIPS_CALL_LO16 weak_label +# ELF-XO32-NEXT: 03 20 f8 09 jalr $25 +# ELF-XO32-NEXT: R_MIPS_JALR weak_label # N32: lw $25, %call16(weak_label)($gp) # encoding: [0x8f,0x99,A,A] # N32: # fixup A - offset: 0, value: %call16(weak_label), kind: fixup_Mips_CALL16 @@ -623,7 +623,7 @@ local_label: # O32-MM-NEXT: # fixup A - offset: 0, value: %got(.text), kind: fixup_MICROMIPS_GOT16 # O32-MM-NEXT: addiu $25, $25, %lo(.text) # encoding: [0x33,0x39,A,A] # O32-MM-NEXT: # fixup A - offset: 0, value: %lo(.text), kind: fixup_MICROMIPS_LO16 -# O42-MM-NEXT: .reloc ($tmp3), R_MICROMIPS_JALR, .text +# O32-MM-NEXT: .reloc ($tmp3), R_MICROMIPS_JALR, .text # MIPS: jalr $25 # encoding: [0x03,0x20,0xf8,0x09] # MM: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c] @@ -689,7 +689,7 @@ local_label: # O32-MM-NEXT: # fixup A - offset: 0, value: %got(.text+8), kind: fixup_MICROMIPS_GOT16 # O32-MM-NEXT: addiu $25, $25, %lo(.text+8) # encoding: [0x33,0x39,A,A] # O32-MM-NEXT: # fixup A - offset: 0, value: %lo(.text+8), kind: fixup_MICROMIPS_LO16 -# O42-MM-NEXT: .reloc ($tmp4), R_MICROMIPS_JALR, .text +# O32-MM-NEXT: .reloc ($tmp4), R_MICROMIPS_JALR, .text # MIPS: jalr $25 # encoding: [0x03,0x20,0xf8,0x09] # MM: jalr $ra, $25 # encoding: [0x03,0xf9,0x0f,0x3c] diff --git a/llvm/test/MC/Mips/macro-rem.s b/llvm/test/MC/Mips/macro-rem.s index 40812949664d6..1f10a5392c07f 100644 --- a/llvm/test/MC/Mips/macro-rem.s +++ b/llvm/test/MC/Mips/macro-rem.s @@ -95,7 +95,7 @@ # CHECK-NOTRAP: bnez $6, $tmp2 # encoding: [A,A,0xc0,0x14] # CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x1a,0x00,0xa6,0x00] # CHECK-NOTRAP: break 7 # encoding: [0x0d,0x00,0x07,0x00] -# CHECk-NOTRAP: $tmp2 +# CHECK-NOTRAP: $tmp2 # CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK-NOTRAP: bne $6, $1, $tmp3 # encoding: [A,A,0xc1,0x14] # CHECK-NOTRAP: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid.s b/llvm/test/MC/Mips/micromips-dsp/invalid.s index 05fc77440d3ef..52120a02ce8cd 100644 --- a/llvm/test/MC/Mips/micromips-dsp/invalid.s +++ b/llvm/test/MC/Mips/micromips-dsp/invalid.s @@ -9,16 +9,14 @@ shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index a995c37b15c3a..e3a68cb3bd444 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -302,13 +302,13 @@ sce $2, 8($4) # CHECK: sce $2, 8($4) # encoding: [0x60,0x syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c] syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] # FIXME: ldc1 should accept uneven registers -# ldc1 $f7, 300($10) # -CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c] +# ldc1 $f7, 300($10) # COM: CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c] ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c] lwc1 $f2, 4($6) # CHECK: lwc1 $f2, 4($6) # encoding: [0x9c,0x46,0x00,0x04] # CHECK-NEXT: # ; // WRITER-NEXT: }; // ALIAS: static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { -// ALIAS-NEXT switch (VariantID) { -// ALIAS-NEXT case 0: -// ALIAS-NEXT switch (Mnemonic.size()) { -// ALIAS-NEXT default: break; -// ALIAS-NEXT case 5: // 2 strings to match. -// ALIAS-NEXT if (memcmp(Mnemonic.data()+0, "inst", 4) != 0) -// ALIAS-NEXT break; -// ALIAS-NEXT switch (Mnemonic[4]) { -// ALIAS-NEXT default: break; -// ALIAS-NEXT case 'a': // 1 string to match. -// ALIAS-NEXT Mnemonic = "ainst"; // "insta" -// ALIAS-NEXT return; -// ALIAS-NEXT case 'b': // 1 string to match. -// ALIAS-NEXT Mnemonic = "binst"; // "instb" -// ALIAS-NEXT return; +// ALIAS-NEXT: switch (VariantID) { +// ALIAS-NEXT: case 0: +// ALIAS-NEXT: switch (Mnemonic.size()) { +// ALIAS-NEXT: default: break; +// ALIAS-NEXT: case 5: // 2 strings to match. +// ALIAS-NEXT: if (memcmp(Mnemonic.data()+0, "inst", 4) != 0) +// ALIAS-NEXT: break; +// ALIAS-NEXT: switch (Mnemonic[4]) { +// ALIAS-NEXT: default: break; +// ALIAS-NEXT: case 'a': // 1 string to match. +// ALIAS-NEXT: Mnemonic = "ainst"; // "insta" +// ALIAS-NEXT: return; +// ALIAS-NEXT: case 'b': // 1 string to match. +// ALIAS-NEXT: Mnemonic = "binst"; // "instb" +// ALIAS-NEXT: return; diff --git a/llvm/test/Transforms/Attributor/returned.ll b/llvm/test/Transforms/Attributor/returned.ll index e94cb95069694..2908bfff1bdde 100644 --- a/llvm/test/Transforms/Attributor/returned.ll +++ b/llvm/test/Transforms/Attributor/returned.ll @@ -1415,7 +1415,7 @@ define ptr @dont_use_const() #0 { ; ; Verify we do not derive constraints for @_Z3fooP1X as if it was returning `null`. ; -; CHEKC-NOT: noalias +; CHECK-NOT: noalias ; CHECK-NOT: align 536870912 %struct.Y = type { %struct.X } diff --git a/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll b/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll index 256261d0dd11f..ea8abfb554d12 100644 --- a/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll +++ b/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll @@ -72,7 +72,7 @@ declare void @dummy1(ptr, ptr, ptr, ptr, ptr, ptr) ;CHECK: call void @dummy4() ;CHECK-LABEL: NextCond.split: ;CHECK: call void @dummy3() -;CheCK-LABEL: CallSiteBB: +;CHECK-LABEL: CallSiteBB: ;CHECK: call void @foo(i1 %tobool1) define void @caller2(i1 %c, ptr %a_elt, ptr %b_elt, ptr %c_elt) { entry: diff --git a/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll b/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll index fd3b7bd815300..531d3c36ac299 100644 --- a/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll +++ b/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll @@ -26,7 +26,7 @@ step: invoke void @llvm.coro.await.suspend.void(ptr %awaiter, ptr %hdl, ptr @await_suspend_wrapper_void) to label %step.continue unwind label %pad -; CHECK [[STEP_CONT]]: +; CHECK: [[STEP_CONT]]: step.continue: %suspend = call i8 @llvm.coro.suspend(token %save, i1 false) switch i8 %suspend, label %ret [ diff --git a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll index 2978f85be2385..37fb9fea77044 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll @@ -39,7 +39,7 @@ ; CHECK-DAG: ![[UNALIGNED_UNKNOWN]] = !DIDerivedType(tag: DW_TAG_member, name: "_6",{{.*}}baseType: ![[UNALIGNED_UNKNOWN_BASE:[0-9]+]], size: 9 ; CHECK-DAG: ![[UNALIGNED_UNKNOWN_BASE]] = !DICompositeType(tag: DW_TAG_array_type, baseType: ![[UNKNOWN_TYPE_BASE]], size: 16,{{.*}} elements: ![[UNALIGNED_UNKNOWN_ELEMENTS:[0-9]+]]) ; CHECK-DAG: ![[UNALIGNED_UNKNOWN_ELEMENTS]] = !{![[UNALIGNED_UNKNOWN_SUBRANGE:[0-9]+]]} -; CHECk-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0) +; CHECK-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0) ; CHECK-DAG: ![[STRUCT]] = !DIDerivedType(tag: DW_TAG_member, name: "struct_big_structure_7", scope: ![[FRAME_TYPE]], file: ![[FILE]], line: [[PROMISE_VAR_LINE]], baseType: ![[STRUCT_BASE:[0-9]+]] ; CHECK-DAG: ![[STRUCT_BASE]] = !DICompositeType(tag: DW_TAG_structure_type, name: "struct_big_structure"{{.*}}, align: 64, flags: DIFlagArtificial, elements: ![[STRUCT_ELEMENTS:[0-9]+]] ; CHECK-DAG: ![[STRUCT_ELEMENTS]] = !{![[MEM_TYPE:[0-9]+]]} diff --git a/llvm/test/Transforms/FunctionAttrs/nonnull.ll b/llvm/test/Transforms/FunctionAttrs/nonnull.ll index 4432c4f3c541a..2a78291b11e86 100644 --- a/llvm/test/Transforms/FunctionAttrs/nonnull.ll +++ b/llvm/test/Transforms/FunctionAttrs/nonnull.ll @@ -716,7 +716,6 @@ declare i8 @use1safecall(ptr %x) nounwind willreturn ; nounwind+willreturn guara ; Without noundef, nonnull cannot be propagated to the parent define void @parent_poison(ptr %a) { -; FNATTR-LABEL: @parent_poison(ptr %a) ; FNATTRS-LABEL: define void @parent_poison( ; FNATTRS-SAME: ptr [[A:%.*]]) { ; FNATTRS-NEXT: call void @use1nonnull_without_noundef(ptr [[A]]) diff --git a/llvm/test/Transforms/GVNSink/sink-common-code.ll b/llvm/test/Transforms/GVNSink/sink-common-code.ll index 5c83a19c35cf1..c5871bb8e8404 100644 --- a/llvm/test/Transforms/GVNSink/sink-common-code.ll +++ b/llvm/test/Transforms/GVNSink/sink-common-code.ll @@ -78,12 +78,12 @@ declare i32 @foo(i32, i32) nounwind readnone ; ret i32 %ret ;} ; -; -CHECK-LABEL: test3 -; -CHECK: select -; -CHECK: call -; -CHECK: call -; -CHECK: add -; -CHECK-NOT: br +; COM: CHECK-LABEL: test3 +; COM: CHECK: select +; COM: CHECK: call +; COM: CHECK: call +; COM: CHECK: add +; COM: CHECK-NOT: br define i32 @test4(i1 zeroext %flag, i32 %x, ptr %y) { entry: diff --git a/llvm/test/Transforms/Inline/update_invoke_prof.ll b/llvm/test/Transforms/Inline/update_invoke_prof.ll index f6b86dfe5bb1b..b5fb669c93cbd 100644 --- a/llvm/test/Transforms/Inline/update_invoke_prof.ll +++ b/llvm/test/Transforms/Inline/update_invoke_prof.ll @@ -66,7 +66,7 @@ ret: ; CHECK: invoke void @callee2( ; CHECK-NEXT: {{.*}} !prof ![[PROF3:[0-9]+]] -; CHECK-LABL: @callee( +; CHECK-LABEL: @callee( ; CHECK: invoke void %func( ; CHECK-NEXT: {{.*}} !prof ![[PROF4:[0-9]+]] ; CHECK: invoke void @callee1( diff --git a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll index e379b32b45734..62573398fc16a 100644 --- a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll +++ b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll @@ -56,7 +56,7 @@ entry: call void @llvm.lifetime.start.p0(i64 1, ptr %text) call void @llvm.lifetime.end.p0(i64 1, ptr %text) - ; CHECK-NO: call void @llvm.lifetime + ; CHECK-NOT: call void @llvm.lifetime call void @foo(ptr %text) ; Keep alloca alive diff --git a/llvm/test/Transforms/InstCombine/str-int-2.ll b/llvm/test/Transforms/InstCombine/str-int-2.ll index ae67422d12078..b6c90ef04a3e2 100644 --- a/llvm/test/Transforms/InstCombine/str-int-2.ll +++ b/llvm/test/Transforms/InstCombine/str-int-2.ll @@ -119,7 +119,7 @@ define i64 @atol_test() #0 { ; CHECK-LABEL: @atol_test( ; CHECK-NEXT: ret i64 499496729 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i64 @atol(ptr @.str.6) #4 ret i64 %call } @@ -136,7 +136,7 @@ define i64 @strtoll_test() #0 { ; CHECK-LABEL: @strtoll_test( ; CHECK-NEXT: ret i64 4994967295 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i64 @strtoll(ptr @.str.7, ptr null, i32 10) #5 ret i64 %call } diff --git a/llvm/test/Transforms/InstCombine/str-int.ll b/llvm/test/Transforms/InstCombine/str-int.ll index ee8d04d2f0e2a..ff8f8faeb19d3 100644 --- a/llvm/test/Transforms/InstCombine/str-int.ll +++ b/llvm/test/Transforms/InstCombine/str-int.ll @@ -123,7 +123,7 @@ define i32 @atol_test() #0 { ; CHECK-LABEL: @atol_test( ; CHECK-NEXT: ret i32 499496729 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i32 @atol(ptr @.str.6) #4 ret i32 %call } @@ -140,7 +140,7 @@ define i64 @strtoll_test() #0 { ; CHECK-LABEL: @strtoll_test( ; CHECK-NEXT: ret i64 4994967295 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i64 @strtoll(ptr @.str.7, ptr null, i32 10) #5 ret i64 %call } diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll index a732984d697ad..754e0d32cc1d0 100644 --- a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll +++ b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll @@ -32,7 +32,7 @@ for.end: ret void } -; CHECK_LABEL: @funca +; CHECK-LABEL: @funca ; Peeled iteration ; CHECK: %[[REG1:[0-9]+]] = load i8, ptr @Comma diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll index 75f03c7b1a699..c7edf9bdfaf6b 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll @@ -259,7 +259,7 @@ for.cond.cleanup: ; preds = %for.body define i4 @test_i4_load(ptr %ddst) { ; CHECK-LABEL: define i4 @test_i4_load ; CHECK-NOT: vector.body: -; CHECk: ret i4 %{{.*}} +; CHECK: ret i4 %{{.*}} ; entry: br label %for.body @@ -282,7 +282,7 @@ define i8 @test_load_i8(ptr %ddst) { ; CHECK-LABEL: @test_load_i8( ; CHECK: vector.body: ; CHECK: load <4 x i8>, ptr {{.*}}, align 1, !nontemporal !0 -; CHECk: ret i8 %{{.*}} +; CHECK: ret i8 %{{.*}} ; entry: br label %for.body @@ -305,7 +305,7 @@ define half @test_half_load(ptr %ddst) { ; CHECK-LABEL: @test_half_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x half>, ptr {{.*}}, align 2, !nontemporal !0 -; CHECk: ret half %{{.*}} +; CHECK: ret half %{{.*}} ; entry: br label %for.body @@ -328,7 +328,7 @@ define i16 @test_i16_load(ptr %ddst) { ; CHECK-LABEL: @test_i16_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i16>, ptr {{.*}}, align 2, !nontemporal !0 -; CHECk: ret i16 %{{.*}} +; CHECK: ret i16 %{{.*}} ; entry: br label %for.body @@ -351,7 +351,7 @@ define i32 @test_i32_load(ptr %ddst) { ; CHECK-LABEL: @test_i32_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i32>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret i32 %{{.*}} +; CHECK: ret i32 %{{.*}} ; entry: br label %for.body @@ -373,7 +373,7 @@ for.cond.cleanup: ; preds = %for.body define i33 @test_i33_load(ptr %ddst) { ; CHECK-LABEL: @test_i33_load ; CHECK-NOT: vector.body: -; CHECk: ret i33 %{{.*}} +; CHECK: ret i33 %{{.*}} ; entry: br label %for.body @@ -395,7 +395,7 @@ for.cond.cleanup: ; preds = %for.body define i40 @test_i40_load(ptr %ddst) { ; CHECK-LABEL: @test_i40_load ; CHECK-NOT: vector.body: -; CHECk: ret i40 %{{.*}} +; CHECK: ret i40 %{{.*}} ; entry: br label %for.body @@ -418,7 +418,7 @@ define i64 @test_i64_load(ptr %ddst) { ; CHECK-LABEL: @test_i64_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i64>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret i64 %{{.*}} +; CHECK: ret i64 %{{.*}} ; entry: br label %for.body @@ -441,7 +441,7 @@ define double @test_double_load(ptr %ddst) { ; CHECK-LABEL: @test_double_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x double>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret double %{{.*}} +; CHECK: ret double %{{.*}} ; entry: br label %for.body @@ -464,7 +464,7 @@ define i128 @test_i128_load(ptr %ddst) { ; CHECK-LABEL: @test_i128_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i128>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret i128 %{{.*}} +; CHECK: ret i128 %{{.*}} ; entry: br label %for.body @@ -486,7 +486,7 @@ for.cond.cleanup: ; preds = %for.body define i256 @test_256_load(ptr %ddst) { ; CHECK-LABEL: @test_256_load ; CHECK-NOT: vector.body: -; CHECk: ret i256 %{{.*}} +; CHECK: ret i256 %{{.*}} ; entry: br label %for.body diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll index 7c1247e9ebc8f..36a8b366381ba 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll @@ -911,7 +911,7 @@ define float @fadd_scalar_vf_fmf(ptr noalias nocapture readonly %a, i64 %n) { ; CHECK-UNORDERED: [[SUM_07:%.*]] = phi float [ [[MERGE_RDX]], %scalar.ph ], [ [[FADD5:%.*]], %for.body ] ; CHECK-UNORDERED: [[LOAD5:%.*]] = load float, ptr ; CHECK-UNORDERED: [[FADD5]] = fadd nnan float [[LOAD5]], [[SUM_07]] -; CHECK-UORDERED: for.end +; CHECK-UNORDERED: for.end ; CHECK-UNORDERED: [[RES:%.*]] = phi float [ [[FADD5]], %for.body ], [ [[BIN_RDX3]], %middle.block ] ; CHECK-UNORDERED: ret float [[RES]] diff --git a/llvm/test/Transforms/LoopVectorize/branch-weights.ll b/llvm/test/Transforms/LoopVectorize/branch-weights.ll index e4baae43aa797..56b2f70dacbe4 100644 --- a/llvm/test/Transforms/LoopVectorize/branch-weights.ll +++ b/llvm/test/Transforms/LoopVectorize/branch-weights.ll @@ -75,8 +75,8 @@ exit: ; CHECK: [[PROF_F0_ENTRY]] = !{!"branch_weights", i32 12, i32 1} ; CHECK: [[PROF_F0_UNLIKELY]] = !{!"branch_weights", i32 1, i32 127} -; CEHCK: [[PROF_F0_VECTOR_BODY]] = !{!"branch_weights", i32 1, i32 307} +; CHECK: [[PROF_F0_VECTOR_BODY]] = !{!"branch_weights", i32 1, i32 307} ; CHECK: [[PROF_F0_MIDDLE_BLOCKS]] = !{!"branch_weights", i32 1, i32 3} ; CHECK: [[PROF_F0_VEC_EPILOGUE_SKIP]] = !{!"branch_weights", i32 4, i32 0} ; CHECK: [[PROF_F0_VEC_EPILOG_VECTOR_BODY]] = !{!"branch_weights", i32 0, i32 0} -; CEHCK: [[PROF_F0_LOOP]] = !{!"branch_weights", i32 2, i32 1} +; CHECK: [[PROF_F0_LOOP]] = !{!"branch_weights", i32 2, i32 1} diff --git a/llvm/test/Transforms/LoopVectorize/memdep.ll b/llvm/test/Transforms/LoopVectorize/memdep.ll index b891b4312f18d..eb8c75741c0c0 100644 --- a/llvm/test/Transforms/LoopVectorize/memdep.ll +++ b/llvm/test/Transforms/LoopVectorize/memdep.ll @@ -244,7 +244,7 @@ for.end: ; RIGHTVF-LABEL: @pr34283 ; RIGHTVF: <4 x i64> -; WRONGVF-LABLE: @pr34283 +; WRONGVF-LABEL: @pr34283 ; WRONGVF-NOT: <8 x i64> @a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16 diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll index 430baa1cb4f8c..c426737963c52 100644 --- a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll +++ b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-non-integral-addrspace.ll @@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:10:11:12:13" declare i64 @julia_steprange_last_4949() define void @"japi1_align!_9477"(ptr %arg) { -; LV-LAVEL: L26.lver.check +; LV-LABEL: L26.lver.check ; LV: [[OFMul:%[^ ]*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 4, i64 [[Step:%[^ ]*]]) ; LV-NEXT: [[OFMulResult:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 0 ; LV-NEXT: [[OFMulOverflow:%[^ ]*]] = extractvalue { i64, i1 } [[OFMul]], 1 diff --git a/llvm/test/Transforms/ObjCARC/rv.ll b/llvm/test/Transforms/ObjCARC/rv.ll index ae35d28e5b011..209b49b30f4a5 100644 --- a/llvm/test/Transforms/ObjCARC/rv.ll +++ b/llvm/test/Transforms/ObjCARC/rv.ll @@ -103,9 +103,9 @@ entry: ; directly to a return value. ; TODO -; HECK: define ptr @test5 -; HECK: call ptr @returner() -; HECK-NEXT: ret ptr %call +; COM: CHECK: define ptr @test5 +; COM: CHECK: call ptr @returner() +; COM: CHECK-NEXT: ret ptr %call ;define ptr @test5() { ;entry: ; %call = call ptr @returner() diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll index d279f342666a7..f30abc32468e7 100644 --- a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll +++ b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll @@ -37,7 +37,7 @@ for.cond: ; preds = %for.inc, %entry for.body: ; preds = %for.cond ; CHECK: for.body: ; NOTENTRY: %pgocount1 = load i64, ptr @"__profc_?run@@YAXH@Z" -; TENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH@Z", i32 0, i32 1) +; ENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH@Z", i32 0, i32 1) ; CHECK: %1 = add i64 %pgocount1, 1 ; NOTENTRY: store i64 %1, ptr @"__profc_?run@@YAXH@Z" ; ENTRY: store i64 %1, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH@Z", i32 0, i32 1) diff --git a/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll b/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll index 5e23c93af71d0..9deffd715f448 100644 --- a/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll +++ b/llvm/test/Transforms/PGOProfile/icp_covariant_invoke_return.ll @@ -35,16 +35,16 @@ invoke.cont: ; ICALL-PROM: [[DIRCALL_RET:%[0-9]+]] = invoke ptr @_ZN1D4funcEv(ptr %call) ; ICALL-PROM-NEXT: to label %if.end.icp unwind label %lpad ; ICALL-PROM:if.false.orig_indirect: -; ICAll-PROM: %call2 = invoke ptr %tmp3(ptr %call) -; ICAll-PROM: to label %invoke.cont1 unwind label %lpad +; ICALL-PROM: %call2 = invoke ptr %tmp3(ptr %call) +; ICALL-PROM: to label %invoke.cont1 unwind label %lpad ; ICALL-PROM:if.end.icp: ; ICALL-PROM: br label %invoke.cont1 %call2 = invoke ptr %tmp3(ptr %call) to label %invoke.cont1 unwind label %lpad, !prof !1 invoke.cont1: -; ICAll-PROM: [[PHI_RET:%[0-9]+]] = phi ptr [ %call2, %if.false.orig_indirect ], [ [[DIRCALL_RET]], %if.end.icp ] -; ICAll-PROM: %isnull = icmp eq ptr [[PHI_RET]], null +; ICALL-PROM: [[PHI_RET:%[0-9]+]] = phi ptr [ %call2, %if.false.orig_indirect ], [ [[DIRCALL_RET]], %if.end.icp ] +; ICALL-PROM: %isnull = icmp eq ptr [[PHI_RET]], null %isnull = icmp eq ptr %call2, null br i1 %isnull, label %delete.end, label %delete.notnull diff --git a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll index e6c2a7e629a5d..cea752ad6898d 100644 --- a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll +++ b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll @@ -21,7 +21,7 @@ entry: define float @f_writeonly(float %val) { ; CHECK-LABEL: @f_writeonly( -; CHECK-NEXt: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]] +; CHECK-NEXT: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]] %res = tail call float @sqrtf(float %val) writeonly ret float %res } diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll index f0b6fdf62d969..d52794e0d2faa 100644 --- a/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll +++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll @@ -20,8 +20,8 @@ F: br label %Merge Merge: ;; Check branch T and F are gone, and their probes (probe 2 and 3) are gone too. -; JT-LABEL-NO: T -; JT-LABEL-NO: F +; JT-NOT{LITERAL}: T: +; JT-NOT{LITERAL}: F: ; JT-LABEL: Merge ; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 4 ; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 3 @@ -43,8 +43,8 @@ Merge: define i32 @test(i32 %a, i32 %b, i32 %c) { ;; Check block bb1 and bb2 are gone, and their probes (probe 2 and 3) are gone too. ; SC-LABEL: @test( -; SC-LABEL-NO: bb1 -; SC-LABEL-NO: bb2 +; SC-NOT{LITERAL}: bb1: +; SC-NOT{LITERAL}: bb2: ; SC: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 0 ; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 2 ; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 3 diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll index 5d01e78221e38..3bc18c7cdd7bf 100644 --- a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll +++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll @@ -10,7 +10,7 @@ entry: if.end: ; preds = %entry ;; Check pseudo probes are next to each other at the beginning of this block. -; IR-label: if.end +; IR-LABEL: if.end ; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1) ; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 3, i32 0, i64 -1) call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1) @@ -19,7 +19,7 @@ if.end: ; preds = %entry %2 = and i16 %1, 16 %3 = icmp eq i16 %2, 0 ;; Check the load-and-cmp sequence is fold into a test instruction. -; MIR-label: bb.1.if.end +; MIR-LABEL: bb.1.if.end ; MIR: %[[#REG:]]:gr64 = IMPLICIT_DEF ; MIR: TEST8mi killed %[[#REG]], 1, $noreg, 0, $noreg, 16 ; MIR: JCC_1 diff --git a/llvm/test/Verifier/convergencectrl-invalid.ll b/llvm/test/Verifier/convergencectrl-invalid.ll index e1fffcd1c6033..90f592365b2d3 100644 --- a/llvm/test/Verifier/convergencectrl-invalid.ll +++ b/llvm/test/Verifier/convergencectrl-invalid.ll @@ -21,7 +21,7 @@ define void @wrong_token() { } ; CHECK: Convergence control token can only be used in a convergent call. -; CHECK-NEXT call void @g(){{.*}}%t05_tok1 +; CHECK-NEXT: call void @g(){{.*}}%t05_tok1 define void @missing.attribute() { %t05_tok1 = call token @llvm.experimental.convergence.anchor() call void @g() [ "convergencectrl"(token %t05_tok1) ] @@ -47,7 +47,7 @@ define void @multiple_bundles() { } ; CHECK: Cannot mix controlled and uncontrolled convergence in the same function -; CHECK-NEXT call void @f() +; CHECK-NEXT: call void @f() define void @mixed1() { call void @g() ; not convergent %t10_tok1 = call token @llvm.experimental.convergence.anchor() diff --git a/llvm/test/tools/dsymutil/fat-binary-output.test b/llvm/test/tools/dsymutil/fat-binary-output.test index 46b86b0513735..6ab833b01f1a3 100644 --- a/llvm/test/tools/dsymutil/fat-binary-output.test +++ b/llvm/test/tools/dsymutil/fat-binary-output.test @@ -26,7 +26,7 @@ CHECK: DW_AT_name{{.*}} "x86_64h_var" CHECK: Running lipo CHECK-NEXT: lipo -create -CHECK-SAME [[TMP_PATH:.*?]]fat-test.dylib.tmp{{......}}.dwarf [[TMP_PATH]]fat-test.dylib.tmp{{......}}.dwarf [[TMP_PATH]]fat-test.dylib.tmp{{......}}.dwarf +CHECK-SAME: [[TMP_PATH:.*?]]fat-test.dylib.tmp{{......}}.dwarf [[TMP_PATH]]fat-test.dylib.tmp{{......}}.dwarf [[TMP_PATH]]fat-test.dylib.tmp{{......}}.dwarf CHECK-SAME: -segalign x86_64 20 -segalign i386 20 -segalign x86_64h 20 CHECK-SAME: -output [[INPUTS_PATH]]fat-test.dylib.dwarf diff --git a/llvm/test/tools/gold/X86/global_with_section.ll b/llvm/test/tools/gold/X86/global_with_section.ll index 2ba0a16e23782..e4ec41ea4dc59 100644 --- a/llvm/test/tools/gold/X86/global_with_section.ll +++ b/llvm/test/tools/gold/X86/global_with_section.ll @@ -45,7 +45,7 @@ target triple = "x86_64-unknown-linux-gnu" ; Confirm via a variable with a non-C identifier section that we are getting ; the expected internalization. -; CHECK-REGULARLTO-DAG: @var_with_nonC_section = internal global i32 0, section ".nonCsection" +; CHECK2-REGULARLTO-DAG: @var_with_nonC_section = internal global i32 0, section ".nonCsection" ; Check we dropped definition of dead variable. ; CHECK-THINLTO-NOT: @var_with_nonC_section @var_with_nonC_section = global i32 0, section ".nonCsection" diff --git a/llvm/test/tools/llvm-ar/replace-update.test b/llvm/test/tools/llvm-ar/replace-update.test index c056565f144c5..498febdac0193 100644 --- a/llvm/test/tools/llvm-ar/replace-update.test +++ b/llvm/test/tools/llvm-ar/replace-update.test @@ -57,7 +57,7 @@ # MULTIPLE-SYM: symbolnew1 # MULTIPLE-SYM-NEXT: symbol2 -# MULTIPLE-SYM-NEXTs: symbolnew3 +# MULTIPLE-SYM-NEXT: symbolnew3 ## Replace newer members with multiple older files: # RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o diff --git a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json index ce13fc2ff6e34..33c517da91b5e 100644 --- a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json +++ b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json @@ -29,7 +29,7 @@ CHECK-SAME: {"branches":{"count":0,"covered":0,"notcovered":0,"percent":0}, CHECK-SAME: "functions":{"count":1,"covered":1,"percent":100}, CHECK-SAME: "instantiations":{"count":1,"covered":1,"percent":100}, CHECK-SAME: "lines":{"count":1,"covered":1,"percent":100}, -CHECk-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0}, +CHECK-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0}, CHECK-SAME: "regions":{"count":1,"covered":1,"notcovered":0,"percent":100}}} CHECK-SAME: ], CHECK-SAME: "type":"llvm.coverage.json.export" diff --git a/llvm/test/tools/llvm-cov/coverage_watermark.test b/llvm/test/tools/llvm-cov/coverage_watermark.test index 5c48b4f0fb4bf..97b9d240e0b09 100644 --- a/llvm/test/tools/llvm-cov/coverage_watermark.test +++ b/llvm/test/tools/llvm-cov/coverage_watermark.test @@ -29,7 +29,7 @@ ORIGIN: RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -format html -show-region-summary -show-instantiation-summary -o %t.html.dir -path-equivalence=/tmp,%S -coverage-watermark 80,70 %S/showTemplateInstantiations.cpp RUN: FileCheck -check-prefix=DOWNGRADE1 %s -input-file %t.html.dir/index.html -DOWNGRADE:1 Totals +DOWNGRADE1: Totals DOWNGRADE1: DOWNGRADE1: 100.00% (2/2) DOWNGRADE1: @@ -45,7 +45,7 @@ DOWNGRADE1: RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -format html -show-region-summary -show-instantiation-summary -o %t.html.dir -path-equivalence=/tmp,%S -coverage-watermark 70,50 %S/showTemplateInstantiations.cpp RUN: FileCheck -check-prefix=DOWNGRADE2 %s -input-file %t.html.dir/index.html -DOWNGRADE:1 Totals +DOWNGRADE2: Totals DOWNGRADE2: DOWNGRADE2: 100.00% (2/2) DOWNGRADE2: @@ -54,6 +54,6 @@ DOWNGRADE2: DOWNGRADE2: 75.00% (9/12) DOWNGRADE2: DOWNGRADE2: 66.67% (4/6) -DOWNGRADE1: -DOWNGRADE1: - (0/0) -DOWNGRADE1: +DOWNGRADE2: +DOWNGRADE2: - (0/0) +DOWNGRADE2: diff --git a/llvm/test/tools/llvm-cov/zeroFunctionFile.c b/llvm/test/tools/llvm-cov/zeroFunctionFile.c index f463007fe7f60..1e5467d497aaa 100644 --- a/llvm/test/tools/llvm-cov/zeroFunctionFile.c +++ b/llvm/test/tools/llvm-cov/zeroFunctionFile.c @@ -15,6 +15,6 @@ int main() { // RUN: llvm-cov show -j 1 %S/Inputs/zeroFunctionFile.covmapping -format html -instr-profile %t.profdata -o %t.dir // RUN: FileCheck %s -input-file=%t.dir/index.html -check-prefix=HTML -// HTML-NO: 0.00% (0/0) +// HTML-NOT: 0.00% (0/0) // HTML: Files which contain no functions // HTML: zeroFunctionFile.h diff --git a/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s b/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s index e56fcd8352ac0..31bcaaccf4698 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s @@ -3,7 +3,7 @@ # CHECK: error: Simplified template DW_AT_name could not be reconstituted: # CHECK: original: t1 -# CHECK reconstituted: t1 +# CHECK: reconstituted: t1 .text .file "verify.cpp" .file 1 "/usr/local/google/home/blaikie/dev/scratch" "verify.cpp" diff --git a/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test b/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test index 3f55d687474a7..3346a5ba48c48 100644 --- a/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test +++ b/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test @@ -90,7 +90,7 @@ #DWARF-CHECK: 0x[[F4RANGE_OFF]]: [DW_RLE_base_addressx]: 0x0000000000000003 #DWARF-CHECK: {{.}}: [DW_RLE_offset_pair ]: 0x0000000000000000, 0x0000000000000010 #DWARF-CHECK: {{.}}: [DW_RLE_end_of_list ] -#DWARF-CHECK 0x[[CURANGE_OFF]]: [DW_RLE_base_addressx]: 0x0000000000000000 +#DWARF-CHECK: 0x[[CURANGE_OFF]]: [DW_RLE_base_addressx]: 0x0000000000000000 #DWARF-CHECK: {{.}}: [DW_RLE_offset_pair ]: 0x0000000000000000, 0x0000000000000040 #DWARF-CHECK: {{.}}: [DW_RLE_end_of_list ] diff --git a/llvm/test/tools/llvm-lib/duplicate.test b/llvm/test/tools/llvm-lib/duplicate.test index 87dae66cb80be..6cdce687c0184 100644 --- a/llvm/test/tools/llvm-lib/duplicate.test +++ b/llvm/test/tools/llvm-lib/duplicate.test @@ -22,4 +22,4 @@ RUN: llvm-nm --print-armap %t/foo.lib | FileCheck %s --check-prefix=DUP # DUP-NEXT: a in abc.o # DUP-NEXT: b in bar.o # DUP-NEXT: c in abc.o -# DUP-EMPTY +# DUP-EMPTY: diff --git a/llvm/test/tools/llvm-objcopy/ELF/update-section.test b/llvm/test/tools/llvm-objcopy/ELF/update-section.test index 79cfe0e719418..49a533e2221dd 100644 --- a/llvm/test/tools/llvm-objcopy/ELF/update-section.test +++ b/llvm/test/tools/llvm-objcopy/ELF/update-section.test @@ -160,7 +160,7 @@ ProgramHeaders: # LONG-SAME: {{ }}9{{$}} # LONG: SectionData ( # LONG-NEXT: |111122223| -# LONT-NEXT: ) +# LONG-NEXT: ) # ADD-UPDATE: Name: .added # ADD-UPDATE: Size: diff --git a/llvm/test/tools/llvm-objcopy/MachO/code_signature_lc_update.test b/llvm/test/tools/llvm-objcopy/MachO/code_signature_lc_update.test index c25491ed3f9e1..8aeff27a02f9b 100644 --- a/llvm/test/tools/llvm-objcopy/MachO/code_signature_lc_update.test +++ b/llvm/test/tools/llvm-objcopy/MachO/code_signature_lc_update.test @@ -4,12 +4,12 @@ ## Check offset, size and index of text segment command # CHECK-ORIGINAL: Load command 1 -# CHECK-ORIGINAL-NEXT cmdsize -# CHECK-ORIGINAL-NEXT segname __TEXT -# CHECK-ORIGINAL-NEXT vmaddr -# CHECK-ORIGINAL-NEXT vmsize -# CHECK-ORIGINAL-NEXT fileoff 0 -# CHECK-ORIGINAL-NEXT filesize 16384 +# CHECK-ORIGINAL-NEXT: cmdsize +# CHECK-ORIGINAL-NEXT: segname __TEXT +# CHECK-ORIGINAL-NEXT: vmaddr +# CHECK-ORIGINAL-NEXT: vmsize +# CHECK-ORIGINAL-NEXT: fileoff 0 +# CHECK-ORIGINAL-NEXT: filesize 16384 ## Check offset and index of code signature command # CHECK-ORIGINAL: Load command 14 @@ -29,12 +29,12 @@ ## Verify the text segment command index increased by 1 # CHECK-PREPEND: Load command 2 -# CHECK-PREPEND-NEXT cmdsize -# CHECK-PREPEND-NEXT segname __TEXT -# CHECK-PREPEND-NEXT vmaddr -# CHECK-PREPEND-NEXT vmsize -# CHECK-PREPEND-NEXT fileoff 0 -# CHECK-PREPEND-NEXT filesize 16384 +# CHECK-PREPEND-NEXT: cmdsize +# CHECK-PREPEND-NEXT: segname __TEXT +# CHECK-PREPEND-NEXT: vmaddr +# CHECK-PREPEND-NEXT: vmsize +# CHECK-PREPEND-NEXT: fileoff 0 +# CHECK-PREPEND-NEXT: filesize 16384 ## Verify the code signature command index increased by 1 # CHECK-PREPEND: Load command 15 @@ -54,12 +54,12 @@ ## Verify text segment command index returned to orignal # CHECK-REMOVE: Load command 1 -# CHECK-REMOVE-NEXT cmdsize -# CHECK-REMOVE-NEXT segname __TEXT -# CHECK-REMOVE-NEXT vmaddr -# CHECK-REMOVE-NEXT vmsize -# CHECK-REMOVE-NEXT fileoff 0 -# CHECK-REMOVE-NEXT filesize 16384 +# CHECK-REMOVE-NEXT: cmdsize +# CHECK-REMOVE-NEXT: segname __TEXT +# CHECK-REMOVE-NEXT: vmaddr +# CHECK-REMOVE-NEXT: vmsize +# CHECK-REMOVE-NEXT: fileoff 0 +# CHECK-REMOVE-NEXT: filesize 16384 ## Verify text segment command index returned to original # CHECK-REMOVE: Load command 14 diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s index 771bce5023933..37271fb902b4d 100644 --- a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s +++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s @@ -5,6 +5,6 @@ strd: strd r0, r1, [r2, +r3] -@ CHECK-LABEL strd +@ CHECK-LABEL: strd @ CHECK: e18200f3 strd r0, r1, [r2, r3] diff --git a/llvm/test/tools/llvm-objdump/X86/start-stop-address.test b/llvm/test/tools/llvm-objdump/X86/start-stop-address.test index c2d51e4b1fdf7..7e38bbb22ef1f 100644 --- a/llvm/test/tools/llvm-objdump/X86/start-stop-address.test +++ b/llvm/test/tools/llvm-objdump/X86/start-stop-address.test @@ -16,7 +16,7 @@ // CHECK-NEXT: 2b: 48 8b 45 f0 movq -16(%rbp), %rax // CHECK-NOT: {{.}} -// CROSSECTION-NOT: Disassembly +// CROSSSECTION-NOT: Disassembly // CROSSSECTION: Disassembly of section .text: // CROSSSECTION-EMPTY: // CROSSSECTION-NEXT: : diff --git a/llvm/test/tools/llvm-profgen/disassemble.test b/llvm/test/tools/llvm-profgen/disassemble.test index 87644293f996b..e2577b4f47b87 100644 --- a/llvm/test/tools/llvm-profgen/disassemble.test +++ b/llvm/test/tools/llvm-profgen/disassemble.test @@ -14,13 +14,13 @@ ; CHECK-NEXT: 20176f: retq ; CHECK: : -; CHECK-NEXT 201770: movl $1, %ecx -; CHECK-NEXT 201775: movl $2863311531, %r8d -; CHECK-NEXT 20177b: jmp 0x78e -; CHECK-NEXT 20177d: nopl (%rax) -; CHECK-NEXT 201780: addl $30, %esi -; CHECK-NEXT 201783: addl $1, %ecx -; CHECK-NEXT 201786: cmpl $16000001, %ecx +; CHECK-NEXT: 201770: movl $1, %ecx +; CHECK-NEXT: 201775: movl $2863311531, %r8d +; CHECK-NEXT: 20177b: jmp 0x78e +; CHECK-NEXT: 20177d: nopl (%rax) +; CHECK-NEXT: 201780: addl $30, %esi +; CHECK-NEXT: 201783: addl $1, %ecx +; CHECK-NEXT: 201786: cmpl $16000001, %ecx ; clang -O3 -fuse-ld=lld -fpseudo-probe-for-profiling diff --git a/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test b/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test index 3a264e3b1108b..cb067d53d74af 100644 --- a/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test +++ b/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test @@ -1,8 +1,8 @@ ; RUN: llvm-profgen --format=text --llvm-sample-profile=%S/Inputs/filter-ambiguous-profile.prof --binary=%S/Inputs/inline-cs-noprobe.perfbin --csspgo-preinliner=0 --output=%t1 || FileCheck %s --input-file %t1 ;CHECK: foo:12345:1000 -;CHECK-NEXT 1: 1000 -;CHECK-NEXT 4: bar:1000 -;CHECK-NEXT 1: 1000 -;CHECK-NEXT 3: goo:300 -;CHECK-NEXT 1: 300 +;CHECK-NEXT: 1: 1000 +;CHECK-NEXT: 4: bar:1000 +;CHECK-NEXT: 1: 1000 +;CHECK-NEXT: 3: goo:300 +;CHECK-NEXT: 1: 300 diff --git a/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test b/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test index c673028584c0d..adbb600e508a4 100644 --- a/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test +++ b/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test @@ -93,14 +93,14 @@ ; CHECK: 3: 1 ; CHECK: 5: 4 fb:4 ; CHECK: 6: 1 fa:1 -; CHECK !CFGChecksum: 563022570642068 +; CHECK: !CFGChecksum: 563022570642068 ; CHECK: [main:2 @ foo:5 @ fa:8 @ fa:7 @ fb:5 @ fb:6 @ fa:8 @ fa:7 @ fb:6 @ fa]:6:2 ; CHECK: 1: 2 ; CHECK: 3: 2 ; CHECK: 4: 1 ; CHECK: 7: 1 fb:1 ; CHECK: !CFGChecksum: 563070469352221 - CHECK: [main:2 @ foo:5 @ fa:8 @ fa:7 @ fb:5 @ fb:6 @ fa]:4:1 +; CHECK: [main:2 @ foo:5 @ fa:8 @ fa:7 @ fb:5 @ fb:6 @ fa]:4:1 ; CHECK: 1: 1 ; CHECK: 3: 1 ; CHECK: 5: 1 diff --git a/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test b/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test index 81d193ad30efa..06177d8c1685d 100644 --- a/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test +++ b/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test @@ -104,84 +104,84 @@ MFUN32-NEXT: SubSectionType: Symbols (0xF1) MFUN32-NEXT: SubSectionSize: 0x8 MFUN32: ] MFUN32-NEXT: FunctionLineTable [ -MFUN32-NEXT LinkageName: _x -MFUN32-NEXT Flags: 0x0 -MFUN32-NEXT CodeSize: 0xA -MFUN32-NEXT FilenameSegment [ -MFUN32-NEXT Filename: d:\source.c -MFUN32-NEXT +0x0 [ -MFUN32-NEXT LineNumberStart: 3 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x3 [ -MFUN32-NEXT LineNumberStart: 4 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x8 [ -MFUN32-NEXT LineNumberStart: 5 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT FunctionLineTable [ -MFUN32-NEXT LinkageName: _y -MFUN32-NEXT Flags: 0x0 -MFUN32-NEXT CodeSize: 0xA -MFUN32-NEXT FilenameSegment [ -MFUN32-NEXT Filename: d:\source.c -MFUN32-NEXT +0x0 [ -MFUN32-NEXT LineNumberStart: 7 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x3 [ -MFUN32-NEXT LineNumberStart: 8 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x8 [ -MFUN32-NEXT LineNumberStart: 9 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT FunctionLineTable [ -MFUN32-NEXT LinkageName: _f -MFUN32-NEXT Flags: 0x0 -MFUN32-NEXT CodeSize: 0x14 -MFUN32-NEXT FilenameSegment [ -MFUN32-NEXT Filename: d:\source.c -MFUN32-NEXT +0x0 [ -MFUN32-NEXT LineNumberStart: 11 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x3 [ -MFUN32-NEXT LineNumberStart: 12 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x8 [ -MFUN32-NEXT LineNumberStart: 13 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0xD [ -MFUN32-NEXT LineNumberStart: 14 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x12 [ -MFUN32-NEXT LineNumberStart: 15 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT ] +MFUN32-NEXT: LinkageName: _x +MFUN32-NEXT: Flags: 0x0 +MFUN32-NEXT: CodeSize: 0xA +MFUN32-NEXT: FilenameSegment [ +MFUN32-NEXT: Filename: d:\source.c +MFUN32-NEXT: +0x0 [ +MFUN32-NEXT: LineNumberStart: 3 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x3 [ +MFUN32-NEXT: LineNumberStart: 4 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x8 [ +MFUN32-NEXT: LineNumberStart: 5 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: FunctionLineTable [ +MFUN32-NEXT: LinkageName: _y +MFUN32-NEXT: Flags: 0x0 +MFUN32-NEXT: CodeSize: 0xA +MFUN32-NEXT: FilenameSegment [ +MFUN32-NEXT: Filename: d:\source.c +MFUN32-NEXT: +0x0 [ +MFUN32-NEXT: LineNumberStart: 7 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x3 [ +MFUN32-NEXT: LineNumberStart: 8 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x8 [ +MFUN32-NEXT: LineNumberStart: 9 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: FunctionLineTable [ +MFUN32-NEXT: LinkageName: _f +MFUN32-NEXT: Flags: 0x0 +MFUN32-NEXT: CodeSize: 0x14 +MFUN32-NEXT: FilenameSegment [ +MFUN32-NEXT: Filename: d:\source.c +MFUN32-NEXT: +0x0 [ +MFUN32-NEXT: LineNumberStart: 11 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x3 [ +MFUN32-NEXT: LineNumberStart: 12 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x8 [ +MFUN32-NEXT: LineNumberStart: 13 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0xD [ +MFUN32-NEXT: LineNumberStart: 14 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x12 [ +MFUN32-NEXT: LineNumberStart: 15 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: ] MFUN32: ] MFUN64: CodeViewDebugInfo [ diff --git a/llvm/test/tools/llvm-reduce/skip-delta-passes.ll b/llvm/test/tools/llvm-reduce/skip-delta-passes.ll index b1f9cfc9a2bfa..d18982d3f8352 100644 --- a/llvm/test/tools/llvm-reduce/skip-delta-passes.ll +++ b/llvm/test/tools/llvm-reduce/skip-delta-passes.ll @@ -11,7 +11,7 @@ ; RESULT: define void @foo() { ; RESULT-NEXT: store i32 ; RESULT-NEXT: ret void -; RESULT0-NOT: attributes +; RESULT-NOT: attributes ; ERROR: unknown pass "foo" define void @foo() #0 { diff --git a/llvm/test/tools/llvm-remarkutil/no-instruction-count.test b/llvm/test/tools/llvm-remarkutil/no-instruction-count.test index 33838796f9cca..12b640030be66 100644 --- a/llvm/test/tools/llvm-remarkutil/no-instruction-count.test +++ b/llvm/test/tools/llvm-remarkutil/no-instruction-count.test @@ -2,4 +2,4 @@ RUN: llvm-remarkutil instruction-count --parser=yaml %p/Inputs/made-up-fake-rema RUN: llvm-remarkutil yaml2bitstream %p/Inputs/made-up-fake-remarks.yaml | llvm-remarkutil instruction-count --parser=bitstream | FileCheck %s ; CHECK-LABEL: Function,InstructionCount -; CHECK-EMPTY +; CHECK-EMPTY: diff --git a/llvm/test/tools/llvm-symbolizer/flag-grouping.test b/llvm/test/tools/llvm-symbolizer/flag-grouping.test index 7bcb68dd47067..14ffb454752c2 100644 --- a/llvm/test/tools/llvm-symbolizer/flag-grouping.test +++ b/llvm/test/tools/llvm-symbolizer/flag-grouping.test @@ -6,5 +6,5 @@ RUN: llvm-symbolizer -apCie%p/Inputs/addr.exe < %p/Inputs/addr.inp | FileCheck % CHECK: ?? at ??:0:0 CHECK: 0x40054d: inctwo CHECK: (inlined by) inc -CHECK (inlined by) main +CHECK: (inlined by) main CHECK: ?? at ??:0:0 diff --git a/llvm/test/tools/lto/discard-value-names.ll b/llvm/test/tools/lto/discard-value-names.ll index 04d25eaf6067c..2c236f5266cd8 100644 --- a/llvm/test/tools/lto/discard-value-names.ll +++ b/llvm/test/tools/lto/discard-value-names.ll @@ -14,7 +14,7 @@ ; DISCARD: %add = add i32 ; KEEP: %cmp.i = icmp -; KEEP : %add = add i32 +; KEEP: %add = add i32 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.10.0"