From d2a522da0cec4ff37a92d22530f27e7e78577f01 Mon Sep 17 00:00:00 2001 From: klensy Date: Sat, 8 Jun 2024 17:19:22 +0300 Subject: [PATCH 1/2] working tests from #93673 --- .../AArch64/sve-shuffle-broadcast.ll | 2 +- llvm/test/Assembler/bfloat.ll | 8 +- llvm/test/CodeGen/AArch64/arm64_32-atomics.ll | 20 +-- .../CodeGen/AArch64/arm64ec-entry-thunks.ll | 2 +- llvm/test/CodeGen/AArch64/fpimm.ll | 2 +- .../AArch64/speculation-hardening-sls.ll | 4 +- .../stp-opt-with-renaming-undef-assert.mir | 2 +- llvm/test/CodeGen/ARM/dsp-loop-indexing.ll | 2 +- llvm/test/CodeGen/ARM/shifter_operand.ll | 1 - .../CodeGen/ARM/speculation-hardening-sls.ll | 2 +- llvm/test/CodeGen/ARM/sxt_rot.ll | 1 - .../test/CodeGen/Mips/optimizeAndPlusShift.ll | 18 +- llvm/test/CodeGen/NVPTX/idioms.ll | 10 +- .../intel-usm-addrspaces.ll | 2 +- llvm/test/CodeGen/SystemZ/prefetch-04.ll | 2 +- .../Thumb2/LowOverheadLoops/branch-targets.ll | 6 +- llvm/test/CodeGen/X86/global-sections.ll | 6 +- llvm/test/CodeGen/X86/tailregccpic.ll | 4 +- .../InstrRef/livedebugvalues_illegal_locs.mir | 6 +- .../InstrRef/single-assign-propagation.mir | 6 +- llvm/test/MC/AArch64/SME/feature.s | 2 +- llvm/test/MC/ARM/coff-relocations.s | 2 +- llvm/test/MC/AsmParser/labels.s | 4 +- llvm/test/MC/COFF/cv-inline-linetable.s | 6 +- .../MC/Disassembler/AArch64/armv8.6a-bf16.txt | 16 +- llvm/test/MC/Disassembler/ARM/arm-tests.txt | 2 +- .../Mips/mips32r6/valid-mips32r6.txt | 6 +- .../Mips/mips64r6/valid-mips64r6.txt | 6 +- .../PowerPC/ppc64-encoding-dfp.txt | 2 +- .../Disassembler/PowerPC/ppc64-encoding.txt | 2 +- .../Disassembler/PowerPC/ppc64le-encoding.txt | 2 +- llvm/test/MC/Disassembler/X86/x86-16.txt | 32 ++-- llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s | 2 +- .../MC/LoongArch/Relocations/relax-align.s | 2 +- .../test/MC/M68k/Arith/Classes/MxFBinary_FF.s | 16 +- llvm/test/MC/MachO/lto-set-conditional.s | 4 +- llvm/test/MC/Mips/macro-rem.s | 2 +- llvm/test/MC/Mips/micromips-dsp/invalid.s | 10 +- llvm/test/MC/Mips/micromips/valid.s | 4 +- llvm/test/MC/Mips/mips-pdr-bad.s | 4 +- llvm/test/MC/Mips/mips32r6/invalid.s | 17 +- llvm/test/MC/Mips/mips64r6/invalid.s | 17 +- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s | 26 +-- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s | 6 +- llvm/test/MC/RISCV/compress-rv64i.s | 4 +- llvm/test/MC/RISCV/elf-flags.s | 4 +- llvm/test/MC/RISCV/zicfiss-valid.s | 12 +- llvm/test/MC/WebAssembly/globals.s | 2 +- llvm/test/MC/X86/apx/evex-format-intel.s | 4 +- llvm/test/MC/Xtensa/Relocations/relocations.s | 62 +++---- llvm/test/TableGen/MixedCasedMnemonic.td | 30 ++-- .../CallSiteSplitting/callsite-split.ll | 2 +- .../coro-await-suspend-lower-invoke.ll | 2 +- .../Coroutines/coro-debug-coro-frame.ll | 2 +- llvm/test/Transforms/FunctionAttrs/nonnull.ll | 1 - .../Transforms/GVNSink/sink-common-code.ll | 12 +- .../InstCombine/lifetime-sanitizer.ll | 2 +- llvm/test/Transforms/InstCombine/str-int-2.ll | 4 +- llvm/test/Transforms/InstCombine/str-int.ll | 4 +- llvm/test/Transforms/LoopUnroll/peel-loop2.ll | 2 +- .../AArch64/nontemporal-load-store.ll | 22 +-- .../LoopVectorize/AArch64/strict-fadd.ll | 2 +- llvm/test/Transforms/LoopVectorize/memdep.ll | 2 +- llvm/test/Transforms/ObjCARC/rv.ll | 6 +- .../counter_promo_exit_catchswitch.ll | 2 +- .../X86/good-prototype.ll | 2 +- .../SampleProfile/pseudo-probe-dangle.ll | 8 +- .../pseudo-probe-selectionDAG.ll | 4 +- llvm/test/Verifier/convergencectrl-invalid.ll | 4 +- .../tools/gold/X86/global_with_section.ll | 2 +- llvm/test/tools/llvm-ar/replace-update.test | 2 +- .../Inputs/binary-formats.canonical.json | 2 +- .../tools/llvm-cov/coverage_watermark.test | 10 +- llvm/test/tools/llvm-cov/zeroFunctionFile.c | 2 +- .../X86/simplified-template-names-fail.s | 2 +- .../ELF/X86/dwarf5-rnglists.test | 2 +- llvm/test/tools/llvm-lib/duplicate.test | 2 +- .../llvm-objcopy/ELF/update-section.test | 2 +- .../tools/llvm-objdump/ELF/ARM/v5te-subarch.s | 2 +- .../llvm-objdump/X86/start-stop-address.test | 2 +- .../filter-ambiguous-profile.test | 10 +- .../recursion-compression-pseudoprobe.test | 4 +- .../COFF/codeview-linetables.test | 156 +++++++++--------- .../tools/llvm-reduce/skip-delta-passes.ll | 2 +- .../llvm-remarkutil/no-instruction-count.test | 2 +- .../tools/llvm-symbolizer/flag-grouping.test | 2 +- llvm/test/tools/lto/discard-value-names.ll | 2 +- 87 files changed, 350 insertions(+), 357 deletions(-) diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll index a2526d9f5591a..c2aab35194831 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-shuffle-broadcast.ll @@ -31,7 +31,7 @@ define void @broadcast() #0{ ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = shufflevector undef, undef, zeroinitializer ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = shufflevector undef, undef, zeroinitializer ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = shufflevector undef, undef, zeroinitializer -; CHECK-NETX: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void %zero = shufflevector undef, undef, zeroinitializer %1 = shufflevector undef, undef, zeroinitializer diff --git a/llvm/test/Assembler/bfloat.ll b/llvm/test/Assembler/bfloat.ll index 3a3b4c2b277db..6f935c5dac154 100644 --- a/llvm/test/Assembler/bfloat.ll +++ b/llvm/test/Assembler/bfloat.ll @@ -37,25 +37,25 @@ define float @check_bfloat_convert() { ret float %tmp } -; ASSEM-DISASS-LABEL @snan_bfloat +; ASSEM-DISASS-LABEL: @snan_bfloat define bfloat @snan_bfloat() { ; ASSEM-DISASS: ret bfloat 0xR7F81 ret bfloat 0xR7F81 } -; ASSEM-DISASS-LABEL @qnan_bfloat +; ASSEM-DISASS-LABEL: @qnan_bfloat define bfloat @qnan_bfloat() { ; ASSEM-DISASS: ret bfloat 0xR7FC0 ret bfloat 0xR7FC0 } -; ASSEM-DISASS-LABEL @pos_inf_bfloat +; ASSEM-DISASS-LABEL: @pos_inf_bfloat define bfloat @pos_inf_bfloat() { ; ASSEM-DISASS: ret bfloat 0xR7F80 ret bfloat 0xR7F80 } -; ASSEM-DISASS-LABEL @neg_inf_bfloat +; ASSEM-DISASS-LABEL: @neg_inf_bfloat define bfloat @neg_inf_bfloat() { ; ASSEM-DISASS: ret bfloat 0xRFF80 ret bfloat 0xRFF80 diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll index 0000262e833da..19b9205dc1786 100644 --- a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll +++ b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll @@ -2,70 +2,70 @@ ; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS define i8 @test_load_8(ptr %addr) { -; CHECK-LABAL: test_load_8: +; CHECK-LABEL: test_load_8: ; CHECK: ldarb w0, [x0] %val = load atomic i8, ptr %addr seq_cst, align 1 ret i8 %val } define i16 @test_load_16(ptr %addr) { -; CHECK-LABAL: test_load_16: +; CHECK-LABEL: test_load_16: ; CHECK: ldarh w0, [x0] %val = load atomic i16, ptr %addr acquire, align 2 ret i16 %val } define i32 @test_load_32(ptr %addr) { -; CHECK-LABAL: test_load_32: +; CHECK-LABEL: test_load_32: ; CHECK: ldar w0, [x0] %val = load atomic i32, ptr %addr seq_cst, align 4 ret i32 %val } define i64 @test_load_64(ptr %addr) { -; CHECK-LABAL: test_load_64: +; CHECK-LABEL: test_load_64: ; CHECK: ldar x0, [x0] %val = load atomic i64, ptr %addr seq_cst, align 8 ret i64 %val } define ptr @test_load_ptr(ptr %addr) { -; CHECK-LABAL: test_load_ptr: +; CHECK-LABEL: test_load_ptr: ; CHECK: ldar w0, [x0] %val = load atomic ptr, ptr %addr seq_cst, align 8 ret ptr %val } define void @test_store_8(ptr %addr) { -; CHECK-LABAL: test_store_8: +; CHECK-LABEL: test_store_8: ; CHECK: stlrb wzr, [x0] store atomic i8 0, ptr %addr seq_cst, align 1 ret void } define void @test_store_16(ptr %addr) { -; CHECK-LABAL: test_store_16: +; CHECK-LABEL: test_store_16: ; CHECK: stlrh wzr, [x0] store atomic i16 0, ptr %addr seq_cst, align 2 ret void } define void @test_store_32(ptr %addr) { -; CHECK-LABAL: test_store_32: +; CHECK-LABEL: test_store_32: ; CHECK: stlr wzr, [x0] store atomic i32 0, ptr %addr seq_cst, align 4 ret void } define void @test_store_64(ptr %addr) { -; CHECK-LABAL: test_store_64: +; CHECK-LABEL: test_store_64: ; CHECK: stlr xzr, [x0] store atomic i64 0, ptr %addr seq_cst, align 8 ret void } define void @test_store_ptr(ptr %addr) { -; CHECK-LABAL: test_store_ptr: +; CHECK-LABEL: test_store_ptr: ; CHECK: stlr wzr, [x0] store atomic ptr null, ptr %addr seq_cst, align 8 ret void diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll index 6aeeeed94543d..4abc39007a3a7 100644 --- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll +++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s define void @no_op() nounwind { -; CHECK-LABEL .def $ientry_thunk$cdecl$v$v; +; CHECK-LABEL: .def $ientry_thunk$cdecl$v$v; ; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$v$v ; CHECK: // %bb.0: ; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill diff --git a/llvm/test/CodeGen/AArch64/fpimm.ll b/llvm/test/CodeGen/AArch64/fpimm.ll index b92bb4245c7f3..e2944243338f5 100644 --- a/llvm/test/CodeGen/AArch64/fpimm.ll +++ b/llvm/test/CodeGen/AArch64/fpimm.ll @@ -38,7 +38,7 @@ define void @check_double() { ; 64-bit ORR followed by MOVK. ; CHECK-DAG: mov [[XFP0:x[0-9]+]], #1082331758844 ; CHECK-DAG: movk [[XFP0]], #64764, lsl #16 -; CHECk-DAG: fmov {{d[0-9]+}}, [[XFP0]] +; CHECK-DAG: fmov {{d[0-9]+}}, [[XFP0]] %newval3 = fadd double %val, 0xFCFCFC00FC store volatile double %newval3, ptr @varf64 diff --git a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll index f380b2d05d863..fe08fa5642574 100644 --- a/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll +++ b/llvm/test/CodeGen/AArch64/speculation-hardening-sls.ll @@ -192,7 +192,7 @@ entry: ; CHECK: .Lfunc_end } -; HARDEN-label: __llvm_slsblr_thunk_x0: +; HARDEN-LABEL: __llvm_slsblr_thunk_x0: ; HARDEN: mov x16, x0 ; HARDEN: br x16 ; ISBDSB-NEXT: dsb sy @@ -208,7 +208,7 @@ entry: ; HARDEN-COMDAT-OFF-NOT: .hidden __llvm_slsblr_thunk_x19 ; HARDEN-COMDAT-OFF-NOT: .weak __llvm_slsblr_thunk_x19 ; HARDEN-COMDAT-OFF: .type __llvm_slsblr_thunk_x19,@function -; HARDEN-label: __llvm_slsblr_thunk_x19: +; HARDEN-LABEL: __llvm_slsblr_thunk_x19: ; HARDEN: mov x16, x19 ; HARDEN: br x16 ; ISBDSB-NEXT: dsb sy diff --git a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir index 66d2067b531a3..bfdb1763776b4 100644 --- a/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir +++ b/llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir @@ -12,7 +12,7 @@ # This test also checks that pairwise store STP is generated. -# CHECK-LABLE: test +# CHECK-LABEL: test # CHECK: bb.0: # CHECK-NEXT: liveins: $x0, $x17, $x18 # CHECK: renamable $q13_q14_q15 = LD3Threev16b undef renamable $x17 :: (load (s384) from `ptr undef`, align 64) diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll index 9fb64471e9881..892e66aed4e5f 100644 --- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll +++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll @@ -22,7 +22,7 @@ ; CHECK-DEFAULT: ldr{{.*}}, #4] ; CHECK-DEFAULT: str{{.*}}, #4] ; CHECK-DEFAULT: ldr{{.*}}, #8]! -; CHECK-DEAFULT: ldr{{.*}}, #8]! +; CHECK-DEFAULT: ldr{{.*}}, #8]! ; CHECK-DEFAULT: str{{.*}}, #8]! ; CHECK-COMPLEX: ldr{{.*}}, #8]! diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll index bf2e8aa911c64..00922b1bf2492 100644 --- a/llvm/test/CodeGen/ARM/shifter_operand.ll +++ b/llvm/test/CodeGen/ARM/shifter_operand.ll @@ -121,7 +121,6 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) { ; CHECK-THUMB-NEXT: orrs r0, r1 ; CHECK-THUMB-NEXT: bx lr entry: -; CHECk-THUMB: orrs r0, r1 %mul = mul i32 %y, 63767 %or = or i32 %mul, %x ret i32 %or diff --git a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll index f25d73a12246f..1f60f120dc86a 100644 --- a/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll +++ b/llvm/test/CodeGen/ARM/speculation-hardening-sls.ll @@ -248,7 +248,7 @@ entry: ; HARDEN-COMDAT-OFF-NOT: .hidden {{__llvm_slsblr_thunk_(arm|thumb)_r5}} ; HARDEN-COMDAT-OFF-NOT: .weak {{__llvm_slsblr_thunk_(arm|thumb)_r5}} ; HARDEN-COMDAT-OFF: .type {{__llvm_slsblr_thunk_(arm|thumb)_r5}},%function -; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}: +; HARDEN-LABEL: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}: ; HARDEN: bx r5 ; ISBDSB-NEXT: dsb sy ; ISBDSB-NEXT: isb diff --git a/llvm/test/CodeGen/ARM/sxt_rot.ll b/llvm/test/CodeGen/ARM/sxt_rot.ll index e9649c7a7fd9a..775e45201105c 100644 --- a/llvm/test/CodeGen/ARM/sxt_rot.ll +++ b/llvm/test/CodeGen/ARM/sxt_rot.ll @@ -22,7 +22,6 @@ define signext i8 @test1(i32 %A) { ; CHECK-V7: @ %bb.0: ; CHECK-V7-NEXT: sbfx r0, r0, #8, #8 ; CHECK-V7-NEXT: bx lr -; CHECk-V7: sbfx r0, r0, #8, #8 %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C diff --git a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll index bf69adf6702f0..58920483e24bf 100644 --- a/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll +++ b/llvm/test/CodeGen/Mips/optimizeAndPlusShift.ll @@ -3,11 +3,11 @@ ; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnuabi64 | FileCheck %s --check-prefixes=MIPS64 define i32 @shl_32(i32 %a, i32 %b) { -; MIPS32-LABLE: shl_32: +; MIPS32-LABEL: shl_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: sllv $2, $4, $5 -; MIPS64-LABLE: shl_32: +; MIPS64-LABEL: shl_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -19,11 +19,11 @@ define i32 @shl_32(i32 %a, i32 %b) { } define i32 @lshr_32(i32 %a, i32 %b) { -; MIPS32-LABLE: lshr_32: +; MIPS32-LABEL: lshr_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: srlv $2, $4, $5 -; MIPS64-LABLE: lshr_32: +; MIPS64-LABEL: lshr_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -35,11 +35,11 @@ define i32 @lshr_32(i32 %a, i32 %b) { } define i32 @ashr_32(i32 %a, i32 %b) { -; MIPS32-LABLE: ashr_32: +; MIPS32-LABEL: ashr_32: ; MIPS32: # %bb.0: ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: srav $2, $4, $5 -; MIPS64-LABLE: ashr_32: +; MIPS64-LABEL: ashr_32: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: sll $2, $4, 0 @@ -51,7 +51,7 @@ define i32 @ashr_32(i32 %a, i32 %b) { } define i64 @shl_64(i64 %a, i64 %b) { -; MIPS64-LABLE: shl_64: +; MIPS64-LABEL: shl_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra @@ -62,7 +62,7 @@ define i64 @shl_64(i64 %a, i64 %b) { } define i64 @lshr_64(i64 %a, i64 %b) { -; MIPS64-LABLE: lshr_64: +; MIPS64-LABEL: lshr_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra @@ -73,7 +73,7 @@ define i64 @lshr_64(i64 %a, i64 %b) { } define i64 @ashr_64(i64 %a, i64 %b) { -; MIPS64-LABLE: ashr_64: +; MIPS64-LABEL: ashr_64: ; MIPS64: # %bb.0: ; MIPS64-NEXT: sll $1, $5, 0 ; MIPS64-NEXT: jr $ra diff --git a/llvm/test/CodeGen/NVPTX/idioms.ll b/llvm/test/CodeGen/NVPTX/idioms.ll index efd61f905dab4..7b1c22d2477af 100644 --- a/llvm/test/CodeGen/NVPTX/idioms.ll +++ b/llvm/test/CodeGen/NVPTX/idioms.ll @@ -42,7 +42,7 @@ define %struct.S16 @i32_to_2xi16(i32 noundef %in) { %high = trunc i32 %high32 to i16 ; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_param_0]; ; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]]; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; %s1 = insertvalue %struct.S16 poison, i16 %low, 0 %s = insertvalue %struct.S16 %s1, i16 %high, 1 ret %struct.S16 %s @@ -56,7 +56,7 @@ define %struct.S16 @i32_to_2xi16_lh(i32 noundef %in) { %low = trunc i32 %in to i16 ; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_lh_param_0]; ; CHECK-DAG: cvt.u16.u32 %rs{{[0-9+]}}, %[[R32]]; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; %s1 = insertvalue %struct.S16 poison, i16 %low, 0 %s = insertvalue %struct.S16 %s1, i16 %high, 1 ret %struct.S16 %s @@ -84,7 +84,7 @@ define %struct.S32 @i64_to_2xi32(i64 noundef %in) { %high = trunc i64 %high64 to i32 ; CHECK: ld.param.u64 %[[R64:rd[0-9]+]], [i64_to_2xi32_param_0]; ; CHECK-DAG: cvt.u32.u64 %r{{[0-9+]}}, %[[R64]]; -; CHECK-DAG mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]]; +; CHECK-DAG: mov.b64 {tmp, %r{{[0-9+]}}}, %[[R64]]; %s1 = insertvalue %struct.S32 poison, i32 %low, 0 %s = insertvalue %struct.S32 %s1, i32 %high, 1 ret %struct.S32 %s @@ -114,8 +114,8 @@ define %struct.S16 @i32_to_2xi16_shr(i32 noundef %i){ %h = trunc i32 %h32 to i16 ; CHECK: ld.param.u32 %[[R32:r[0-9]+]], [i32_to_2xi16_shr_param_0]; ; CHECK: shr.s32 %[[R32H:r[0-9]+]], %[[R32]], 16; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; -; CHECK-DAG mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32]]; +; CHECK-DAG: mov.b32 {tmp, %rs{{[0-9+]}}}, %[[R32H]]; %s0 = insertvalue %struct.S16 poison, i16 %l, 0 %s1 = insertvalue %struct.S16 %s0, i16 %h, 1 ret %struct.S16 %s1 diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll index e963e3035be4d..5596f62de7fec 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_usm_storage_classes/intel-usm-addrspaces.ll @@ -7,7 +7,7 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-: Capability USMStorageClassesINTEL -; CHECK-SPIRV-WITHOUT-NO: Capability USMStorageClassesINTEL +; CHECK-SPIRV-WITHOUT-NOT: Capability USMStorageClassesINTEL ; CHECK-SPIRV-EXT-DAG: %[[DevTy:[0-9]+]] = OpTypePointer DeviceOnlyINTEL %[[#]] ; CHECK-SPIRV-EXT-DAG: %[[HostTy:[0-9]+]] = OpTypePointer HostOnlyINTEL %[[#]] ; CHECK-SPIRV-DAG: %[[CrsWrkTy:[0-9]+]] = OpTypePointer CrossWorkgroup %[[#]] diff --git a/llvm/test/CodeGen/SystemZ/prefetch-04.ll b/llvm/test/CodeGen/SystemZ/prefetch-04.ll index 61a2a1460c583..10755bdb66eb5 100644 --- a/llvm/test/CodeGen/SystemZ/prefetch-04.ll +++ b/llvm/test/CodeGen/SystemZ/prefetch-04.ll @@ -6,7 +6,7 @@ ; ; CHECK-LABEL: for.body ; CHECK: call void @llvm.prefetch.p0(ptr %scevgep, i32 1, i32 3, i32 1 -; CHECK-not: call void @llvm.prefetch +; CHECK-NOT: call void @llvm.prefetch define void @fun(ptr nocapture %Src, ptr nocapture readonly %Dst) { entry: diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll index 165e73c2e8827..680d9e02a5c5c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/branch-targets.ll @@ -406,7 +406,7 @@ for.cond.cleanup: ; CHECK-MID: tB %bb.1 ; CHECK-MID: bb.1.while.body: ; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1 -; CHECk-MID: tB %bb.2 +; CHECK-MID: tB %bb.2 ; CHECK-MID: bb.2.while.end: define void @check_negated_xor_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { entry: @@ -440,7 +440,7 @@ while.end: ; CHECK-MID: tB %bb.1 ; CHECK-MID: bb.1.while.body: ; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1 -; CHECk-MID: tB %bb.2 +; CHECK-MID: tB %bb.2 ; CHECK-MID: bb.2.while.end: define void @check_negated_cmp_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { entry: @@ -474,7 +474,7 @@ while.end: ; CHECK-MID: tB %bb.1 ; CHECK-MID: bb.1.while.body: ; CHECK-MID: renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1 -; CHECk-MID: tB %bb.2 +; CHECK-MID: tB %bb.2 ; CHECK-MID: bb.2.while.end: define void @check_negated_reordered_wls(ptr nocapture %a, ptr nocapture readonly %b, i32 %N) { entry: diff --git a/llvm/test/CodeGen/X86/global-sections.ll b/llvm/test/CodeGen/X86/global-sections.ll index b300fc87e38ab..ebfb25fecae38 100644 --- a/llvm/test/CodeGen/X86/global-sections.ll +++ b/llvm/test/CodeGen/X86/global-sections.ll @@ -35,9 +35,9 @@ bb5: ret void } -; LINUX: .size F2, -; LINUX-NEX: .cfi_endproc -; LINUX-NEX: .section .rodata,"a",@progbits +; LINUX: .size F2, +; LINUX-NEXT: .cfi_endproc +; LINUX-NEXT: .section .rodata,"a",@progbits ; LINUX-SECTIONS: .section .text.F2,"ax",@progbits ; LINUX-SECTIONS: .size F2, diff --git a/llvm/test/CodeGen/X86/tailregccpic.ll b/llvm/test/CodeGen/X86/tailregccpic.ll index f89c4ac4df599..a3a17d3b05397 100644 --- a/llvm/test/CodeGen/X86/tailregccpic.ll +++ b/llvm/test/CodeGen/X86/tailregccpic.ll @@ -13,12 +13,12 @@ entry: ret void } -;CHECK-LABLE: tail_call_regcall: +;CHECK-LABEL: tail_call_regcall: ;CHECK: # %bb.0: ;CHECK-NEXT: jmp __regcall3__func # TAILCALL ;CHECK-NEXT: .Lfunc_end0: -;CHECK-LABLE: __regcall3__func: +;CHECK-LABEL: __regcall3__func: ;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx ;CHECK-NEXT: movl a0@GOT(%ecx), %ecx ;CHECK-NEXT: movl %eax, (%ecx) diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir index 10f12458a9963..f369cdb16ab03 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir @@ -43,7 +43,7 @@ debugValueSubstitutions: body: | bb.0.entry: successors: %bb.1, %bb.2 - ; CHECK-LABE: bb.0.entry: + ; CHECK-LABEL: bb.0.entry: $rax = MOV64ri 1, debug-instr-number 1, debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !17 @@ -69,8 +69,8 @@ body: | ;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17 ;DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(4, 0), debug-location !17 ;;; Test non-def operand - ;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0) - ;; check-next: DBG_VALUE_LIST {{.+}}, $noreg + ; COM: CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0) + ; COM: CHECK-NEXT: DBG_VALUE_LIST {{.+}}, $noreg $noreg = MOV32ri 1, debug-instr-number 5, debug-location !17 DBG_INSTR_REF !16, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(5, 0), debug-location !17 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir index c1ae0ab9c95a9..6087522bb2ec1 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/single-assign-propagation.mir @@ -55,11 +55,11 @@ ## to bb.3, but not into bb.4 because of the intervening out-of-scope block. ## Disabled actual testing of this because it's just for comparison purposes. # -# varloc-label: bb.1: +# varloc-LABEL: bb.1: # varloc: DBG_VALUE -# varloc-label: bb.2: +# varloc-LABEL: bb.2: ## No location here because it's out-of-scope. -# varloc-label: bb.3: +# varloc-LABEL: bb.3: # varloc: DBG_VALUE # ## Common tail for 'test2' -- this is checking that the assignment of undef or diff --git a/llvm/test/MC/AArch64/SME/feature.s b/llvm/test/MC/AArch64/SME/feature.s index f6193b1557b1b..87afb5b333eb5 100644 --- a/llvm/test/MC/AArch64/SME/feature.s +++ b/llvm/test/MC/AArch64/SME/feature.s @@ -8,4 +8,4 @@ tbx z0.b, z1.b, z2.b // Verify +sme flags imply +bf16 bfdot z0.s, z1.h, z2.h -// CHECK-INST: bfdot z0.s, z1.h, z2.h +// CHECK: bfdot z0.s, z1.h, z2.h diff --git a/llvm/test/MC/ARM/coff-relocations.s b/llvm/test/MC/ARM/coff-relocations.s index 5225b5e656762..16993cf7a8588 100644 --- a/llvm/test/MC/ARM/coff-relocations.s +++ b/llvm/test/MC/ARM/coff-relocations.s @@ -25,7 +25,7 @@ branch24t_1: bl target @ CHECK-ENCODING-LABEL: : -@ CHECK-ENCODING-NEXR: bl {{.+}} @ imm = #0 +@ CHECK-ENCODING-NEXT: bl {{.+}} @ imm = #0 .thumb_func branch20t: diff --git a/llvm/test/MC/AsmParser/labels.s b/llvm/test/MC/AsmParser/labels.s index 599ce72c44eef..4d6653bfb7de4 100644 --- a/llvm/test/MC/AsmParser/labels.s +++ b/llvm/test/MC/AsmParser/labels.s @@ -29,7 +29,7 @@ foo: // CHECK: .long 11 .long "a 0" -// XXCHCK: .section "a 1,a 2" +// COM: CHECK: .section "a 1,a 2" //.section "a 1", "a 2" // CHECK: .globl "a 3" @@ -46,7 +46,7 @@ foo: // FIXME: We don't bother to support .lsym. -// CHECX: .lsym "a 8",1 +// COM: CHECK: .lsym "a 8",1 // .lsym "a 8", 1 // CHECK: .set "a 9", a-b diff --git a/llvm/test/MC/COFF/cv-inline-linetable.s b/llvm/test/MC/COFF/cv-inline-linetable.s index 2748fa71df75c..4cea3b1576896 100644 --- a/llvm/test/MC/COFF/cv-inline-linetable.s +++ b/llvm/test/MC/COFF/cv-inline-linetable.s @@ -76,9 +76,9 @@ Lfunc_end0: # PDB-NEXT: 0B26 code 0x1F (+0x6) line 2 (+1) # PDB-NEXT: 0B27 code 0x26 (+0x7) line 3 (+1) # PDB-NEXT: 0407 code end 0x2D (+0x7) -# PEB: S_INLINESITE_END -# PEB: S_INLINESITE_END -# PEB: S_PROC_ID_END +# PDB: S_INLINESITE_END +# PDB: S_INLINESITE_END +# PDB: S_PROC_ID_END .section .debug$T,"dr" .long 4 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt index 1d37bbcaf3865..ebaeeba50d10f 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt @@ -22,13 +22,13 @@ # CHECK: bfdot v2.4s, v3.8h, v4.2h[2] # CHECK: bfdot v2.4s, v3.8h, v4.2h[3] # NOBF16: warning: invalid instruction encoding -# NOBF-NEXT: [0x62,0xf0,0x44,0x4f] +# NOBF16-NEXT: [0x62,0xf0,0x44,0x4f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf0,0x64,0x4f] +# NOBF16-NEXT: [0x62,0xf0,0x64,0x4f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x44,0x4f] +# NOBF16-NEXT: [0x62,0xf8,0x44,0x4f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x64,0x4f] +# NOBF16-NEXT: [0x62,0xf8,0x64,0x4f] [0x62,0xf0,0x44,0x0f] @@ -40,13 +40,13 @@ # CHECK: bfdot v2.2s, v3.4h, v4.2h[2] # CHECK: bfdot v2.2s, v3.4h, v4.2h[3] # NOBF16: warning: invalid instruction encoding -# NOBF-NEXT: [0x62,0xf0,0x44,0x0f] +# NOBF16-NEXT: [0x62,0xf0,0x44,0x0f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf0,0x64,0x0f] +# NOBF16-NEXT: [0x62,0xf0,0x64,0x0f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x44,0x0f] +# NOBF16-NEXT: [0x62,0xf8,0x44,0x0f] # NOBF16: warning: invalid instruction encoding -# NOBF6-NEXT: [0x62,0xf8,0x64,0x0f] +# NOBF16-NEXT: [0x62,0xf8,0x64,0x0f] [0x62,0xec,0x44,0x6e] diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index 008bb1154e57f..fb999c3349c79 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -48,7 +48,7 @@ # FIXME: LDC encoding information is incorrect. Re-enable this along with more # robust testing for other values when we get it fleshed out and working # properly. -# CHECKx: ldclvc p5, cr15, [r8], #-0 +# COM: CHECK: ldclvc p5, cr15, [r8], #-0 #0x00 0xf5 0x78 0x7c # CHECK: ldc p13, c9, [r2, #0]! diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt index e1ba009f3c4c8..9708821affae0 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt @@ -39,7 +39,7 @@ 0x04 0x11 0x14 0x9b # CHECK: bal 21104 # The encode/decode functions are not inverses of each other. 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 -0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 +0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 @@ -162,13 +162,13 @@ 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260 -0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20 +0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260 0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260 -0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20 +0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260 0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt index 0030e51d6c238..28cd1619e80ad 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt @@ -56,7 +56,7 @@ 0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, 43981 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336 -0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20 +0x18 0x02 0xff 0xfa # CHECK: blezalc $2, -20 # The encode/decode functions are not inverses of each other in the immediate case. 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20 @@ -181,13 +181,13 @@ 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260 -0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20 +0x58 0x05 0xff 0xfa # CHECK: blezc $5, -20 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260 0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260 -0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20 +0x5c 0x05 0xff 0xfa # CHECK: bgtzc $5, -20 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260 0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt index 91831b64d4472..9ed3ac5a8fb9d 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt @@ -156,7 +156,7 @@ # CHECK: dcffixq. 12, 8 0xfd 0x80 0x46 0x45 -# CHECK : dcffixqq 18, 20 +# CHECK: dcffixqq 18, 20 0xfe 0x40 0xa7 0xc4 # CHECK: dctfix 8, 4 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt index 567c4fa5bd5ab..54bf5c4da43c0 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -325,7 +325,7 @@ # CHECK: subfeo 2, 3, 4 0x7c 0x43 0x25 0x10 -# CHECKE: subfeo. 2, 3, 4 +# CHECK: subfeo. 2, 3, 4 0x7c 0x43 0x25 0x11 # CHECK: addme 2, 3 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt index 15427e91a5b2a..269b561c91bf4 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt @@ -313,7 +313,7 @@ # CHECK: subfeo 2, 3, 4 0x10 0x25 0x43 0x7c -# CHECKE: subfeo. 2, 3, 4 +# CHECK: subfeo. 2, 3, 4 0x11 0x25 0x43 0x7c # CHECK: addme 2, 3 diff --git a/llvm/test/MC/Disassembler/X86/x86-16.txt b/llvm/test/MC/Disassembler/X86/x86-16.txt index 7de31411885ce..df91cd0d5bcd9 100644 --- a/llvm/test/MC/Disassembler/X86/x86-16.txt +++ b/llvm/test/MC/Disassembler/X86/x86-16.txt @@ -222,46 +222,46 @@ # CHECK: movw (%eax), %cs 0x67 0x8e 0x08 -# CHECKX: movl %cr0, %eax +# CHECK: movl %cr0, %eax 0x0f 0x20 0xc0 -# CHECKX: movl %cr1, %eax +# CHECK: movl %cr1, %eax 0x0f 0x20 0xc8 -# CHECKX: movl %cr2, %eax +# CHECK: movl %cr2, %eax 0x0f 0x20 0xd0 -# CHECKX: movl %cr3, %eax +# CHECK: movl %cr3, %eax 0x0f 0x20 0xd8 -# CHECKX: movl %cr4, %eax +# CHECK: movl %cr4, %eax 0x0f 0x20 0xe0 -# CHECKX: movl %dr0, %eax +# CHECK: movl %dr0, %eax 0x0f 0x21 0xc0 -# CHECKX: movl %dr1, %eax +# CHECK: movl %dr1, %eax 0x0f 0x21 0xc8 -# CHECKX: movl %dr1, %eax +# CHECK: movl %dr1, %eax 0x0f 0x21 0xc8 -# CHECKX: movl %dr2, %eax +# CHECK: movl %dr2, %eax 0x0f 0x21 0xd0 -# CHECKX: movl %dr3, %eax +# CHECK: movl %dr3, %eax 0x0f 0x21 0xd8 -# CHECKX: movl %dr4, %eax +# CHECK: movl %dr4, %eax 0x0f 0x21 0xe0 -# CHECKX: movl %dr5, %eax +# CHECK: movl %dr5, %eax 0x0f 0x21 0xe8 -# CHECKX: movl %dr6, %eax +# CHECK: movl %dr6, %eax 0x0f 0x21 0xf0 -# CHECKX: movl %dr7, %eax +# CHECK: movl %dr7, %eax 0x0f 0x21 0xf8 # CHECK: wait @@ -765,10 +765,10 @@ # CHECK: fsubp %st, %st(2) 0xde 0xe2 -# CHECKX: nop +# CHECK: nop 0x66 0x90 -# CHECKX: nop +# CHECK: nop 0x90 # CHECK: xchgl %ecx, %eax diff --git a/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s b/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s index a43c8084dbfa0..df05d136d7b97 100644 --- a/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s +++ b/llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s @@ -34,4 +34,4 @@ r0 += add(r1, r2) } -# CHECK { r0 += add(r1,r2) } +# CHECK:{ r0 += add(r1,r2) } diff --git a/llvm/test/MC/LoongArch/Relocations/relax-align.s b/llvm/test/MC/LoongArch/Relocations/relax-align.s index 477d5ca24ec7d..3103a7b1055cb 100644 --- a/llvm/test/MC/LoongArch/Relocations/relax-align.s +++ b/llvm/test/MC/LoongArch/Relocations/relax-align.s @@ -58,7 +58,7 @@ break 6 # RELAX-INSTR-NEXT: nop ret -# INSNR-NEXT: ret +# INSTR-NEXT: ret ## Test the symbol index is different from .text. .section .text2, "ax" diff --git a/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s b/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s index af8ba714ef80a..90b3f4f4951df 100644 --- a/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s +++ b/llvm/test/MC/M68k/Arith/Classes/MxFBinary_FF.s @@ -17,33 +17,33 @@ fdadd.x %fp3, %fp4 fsub.x %fp1, %fp2 ; CHECK: fssub.x %fp3, %fp4 -; CHECK-SAME; encoding: [0xf2,0x00,0x0e,0x68] +; CHECK-SAME: encoding: [0xf2,0x00,0x0e,0x68] fssub.x %fp3, %fp4 ; CHECK: fdsub.x %fp5, %fp6 -; CHECK-SAME; encoding: [0xf2,0x00,0x17,0x6c] +; CHECK-SAME: encoding: [0xf2,0x00,0x17,0x6c] fdsub.x %fp5, %fp6 ; CHECK: fmul.x %fp2, %fp3 -; CHECK-SAME; encoding: [0xf2,0x00,0x09,0xa3] +; CHECK-SAME: encoding: [0xf2,0x00,0x09,0xa3] fmul.x %fp2, %fp3 ; CHECK: fsmul.x %fp4, %fp5 -; CHECK-SAME; encoding: [0xf2,0x00,0x12,0xe3] +; CHECK-SAME: encoding: [0xf2,0x00,0x12,0xe3] fsmul.x %fp4, %fp5 ; CHECK: fdmul.x %fp6, %fp7 -; CHECK-SAME; encoding: [0xf2,0x00,0x1b,0xe7] +; CHECK-SAME: encoding: [0xf2,0x00,0x1b,0xe7] fdmul.x %fp6, %fp7 ; CHECK: fdiv.x %fp3, %fp4 -; CHECK-SAME; encoding: [0xf2,0x00,0x0e,0x20] +; CHECK-SAME: encoding: [0xf2,0x00,0x0e,0x20] fdiv.x %fp3, %fp4 ; CHECK: fsdiv.x %fp5, %fp6 -; CHECK-SAME; encoding: [0xf2,0x00,0x17,0x60] +; CHECK-SAME: encoding: [0xf2,0x00,0x17,0x60] fsdiv.x %fp5, %fp6 ; CHECK: fddiv.x %fp7, %fp0 -; CHECK-SAME; encoding: [0xf2,0x00,0x1c,0x64] +; CHECK-SAME: encoding: [0xf2,0x00,0x1c,0x64] fddiv.x %fp7, %fp0 diff --git a/llvm/test/MC/MachO/lto-set-conditional.s b/llvm/test/MC/MachO/lto-set-conditional.s index 0007d4a259cbc..1ea26eaa231ec 100644 --- a/llvm/test/MC/MachO/lto-set-conditional.s +++ b/llvm/test/MC/MachO/lto-set-conditional.s @@ -57,14 +57,14 @@ a: # CHECK: Symbol { # CHECK-NEXT: Name: m # CHECK: Flags [ -# CHECK-NOT : NoDeadStrip +# CHECK-NOT: NoDeadStrip # CHECK: Value: 0x2 m: # CHECK: Symbol { # CHECK-NEXT: Name: h # CHECK: Flags [ -# CHECK-NOT : NoDeadStrip +# CHECK-NOT: NoDeadStrip # CHECK: Value: 0x2 .lto_set_conditional h, m diff --git a/llvm/test/MC/Mips/macro-rem.s b/llvm/test/MC/Mips/macro-rem.s index 40812949664d6..1f10a5392c07f 100644 --- a/llvm/test/MC/Mips/macro-rem.s +++ b/llvm/test/MC/Mips/macro-rem.s @@ -95,7 +95,7 @@ # CHECK-NOTRAP: bnez $6, $tmp2 # encoding: [A,A,0xc0,0x14] # CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x1a,0x00,0xa6,0x00] # CHECK-NOTRAP: break 7 # encoding: [0x0d,0x00,0x07,0x00] -# CHECk-NOTRAP: $tmp2 +# CHECK-NOTRAP: $tmp2 # CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24] # CHECK-NOTRAP: bne $6, $1, $tmp3 # encoding: [A,A,0xc1,0x14] # CHECK-NOTRAP: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c] diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid.s b/llvm/test/MC/Mips/micromips-dsp/invalid.s index 05fc77440d3ef..52120a02ce8cd 100644 --- a/llvm/test/MC/Mips/micromips-dsp/invalid.s +++ b/llvm/test/MC/Mips/micromips-dsp/invalid.s @@ -9,16 +9,14 @@ shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index a995c37b15c3a..e3a68cb3bd444 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -302,13 +302,13 @@ sce $2, 8($4) # CHECK: sce $2, 8($4) # encoding: [0x60,0x syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c] syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] # FIXME: ldc1 should accept uneven registers -# ldc1 $f7, 300($10) # -CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c] +# ldc1 $f7, 300($10) # COM: CHECK: ldc1 $f7, 300($10) # encoding: [0xbc,0xea,0x01,0x2c] ldc1 $f8, 300($10) # CHECK: ldc1 $f8, 300($10) # encoding: [0xbd,0x0a,0x01,0x2c] lwc1 $f2, 4($6) # CHECK: lwc1 $f2, 4($6) # encoding: [0x9c,0x46,0x00,0x04] # CHECK-NEXT: # ; // WRITER-NEXT: }; // ALIAS: static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { -// ALIAS-NEXT switch (VariantID) { -// ALIAS-NEXT case 0: -// ALIAS-NEXT switch (Mnemonic.size()) { -// ALIAS-NEXT default: break; -// ALIAS-NEXT case 5: // 2 strings to match. -// ALIAS-NEXT if (memcmp(Mnemonic.data()+0, "inst", 4) != 0) -// ALIAS-NEXT break; -// ALIAS-NEXT switch (Mnemonic[4]) { -// ALIAS-NEXT default: break; -// ALIAS-NEXT case 'a': // 1 string to match. -// ALIAS-NEXT Mnemonic = "ainst"; // "insta" -// ALIAS-NEXT return; -// ALIAS-NEXT case 'b': // 1 string to match. -// ALIAS-NEXT Mnemonic = "binst"; // "instb" -// ALIAS-NEXT return; +// ALIAS-NEXT: switch (VariantID) { +// ALIAS-NEXT: case 0: +// ALIAS-NEXT: switch (Mnemonic.size()) { +// ALIAS-NEXT: default: break; +// ALIAS-NEXT: case 5: // 2 strings to match. +// ALIAS-NEXT: if (memcmp(Mnemonic.data()+0, "inst", 4) != 0) +// ALIAS-NEXT: break; +// ALIAS-NEXT: switch (Mnemonic[4]) { +// ALIAS-NEXT: default: break; +// ALIAS-NEXT: case 'a': // 1 string to match. +// ALIAS-NEXT: Mnemonic = "ainst"; // "insta" +// ALIAS-NEXT: return; +// ALIAS-NEXT: case 'b': // 1 string to match. +// ALIAS-NEXT: Mnemonic = "binst"; // "instb" +// ALIAS-NEXT: return; \ No newline at end of file diff --git a/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll b/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll index 256261d0dd11f..ea8abfb554d12 100644 --- a/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll +++ b/llvm/test/Transforms/CallSiteSplitting/callsite-split.ll @@ -72,7 +72,7 @@ declare void @dummy1(ptr, ptr, ptr, ptr, ptr, ptr) ;CHECK: call void @dummy4() ;CHECK-LABEL: NextCond.split: ;CHECK: call void @dummy3() -;CheCK-LABEL: CallSiteBB: +;CHECK-LABEL: CallSiteBB: ;CHECK: call void @foo(i1 %tobool1) define void @caller2(i1 %c, ptr %a_elt, ptr %b_elt, ptr %c_elt) { entry: diff --git a/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll b/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll index fd3b7bd815300..531d3c36ac299 100644 --- a/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll +++ b/llvm/test/Transforms/Coroutines/coro-await-suspend-lower-invoke.ll @@ -26,7 +26,7 @@ step: invoke void @llvm.coro.await.suspend.void(ptr %awaiter, ptr %hdl, ptr @await_suspend_wrapper_void) to label %step.continue unwind label %pad -; CHECK [[STEP_CONT]]: +; CHECK: [[STEP_CONT]]: step.continue: %suspend = call i8 @llvm.coro.suspend(token %save, i1 false) switch i8 %suspend, label %ret [ diff --git a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll index 1d668fd0222f7..d1242ac7348c2 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll @@ -38,7 +38,7 @@ ; CHECK-DAG: ![[UNALIGNED_UNKNOWN]] = !DIDerivedType(tag: DW_TAG_member, name: "_6",{{.*}}baseType: ![[UNALIGNED_UNKNOWN_BASE:[0-9]+]], size: 9 ; CHECK-DAG: ![[UNALIGNED_UNKNOWN_BASE]] = !DICompositeType(tag: DW_TAG_array_type, baseType: ![[UNKNOWN_TYPE_BASE]], size: 16,{{.*}} elements: ![[UNALIGNED_UNKNOWN_ELEMENTS:[0-9]+]]) ; CHECK-DAG: ![[UNALIGNED_UNKNOWN_ELEMENTS]] = !{![[UNALIGNED_UNKNOWN_SUBRANGE:[0-9]+]]} -; CHECk-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0) +; CHECK-DAG: ![[UNALIGNED_UNKNOWN_SUBRANGE]] = !DISubrange(count: 2, lowerBound: 0) ; CHECK-DAG: ![[STRUCT]] = !DIDerivedType(tag: DW_TAG_member, name: "struct_big_structure_7", scope: ![[FRAME_TYPE]], file: ![[FILE]], line: [[CORO_FRAME_LINE]], baseType: ![[STRUCT_BASE:[0-9]+]] ; CHECK-DAG: ![[STRUCT_BASE]] = !DICompositeType(tag: DW_TAG_structure_type, name: "struct_big_structure"{{.*}}, align: 64, flags: DIFlagArtificial, elements: ![[STRUCT_ELEMENTS:[0-9]+]] ; CHECK-DAG: ![[STRUCT_ELEMENTS]] = !{![[MEM_TYPE:[0-9]+]]} diff --git a/llvm/test/Transforms/FunctionAttrs/nonnull.ll b/llvm/test/Transforms/FunctionAttrs/nonnull.ll index 0f6762f0d4342..b6f471634f117 100644 --- a/llvm/test/Transforms/FunctionAttrs/nonnull.ll +++ b/llvm/test/Transforms/FunctionAttrs/nonnull.ll @@ -717,7 +717,6 @@ declare i8 @use1safecall(ptr %x) nounwind willreturn ; nounwind+willreturn guara ; Without noundef, nonnull cannot be propagated to the parent define void @parent_poison(ptr %a) { -; FNATTR-LABEL: @parent_poison(ptr %a) ; FNATTRS-LABEL: define void @parent_poison( ; FNATTRS-SAME: ptr [[A:%.*]]) { ; FNATTRS-NEXT: call void @use1nonnull_without_noundef(ptr [[A]]) diff --git a/llvm/test/Transforms/GVNSink/sink-common-code.ll b/llvm/test/Transforms/GVNSink/sink-common-code.ll index c77a85f95f1a5..98f66e13206bd 100644 --- a/llvm/test/Transforms/GVNSink/sink-common-code.ll +++ b/llvm/test/Transforms/GVNSink/sink-common-code.ll @@ -78,12 +78,12 @@ declare i32 @foo(i32, i32) nounwind readnone ; ret i32 %ret ;} ; -; -CHECK-LABEL: test3 -; -CHECK: select -; -CHECK: call -; -CHECK: call -; -CHECK: add -; -CHECK-NOT: br +; COM: CHECK-LABEL: test3 +; COM: CHECK: select +; COM: CHECK: call +; COM: CHECK: call +; COM: CHECK: add +; COM: CHECK-NOT: br define i32 @test4(i1 zeroext %flag, i32 %x, ptr %y) { entry: diff --git a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll index e379b32b45734..62573398fc16a 100644 --- a/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll +++ b/llvm/test/Transforms/InstCombine/lifetime-sanitizer.ll @@ -56,7 +56,7 @@ entry: call void @llvm.lifetime.start.p0(i64 1, ptr %text) call void @llvm.lifetime.end.p0(i64 1, ptr %text) - ; CHECK-NO: call void @llvm.lifetime + ; CHECK-NOT: call void @llvm.lifetime call void @foo(ptr %text) ; Keep alloca alive diff --git a/llvm/test/Transforms/InstCombine/str-int-2.ll b/llvm/test/Transforms/InstCombine/str-int-2.ll index 1d9bd3211e038..b5da77c3f5fbe 100644 --- a/llvm/test/Transforms/InstCombine/str-int-2.ll +++ b/llvm/test/Transforms/InstCombine/str-int-2.ll @@ -119,7 +119,7 @@ define i64 @atol_test() #0 { ; CHECK-LABEL: @atol_test( ; CHECK-NEXT: ret i64 499496729 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i64 @atol(ptr @.str.6) #4 ret i64 %call } @@ -136,7 +136,7 @@ define i64 @strtoll_test() #0 { ; CHECK-LABEL: @strtoll_test( ; CHECK-NEXT: ret i64 4994967295 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i64 @strtoll(ptr @.str.7, ptr null, i32 10) #5 ret i64 %call } diff --git a/llvm/test/Transforms/InstCombine/str-int.ll b/llvm/test/Transforms/InstCombine/str-int.ll index d724f0ea156de..262b776a7833a 100644 --- a/llvm/test/Transforms/InstCombine/str-int.ll +++ b/llvm/test/Transforms/InstCombine/str-int.ll @@ -123,7 +123,7 @@ define i32 @atol_test() #0 { ; CHECK-LABEL: @atol_test( ; CHECK-NEXT: ret i32 499496729 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i32 @atol(ptr @.str.6) #4 ret i32 %call } @@ -140,7 +140,7 @@ define i64 @strtoll_test() #0 { ; CHECK-LABEL: @strtoll_test( ; CHECK-NEXT: ret i64 4994967295 ; -; CHECK-NEXT +; FIXME: COM: CHECK-NEXT: %call = call i64 @strtoll(ptr @.str.7, ptr null, i32 10) #5 ret i64 %call } diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll index a732984d697ad..754e0d32cc1d0 100644 --- a/llvm/test/Transforms/LoopUnroll/peel-loop2.ll +++ b/llvm/test/Transforms/LoopUnroll/peel-loop2.ll @@ -32,7 +32,7 @@ for.end: ret void } -; CHECK_LABEL: @funca +; CHECK-LABEL: @funca ; Peeled iteration ; CHECK: %[[REG1:[0-9]+]] = load i8, ptr @Comma diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll index 75f03c7b1a699..c7edf9bdfaf6b 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll @@ -259,7 +259,7 @@ for.cond.cleanup: ; preds = %for.body define i4 @test_i4_load(ptr %ddst) { ; CHECK-LABEL: define i4 @test_i4_load ; CHECK-NOT: vector.body: -; CHECk: ret i4 %{{.*}} +; CHECK: ret i4 %{{.*}} ; entry: br label %for.body @@ -282,7 +282,7 @@ define i8 @test_load_i8(ptr %ddst) { ; CHECK-LABEL: @test_load_i8( ; CHECK: vector.body: ; CHECK: load <4 x i8>, ptr {{.*}}, align 1, !nontemporal !0 -; CHECk: ret i8 %{{.*}} +; CHECK: ret i8 %{{.*}} ; entry: br label %for.body @@ -305,7 +305,7 @@ define half @test_half_load(ptr %ddst) { ; CHECK-LABEL: @test_half_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x half>, ptr {{.*}}, align 2, !nontemporal !0 -; CHECk: ret half %{{.*}} +; CHECK: ret half %{{.*}} ; entry: br label %for.body @@ -328,7 +328,7 @@ define i16 @test_i16_load(ptr %ddst) { ; CHECK-LABEL: @test_i16_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i16>, ptr {{.*}}, align 2, !nontemporal !0 -; CHECk: ret i16 %{{.*}} +; CHECK: ret i16 %{{.*}} ; entry: br label %for.body @@ -351,7 +351,7 @@ define i32 @test_i32_load(ptr %ddst) { ; CHECK-LABEL: @test_i32_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i32>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret i32 %{{.*}} +; CHECK: ret i32 %{{.*}} ; entry: br label %for.body @@ -373,7 +373,7 @@ for.cond.cleanup: ; preds = %for.body define i33 @test_i33_load(ptr %ddst) { ; CHECK-LABEL: @test_i33_load ; CHECK-NOT: vector.body: -; CHECk: ret i33 %{{.*}} +; CHECK: ret i33 %{{.*}} ; entry: br label %for.body @@ -395,7 +395,7 @@ for.cond.cleanup: ; preds = %for.body define i40 @test_i40_load(ptr %ddst) { ; CHECK-LABEL: @test_i40_load ; CHECK-NOT: vector.body: -; CHECk: ret i40 %{{.*}} +; CHECK: ret i40 %{{.*}} ; entry: br label %for.body @@ -418,7 +418,7 @@ define i64 @test_i64_load(ptr %ddst) { ; CHECK-LABEL: @test_i64_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i64>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret i64 %{{.*}} +; CHECK: ret i64 %{{.*}} ; entry: br label %for.body @@ -441,7 +441,7 @@ define double @test_double_load(ptr %ddst) { ; CHECK-LABEL: @test_double_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x double>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret double %{{.*}} +; CHECK: ret double %{{.*}} ; entry: br label %for.body @@ -464,7 +464,7 @@ define i128 @test_i128_load(ptr %ddst) { ; CHECK-LABEL: @test_i128_load ; CHECK-LABEL: vector.body: ; CHECK: load <4 x i128>, ptr {{.*}}, align 4, !nontemporal !0 -; CHECk: ret i128 %{{.*}} +; CHECK: ret i128 %{{.*}} ; entry: br label %for.body @@ -486,7 +486,7 @@ for.cond.cleanup: ; preds = %for.body define i256 @test_256_load(ptr %ddst) { ; CHECK-LABEL: @test_256_load ; CHECK-NOT: vector.body: -; CHECk: ret i256 %{{.*}} +; CHECK: ret i256 %{{.*}} ; entry: br label %for.body diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll index 8333c3193d799..748fbb8233588 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll @@ -911,7 +911,7 @@ define float @fadd_scalar_vf_fmf(ptr noalias nocapture readonly %a, i64 %n) { ; CHECK-UNORDERED: [[SUM_07:%.*]] = phi float [ [[MERGE_RDX]], %scalar.ph ], [ [[FADD5:%.*]], %for.body ] ; CHECK-UNORDERED: [[LOAD5:%.*]] = load float, ptr ; CHECK-UNORDERED: [[FADD5]] = fadd nnan float [[LOAD5]], [[SUM_07]] -; CHECK-UORDERED: for.end +; CHECK-UNORDERED: for.end ; CHECK-UNORDERED: [[RES:%.*]] = phi float [ [[FADD5]], %for.body ], [ [[BIN_RDX3]], %middle.block ] ; CHECK-UNORDERED: ret float [[RES]] diff --git a/llvm/test/Transforms/LoopVectorize/memdep.ll b/llvm/test/Transforms/LoopVectorize/memdep.ll index b891b4312f18d..eb8c75741c0c0 100644 --- a/llvm/test/Transforms/LoopVectorize/memdep.ll +++ b/llvm/test/Transforms/LoopVectorize/memdep.ll @@ -244,7 +244,7 @@ for.end: ; RIGHTVF-LABEL: @pr34283 ; RIGHTVF: <4 x i64> -; WRONGVF-LABLE: @pr34283 +; WRONGVF-LABEL: @pr34283 ; WRONGVF-NOT: <8 x i64> @a = common local_unnamed_addr global [64 x i32] zeroinitializer, align 16 diff --git a/llvm/test/Transforms/ObjCARC/rv.ll b/llvm/test/Transforms/ObjCARC/rv.ll index ae35d28e5b011..209b49b30f4a5 100644 --- a/llvm/test/Transforms/ObjCARC/rv.ll +++ b/llvm/test/Transforms/ObjCARC/rv.ll @@ -103,9 +103,9 @@ entry: ; directly to a return value. ; TODO -; HECK: define ptr @test5 -; HECK: call ptr @returner() -; HECK-NEXT: ret ptr %call +; COM: CHECK: define ptr @test5 +; COM: CHECK: call ptr @returner() +; COM: CHECK-NEXT: ret ptr %call ;define ptr @test5() { ;entry: ; %call = call ptr @returner() diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll index d279f342666a7..f30abc32468e7 100644 --- a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll +++ b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll @@ -37,7 +37,7 @@ for.cond: ; preds = %for.inc, %entry for.body: ; preds = %for.cond ; CHECK: for.body: ; NOTENTRY: %pgocount1 = load i64, ptr @"__profc_?run@@YAXH@Z" -; TENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH@Z", i32 0, i32 1) +; ENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH@Z", i32 0, i32 1) ; CHECK: %1 = add i64 %pgocount1, 1 ; NOTENTRY: store i64 %1, ptr @"__profc_?run@@YAXH@Z" ; ENTRY: store i64 %1, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH@Z", i32 0, i32 1) diff --git a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll index e6c2a7e629a5d..cea752ad6898d 100644 --- a/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll +++ b/llvm/test/Transforms/PartiallyInlineLibCalls/X86/good-prototype.ll @@ -21,7 +21,7 @@ entry: define float @f_writeonly(float %val) { ; CHECK-LABEL: @f_writeonly( -; CHECK-NEXt: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]] +; CHECK-NEXT: [[RES:%.*]] = tail call float @sqrtf(float [[VAL:%.*]]) #[[READNONE]] %res = tail call float @sqrtf(float %val) writeonly ret float %res } diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll index f0b6fdf62d969..d52794e0d2faa 100644 --- a/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll +++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll @@ -20,8 +20,8 @@ F: br label %Merge Merge: ;; Check branch T and F are gone, and their probes (probe 2 and 3) are gone too. -; JT-LABEL-NO: T -; JT-LABEL-NO: F +; JT-NOT{LITERAL}: T: +; JT-NOT{LITERAL}: F: ; JT-LABEL: Merge ; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 4 ; JT-NOT: call void @llvm.pseudoprobe(i64 [[#GUID:]], i64 3 @@ -43,8 +43,8 @@ Merge: define i32 @test(i32 %a, i32 %b, i32 %c) { ;; Check block bb1 and bb2 are gone, and their probes (probe 2 and 3) are gone too. ; SC-LABEL: @test( -; SC-LABEL-NO: bb1 -; SC-LABEL-NO: bb2 +; SC-NOT{LITERAL}: bb1: +; SC-NOT{LITERAL}: bb2: ; SC: [[T1:%.*]] = icmp eq i32 [[B:%.*]], 0 ; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 2 ; SC-NOT: call void @llvm.pseudoprobe(i64 [[#]], i64 3 diff --git a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll index 5d01e78221e38..3bc18c7cdd7bf 100644 --- a/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll +++ b/llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll @@ -10,7 +10,7 @@ entry: if.end: ; preds = %entry ;; Check pseudo probes are next to each other at the beginning of this block. -; IR-label: if.end +; IR-LABEL: if.end ; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1) ; IR: call void @llvm.pseudoprobe(i64 5116412291814990879, i64 3, i32 0, i64 -1) call void @llvm.pseudoprobe(i64 5116412291814990879, i64 1, i32 0, i64 -1) @@ -19,7 +19,7 @@ if.end: ; preds = %entry %2 = and i16 %1, 16 %3 = icmp eq i16 %2, 0 ;; Check the load-and-cmp sequence is fold into a test instruction. -; MIR-label: bb.1.if.end +; MIR-LABEL: bb.1.if.end ; MIR: %[[#REG:]]:gr64 = IMPLICIT_DEF ; MIR: TEST8mi killed %[[#REG]], 1, $noreg, 0, $noreg, 16 ; MIR: JCC_1 diff --git a/llvm/test/Verifier/convergencectrl-invalid.ll b/llvm/test/Verifier/convergencectrl-invalid.ll index e1fffcd1c6033..90f592365b2d3 100644 --- a/llvm/test/Verifier/convergencectrl-invalid.ll +++ b/llvm/test/Verifier/convergencectrl-invalid.ll @@ -21,7 +21,7 @@ define void @wrong_token() { } ; CHECK: Convergence control token can only be used in a convergent call. -; CHECK-NEXT call void @g(){{.*}}%t05_tok1 +; CHECK-NEXT: call void @g(){{.*}}%t05_tok1 define void @missing.attribute() { %t05_tok1 = call token @llvm.experimental.convergence.anchor() call void @g() [ "convergencectrl"(token %t05_tok1) ] @@ -47,7 +47,7 @@ define void @multiple_bundles() { } ; CHECK: Cannot mix controlled and uncontrolled convergence in the same function -; CHECK-NEXT call void @f() +; CHECK-NEXT: call void @f() define void @mixed1() { call void @g() ; not convergent %t10_tok1 = call token @llvm.experimental.convergence.anchor() diff --git a/llvm/test/tools/gold/X86/global_with_section.ll b/llvm/test/tools/gold/X86/global_with_section.ll index 2ba0a16e23782..e4ec41ea4dc59 100644 --- a/llvm/test/tools/gold/X86/global_with_section.ll +++ b/llvm/test/tools/gold/X86/global_with_section.ll @@ -45,7 +45,7 @@ target triple = "x86_64-unknown-linux-gnu" ; Confirm via a variable with a non-C identifier section that we are getting ; the expected internalization. -; CHECK-REGULARLTO-DAG: @var_with_nonC_section = internal global i32 0, section ".nonCsection" +; CHECK2-REGULARLTO-DAG: @var_with_nonC_section = internal global i32 0, section ".nonCsection" ; Check we dropped definition of dead variable. ; CHECK-THINLTO-NOT: @var_with_nonC_section @var_with_nonC_section = global i32 0, section ".nonCsection" diff --git a/llvm/test/tools/llvm-ar/replace-update.test b/llvm/test/tools/llvm-ar/replace-update.test index c056565f144c5..498febdac0193 100644 --- a/llvm/test/tools/llvm-ar/replace-update.test +++ b/llvm/test/tools/llvm-ar/replace-update.test @@ -57,7 +57,7 @@ # MULTIPLE-SYM: symbolnew1 # MULTIPLE-SYM-NEXT: symbol2 -# MULTIPLE-SYM-NEXTs: symbolnew3 +# MULTIPLE-SYM-NEXT: symbolnew3 ## Replace newer members with multiple older files: # RUN: llvm-ar ruU %t/multiple.a %t/1.o %t/2.o diff --git a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json index ce13fc2ff6e34..33c517da91b5e 100644 --- a/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json +++ b/llvm/test/tools/llvm-cov/Inputs/binary-formats.canonical.json @@ -29,7 +29,7 @@ CHECK-SAME: {"branches":{"count":0,"covered":0,"notcovered":0,"percent":0}, CHECK-SAME: "functions":{"count":1,"covered":1,"percent":100}, CHECK-SAME: "instantiations":{"count":1,"covered":1,"percent":100}, CHECK-SAME: "lines":{"count":1,"covered":1,"percent":100}, -CHECk-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0}, +CHECK-SAME: "mcdc":{"count":0,"covered":0,"notcovered":0,"percent":0}, CHECK-SAME: "regions":{"count":1,"covered":1,"notcovered":0,"percent":100}}} CHECK-SAME: ], CHECK-SAME: "type":"llvm.coverage.json.export" diff --git a/llvm/test/tools/llvm-cov/coverage_watermark.test b/llvm/test/tools/llvm-cov/coverage_watermark.test index 5c48b4f0fb4bf..97b9d240e0b09 100644 --- a/llvm/test/tools/llvm-cov/coverage_watermark.test +++ b/llvm/test/tools/llvm-cov/coverage_watermark.test @@ -29,7 +29,7 @@ ORIGIN: RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -format html -show-region-summary -show-instantiation-summary -o %t.html.dir -path-equivalence=/tmp,%S -coverage-watermark 80,70 %S/showTemplateInstantiations.cpp RUN: FileCheck -check-prefix=DOWNGRADE1 %s -input-file %t.html.dir/index.html -DOWNGRADE:1 Totals +DOWNGRADE1: Totals DOWNGRADE1: DOWNGRADE1: 100.00% (2/2) DOWNGRADE1: @@ -45,7 +45,7 @@ DOWNGRADE1: RUN: llvm-cov show %S/Inputs/templateInstantiations.covmapping -instr-profile %S/Inputs/templateInstantiations.profdata -format html -show-region-summary -show-instantiation-summary -o %t.html.dir -path-equivalence=/tmp,%S -coverage-watermark 70,50 %S/showTemplateInstantiations.cpp RUN: FileCheck -check-prefix=DOWNGRADE2 %s -input-file %t.html.dir/index.html -DOWNGRADE:1 Totals +DOWNGRADE2: Totals DOWNGRADE2: DOWNGRADE2: 100.00% (2/2) DOWNGRADE2: @@ -54,6 +54,6 @@ DOWNGRADE2: DOWNGRADE2: 75.00% (9/12) DOWNGRADE2: DOWNGRADE2: 66.67% (4/6) -DOWNGRADE1: -DOWNGRADE1: - (0/0) -DOWNGRADE1: +DOWNGRADE2: +DOWNGRADE2: - (0/0) +DOWNGRADE2: diff --git a/llvm/test/tools/llvm-cov/zeroFunctionFile.c b/llvm/test/tools/llvm-cov/zeroFunctionFile.c index f463007fe7f60..1e5467d497aaa 100644 --- a/llvm/test/tools/llvm-cov/zeroFunctionFile.c +++ b/llvm/test/tools/llvm-cov/zeroFunctionFile.c @@ -15,6 +15,6 @@ int main() { // RUN: llvm-cov show -j 1 %S/Inputs/zeroFunctionFile.covmapping -format html -instr-profile %t.profdata -o %t.dir // RUN: FileCheck %s -input-file=%t.dir/index.html -check-prefix=HTML -// HTML-NO: 0.00% (0/0) +// HTML-NOT: 0.00% (0/0) // HTML: Files which contain no functions // HTML: zeroFunctionFile.h diff --git a/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s b/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s index e56fcd8352ac0..31bcaaccf4698 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names-fail.s @@ -3,7 +3,7 @@ # CHECK: error: Simplified template DW_AT_name could not be reconstituted: # CHECK: original: t1 -# CHECK reconstituted: t1 +# CHECK: reconstituted: t1 .text .file "verify.cpp" .file 1 "/usr/local/google/home/blaikie/dev/scratch" "verify.cpp" diff --git a/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test b/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test index 3f55d687474a7..3346a5ba48c48 100644 --- a/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test +++ b/llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test @@ -90,7 +90,7 @@ #DWARF-CHECK: 0x[[F4RANGE_OFF]]: [DW_RLE_base_addressx]: 0x0000000000000003 #DWARF-CHECK: {{.}}: [DW_RLE_offset_pair ]: 0x0000000000000000, 0x0000000000000010 #DWARF-CHECK: {{.}}: [DW_RLE_end_of_list ] -#DWARF-CHECK 0x[[CURANGE_OFF]]: [DW_RLE_base_addressx]: 0x0000000000000000 +#DWARF-CHECK: 0x[[CURANGE_OFF]]: [DW_RLE_base_addressx]: 0x0000000000000000 #DWARF-CHECK: {{.}}: [DW_RLE_offset_pair ]: 0x0000000000000000, 0x0000000000000040 #DWARF-CHECK: {{.}}: [DW_RLE_end_of_list ] diff --git a/llvm/test/tools/llvm-lib/duplicate.test b/llvm/test/tools/llvm-lib/duplicate.test index 87dae66cb80be..6cdce687c0184 100644 --- a/llvm/test/tools/llvm-lib/duplicate.test +++ b/llvm/test/tools/llvm-lib/duplicate.test @@ -22,4 +22,4 @@ RUN: llvm-nm --print-armap %t/foo.lib | FileCheck %s --check-prefix=DUP # DUP-NEXT: a in abc.o # DUP-NEXT: b in bar.o # DUP-NEXT: c in abc.o -# DUP-EMPTY +# DUP-EMPTY: diff --git a/llvm/test/tools/llvm-objcopy/ELF/update-section.test b/llvm/test/tools/llvm-objcopy/ELF/update-section.test index 79cfe0e719418..49a533e2221dd 100644 --- a/llvm/test/tools/llvm-objcopy/ELF/update-section.test +++ b/llvm/test/tools/llvm-objcopy/ELF/update-section.test @@ -160,7 +160,7 @@ ProgramHeaders: # LONG-SAME: {{ }}9{{$}} # LONG: SectionData ( # LONG-NEXT: |111122223| -# LONT-NEXT: ) +# LONG-NEXT: ) # ADD-UPDATE: Name: .added # ADD-UPDATE: Size: diff --git a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s index 771bce5023933..37271fb902b4d 100644 --- a/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s +++ b/llvm/test/tools/llvm-objdump/ELF/ARM/v5te-subarch.s @@ -5,6 +5,6 @@ strd: strd r0, r1, [r2, +r3] -@ CHECK-LABEL strd +@ CHECK-LABEL: strd @ CHECK: e18200f3 strd r0, r1, [r2, r3] diff --git a/llvm/test/tools/llvm-objdump/X86/start-stop-address.test b/llvm/test/tools/llvm-objdump/X86/start-stop-address.test index c2d51e4b1fdf7..7e38bbb22ef1f 100644 --- a/llvm/test/tools/llvm-objdump/X86/start-stop-address.test +++ b/llvm/test/tools/llvm-objdump/X86/start-stop-address.test @@ -16,7 +16,7 @@ // CHECK-NEXT: 2b: 48 8b 45 f0 movq -16(%rbp), %rax // CHECK-NOT: {{.}} -// CROSSECTION-NOT: Disassembly +// CROSSSECTION-NOT: Disassembly // CROSSSECTION: Disassembly of section .text: // CROSSSECTION-EMPTY: // CROSSSECTION-NEXT: : diff --git a/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test b/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test index 3a264e3b1108b..cb067d53d74af 100644 --- a/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test +++ b/llvm/test/tools/llvm-profgen/filter-ambiguous-profile.test @@ -1,8 +1,8 @@ ; RUN: llvm-profgen --format=text --llvm-sample-profile=%S/Inputs/filter-ambiguous-profile.prof --binary=%S/Inputs/inline-cs-noprobe.perfbin --csspgo-preinliner=0 --output=%t1 || FileCheck %s --input-file %t1 ;CHECK: foo:12345:1000 -;CHECK-NEXT 1: 1000 -;CHECK-NEXT 4: bar:1000 -;CHECK-NEXT 1: 1000 -;CHECK-NEXT 3: goo:300 -;CHECK-NEXT 1: 300 +;CHECK-NEXT: 1: 1000 +;CHECK-NEXT: 4: bar:1000 +;CHECK-NEXT: 1: 1000 +;CHECK-NEXT: 3: goo:300 +;CHECK-NEXT: 1: 300 diff --git a/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test b/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test index b8e3e248e7793..f76de3a0ea4da 100644 --- a/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test +++ b/llvm/test/tools/llvm-profgen/recursion-compression-pseudoprobe.test @@ -73,14 +73,14 @@ ; CHECK: 3: 1 ; CHECK: 5: 4 fb:4 ; CHECK: 6: 1 fa:1 -; CHECK !CFGChecksum: 563022570642068 +; CHECK: !CFGChecksum: 563022570642068 ; CHECK: [main:2 @ foo:5 @ fa:8 @ fa:7 @ fb:5 @ fb:6 @ fa:8 @ fa:7 @ fb:6 @ fa]:6:2 ; CHECK: 1: 2 ; CHECK: 3: 2 ; CHECK: 4: 1 ; CHECK: 7: 1 fb:1 ; CHECK: !CFGChecksum: 563070469352221 - CHECK: [main:2 @ foo:5 @ fa:8 @ fa:7 @ fb:5 @ fb:6 @ fa]:4:1 +; CHECK: [main:2 @ foo:5 @ fa:8 @ fa:7 @ fb:5 @ fb:6 @ fa]:4:1 ; CHECK: 1: 1 ; CHECK: 3: 1 ; CHECK: 5: 1 diff --git a/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test b/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test index 81d193ad30efa..06177d8c1685d 100644 --- a/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test +++ b/llvm/test/tools/llvm-readobj/COFF/codeview-linetables.test @@ -104,84 +104,84 @@ MFUN32-NEXT: SubSectionType: Symbols (0xF1) MFUN32-NEXT: SubSectionSize: 0x8 MFUN32: ] MFUN32-NEXT: FunctionLineTable [ -MFUN32-NEXT LinkageName: _x -MFUN32-NEXT Flags: 0x0 -MFUN32-NEXT CodeSize: 0xA -MFUN32-NEXT FilenameSegment [ -MFUN32-NEXT Filename: d:\source.c -MFUN32-NEXT +0x0 [ -MFUN32-NEXT LineNumberStart: 3 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x3 [ -MFUN32-NEXT LineNumberStart: 4 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x8 [ -MFUN32-NEXT LineNumberStart: 5 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT FunctionLineTable [ -MFUN32-NEXT LinkageName: _y -MFUN32-NEXT Flags: 0x0 -MFUN32-NEXT CodeSize: 0xA -MFUN32-NEXT FilenameSegment [ -MFUN32-NEXT Filename: d:\source.c -MFUN32-NEXT +0x0 [ -MFUN32-NEXT LineNumberStart: 7 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x3 [ -MFUN32-NEXT LineNumberStart: 8 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x8 [ -MFUN32-NEXT LineNumberStart: 9 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT FunctionLineTable [ -MFUN32-NEXT LinkageName: _f -MFUN32-NEXT Flags: 0x0 -MFUN32-NEXT CodeSize: 0x14 -MFUN32-NEXT FilenameSegment [ -MFUN32-NEXT Filename: d:\source.c -MFUN32-NEXT +0x0 [ -MFUN32-NEXT LineNumberStart: 11 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x3 [ -MFUN32-NEXT LineNumberStart: 12 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x8 [ -MFUN32-NEXT LineNumberStart: 13 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0xD [ -MFUN32-NEXT LineNumberStart: 14 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT +0x12 [ -MFUN32-NEXT LineNumberStart: 15 -MFUN32-NEXT LineNumberEndDelta: 0 -MFUN32-NEXT IsStatement: Yes -MFUN32-NEXT ] -MFUN32-NEXT ] -MFUN32-NEXT ] +MFUN32-NEXT: LinkageName: _x +MFUN32-NEXT: Flags: 0x0 +MFUN32-NEXT: CodeSize: 0xA +MFUN32-NEXT: FilenameSegment [ +MFUN32-NEXT: Filename: d:\source.c +MFUN32-NEXT: +0x0 [ +MFUN32-NEXT: LineNumberStart: 3 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x3 [ +MFUN32-NEXT: LineNumberStart: 4 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x8 [ +MFUN32-NEXT: LineNumberStart: 5 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: FunctionLineTable [ +MFUN32-NEXT: LinkageName: _y +MFUN32-NEXT: Flags: 0x0 +MFUN32-NEXT: CodeSize: 0xA +MFUN32-NEXT: FilenameSegment [ +MFUN32-NEXT: Filename: d:\source.c +MFUN32-NEXT: +0x0 [ +MFUN32-NEXT: LineNumberStart: 7 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x3 [ +MFUN32-NEXT: LineNumberStart: 8 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x8 [ +MFUN32-NEXT: LineNumberStart: 9 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: FunctionLineTable [ +MFUN32-NEXT: LinkageName: _f +MFUN32-NEXT: Flags: 0x0 +MFUN32-NEXT: CodeSize: 0x14 +MFUN32-NEXT: FilenameSegment [ +MFUN32-NEXT: Filename: d:\source.c +MFUN32-NEXT: +0x0 [ +MFUN32-NEXT: LineNumberStart: 11 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x3 [ +MFUN32-NEXT: LineNumberStart: 12 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x8 [ +MFUN32-NEXT: LineNumberStart: 13 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0xD [ +MFUN32-NEXT: LineNumberStart: 14 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: +0x12 [ +MFUN32-NEXT: LineNumberStart: 15 +MFUN32-NEXT: LineNumberEndDelta: 0 +MFUN32-NEXT: IsStatement: Yes +MFUN32-NEXT: ] +MFUN32-NEXT: ] +MFUN32-NEXT: ] MFUN32: ] MFUN64: CodeViewDebugInfo [ diff --git a/llvm/test/tools/llvm-reduce/skip-delta-passes.ll b/llvm/test/tools/llvm-reduce/skip-delta-passes.ll index b1f9cfc9a2bfa..d18982d3f8352 100644 --- a/llvm/test/tools/llvm-reduce/skip-delta-passes.ll +++ b/llvm/test/tools/llvm-reduce/skip-delta-passes.ll @@ -11,7 +11,7 @@ ; RESULT: define void @foo() { ; RESULT-NEXT: store i32 ; RESULT-NEXT: ret void -; RESULT0-NOT: attributes +; RESULT-NOT: attributes ; ERROR: unknown pass "foo" define void @foo() #0 { diff --git a/llvm/test/tools/llvm-remarkutil/no-instruction-count.test b/llvm/test/tools/llvm-remarkutil/no-instruction-count.test index 33838796f9cca..12b640030be66 100644 --- a/llvm/test/tools/llvm-remarkutil/no-instruction-count.test +++ b/llvm/test/tools/llvm-remarkutil/no-instruction-count.test @@ -2,4 +2,4 @@ RUN: llvm-remarkutil instruction-count --parser=yaml %p/Inputs/made-up-fake-rema RUN: llvm-remarkutil yaml2bitstream %p/Inputs/made-up-fake-remarks.yaml | llvm-remarkutil instruction-count --parser=bitstream | FileCheck %s ; CHECK-LABEL: Function,InstructionCount -; CHECK-EMPTY +; CHECK-EMPTY: diff --git a/llvm/test/tools/llvm-symbolizer/flag-grouping.test b/llvm/test/tools/llvm-symbolizer/flag-grouping.test index 7bcb68dd47067..14ffb454752c2 100644 --- a/llvm/test/tools/llvm-symbolizer/flag-grouping.test +++ b/llvm/test/tools/llvm-symbolizer/flag-grouping.test @@ -6,5 +6,5 @@ RUN: llvm-symbolizer -apCie%p/Inputs/addr.exe < %p/Inputs/addr.inp | FileCheck % CHECK: ?? at ??:0:0 CHECK: 0x40054d: inctwo CHECK: (inlined by) inc -CHECK (inlined by) main +CHECK: (inlined by) main CHECK: ?? at ??:0:0 diff --git a/llvm/test/tools/lto/discard-value-names.ll b/llvm/test/tools/lto/discard-value-names.ll index 04d25eaf6067c..2c236f5266cd8 100644 --- a/llvm/test/tools/lto/discard-value-names.ll +++ b/llvm/test/tools/lto/discard-value-names.ll @@ -14,7 +14,7 @@ ; DISCARD: %add = add i32 ; KEEP: %cmp.i = icmp -; KEEP : %add = add i32 +; KEEP: %add = add i32 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.10.0" From e6b8c56eed63c7e4eb34a8a8d6342d9221f7e7d5 Mon Sep 17 00:00:00 2001 From: klensy Date: Mon, 3 Feb 2025 19:04:10 +0300 Subject: [PATCH 2/2] bless llvm/test/TableGen/MixedCasedMnemonic.td --- llvm/test/TableGen/MixedCasedMnemonic.td | 30 +++++++++++++----------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/test/TableGen/MixedCasedMnemonic.td b/llvm/test/TableGen/MixedCasedMnemonic.td index 5b75f696bd927..2828695d2f4f4 100644 --- a/llvm/test/TableGen/MixedCasedMnemonic.td +++ b/llvm/test/TableGen/MixedCasedMnemonic.td @@ -58,18 +58,20 @@ def :MnemonicAlias<"InstB", "BInst">; // WRITER-NEXT: }; // ALIAS: static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { -// ALIAS-NEXT: switch (VariantID) { -// ALIAS-NEXT: case 0: -// ALIAS-NEXT: switch (Mnemonic.size()) { +// ALIAS-NEXT: switch (Mnemonic.size()) { +// ALIAS-NEXT: default: break; +// ALIAS-NEXT: case 5: // 2 strings to match. +// ALIAS-NEXT: if (memcmp(Mnemonic.data()+0, "inst", 4) != 0) +// ALIAS-NEXT: break; +// ALIAS-NEXT: switch (Mnemonic[4]) { // ALIAS-NEXT: default: break; -// ALIAS-NEXT: case 5: // 2 strings to match. -// ALIAS-NEXT: if (memcmp(Mnemonic.data()+0, "inst", 4) != 0) -// ALIAS-NEXT: break; -// ALIAS-NEXT: switch (Mnemonic[4]) { -// ALIAS-NEXT: default: break; -// ALIAS-NEXT: case 'a': // 1 string to match. -// ALIAS-NEXT: Mnemonic = "ainst"; // "insta" -// ALIAS-NEXT: return; -// ALIAS-NEXT: case 'b': // 1 string to match. -// ALIAS-NEXT: Mnemonic = "binst"; // "instb" -// ALIAS-NEXT: return; \ No newline at end of file +// ALIAS-NEXT: case 'a': // 1 string to match. +// ALIAS-NEXT: Mnemonic = "ainst"; // "insta" +// ALIAS-NEXT: return; +// ALIAS-NEXT: case 'b': // 1 string to match. +// ALIAS-NEXT: Mnemonic = "binst"; // "instb" +// ALIAS-NEXT: return; +// ALIAS-NEXT: } +// ALIAS-NEXT: break; +// ALIAS-NEXT: } +// ALIAS-NEXT: }