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AMDGPU: Add baseline test for lane index simplification (#117962)
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‎llvm/test/Transforms/InstCombine/AMDGPU/lane-index-simplify-demanded-bits.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize32 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s
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; --------------------------------------------------------------------
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; llvm.amdgcn.readlane
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; --------------------------------------------------------------------
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define i32 @readlane_31(i32 %arg) #0 {
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; CHECK-LABEL: define i32 @readlane_31(
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; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 31)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 31)
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ret i32 %res
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}
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define i32 @readlane_32(i32 %arg) #0 {
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; CHECK-LABEL: define i32 @readlane_32(
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; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 32)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 32)
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ret i32 %res
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}
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define i32 @readlane_33(i32 %arg) #0 {
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; CHECK-LABEL: define i32 @readlane_33(
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; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 33)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 33)
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ret i32 %res
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}
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define i32 @readlane_63(i32 %arg) #0 {
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; CHECK-LABEL: define i32 @readlane_63(
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; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 63)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 63)
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ret i32 %res
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}
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define i32 @readlane_64(i32 %arg) #0 {
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; CHECK-LABEL: define i32 @readlane_64(
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; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 64)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 64)
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ret i32 %res
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}
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define i32 @readlane_and_31(i32 %arg, i32 %idx) #0 {
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; CHECK-LABEL: define i32 @readlane_and_31(
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; CHECK-SAME: i32 [[ARG:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[IDX_CLAMP:%.*]] = and i32 [[IDX]], 31
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[IDX_CLAMP]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%idx.clamp = and i32 %idx, 31
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 %idx.clamp)
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ret i32 %res
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}
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define i32 @readlane_and_63(i32 %arg, i32 %idx) #0 {
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; CHECK-LABEL: define i32 @readlane_and_63(
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; CHECK-SAME: i32 [[ARG:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[IDX_CLAMP:%.*]] = and i32 [[IDX]], 63
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[IDX_CLAMP]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%idx.clamp = and i32 %idx, 63
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 %idx.clamp)
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ret i32 %res
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}
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define i32 @readlane_poison(i32 %arg) #0 {
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; CHECK-LABEL: define i32 @readlane_poison(
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; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 poison)
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 poison)
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ret i32 %res
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}
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define float @readlane_f32_63(float %arg) #0 {
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; CHECK-LABEL: define float @readlane_f32_63(
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; CHECK-SAME: float [[ARG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[ARG]], i32 63)
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; CHECK-NEXT: ret float [[RES]]
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;
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%res = call float @llvm.amdgcn.readlane.f32(float %arg, i32 63)
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ret float %res
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}
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; --------------------------------------------------------------------
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; llvm.amdgcn.writelane
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; --------------------------------------------------------------------
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define i32 @writelane_31(i32 %arg0, i32 %arg1) #0 {
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; CHECK-LABEL: define i32 @writelane_31(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 31, i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 31, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_32(i32 %arg0, i32 %arg1) #0 {
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; CHECK-LABEL: define i32 @writelane_32(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 32, i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 32, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_33(i32 %arg0, i32 %arg1) #0 {
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; CHECK-LABEL: define i32 @writelane_33(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 33, i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 33, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_63(i32 %arg0, i32 %arg1) #0 {
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; CHECK-LABEL: define i32 @writelane_63(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 63, i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 63, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_64(i32 %arg0, i32 %arg1) #0 {
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; CHECK-LABEL: define i32 @writelane_64(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 64, i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 64, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_and_31(i32 %arg0, i32 %arg1, i32 %idx) #0 {
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; CHECK-LABEL: define i32 @writelane_and_31(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[IDX_CLAMP:%.*]] = and i32 [[IDX]], 31
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 [[IDX_CLAMP]], i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%idx.clamp = and i32 %idx, 31
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 %idx.clamp, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_and_63(i32 %arg0, i32 %arg1, i32 %idx) #0 {
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; CHECK-LABEL: define i32 @writelane_and_63(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[IDX_CLAMP:%.*]] = and i32 [[IDX]], 63
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 [[IDX_CLAMP]], i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%idx.clamp = and i32 %idx, 63
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 %idx.clamp, i32 %arg1)
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ret i32 %res
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}
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define i32 @writelane_poison(i32 %arg0, i32 %arg1) #0 {
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; CHECK-LABEL: define i32 @writelane_poison(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 poison, i32 [[ARG1]])
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 poison, i32 %arg1)
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ret i32 %res
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}
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define float @writelane_f32_63(float %arg0, float %arg1) #0 {
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; CHECK-LABEL: define float @writelane_f32_63(
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; CHECK-SAME: float [[ARG0:%.*]], float [[ARG1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.writelane.f32(float [[ARG0]], i32 63, float [[ARG1]])
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; CHECK-NEXT: ret float [[RES]]
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;
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%res = call float @llvm.amdgcn.writelane.f32(float %arg0, i32 63, float %arg1)
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ret float %res
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}
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attributes #0 = { nounwind }
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; WAVE32: {{.*}}
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; WAVE64: {{.*}}

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