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[Clang][Xtensa] Add Xtensa target. (#118008)
This PR implements support for generic Xtensa target in CLang. Co-authored-by: Andrei Safronov <[email protected]>
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lines changed

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lines changed

‎clang/include/clang/Basic/TargetInfo.h

+8-1
Original file line numberDiff line numberDiff line change
@@ -358,7 +358,14 @@ class TargetInfo : public TransferrableTargetInfo,
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// void *__saved_reg_area_end_pointer;
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// void *__overflow_area_pointer;
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//} va_list;
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HexagonBuiltinVaList
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HexagonBuiltinVaList,
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// typedef struct __va_list_tag {
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// int* __va_stk;
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// int* __va_reg;
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// int __va_ndx;
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//} va_list;
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XtensaABIBuiltinVaList
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};
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protected:

‎clang/lib/AST/ASTContext.cpp

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Original file line numberDiff line numberDiff line change
@@ -9751,6 +9751,43 @@ static TypedefDecl *CreateHexagonBuiltinVaListDecl(const ASTContext *Context) {
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return Context->buildImplicitTypedef(VaListTagArrayType, "__builtin_va_list");
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}
97539753

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static TypedefDecl *
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CreateXtensaABIBuiltinVaListDecl(const ASTContext *Context) {
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// typedef struct __va_list_tag {
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RecordDecl *VaListTagDecl = Context->buildImplicitRecord("__va_list_tag");
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VaListTagDecl->startDefinition();
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// int* __va_stk;
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// int* __va_reg;
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// int __va_ndx;
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constexpr size_t NumFields = 3;
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QualType FieldTypes[NumFields] = {Context->getPointerType(Context->IntTy),
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Context->getPointerType(Context->IntTy),
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Context->IntTy};
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const char *FieldNames[NumFields] = {"__va_stk", "__va_reg", "__va_ndx"};
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// Create fields
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for (unsigned i = 0; i < NumFields; ++i) {
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FieldDecl *Field = FieldDecl::Create(
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*Context, VaListTagDecl, SourceLocation(), SourceLocation(),
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&Context->Idents.get(FieldNames[i]), FieldTypes[i], /*TInfo=*/nullptr,
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/*BitWidth=*/nullptr,
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/*Mutable=*/false, ICIS_NoInit);
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Field->setAccess(AS_public);
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VaListTagDecl->addDecl(Field);
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}
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VaListTagDecl->completeDefinition();
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Context->VaListTagDecl = VaListTagDecl;
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QualType VaListTagType = Context->getRecordType(VaListTagDecl);
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// } __va_list_tag;
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TypedefDecl *VaListTagTypedefDecl =
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Context->buildImplicitTypedef(VaListTagType, "__builtin_va_list");
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return VaListTagTypedefDecl;
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}
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static TypedefDecl *CreateVaListDecl(const ASTContext *Context,
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TargetInfo::BuiltinVaListKind Kind) {
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switch (Kind) {
@@ -9772,6 +9809,8 @@ static TypedefDecl *CreateVaListDecl(const ASTContext *Context,
97729809
return CreateSystemZBuiltinVaListDecl(Context);
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case TargetInfo::HexagonBuiltinVaList:
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return CreateHexagonBuiltinVaListDecl(Context);
9812+
case TargetInfo::XtensaABIBuiltinVaList:
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return CreateXtensaABIBuiltinVaListDecl(Context);
97759814
}
97769815

97779816
llvm_unreachable("Unhandled __builtin_va_list type kind");

‎clang/lib/Basic/CMakeLists.txt

+1
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,7 @@ add_clang_library(clangBasic
120120
Targets/WebAssembly.cpp
121121
Targets/X86.cpp
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Targets/XCore.cpp
123+
Targets/Xtensa.cpp
123124
TokenKinds.cpp
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TypeTraits.cpp
125126
Version.cpp

‎clang/lib/Basic/Targets.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@
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#include "Targets/WebAssembly.h"
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#include "Targets/X86.h"
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#include "Targets/XCore.h"
43+
#include "Targets/Xtensa.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/DiagnosticFrontend.h"
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#include "llvm/ADT/StringExtras.h"
@@ -751,6 +752,9 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
751752
default:
752753
return std::make_unique<LoongArch64TargetInfo>(Triple, Opts);
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}
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case llvm::Triple::xtensa:
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return std::make_unique<XtensaTargetInfo>(Triple, Opts);
754758
}
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}
756760
} // namespace targets

‎clang/lib/Basic/Targets/Xtensa.cpp

+35
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
//===--- Xtensa.cpp - Implement Xtensa target feature support -------------===//
2+
//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6+
// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements Xtensa TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "Xtensa.h"
16+
#include "clang/Basic/Builtins.h"
17+
#include "clang/Basic/MacroBuilder.h"
18+
#include "clang/Basic/TargetBuiltins.h"
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20+
using namespace clang;
21+
using namespace clang::targets;
22+
23+
void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts,
24+
MacroBuilder &Builder) const {
25+
Builder.defineMacro("__xtensa__");
26+
Builder.defineMacro("__XTENSA__");
27+
if (BigEndian)
28+
Builder.defineMacro("__XTENSA_EB__");
29+
else
30+
Builder.defineMacro("__XTENSA_EL__");
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Builder.defineMacro("__XCHAL_HAVE_BE", BigEndian ? "1" : "0");
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Builder.defineMacro("__XCHAL_HAVE_ABS"); // core arch
33+
Builder.defineMacro("__XCHAL_HAVE_ADDX"); // core arch
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Builder.defineMacro("__XCHAL_HAVE_L32R"); // core arch
35+
}

‎clang/lib/Basic/Targets/Xtensa.h

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@@ -0,0 +1,111 @@
1+
//===--- Xtensa.h - Declare Xtensa target feature support -------*- C++ -*-===//
2+
//
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// The LLVM Compiler Infrastructure
4+
//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6+
// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8+
//
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//===----------------------------------------------------------------------===//
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//
11+
// This file declares Xtensa TargetInfo objects.
12+
//
13+
//===----------------------------------------------------------------------===//
14+
15+
#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H
16+
#define LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H
17+
18+
#include "clang/Basic/TargetInfo.h"
19+
#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/Compiler.h"
22+
#include "llvm/TargetParser/Triple.h"
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24+
#include "clang/Basic/Builtins.h"
25+
#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
27+
28+
namespace clang {
29+
namespace targets {
30+
31+
class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {
32+
static const Builtin::Info BuiltinInfo[];
33+
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protected:
35+
std::string CPU;
36+
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public:
38+
XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
39+
: TargetInfo(Triple) {
40+
// no big-endianess support yet
41+
BigEndian = false;
42+
NoAsmVariants = true;
43+
LongLongAlign = 64;
44+
SuitableAlign = 32;
45+
DoubleAlign = LongDoubleAlign = 64;
46+
SizeType = UnsignedInt;
47+
PtrDiffType = SignedInt;
48+
IntPtrType = SignedInt;
49+
WCharType = SignedInt;
50+
WIntType = UnsignedInt;
51+
UseZeroLengthBitfieldAlignment = true;
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
53+
resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32");
54+
}
55+
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void getTargetDefines(const LangOptions &Opts,
57+
MacroBuilder &Builder) const override;
58+
59+
ArrayRef<Builtin::Info> getTargetBuiltins() const override {
60+
return std::nullopt;
61+
}
62+
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BuiltinVaListKind getBuiltinVaListKind() const override {
64+
return TargetInfo::XtensaABIBuiltinVaList;
65+
}
66+
67+
std::string_view getClobbers() const override { return ""; }
68+
69+
ArrayRef<const char *> getGCCRegNames() const override {
70+
static const char *const GCCRegNames[] = {
71+
// General register name
72+
"a0", "sp", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10",
73+
"a11", "a12", "a13", "a14", "a15",
74+
// Special register name
75+
"sar"};
76+
return llvm::ArrayRef(GCCRegNames);
77+
}
78+
79+
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
80+
return std::nullopt;
81+
}
82+
83+
bool validateAsmConstraint(const char *&Name,
84+
TargetInfo::ConstraintInfo &Info) const override {
85+
switch (*Name) {
86+
default:
87+
return false;
88+
case 'a':
89+
Info.setAllowsRegister();
90+
return true;
91+
}
92+
return false;
93+
}
94+
95+
int getEHDataRegisterNumber(unsigned RegNo) const override {
96+
return (RegNo < 2) ? RegNo : -1;
97+
}
98+
99+
bool isValidCPUName(StringRef Name) const override {
100+
return llvm::StringSwitch<bool>(Name).Case("generic", true).Default(false);
101+
}
102+
103+
bool setCPU(const std::string &Name) override {
104+
CPU = Name;
105+
return isValidCPUName(Name);
106+
}
107+
};
108+
109+
} // namespace targets
110+
} // namespace clang
111+
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H

‎clang/lib/Driver/ToolChains/CommonArgs.cpp

+5
Original file line numberDiff line numberDiff line change
@@ -708,6 +708,11 @@ std::string tools::getCPUName(const Driver &D, const ArgList &Args,
708708
case llvm::Triple::loongarch32:
709709
case llvm::Triple::loongarch64:
710710
return loongarch::getLoongArchTargetCPU(Args, T);
711+
712+
case llvm::Triple::xtensa:
713+
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
714+
return A->getValue();
715+
return "";
711716
}
712717
}
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