From 37a315d077b960ed10af0de4a28c58d556ced37c Mon Sep 17 00:00:00 2001 From: Martin Erhart Date: Tue, 4 Feb 2025 15:38:57 +0000 Subject: [PATCH] [RTG] Custom assembly format for 'rtg.test' operation --- frontends/PyRTG/test/basic.mlir | 2 +- include/circt/Dialect/RTG/IR/RTGOps.td | 6 +- .../Bindings/Python/dialects/rtg.py | 7 +- lib/Dialect/RTG/IR/CMakeLists.txt | 1 + lib/Dialect/RTG/IR/RTGOps.cpp | 111 ++++++++++++++++++ test/CAPI/rtg-pipelines.c | 2 +- test/Dialect/RTG/IR/basic.mlir | 22 ++-- test/Dialect/RTG/IR/errors.mlir | 18 +-- test/Dialect/RTG/Transform/elaboration.mlir | 55 ++++----- .../emit-rtg-isa-assembly-errors.mlir | 4 +- .../emit-rtg-isa-assembly-labels.mlir | 2 +- .../emit-rtg-isa-assembly-split-invalid.mlir | 2 +- .../emit-rtg-isa-assembly-split.mlir | 4 +- .../RTG/Transform/emit-rtg-isa-assembly.mlir | 2 +- .../linear-scan-register-allocation.mlir | 8 +- test/Dialect/RTGTest/IR/basic.mlir | 18 ++- 16 files changed, 183 insertions(+), 81 deletions(-) diff --git a/frontends/PyRTG/test/basic.mlir b/frontends/PyRTG/test/basic.mlir index 17a744ae4ca4..44674f550ab4 100644 --- a/frontends/PyRTG/test/basic.mlir +++ b/frontends/PyRTG/test/basic.mlir @@ -25,7 +25,7 @@ rtg.sequence @seq0() { rtg.label local %0 } -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { %0 = rtg.get_sequence @seq0 : !rtg.sequence %1 = rtg.randomize_sequence %0 rtg.embed_sequence %1 diff --git a/include/circt/Dialect/RTG/IR/RTGOps.td b/include/circt/Dialect/RTG/IR/RTGOps.td index 13cd6460bb56..cc3bf147c948 100644 --- a/include/circt/Dialect/RTG/IR/RTGOps.td +++ b/include/circt/Dialect/RTG/IR/RTGOps.td @@ -481,6 +481,7 @@ def TestOp : RTGOp<"test", [ Symbol, SingleBlock, NoTerminator, + DeclareOpInterfaceMethods, HasParent<"mlir::ModuleOp"> ]> { let summary = "the root of a test"; @@ -509,10 +510,7 @@ def TestOp : RTGOp<"test", [ TypeAttrOf:$target); let regions = (region SizedRegion<1>:$bodyRegion); - let assemblyFormat = [{ - $sym_name `:` $target attr-dict-with-keyword $bodyRegion - }]; - + let hasCustomAssemblyFormat = 1; let hasRegionVerifier = 1; } diff --git a/integration_test/Bindings/Python/dialects/rtg.py b/integration_test/Bindings/Python/dialects/rtg.py index e01d45232e26..aff3370c7ef6 100644 --- a/integration_test/Bindings/Python/dialects/rtg.py +++ b/integration_test/Bindings/Python/dialects/rtg.py @@ -32,8 +32,7 @@ # CHECK: [[V1:%.+]] = rtgtest.cpu_decl <1> # CHECK: rtg.yield [[V0]], [[V1]] : !rtgtest.cpu, !rtgtest.cpu # CHECK: } - # CHECK: rtg.test @test_name : !rtg.dict { - # CHECK: ^bb{{.*}}(%{{.*}}: !rtgtest.cpu, %{{.*}}: !rtgtest.cpu): + # CHECK: rtg.test @test_name(%cpu0: !rtgtest.cpu, %cpu1: !rtgtest.cpu) { # CHECK: } print(m) @@ -62,7 +61,7 @@ seq_get = rtg.GetSequenceOp(rtg.SequenceType.get(), 'sequence_name') rtg.RandomizeSequenceOp(seq_get) - # CHECK: rtg.test @test_name : !rtg.dict<> { + # CHECK: rtg.test @test_name() { # CHECK-NEXT: [[SEQ:%.+]] = rtg.get_sequence @sequence_name # CHECK-NEXT: rtg.randomize_sequence [[SEQ]] # CHECK-NEXT: } @@ -76,7 +75,7 @@ rtgtool.populate_randomizer_pipeline(pm, options) pm.run(m.operation) - # CHECK: rtg.test @test_name : !rtg.dict<> { + # CHECK: rtg.test @test_name() { # CHECK-NEXT: } print(m) diff --git a/lib/Dialect/RTG/IR/CMakeLists.txt b/lib/Dialect/RTG/IR/CMakeLists.txt index b54888576a00..c3a732ba091b 100644 --- a/lib/Dialect/RTG/IR/CMakeLists.txt +++ b/lib/Dialect/RTG/IR/CMakeLists.txt @@ -22,6 +22,7 @@ add_circt_dialect_library(CIRCTRTGDialect CIRCTRTGISAAssemblyTypeInterfacesIncGen CIRCTRTGOpInterfacesIncGen CIRCTRTGTypeInterfacesIncGen + CIRCTSupport MLIRRTGIncGen LINK_LIBS PUBLIC diff --git a/lib/Dialect/RTG/IR/RTGOps.cpp b/lib/Dialect/RTG/IR/RTGOps.cpp index 1ed722e906d3..ed84cc690bf4 100644 --- a/lib/Dialect/RTG/IR/RTGOps.cpp +++ b/lib/Dialect/RTG/IR/RTGOps.cpp @@ -11,8 +11,10 @@ //===----------------------------------------------------------------------===// #include "circt/Dialect/RTG/IR/RTGOps.h" +#include "circt/Support/ParsingUtils.h" #include "mlir/IR/Builders.h" #include "mlir/IR/DialectImplementation.h" +#include "llvm/ADT/SmallString.h" using namespace mlir; using namespace circt; @@ -399,6 +401,115 @@ LogicalResult TestOp::verifyRegions() { return success(); } +ParseResult TestOp::parse(OpAsmParser &parser, OperationState &result) { + // Parse the name as a symbol. + if (parser.parseSymbolName( + result.getOrAddProperties().sym_name)) + return failure(); + + // Parse the function signature. + SmallVector arguments; + SmallVector names; + + auto parseOneArgument = [&]() -> ParseResult { + std::string name; + auto res = + parser.parseOptionalKeywordOrString(&name) || parser.parseColon(); + + auto argLoc = parser.getCurrentLocation(); + if (failed(parser.parseArgument(arguments.emplace_back(), + /*allowType=*/true, /*allowAttrs=*/true))) + return failure(); + + // If no explicit name was provided, try to use the SSA name. + if (res) { + auto inferredName = parsing_util::getNameFromSSA( + result.getContext(), arguments.back().ssaName.name); + if (inferredName.empty()) + return parser.emitError(argLoc, "invalid SSA name for test argument"); + names.push_back(inferredName); + } else { + names.push_back(StringAttr::get(result.getContext(), name)); + } + + return success(); + }; + if (parser.parseCommaSeparatedList(OpAsmParser::Delimiter::Paren, + parseOneArgument, " in argument list")) + return failure(); + + SmallVector argTypes; + SmallVector entries; + SmallVector argLocs; + argTypes.reserve(arguments.size()); + argLocs.reserve(arguments.size()); + for (auto [name, arg] : llvm::zip(names, arguments)) { + argTypes.push_back(arg.type); + argLocs.push_back(arg.sourceLoc ? *arg.sourceLoc : result.location); + entries.push_back({name, arg.type}); + } + auto emitError = [&]() -> InFlightDiagnostic { + return parser.emitError(parser.getCurrentLocation()); + }; + Type type = DictType::getChecked(emitError, result.getContext(), + ArrayRef(entries)); + if (!type) + return failure(); + result.getOrAddProperties().target = TypeAttr::get(type); + + auto loc = parser.getCurrentLocation(); + if (parser.parseOptionalAttrDictWithKeyword(result.attributes)) + return failure(); + if (failed(verifyInherentAttrs(result.name, result.attributes, [&]() { + return parser.emitError(loc) + << "'" << result.name.getStringRef() << "' op "; + }))) + return failure(); + + std::unique_ptr bodyRegionRegion = std::make_unique(); + if (parser.parseRegion(*bodyRegionRegion, arguments)) + return failure(); + + if (bodyRegionRegion->empty()) { + bodyRegionRegion->emplaceBlock(); + bodyRegionRegion->addArguments(argTypes, argLocs); + } + result.addRegion(std::move(bodyRegionRegion)); + + return success(); +} + +void TestOp::print(OpAsmPrinter &p) { + p << ' '; + p.printSymbolName(getSymNameAttr().getValue()); + p << "("; + SmallString<32> resultNameStr; + llvm::interleaveComma( + llvm::zip(getTarget().getEntries(), getBody()->getArguments()), p, + [&](auto entryAndArg) { + auto [entry, arg] = entryAndArg; + + resultNameStr.clear(); + llvm::raw_svector_ostream tmpStream(resultNameStr); + p.printOperand(arg, tmpStream); + if (tmpStream.str().drop_front() != entry.name) + p << entry.name.getValue() << ": "; + p.printRegionArgument(arg); + }); + p << ")"; + p.printOptionalAttrDictWithKeyword( + (*this)->getAttrs(), {getSymNameAttrName(), getTargetAttrName()}); + p << ' '; + p.printRegion(getBodyRegion(), /*printEntryBlockArgs=*/false); +} + +void TestOp::getAsmBlockArgumentNames(Region ®ion, + OpAsmSetValueNameFn setNameFn) { + for (auto [entry, arg] : + llvm::zip(getTarget().getEntries(), region.getArguments())) + setNameFn(arg, entry.name.getValue()); +} + //===----------------------------------------------------------------------===// // TargetOp //===----------------------------------------------------------------------===// diff --git a/test/CAPI/rtg-pipelines.c b/test/CAPI/rtg-pipelines.c index adc0bdeba984..f12ef1a78e20 100644 --- a/test/CAPI/rtg-pipelines.c +++ b/test/CAPI/rtg-pipelines.c @@ -21,7 +21,7 @@ int main(int argc, char **argv) { ctx, mlirStringRefCreateFromCString( "rtg.sequence @seq() {\n" "}\n" - "rtg.test @test : !rtg.dict<> {\n" + "rtg.test @test() {\n" " %0 = rtg.get_sequence @seq : !rtg.sequence\n" "}\n")); if (mlirModuleIsNull(moduleOp)) { diff --git a/test/Dialect/RTG/IR/basic.mlir b/test/Dialect/RTG/IR/basic.mlir index 2cbcb978ed7a..302dbf295aea 100644 --- a/test/Dialect/RTG/IR/basic.mlir +++ b/test/Dialect/RTG/IR/basic.mlir @@ -89,8 +89,8 @@ rtg.target @empty_target : !rtg.dict<> { rtg.yield } -// CHECK-LABEL: rtg.test @empty_test : !rtg.dict<> { -rtg.test @empty_test : !rtg.dict<> { } +// CHECK-LABEL: rtg.test @empty_test() { +rtg.test @empty_test() { } // CHECK-LABEL: rtg.target @target : !rtg.dict { // CHECK: rtg.yield %{{.*}}, %{{.*}} : i32, i32 @@ -115,19 +115,19 @@ rtg.target @context_switch : !rtg.dict<> { } // CHECK-LABEL: @contexts -rtg.test @contexts : !rtg.dict { -^bb0(%arg0: !rtgtest.cpu): +rtg.test @contexts(%ctxt0: !rtgtest.cpu) { // CHECK: rtg.on_context {{%.+}}, {{%.+}} : !rtgtest.cpu %seq = rtg.get_sequence @seq0 : !rtg.sequence - rtg.on_context %arg0, %seq : !rtgtest.cpu + rtg.on_context %ctxt0, %seq : !rtgtest.cpu } -// CHECK-LABEL: rtg.test @test : !rtg.dict { -// CHECK: ^bb0(%arg0: i32, %arg1: i32): -// CHECK: } -rtg.test @test : !rtg.dict { -^bb0(%arg0: i32, %arg1: i32): -} +// CHECK-LABEL: rtg.test @test0 +// CHECK-SAME: (%num_cpus: i32, %num_modes: i32) { +rtg.test @test0(%num_cpus: i32, %num_modes: i32) { } + +// CHECK-LABEL: rtg.test @test1 +// CHECK-SAME: (%num_cpus: i32, %num_modes: i32) { +rtg.test @test1(num_cpus: %a: i32, num_modes: %b: i32) { } // CHECK-LABEL: rtg.sequence @integerHandlingOps rtg.sequence @integerHandlingOps(%arg0: index, %arg1: index) { diff --git a/test/Dialect/RTG/IR/errors.mlir b/test/Dialect/RTG/IR/errors.mlir index e4336e064cdf..6d7763742364 100644 --- a/test/Dialect/RTG/IR/errors.mlir +++ b/test/Dialect/RTG/IR/errors.mlir @@ -83,29 +83,29 @@ rtg.target @target : !rtg.dict { // ----- // expected-error @below {{argument types must match dict entry types}} -rtg.test @test : !rtg.dict { -} +"rtg.test"() <{sym_name="test", target=!rtg.dict}> ({^bb0(%b: i8):}) : () -> () // ----- // expected-error @below {{dictionary must be sorted by names and contain no duplicates, first violation at entry 'a'}} -rtg.test @test : !rtg.dict { -^bb0(%arg0: i32, %arg1: i32): +rtg.test @test(%a: i32, %a: i32) { } // ----- // expected-error @below {{dictionary must be sorted by names and contain no duplicates, first violation at entry 'a'}} -rtg.test @test : !rtg.dict { -^bb0(%arg0: i32, %arg1: i32): +rtg.test @test(%b: i32, %a: i32) { } // ----- +// expected-error @below {{invalid SSA name for test argument}} +rtg.test @test0(%0: i32, %1: i32) { } + +// ----- + // expected-error @below {{empty strings not allowed as entry names}} -rtg.test @test : !rtg.dict<"": i32> { -^bb0(%arg0: i32): -} +rtg.test @test(%dict: !rtg.dict<"": i32>) { } // ----- diff --git a/test/Dialect/RTG/Transform/elaboration.mlir b/test/Dialect/RTG/Transform/elaboration.mlir index a3aca37817a2..d61d4d6e41ae 100644 --- a/test/Dialect/RTG/Transform/elaboration.mlir +++ b/test/Dialect/RTG/Transform/elaboration.mlir @@ -8,7 +8,7 @@ func.func @dummy5(%arg0: i1) -> () {return} // Test the set operations and passing a sequence to another one via argument // CHECK-LABEL: rtg.test @setOperations -rtg.test @setOperations : !rtg.dict<> { +rtg.test @setOperations() { // CHECK-NEXT: [[V0:%.+]] = index.constant 2 // CHECK-NEXT: [[V1:%.+]] = index.constant 3 // CHECK-NEXT: [[V2:%.+]] = index.constant 4 @@ -30,7 +30,7 @@ rtg.test @setOperations : !rtg.dict<> { } // CHECK-LABEL: rtg.test @bagOperations -rtg.test @bagOperations : !rtg.dict<> { +rtg.test @bagOperations() { // CHECK-NEXT: [[V0:%.+]] = index.constant 2 // CHECK-NEXT: [[V1:%.+]] = index.constant 8 // CHECK-NEXT: [[V2:%.+]] = index.constant 3 @@ -56,7 +56,7 @@ rtg.test @bagOperations : !rtg.dict<> { } // CHECK-LABEL: rtg.test @setSize -rtg.test @setSize : !rtg.dict<> { +rtg.test @setSize() { // CHECK-NEXT: [[C:%.+]] = index.constant 1 // CHECK-NEXT: func.call @dummy2([[C]]) // CHECK-NEXT: } @@ -67,7 +67,7 @@ rtg.test @setSize : !rtg.dict<> { } // CHECK-LABEL: rtg.test @bagSize -rtg.test @bagSize : !rtg.dict<> { +rtg.test @bagSize() { // CHECK-NEXT: [[C:%.+]] = index.constant 1 // CHECK-NEXT: func.call @dummy2([[C]]) // CHECK-NEXT: } @@ -85,15 +85,13 @@ rtg.test @bagSize : !rtg.dict<> { // CHECK-LABEL: @targetTest_target1 // CHECK: [[V0:%.+]] = index.constant 1 // CHECK: func.call @dummy2([[V0]]) : -rtg.test @targetTest : !rtg.dict { -^bb0(%arg0: index): - func.call @dummy2(%arg0) : (index) -> () +rtg.test @targetTest(%num_cpus: index) { + func.call @dummy2(%num_cpus) : (index) -> () } // CHECK-NOT: @unmatchedTest -rtg.test @unmatchedTest : !rtg.dict { -^bb0(%arg0: !rtg.sequence): - func.call @dummy3(%arg0) : (!rtg.sequence) -> () +rtg.test @unmatchedTest(%num_cpus: !rtg.sequence) { + func.call @dummy3(%num_cpus) : (!rtg.sequence) -> () } rtg.target @target0 : !rtg.dict { @@ -124,7 +122,7 @@ rtg.sequence @seq1(%arg0: index) { } // CHECK-LABEL: rtg.test @nestedSequences -rtg.test @nestedSequences : !rtg.dict<> { +rtg.test @nestedSequences() { // CHECK: index.constant 0 // CHECK: func.call @dummy2 // CHECK: func.call @dummy2 @@ -141,7 +139,7 @@ rtg.sequence @seq2(%arg0: index) { } // CHECK-LABEL: rtg.test @sameSequenceDifferentArgs -rtg.test @sameSequenceDifferentArgs : !rtg.dict<> { +rtg.test @sameSequenceDifferentArgs() { // CHECK: [[C0:%.+]] = index.constant 0 // CHECK: func.call @dummy2([[C0]]) // CHECK: [[C1:%.+]] = index.constant 1 @@ -164,7 +162,7 @@ rtg.sequence @seq3(%arg0: !rtg.set) { } // CHECK-LABEL: rtg.test @sequenceClosureFixesRandomization -rtg.test @sequenceClosureFixesRandomization : !rtg.dict<> { +rtg.test @sequenceClosureFixesRandomization() { // CHECK: %idx0 = index.constant 0 // CHECK: func.call @dummy2(%idx0 // CHECK: %idx1 = index.constant 1 @@ -185,7 +183,7 @@ rtg.test @sequenceClosureFixesRandomization : !rtg.dict<> { } // CHECK-LABEL: @indexOps -rtg.test @indexOps : !rtg.dict<> { +rtg.test @indexOps() { // CHECK: [[C:%.+]] = index.constant 2 %0 = index.constant 1 @@ -225,7 +223,7 @@ rtg.test @indexOps : !rtg.dict<> { } // CHECK-LABEL: @scfIf -rtg.test @scfIf : !rtg.dict<> { +rtg.test @scfIf() { %0 = index.bool.constant true %1 = index.bool.constant false @@ -269,7 +267,7 @@ rtg.test @scfIf : !rtg.dict<> { } // CHECK-LABEL: @scfFor -rtg.test @scfFor : !rtg.dict<> { +rtg.test @scfFor() { // CHECK-NEXT: [[C0:%.+]] = index.constant 0 // CHECK-NEXT: func.call @dummy2([[C0]]) // CHECK-NEXT: [[C1:%.+]] = index.constant 1 @@ -309,7 +307,7 @@ rtg.test @scfFor : !rtg.dict<> { } // CHECK-LABEL: @fixedRegisters -rtg.test @fixedRegisters : !rtg.dict<> { +rtg.test @fixedRegisters() { // CHECK-NEXT: [[RA:%.+]] = rtg.fixed_reg #rtgtest.ra // CHECK-NEXT: [[SP:%.+]] = rtg.fixed_reg #rtgtest.sp // CHECK-NEXT: [[IMM:%.+]] = rtgtest.immediate #rtgtest.imm12<0> @@ -321,7 +319,7 @@ rtg.test @fixedRegisters : !rtg.dict<> { } // CHECK-LABEL: @virtualRegisters -rtg.test @virtualRegisters : !rtg.dict<> { +rtg.test @virtualRegisters() { // CHECK-NEXT: [[R0:%.+]] = rtg.virtual_reg [#rtgtest.a0 : !rtgtest.ireg, #rtgtest.a1 : !rtgtest.ireg] // CHECK-NEXT: [[R1:%.+]] = rtg.virtual_reg [#rtgtest.s0 : !rtgtest.ireg, #rtgtest.s1 : !rtgtest.ireg] // CHECK-NEXT: [[IMM:%.+]] = rtgtest.immediate #rtgtest.imm12<0> @@ -347,7 +345,7 @@ rtg.test @virtualRegisters : !rtg.dict<> { } // CHECK-LABEL: @labels -rtg.test @labels : !rtg.dict<> { +rtg.test @labels() { // CHECK-NEXT: [[L0:%.+]] = rtg.label_decl "label0" // CHECK-NEXT: rtg.label local [[L0]] // CHECK-NEXT: rtg.label local [[L0]] @@ -375,7 +373,7 @@ rtg.test @labels : !rtg.dict<> { } // CHECK-LABEL: rtg.test @randomIntegers -rtg.test @randomIntegers : !rtg.dict<> { +rtg.test @randomIntegers() { %lower = index.constant 5 %upper = index.constant 10 %0 = rtg.random_number_in_range [%lower, %upper) {rtg.elaboration_custom_seed=0} @@ -390,8 +388,7 @@ rtg.test @randomIntegers : !rtg.dict<> { } // CHECK-LABEL: rtg.test @contexts_contextCpu -rtg.test @contexts : !rtg.dict { -^bb0(%cpu0: !rtgtest.cpu, %cpu1: !rtgtest.cpu): +rtg.test @contexts(%cpu0: !rtgtest.cpu, %cpu1: !rtgtest.cpu) { // CHECK-NEXT: rtg.label_decl "label0" // CHECK-NEXT: rtg.label // CHECK-NEXT: rtg.label_decl "label5" @@ -463,14 +460,14 @@ rtg.sequence @switchNestedCpuSeq(%parent: !rtgtest.cpu, %child: !rtgtest.cpu, %s // ----- -rtg.test @nestedRegionsNotSupported : !rtg.dict<> { +rtg.test @nestedRegionsNotSupported() { // expected-error @below {{ops with nested regions must be elaborated away}} scf.execute_region { scf.yield } } // ----- -rtg.test @untypedAttributes : !rtg.dict<> { +rtg.test @untypedAttributes() { // expected-error @below {{only typed attributes supported for constant-like operations}} %0 = rtgtest.constant_test index {value = [10 : index]} } @@ -479,7 +476,7 @@ rtg.test @untypedAttributes : !rtg.dict<> { func.func @dummy(%arg0: index) {return} -rtg.test @untypedAttributes : !rtg.dict<> { +rtg.test @untypedAttributes() { %0 = rtgtest.constant_test index {value = "str"} // expected-error @below {{materializer of dialect 'builtin' unable to materialize value for attribute '"str"'}} // expected-note @below {{while materializing value for operand#0}} @@ -490,7 +487,7 @@ rtg.test @untypedAttributes : !rtg.dict<> { func.func @dummy2(%arg0: index) -> () {return} -rtg.test @randomIntegers : !rtg.dict<> { +rtg.test @randomIntegers() { %c5 = index.constant 5 // expected-error @below {{cannot select a number from an empty range}} %0 = rtg.random_number_in_range [%c5, %c5) @@ -516,8 +513,7 @@ rtg.target @invalidRandomizationTarget : !rtg.dict { rtg.yield %1 : !rtgtest.cpu } -rtg.test @invalidRandomization : !rtg.dict { -^bb0(%cpu: !rtgtest.cpu): +rtg.test @invalidRandomization(%cpu: !rtgtest.cpu) { %0 = rtg.get_sequence @seq1 : !rtg.sequence %1 = rtg.randomize_sequence %0 %2 = rtg.get_sequence @seq0 : !rtg.sequence @@ -534,8 +530,7 @@ rtg.target @target : !rtg.dict { rtg.yield %0 : !rtgtest.cpu } -rtg.test @contextSwitchNotAvailable : !rtg.dict { -^bb0(%cpu: !rtgtest.cpu): +rtg.test @contextSwitchNotAvailable(%cpu: !rtgtest.cpu) { %0 = rtg.get_sequence @seq : !rtg.sequence // expected-error @below {{no context transition registered to switch from #rtg.default : !rtgtest.cpu to #rtgtest.cpu<0> : !rtgtest.cpu}} rtg.on_context %cpu, %0 : !rtgtest.cpu diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-errors.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-errors.mlir index eaf42236d4b0..959e437fbd9b 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-errors.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-errors.mlir @@ -1,6 +1,6 @@ // RUN: circt-opt --rtg-emit-isa-assembly=unsupported-instructions=rtgtest.rv32i.beq %s --split-input-file --verify-diagnostics -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { %rd = rtg.fixed_reg #rtgtest.ra %rs = rtg.fixed_reg #rtgtest.s0 %label = rtg.label_decl "label_name" @@ -11,7 +11,7 @@ rtg.test @test0 : !rtg.dict<> { // ----- -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { %0 = index.constant 0 // expected-error @below {{label arguments must be elaborated before emission}} %label = rtg.label_decl "label_name_{{0}}", %0 diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir index 3a3f3f6edbd7..c3f8165119ac 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-labels.mlir @@ -3,7 +3,7 @@ // CHECK:# Begin of test0 // CHECK-EMPTY: -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { %rd = rtg.fixed_reg #rtgtest.ra %rs = rtg.fixed_reg #rtgtest.s0 %label = rtg.label_decl "label_name" diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split-invalid.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split-invalid.mlir index 688c79135f8c..3cb6f231ed68 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split-invalid.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split-invalid.mlir @@ -2,5 +2,5 @@ // expected-error @below {{'split-output' option only valid in combination with a valid 'path' argument}} module { - rtg.test @test0 : !rtg.dict<> {} + rtg.test @test0() {} } diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split.mlir index 63cc86ce6346..6ca7bec56d1a 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly-split.mlir @@ -4,7 +4,7 @@ // CHECK: Begin of test0 // CHECK-EMPTY: -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { // CHECK-TEST0: ebreak rtgtest.rv32i.ebreak } @@ -15,7 +15,7 @@ rtg.test @test0 : !rtg.dict<> { // CHECK-NEXT: Begin of test1 // CHECK-EMPTY: -rtg.test @test1 : !rtg.dict<> { +rtg.test @test1() { // CHECK-TEST1: ecall rtgtest.rv32i.ecall } diff --git a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir index ee4e32ed17b3..f1063ca69616 100644 --- a/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir +++ b/test/Dialect/RTG/Transform/emit-rtg-isa-assembly.mlir @@ -6,7 +6,7 @@ // CHECK-ALLOWED:# Begin of test0 // CHECK-ALLOWED-EMPTY: -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { %rd = rtg.fixed_reg #rtgtest.ra %rs = rtg.fixed_reg #rtgtest.s0 %imm = rtgtest.immediate #rtgtest.imm12<0> diff --git a/test/Dialect/RTG/Transform/linear-scan-register-allocation.mlir b/test/Dialect/RTG/Transform/linear-scan-register-allocation.mlir index 79d2ce7f3796..84d9c20eec9b 100644 --- a/test/Dialect/RTG/Transform/linear-scan-register-allocation.mlir +++ b/test/Dialect/RTG/Transform/linear-scan-register-allocation.mlir @@ -1,7 +1,7 @@ // RUN: circt-opt --rtg-linear-scan-register-allocation --split-input-file --verify-diagnostics %s | FileCheck %s // CHECK-LABEL: @test0 -rtg.test @test0 : !rtg.dict<> { +rtg.test @test0() { // CHECK: [[V0:%.+]] = rtg.fixed_reg #rtgtest.ra // CHECK: [[V1:%.+]] = rtg.fixed_reg #rtgtest.s1 // CHECK: [[V2:%.+]] = rtg.fixed_reg #rtgtest.s0 @@ -22,7 +22,7 @@ rtg.test @test0 : !rtg.dict<> { } // CHECK-LABEL: @withFixedRegs -rtg.test @withFixedRegs : !rtg.dict<> { +rtg.test @withFixedRegs() { // CHECK: [[V0:%.+]] = rtg.fixed_reg #rtgtest.ra // CHECK: [[V1:%.+]] = rtg.fixed_reg #rtgtest.s1 // CHECK: [[V2:%.+]] = rtg.fixed_reg #rtgtest.s0 @@ -44,7 +44,7 @@ rtg.test @withFixedRegs : !rtg.dict<> { // ----- -rtg.test @spilling : !rtg.dict<> { +rtg.test @spilling() { %0 = rtg.virtual_reg [#rtgtest.ra] // expected-error @below {{need to spill this register, but not supported yet}} %1 = rtg.virtual_reg [#rtgtest.ra] @@ -54,7 +54,7 @@ rtg.test @spilling : !rtg.dict<> { // ----- -rtg.test @unsupportedUser : !rtg.dict<> { +rtg.test @unsupportedUser() { %0 = rtg.virtual_reg [#rtgtest.ra] // expected-error @below {{only operations implementing 'InstructionOpInterface are allowed to use registers}} rtg.set_create %0 : !rtgtest.ireg diff --git a/test/Dialect/RTGTest/IR/basic.mlir b/test/Dialect/RTGTest/IR/basic.mlir index c081285cfe14..98f371419a23 100644 --- a/test/Dialect/RTGTest/IR/basic.mlir +++ b/test/Dialect/RTGTest/IR/basic.mlir @@ -8,15 +8,14 @@ rtg.target @cpus : !rtg.dict { rtg.yield %0 : !rtgtest.cpu } -rtg.test @misc : !rtg.dict<> { +rtg.test @misc() { // CHECK: rtgtest.constant_test i32 {value = "str"} %0 = rtgtest.constant_test i32 {value = "str"} } // CHECK-LABEL: rtg.test @registers // CHECK-SAME: !rtgtest.ireg -rtg.test @registers : !rtg.dict { -^bb0(%reg: !rtgtest.ireg): +rtg.test @registers(%reg: !rtgtest.ireg) { // CHECK: rtg.fixed_reg #rtgtest.zero : !rtgtest.ireg // CHECK: rtg.fixed_reg #rtgtest.ra : !rtgtest.ireg // CHECK: rtg.fixed_reg #rtgtest.sp : !rtgtest.ireg @@ -87,7 +86,7 @@ rtg.test @registers : !rtg.dict { } // CHECK-LABEL: @immediates -rtg.test @immediates : !rtg.dict<> { +rtg.test @immediates() { // CHECK: rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5 rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5 // CHECK: rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12 @@ -101,9 +100,8 @@ rtg.test @immediates : !rtg.dict<> { } // CHECK-LABEL: @instructions -rtg.test @instructions : !rtg.dict { -// CHECK: ([[IMM:%.+]]: !rtgtest.imm12, [[IMM13:%.+]]: !rtgtest.imm13, [[IMM21:%.+]]: !rtgtest.imm21, [[IMM32:%.+]]: !rtgtest.imm32, [[IMM5:%.+]]: !rtgtest.imm5, [[LABEL:%.+]]: !rtg.label, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg) -^bb0(%imm: !rtgtest.imm12, %imm13: !rtgtest.imm13, %imm21: !rtgtest.imm21, %imm32: !rtgtest.imm32, %imm5: !rtgtest.imm5, %label: !rtg.label, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg): +// CHECK-SAME: ([[IMM:%.+]]: !rtgtest.imm12, [[IMM13:%.+]]: !rtgtest.imm13, [[IMM21:%.+]]: !rtgtest.imm21, [[IMM32:%.+]]: !rtgtest.imm32, [[IMM5:%.+]]: !rtgtest.imm5, [[LABEL:%.+]]: !rtg.label, [[RD:%.+]]: !rtgtest.ireg, [[RS:%.+]]: !rtgtest.ireg) +rtg.test @instructions(%imm: !rtgtest.imm12, %imm13: !rtgtest.imm13, %imm21: !rtgtest.imm21, %imm32: !rtgtest.imm32, %imm5: !rtgtest.imm5, %label: !rtg.label, %rd: !rtgtest.ireg, %rs: !rtgtest.ireg) { // CHECK: rtgtest.rv32i.jalr [[RD]], [[RS]], [[IMM]] rtgtest.rv32i.jalr %rd, %rs, %imm // CHECK: rtgtest.rv32i.lb [[RD]], [[RS]], [[IMM]] @@ -210,21 +208,21 @@ rtg.test @instructions : !rtg.dict { +rtg.test @immediateTooBig() { // expected-error @below {{cannot represent 2000000 with 12 bits}} rtgtest.immediate #rtgtest.imm12<2000000> : !rtgtest.imm12 } // ----- -rtg.test @emptyAllowed : !rtg.dict<> { +rtg.test @emptyAllowed() { // expected-error @below {{must have at least one allowed register}} rtg.virtual_reg [] } // ----- -rtg.test @invalidAllowedAttr : !rtg.dict<> { +rtg.test @invalidAllowedAttr() { // expected-error @below {{allowed register attributes must be of RegisterAttrInterface}} rtg.virtual_reg ["invalid"] }