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‎ALU.v

+201
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‎CU.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/12/23 16:47:49
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// Design Name:
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// Module Name: CU
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CU(Inst,Func,ID_B_code,RegDst,Se,RegWrite,ALUXSrc,ALUYSrc,ALUControl,MemWrite,PCSrc,MemtoReg,load_option,save_option,usigned,c_adventure);
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input [5:0]Func;
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input [31:0]Inst;
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input c_adventure,ID_B_code;
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output RegDst,Se,RegWrite,ALUXSrc,ALUYSrc,MemWrite,MemtoReg,usigned;
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output [2:0]PCSrc,load_option;
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output [1:0]save_option;
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output [3:0]ALUControl;
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wire R_type=~Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_lb = Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_lbu = Inst[31] & ~Inst[30] & ~Inst[29] & Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_lh = Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & ~Inst[27] & Inst[26];
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wire I_lhu = Inst[31] & ~Inst[30] & ~Inst[29] & Inst[28] & ~Inst[27] & Inst[26];
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wire I_lw = Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & Inst[27] & Inst[26];
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wire I_sb = Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_sh = Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & ~Inst[27] & Inst[26];
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wire I_sw = Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & Inst[27] & Inst[26];
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wire I_add = R_type & Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & ~Func[1] & ~Func[0];
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wire I_addu = R_type & Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & ~Func[1] & Func[0];
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wire I_sub = R_type & Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & Func[1] & ~Func[0];
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wire I_subu = R_type & Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & Func[1] & Func[0];
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wire I_sll = R_type & ~Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & ~Func[1] & ~Func[0] & (Inst!=0);
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wire I_srl = R_type & ~Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & Func[1] & ~Func[0];
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wire I_sra = R_type & ~Func[5] & ~Func[4] & ~Func[3] & ~Func[2] & Func[1] & Func[0];
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wire I_sllv = R_type & ~Func[5] & ~Func[4] & ~Func[3] & Func[2] & ~Func[1] & ~Func[0] & (Inst!=0);
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wire I_srlv = R_type & ~Func[5] & ~Func[4] & ~Func[3] & Func[2] & Func[1] & ~Func[0];
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wire I_srav = R_type & ~Func[5] & ~Func[4] & ~Func[3] & Func[2] & Func[1] & Func[0];
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wire I_and = R_type & Func[5] & ~Func[4] & ~Func[3] & Func[2] & ~Func[1] & ~Func[0];
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wire I_or = R_type & Func[5] & ~Func[4] & ~Func[3] & Func[2] & ~Func[1] & Func[0];
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wire I_xor = R_type & Func[5] & ~Func[4] & ~Func[3] & Func[2] & Func[1] & ~Func[0];
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wire I_nor = R_type & Func[5] & ~Func[4] & ~Func[3] & Func[2] & Func[1] & Func[0];
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wire I_addi = ~Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_addiu = ~Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & ~Inst[27] & Inst[26];
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wire I_andi = ~Inst[31] & ~Inst[30] & Inst[29] & Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_ori = ~Inst[31] & ~Inst[30] & Inst[29] & Inst[28] & ~Inst[27] & Inst[26];
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wire I_xori = ~Inst[31] & ~Inst[30] & Inst[29] & Inst[28] & Inst[27] & ~Inst[26];
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wire I_lui = ~Inst[31] & ~Inst[30] & Inst[29] & Inst[28] & Inst[27] & Inst[26];
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wire I_slt = R_type & Func[5] & ~Func[4] & Func[3] & ~Func[2] & Func[1] & ~Func[0];
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wire I_slti = ~Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & Inst[27] & ~Inst[26];
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wire I_sltiu = ~Inst[31] & ~Inst[30] & Inst[29] & ~Inst[28] & Inst[27] & Inst[26];
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wire I_sltu = R_type & Func[5] & ~Func[4] & Func[3] & ~Func[2] & Func[1] & Func[0];
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wire I_beq = ~Inst[31] & ~Inst[30] & ~Inst[29] & Inst[28] & ~Inst[27] & ~Inst[26];
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wire I_bne = ~Inst[31] & ~Inst[30] & ~Inst[29] & Inst[28] & ~Inst[27] & Inst[26];
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wire I_blez = ~Inst[31] & ~Inst[30] & ~Inst[29] & Inst[28] & Inst[27] & ~Inst[26];
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wire I_bgtz = ~Inst[31] & ~Inst[30] & ~Inst[29] & Inst[28] & Inst[27] & Inst[26];
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wire I_bltz = ~Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & ~Inst[27] & Inst[26] & ~ID_B_code;
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wire I_bgez = ~Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & ~Inst[27] & Inst[26] & ID_B_code;
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wire I_j = ~Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & Inst[27] & ~Inst[26];
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wire I_jal = ~Inst[31] & ~Inst[30] & ~Inst[29] & ~Inst[28] & Inst[27] & Inst[26];
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wire I_jalr = R_type & ~Func[5] & ~Func[4] & Func[3] & ~Func[2] & ~Func[1] & Func[0];
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wire I_jr = R_type & ~Func[5] & ~Func[4] & Func[3] & ~Func[2] & ~Func[1] & ~Func[0];
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assign RegDst = I_lb | I_lbu | I_lh | I_lhu | I_lw | I_addi | I_addiu | I_andi | I_ori | I_xori | I_lui | I_slti | I_sltiu;
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assign Se = I_lb | I_lbu | I_lh | I_lhu | I_lw | I_sb | I_sh | I_sw | I_addi | I_addiu | I_slti | I_sltiu | I_beq | I_bne | I_blez | I_bgtz | I_bltz | I_bgez;
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assign RegWrite = I_lb | I_lbu | I_lh | I_lhu | I_lw | I_add | I_addu | I_sub | I_subu | I_sll | I_srl | I_sra | I_sllv | I_srlv | I_srav | I_and | I_or | I_xor | I_nor | I_addi | I_addiu | I_andi | I_ori | I_xori | I_lui | I_slt | I_slti | I_sltiu | I_sltu;
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assign ALUXSrc = I_sll | I_srl | I_sra;
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assign ALUYSrc = I_add | I_addu | I_sub | I_subu | I_and | I_or | I_xor | I_nor | I_slt | I_sltu | I_beq | I_bne | I_j | I_jal | I_jalr | I_jr | I_sll | I_srl | I_sra | I_sllv | I_srlv | I_srav;
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assign ALUControl[0] =I_sub | I_subu | I_sll | I_sllv | I_or | I_nor | I_ori | I_slt | I_slti | I_sltiu | I_sltu | I_beq | I_bne | I_bgtz | I_bgez;
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assign ALUControl[1] =I_sll | I_sllv | I_and | I_or | I_andi | I_ori | I_lui | I_blez | I_bgtz | I_sra | I_srav;
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assign ALUControl[2] =I_sll | I_sllv | I_xor | I_nor | I_xori | I_lui | I_bltz | I_bgez | I_sra | I_srav;
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assign ALUControl[3] =I_srl | I_sra | I_srlv | I_srav | I_slt | I_slti | I_sltiu | I_sltu | I_blez | I_bgtz | I_bltz | I_bgez | I_sll | I_sllv;
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assign MemWrite = I_sb | I_sh | I_sw;
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assign PCSrc[0] = (I_blez & c_adventure) | (I_bgtz & c_adventure)| (I_bltz & c_adventure)| (I_bgez & c_adventure)| I_jal | I_jalr | (I_beq & c_adventure) | (I_bne & ~c_adventure);
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assign PCSrc[1] = I_j | I_jal;
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assign PCSrc[2] = I_jalr | I_jr;
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assign MemtoReg = I_lb | I_lbu | I_lh | I_lhu | I_lw;
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assign load_option[0] = I_lb | I_lbu | I_lh | I_lhu;
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assign load_option[1] = I_lh | I_lhu;
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assign load_option[2] = I_lh | I_lb;
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assign save_option[0] = I_sb;
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assign save_option[1] = I_sh;
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assign usigned = I_lbu | I_lhu | I_addu | I_subu | I_addiu | I_sltiu | I_sltu;
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endmodule
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‎FU.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2020/01/13 17:40:15
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// Design Name:
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// Module Name: FU
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module FU(E_RegWrite,E_WriteReg,E_MemtoReg,M_RegWrite,M_WriteReg,M_MemtoReg,ID_rs,ID_rt,ID_FwdA,ID_FwdB,ID_Op,ID_func,c_adventure,stall,stallstall);
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input [4:0] E_WriteReg,M_WriteReg,ID_rs,ID_rt;
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input E_RegWrite,M_RegWrite,E_MemtoReg,M_MemtoReg,c_adventure;
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input [5:0] ID_Op,ID_func;
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output reg [1:0] ID_FwdA,ID_FwdB;
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output stall,stallstall;
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always@(E_WriteReg,M_WriteReg,E_RegWrite,M_RegWrite,ID_rs,ID_rt)begin
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ID_FwdA=2'b00;
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if((ID_rs==E_WriteReg)&(E_WriteReg!=0)&(E_RegWrite==1))begin
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ID_FwdA=2'b01;
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end
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else begin
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if((ID_rs==M_WriteReg)&(M_WriteReg!=0)&(M_RegWrite==1))begin
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ID_FwdA=2'b10;
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end
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end
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end
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always@(E_WriteReg,M_WriteReg,E_RegWrite,M_RegWrite,ID_rs,ID_rt)begin
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ID_FwdB=2'b00;
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if((ID_rt==E_WriteReg)&(E_WriteReg!=0)&(E_RegWrite==1))begin
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ID_FwdB=2'b01;
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end
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else begin
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if((ID_rt==M_WriteReg)&(M_WriteReg!=0)&(M_RegWrite==1))begin
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ID_FwdB=2'b10;
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end
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end
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end
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wire ID_beq=~ID_Op[5]&~ID_Op[4]&~ID_Op[3]&ID_Op[2]&~ID_Op[1]&~ID_Op[0];
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wire ID_bne=~ID_Op[5]&~ID_Op[4]&~ID_Op[3]&ID_Op[2]&~ID_Op[1]&ID_Op[0];
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wire ID_jalr=~ID_Op[5]&~ID_Op[4]&~ID_Op[3]&~ID_Op[2]&~ID_Op[1]&~ID_Op[0]&~ID_func[5]&~ID_func[4]&ID_func[3]&~ID_func[2]&~ID_func[1]&ID_func[0];
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//lw+add add+beq(jalr) lw+x+beq
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assign stall=(((ID_rs==E_WriteReg)|(ID_rt==E_WriteReg))&(E_MemtoReg==1)&(E_WriteReg!=0)&(E_RegWrite==1))|((ID_beq | ID_bne | ID_jalr)&((ID_rs==E_WriteReg)|(ID_rt==E_WriteReg))&(E_WriteReg!=0)&(E_RegWrite==1))|(((ID_rs==M_WriteReg)|(ID_rt==M_WriteReg))&(M_MemtoReg==1)&(M_WriteReg!=0)&(M_RegWrite==1)&ID_beq);
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//lw+beq
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assign stallstall=((ID_rs==E_WriteReg)|(ID_rt==E_WriteReg))&(E_MemtoReg==1)&(E_WriteReg!=0)&(E_RegWrite==1)&ID_beq;
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endmodule

‎MUX.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/12/23 16:47:49
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// Design Name:
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// Module Name: MUX
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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//决定nextAddr，分别为pc+4,b,j,jr
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module MUX4X32_addr (PCAdd4, B, J, Jr, PCSrc, nextAddr);
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input [31:0] PCAdd4, B, J, Jr;
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input [2:0] PCSrc;
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output [31:0] nextAddr;
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function [31:0] select;
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input [31:0] PCAdd4, B, J, Jr;
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input [2:0] PCSrc;
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case(PCSrc)
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3'b000: select = PCAdd4;
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3'b001: select = B;
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3'b010: select = J;
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3'b011: select = J;
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3'b100: select = Jr;
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3'b101: select = Jr;
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endcase
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endfunction
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assign nextAddr = select (PCAdd4, B, J, Jr, PCSrc);
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endmodule
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//选择写的地址，rd还是rt,1为rt
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module MUX2X5(rd,rt,RegDst,Y);
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input [4:0] rd,rt;
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input RegDst;
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output [4:0] Y;
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function [4:0] select;
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input [4:0] rd,rt;
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input RegDst;
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case(RegDst)
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1:select=rt;
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0:select=rd;
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endcase
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endfunction
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assign Y=select(rd,rt,RegDst);
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endmodule
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//旁路选择器，从Q,EX/MEM,MEM/WB,0中选一个
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module MUX3X32 (Q, EX_MEM, MEM_WB, S, Y);
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input [31:0] Q, EX_MEM, MEM_WB;
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input [1:0] S;
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output [31:0] Y;
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function [31:0] select;
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input [31:0] Q, EX_MEM, MEM_WB;
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input [1:0] S;
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case(S)
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2'b00: select = Q;
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2'b01: select = EX_MEM;
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2'b10: select = MEM_WB;
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endcase
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endfunction
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assign Y = select (Q, EX_MEM, MEM_WB, S);
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endmodule
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//选择ALU x端
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//选择ALU y端的来源，是来自于扩展为32位的立即数，还是Qb，forward啥的，0的时候为扩展
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//选择写回寄存器堆的数据来源，是从dm里面来还是从alu里面来
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module MUX2X32(EXT,Qb_FORWARD,S,Y);
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input [31:0] EXT,Qb_FORWARD;
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input S;
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output [31:0] Y;
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function [31:0] select;
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input [31:0] EXT,Qb_FORWARD;
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input S;
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case(S)
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0:select=EXT;
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1:select=Qb_FORWARD;
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endcase
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endfunction
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assign Y=select(EXT,Qb_FORWARD,S);
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endmodule
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//ID阶段的旁路选择器
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module MUX2X32_forward(ID_Q,ALU_OUT,Fwd,Y);
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input [31:0] ID_Q,ALU_OUT;
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input [1:0] Fwd;
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output [31:0] Y;
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function [31:0] select;
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input [31:0] ID_Q,ALU_OUT;
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input [1:0] Fwd;
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case(Fwd)
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2'b00: select = ID_Q;
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2'b01: select = ALU_OUT;
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endcase
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endfunction
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assign Y = select (ID_Q,ALU_OUT,Fwd);
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endmodule
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//选择load的数据
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module MUX5X32(lb,lbu,lh,lhu,lw,load_option,ext_Dout);
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input [31:0] lb,lbu,lh,lhu,lw;
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input [2:0]load_option;
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output [31:0] ext_Dout;
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function [31:0] select;
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input [31:0]lb,lbu,lh,lhu,lw;
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input [2:0]load_option;
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case(load_option)
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3'b000:select=lw;
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3'b101:select=lb;
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3'b001:select=lbu;
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3'b111:select=lh;
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3'b011:select=lhu;
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endcase
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endfunction
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assign ext_Dout=select(lb,lbu,lh,lhu,lw,load_option);
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endmodule

‎PC.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/12/23 16:47:49
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// Design Name:
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// Module Name: PC
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module PC(Result,Clk,Reset,Address,stall,stallstall); //En=1可以写，stall=0没有发生lw数据冒险
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input Clk;//时钟
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input Reset;//是否重置地址。0-初始化PC，否则接受新地址
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input[31:0] Result;
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input stall,stallstall;
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output reg[31:0] Address;
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wire En;
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assign En=(~stall)&(~stallstall);
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initial begin
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Address <= 32'h00003000;
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end
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always @(posedge Clk or negedge Reset)
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begin
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if(En==1)
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begin
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if (!Reset) //如果为0则初始化PC，否则接受新地址
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begin
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Address <= 32'h000003000;
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end
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else
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begin
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Address = Result;
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end
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end
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end
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endmodule
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