diff --git a/arch/riscv/rules.mk b/arch/riscv/rules.mk
index c2c2efb8b..0c9a74064 100644
--- a/arch/riscv/rules.mk
+++ b/arch/riscv/rules.mk
@@ -24,6 +24,7 @@ RISCV_MMU ?= none
 RISCV_FPU ?= false
 SUBARCH ?= 32
 RISCV_MODE ?= machine
+RISCV_EXTENSION_LIST ?=
 ARCH_RISCV_EMBEDDED ?= false
 ARCH_RISCV_TWOSEGMENT ?= false
 
@@ -134,6 +135,16 @@ ifeq (true,$(call TOBOOL,$(RISCV_FPU)))
     GLOBAL_DEFINES += RISCV_FPU=1
 endif
 
+# based on a list of optional extensions passed in, collapse the extensions into
+# a string appended to the end of the -march line below
+$(info RISCV_EXTENSION_LIST = $(RISCV_EXTENSION_LIST))
+ifneq ($(RISCV_EXTENSION_LIST),)
+    RISCV_MARCH_EXTENSIONS := _$(subst $(SPACE),_,$(RISCV_EXTENSION_LIST))
+else
+    RISCV_MARCH_EXTENSIONS :=
+endif
+#$(info RISCV_MARCH_EXTENSIONS = $(RISCV_MARCH_EXTENSIONS))
+
 # for the moment simply build all sources the same way, with or without float based on
 # the configuration of the platform
 ARCH_COMPILEFLAGS_FLOAT :=
@@ -143,9 +154,9 @@ ARCH_COMPILEFLAGS_NOFLOAT :=
 # compiler codegen flags
 ifeq ($(SUBARCH),32)
     ifeq (true,$(call TOBOOL,$(RISCV_FPU)))
-        ARCH_COMPILEFLAGS := -march=rv32gc -mabi=ilp32d
+        ARCH_COMPILEFLAGS := -march=rv32gc$(RISCV_MARCH_EXTENSIONS) -mabi=ilp32d
     else
-        ARCH_COMPILEFLAGS := -march=rv32imac -mabi=ilp32
+        ARCH_COMPILEFLAGS := -march=rv32imac$(RISCV_MARCH_EXTENSIONS) -mabi=ilp32
     endif
 
     # override machine for ld -r
@@ -157,9 +168,9 @@ else ifeq ($(SUBARCH),64)
         # HACK: use rv64imafdc instead of the equivalent rv64gc due to
         # older toolchains not supporting the mapping of one to the other
         # when selecting libgcc.
-        ARCH_COMPILEFLAGS := -march=rv64imafdc -mabi=lp64d -mcmodel=medany
+        ARCH_COMPILEFLAGS := -march=rv64imafdc$(RISCV_MARCH_EXTENSIONS) -mabi=lp64d -mcmodel=medany
     else
-        ARCH_COMPILEFLAGS := -march=rv64imac -mabi=lp64 -mcmodel=medany
+        ARCH_COMPILEFLAGS := -march=rv64imac$(RISCV_MARCH_EXTENSIONS) -mabi=lp64 -mcmodel=medany
     endif
 
     # override machine for ld -r
@@ -168,6 +179,8 @@ else
     $(error SUBARCH not set or set to something unknown)
 endif
 
+undefine RISCV_MARCH_EXTENSIONS
+
 # test to see if -misa-spec=2.2 is a valid switch.
 # misa-spec is added to make sure the compiler picks up the zicsr extension by default.
 MISA_SPEC := $(shell $(TOOLCHAIN_PREFIX)gcc $(ARCH_COMPILEFLAGS) -misa-spec=2.2 -E - < /dev/null > /dev/null 2>1 && echo supported)
diff --git a/platform/jh7110/rules.mk b/platform/jh7110/rules.mk
index 3360df1c9..54efd72da 100644
--- a/platform/jh7110/rules.mk
+++ b/platform/jh7110/rules.mk
@@ -10,6 +10,7 @@ SMP_MAX_CPUS ?= 4
 LK_HEAP_IMPLEMENTATION ?= dlmalloc
 RISCV_FPU ?= true
 RISCV_MMU ?= sv39
+RISCV_EXTENSION_LIST ?= zba zbb
 
 MODULE_DEPS += lib/cbuf
 MODULE_DEPS += lib/fdt
diff --git a/platform/qemu-virt-riscv/rules.mk b/platform/qemu-virt-riscv/rules.mk
index 74276bcd7..fda55ef35 100644
--- a/platform/qemu-virt-riscv/rules.mk
+++ b/platform/qemu-virt-riscv/rules.mk
@@ -9,6 +9,7 @@ WITH_SMP ?= true
 SMP_MAX_CPUS ?= 8
 LK_HEAP_IMPLEMENTATION ?= dlmalloc
 RISCV_FPU ?= true
+RISCV_EXTENSION_LIST ?= zba zbb zbc zbs
 
 ifeq ($(RISCV_MODE),supervisor)
 ifeq ($(SUBARCH),32)