From 1721900b797bd8fbcfbc40a6f6f5497951e50a2f Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Sun, 11 Aug 2019 15:59:40 +0200 Subject: [PATCH 1/8] linuxboot: set serial speed to 115200 --- config/linux-linuxboot.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/linux-linuxboot.config b/config/linux-linuxboot.config index a454a0962..caf0c5427 100644 --- a/config/linux-linuxboot.config +++ b/config/linux-linuxboot.config @@ -66,7 +66,7 @@ CONFIG_KEXEC_FILE=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_PHYSICAL_ALIGN=0x1000000 CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="earlyprintk=serial,ttyS0,57600 console=ttyS0,57600 nosmp" +CONFIG_CMDLINE="earlyprintk=serial,ttyS0,115200 console=ttyS0,115200 " # CONFIG_MODIFY_LDT_SYSCALL is not set # CONFIG_SUSPEND is not set CONFIG_ACPI_DEBUG=y From 4f3b6682a674d28448aa6e419b2bd996a3fd7608 Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Sun, 11 Aug 2019 16:00:41 +0200 Subject: [PATCH 2/8] supermicro-x11ssh: firmware install works, need sata drivers to boot --- .../supermicro-x11ssh.config | 34 + config/coreboot-supermicro-x11ssh.config | 838 ++++++++++++ modules/coreboot | 7 +- patches/coreboot/0100-supermicro-x11ssh.patch | 1179 +++++++++++++++++ 4 files changed, 2055 insertions(+), 3 deletions(-) create mode 100644 boards/supermicro-x11ssh/supermicro-x11ssh.config create mode 100644 config/coreboot-supermicro-x11ssh.config create mode 100644 patches/coreboot/0100-supermicro-x11ssh.patch diff --git a/boards/supermicro-x11ssh/supermicro-x11ssh.config b/boards/supermicro-x11ssh/supermicro-x11ssh.config new file mode 100644 index 000000000..ef759c02a --- /dev/null +++ b/boards/supermicro-x11ssh/supermicro-x11ssh.config @@ -0,0 +1,34 @@ +# Configuration for a Supermicro X11SSH-T / -TF server +# It has an AST2400 BMC for vga output; the built in i915 is not accessible +export CONFIG_COREBOOT=y +CONFIG_COREBOOT_CONFIG=config/coreboot-supermicro-x11ssh.config +CONFIG_LINUX_CONFIG=config/linux-linuxboot.config + +CONFIG_CRYPTSETUP=y +CONFIG_FLASHROM=y +CONFIG_FLASHTOOLS=y +CONFIG_GPG2=y +CONFIG_KEXEC=y +CONFIG_UTIL_LINUX=y +CONFIG_LVM2=y +CONFIG_MBEDTLS=y +CONFIG_PCIUTILS=y +CONFIG_POPT=y +CONFIG_QRENCODE=y +CONFIG_TPMTOTP=y +CONFIG_DROPBEAR=y + +# Serial console only, no graphics + +CONFIG_LINUX_USB=y +CONFIG_LINUX_E1000E=y + +export CONFIG_TPM=y +export CONFIG_BOOTSCRIPT=/bin/ash +export CONFIG_BOOT_REQ_HASH=n +export CONFIG_BOOT_REQ_ROLLBACK=n +export CONFIG_BOOT_KERNEL_ADD="intel_iommu=on intel_iommu=igfx_off" +export CONFIG_BOOT_KERNEL_REMOVE="quiet" +export CONFIG_BOOT_DEV="/dev/sda1" +export CONFIG_USB_BOOT_DEV="/dev/sdb1" + diff --git a/config/coreboot-supermicro-x11ssh.config b/config/coreboot-supermicro-x11ssh.config new file mode 100644 index 000000000..e8c6a9b5b --- /dev/null +++ b/config/coreboot-supermicro-x11ssh.config @@ -0,0 +1,838 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="-heads" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +CONFIG_CCACHE=y +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +CONFIG_TSEG_STAGE_CACHE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PORTWELL is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +CONFIG_VENDOR_SUPERMICRO=y +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_MAINBOARD_DIR="supermicro/x11ssh" +CONFIG_MAINBOARD_PART_NUMBER="X11SSH-TF" +CONFIG_MAX_CPUS=8 +CONFIG_CBFS_SIZE=0x00800000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_MAINBOARD_VENDOR="Supermicro" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_VGA_BIOS_ID="8086,0406" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0xC000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Supermicro" +CONFIG_VARIANT_DIR="tf" +CONFIG_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_POST_IO=y +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x40000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_HAVE_INTEL_FIRMWARE=y +CONFIG_POST_DEVICE=y +CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 +# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set +CONFIG_TPM_INIT=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=4 +CONFIG_TPM_PIRQ=0x0 +CONFIG_VBOOT_VBNV_OFFSET=0x2a +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="X11SSH-TF" +CONFIG_IFD_BIN_PATH="../../blobs/supermicro-x11ssh/ifd.bin" +CONFIG_ME_BIN_PATH="../../blobs/supermicro-x11ssh/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd" +CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd" +CONFIG_FSP_S_CBFS="fsps.bin" +CONFIG_FSP_M_CBFS="fspm.bin" +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_INTEL_WIFI=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +CONFIG_HEAP_SIZE=0x80000 +# CONFIG_BOARD_SUPERMICRO_H8DMR_FAM10 is not set +# CONFIG_BOARD_SUPERMICRO_H8QME_FAM10 is not set +# CONFIG_BOARD_SUPERMICRO_H8SCM_FAM10 is not set +# CONFIG_BOARD_SUPERMICRO_X10SLM_PLUS_F is not set +CONFIG_BOARD_SUPERMICRO_X11SSH_PLUS_TF=y +CONFIG_BOARD_SUPERMICRO_BASEBOARD_X11SSH=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y +CONFIG_VBOOT_SLOTS_RW_AB=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x8086 +CONFIG_CONSOLE_POST=y +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_LINUX_COMMAND_LINE="" +CONFIG_BOARD_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y +CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set +CONFIG_POWER_STATE_ON_AFTER_FAILURE=y +# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set +CONFIG_MAINBOARD_POWER_FAILURE_STATE=1 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_SMM_RESERVED_SIZE=0x200000 +CONFIG_SMM_MODULE_STACK_SIZE=0x800 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120 +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_PCR_BASE_ADDRESS=0xfd000000 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" +# CONFIG_NHLT_MAX98357 is not set +# CONFIG_NHLT_DA7219 is not set +CONFIG_IFD_CHIPSET="sklkbl" +CONFIG_CPU_BCLK_MHZ=100 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30 +CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35 +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2 +CONFIG_SOC_INTEL_I2C_DEV_MAX=6 +# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_TTYS0_BASE=0x3f8 +# CONFIG_NHLT_MAX98373 is not set +CONFIG_MAX_ROOT_PORTS=24 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y +CONFIG_SOC_INTEL_KABYLAKE=y +CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10 +CONFIG_MAINBOARD_USES_FSP2_0=y +CONFIG_USE_FSP2_0_DRIVER=y +# CONFIG_EXCLUDE_NATIVE_SD_INTERFACE is not set +CONFIG_SKYLAKE_SOC_PCH_H=y +# CONFIG_NHLT_DMIC_2CH is not set +# CONFIG_NHLT_DMIC_4CH is not set +# CONFIG_NHLT_NAU88L25 is not set +# CONFIG_NHLT_SSM4567 is not set +# CONFIG_NHLT_RT5514 is not set +# CONFIG_NHLT_RT5663 is not set +# CONFIG_NHLT_MAX98927 is not set +# CONFIG_NO_FADT_8042 is not set +CONFIG_SOC_INTEL_COMMON=y + +# +# Intel SoC Common Code +# +CONFIG_SOC_INTEL_COMMON_BLOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y +# CONFIG_INTEL_CAR_NEM is not set +# CONFIG_INTEL_CAR_CQOS is not set +CONFIG_INTEL_CAR_NEM_ENHANCED=y +# CONFIG_USE_INTEL_FSP_MP_INIT is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y +CONFIG_SOC_INTEL_COMMON_BLOCK_EBDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y +CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y +CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y +# CONFIG_SKIP_GRAPHICS_ENABLING is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y +CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y +# CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set +CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y +CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y +# CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y +# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 +# CONFIG_HECI_DISABLE_USING_SMM is not set +CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y +CONFIG_SA_PCIEX_LENGTH=0x4000000 +CONFIG_PCIEX_LENGTH_64MB=y +# CONFIG_SA_ENABLE_IMR is not set +CONFIG_SA_ENABLE_DPR=y +CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y +CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y +CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y + +# +# Intel SoC Common PCH Code +# +CONFIG_SOC_INTEL_COMMON_PCH_BASE=y +CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y +CONFIG_PCH_SPECIFIC_OPTIONS=y + +# +# Intel SoC Common coreboot stages +# +# CONFIG_DISPLAY_SMM_MEMORY_MAP is not set +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y +# CONFIG_ACPI_CONSOLE is not set +# CONFIG_MMA is not set +# CONFIG_SOC_INTEL_COMMON_ACPI is not set +CONFIG_SOC_INTEL_COMMON_NHLT=y +# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QUALCOMM_COMMON is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +# CONFIG_ENABLE_VMX is not set +# CONFIG_SET_IA32_FC_LOCK_BIT is not set +CONFIG_MICROCODE_UPDATE_PRE_RAM=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_PARALLEL_MP=y +CONFIG_PARALLEL_MP_AP_WORK=y +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_NO_FIXED_XIP_ROM_SIZE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_NO_SMM is not set +# CONFIG_SMM_ASEG is not set +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +CONFIG_SMM_STUB_STACK_SIZE=0x400 +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_X86_AMD_INIT_SIPI is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y +CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y + +# +# Super I/O +# +CONFIG_SUPERIO_ASPEED_AST2400=y +CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM=y +# CONFIG_SUPERIO_FINTEK_FAN_CONTROL is not set + +# +# Embedded Controllers +# +# CONFIG_EC_GOOGLE_WILCO is not set + +# +# Intel Firmware +# +CONFIG_HAVE_ME_BIN=y +# CONFIG_CHECK_ME is not set +# CONFIG_USE_ME_CLEANER is not set +# CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not set +# CONFIG_MAINBOARD_USES_IFD_EC_REGION is not set +# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_UNLOCK_FLASH_REGIONS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +CONFIG_UDK_2015_BINDING=y +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2015 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +# CONFIG_CBMEM_TOP_BACKUP is not set +CONFIG_EARLY_EBDA_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +# CONFIG_PIRQ_ROUTE is not set + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_FSP_GOP=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_RUN_FSP_GOP is not set +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_INTEL_GMA_ADD_VBT is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000 +# CONFIG_MAINBOARD_HAS_CRB_TPM is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +CONFIG_IPMI_KCS=y +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_MRC_SETTINGS_PROTECT=y +# CONFIG_HAS_RECOVERY_MRC_CACHE is not set +# CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set +# CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set +# CONFIG_MRC_WRITE_NV_LATE is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_VPD is not set +CONFIG_DRIVERS_GENERIC_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_AMD_PI is not set +CONFIG_DRIVERS_ASPEED_AST2050=y +CONFIG_DRIVERS_ASPEED_AST_COMMON=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_DESIGNWARE=y +# CONFIG_DRIVERS_I2C_DESIGNWARE_DEBUG is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +CONFIG_FSP_USE_REPO=y +# CONFIG_DISPLAY_HOBS is not set +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_PLATFORM_USES_FSP2_0=y +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set +# CONFIG_DISPLAY_FSP_HEADER is not set +# CONFIG_FSP_CAR is not set +CONFIG_FSP_M_XIP=y +# CONFIG_FSP_T_XIP is not set +# CONFIG_FSP_USES_CB_STACK is not set +# CONFIG_VERIFY_HOBS is not set +# CONFIG_DISPLAY_FSP_VERSION_INFO is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_HAVE_INTEL_PTT is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +CONFIG_VGA=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_TPM2=y +# CONFIG_USER_NO_TPM is not set +# CONFIG_USER_TPM1 is not set +CONFIG_USER_TPM2=y +CONFIG_DEBUG_TPM=y +# CONFIG_TPM_RDRESP_NEED_DELAY is not set + +# +# Memory initialization +# +CONFIG_PLATFORM_HAS_DRAM_CLEAR=y +# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y +CONFIG_RTC=y + +# +# Console +# +CONFIG_BOOTBLOCK_CONSOLE=y +CONFIG_POSTCAR_CONSOLE=y +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_NO_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +CONFIG_ACPI_NHLT=y + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +CONFIG_PAYLOAD_LINUX=y +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="../../build/supermicro-x11ssh/bzImage" +# CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_NONE is not set +# CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ is not set +CONFIG_LINUX_INITRD="../../build/supermicro-x11ssh/initrd.cpio.xz" +# CONFIG_SEABIOS_STABLE is not set +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +# CONFIG_COMPRESSED_PAYLOAD_LZMA is not set +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# + +# +# CPU Debug Settings +# +CONFIG_HAVE_DISPLAY_MTRRS=y +# CONFIG_DISPLAY_MTRRS is not set + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +CONFIG_HAVE_DEBUG_GPIO=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_HAVE_EM100_SUPPORT=y +# CONFIG_EM100 is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_GENERIC_GPIO_LIB=y +CONFIG_C_ENVIRONMENT_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_POSTCAR=y +CONFIG_HAVE_RAMSTAGE=y diff --git a/modules/coreboot b/modules/coreboot index b2dfec590..ed27b69ec 100644 --- a/modules/coreboot +++ b/modules/coreboot @@ -1,8 +1,9 @@ modules-$(CONFIG_COREBOOT) += coreboot -#coreboot_version := git -#coreboot_repo := https://github.com/osresearch/coreboot -coreboot_version := 4.8.1 +# For the supermicro we're pulling from gerrit review 32734 +coreboot_version := git +coreboot_repo := https://review.coreboot.org/coreboot +#coreboot_version := 4.8.1 coreboot_base_dir := coreboot-$(coreboot_version) coreboot_dir := $(coreboot_base_dir)/$(BOARD) coreboot_tar := coreboot-$(coreboot_version).tar.xz diff --git a/patches/coreboot/0100-supermicro-x11ssh.patch b/patches/coreboot/0100-supermicro-x11ssh.patch new file mode 100644 index 000000000..46a66d110 --- /dev/null +++ b/patches/coreboot/0100-supermicro-x11ssh.patch @@ -0,0 +1,1179 @@ +From 2d795267e2fe78af4eb4070e2562aed5fec25dde Mon Sep 17 00:00:00 2001 +From: Christian Walter +Date: Fri, 10 May 2019 15:52:00 +0200 +Subject: [PATCH] mb/supermicro/x11ssh: Add Supermicro X11SSH-TF + +Add support for the X11SSH-TF which is based on Intel KBL. + +Working: +* SeaBios payload +* LinuxBoot payload +* IPMI of BMC +* PCIe, SATA, USB ports +* RS232 serial +* Native graphics init + +Not working: +* Tianocore doesn't work yet as the Aspeed NGI is text mode only. +* Intel SGX, due to random crashes in soc/intel/common + +For more details have a look at the documentation. + +Please apply those patches as well for good user experience: + +I456be647b159f7a2ea7d94986a24424e56dcc8c4 +I22c6885eae6fd7c778ac37b18f95b8775e9064e3 +Ica0c20255f661dd61edc3a7d15646b7447c4658e + +Signed-off-by: Christian Walter +Signed-off-by: Patrick Rudolph +Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 +--- + +diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md +index 0f3105f..08689b7 100644 +--- a/Documentation/mainboard/index.md ++++ b/Documentation/mainboard/index.md +@@ -111,6 +111,7 @@ + ## Supermicro + + - [X10SLM+-F](supermicro/x10slm-f.md) ++- [X11SSH-TF](supermicro/x11ssh-tf.md) + + ## UP + +diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11ssh-tf.md +new file mode 100644 +index 0000000..e23309d +--- /dev/null ++++ b/Documentation/mainboard/supermicro/x11ssh-tf.md +@@ -0,0 +1,73 @@ ++# Supermicro X11SSH-TF ++ ++This section details how to run coreboot on the [Supermicro X11SSH-TF]. ++ ++## Required proprietary blobs ++ ++* [Intel FSP2.0] ++* Intel ME ++ ++## Flashing coreboot ++ ++The board can be flashed externally using *some* programmers. ++The CH341 was found working, while Dediprog won't detect the chip. ++ ++For more details have a look at the [Flashing tutorial]. ++ ++The flash IC can be found between the two PCIe slots near the southbridge: ++![](x11ssh_flash.jpg) ++ ++## BMC (IPMI) ++ ++This board has an ASPEED [AST2400], which has BMC functionality. The ++BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the ++mainboard near the [AST2400]. This chip is an [MX25L25635F]. ++ ++## Known issues ++ ++- Intel SGX causes secondary APs to crash (disabled for now). ++- MP init causes secondary APs to crash (fix in gerrit). ++- Tianocore doesn't work with Aspeed NGI, as it's text mode only. ++- The IPMI driver times out on cold boot (fix in gerrit). ++ ++## Working ++ ++- USB ++- 2x 10GB Ethernet ++- SATA ++- RS232 ++- VGA on Aspeed ++- SuperIO initialisation ++- ECC DRAM detection ++- PCIe slots ++- TPM on TPM expansion header ++- BMC (IPMI) ++ ++## Technology ++ ++```eval_rst +++------------------+--------------------------------------------------+ ++| CPU | Intel Kaby Lake | +++------------------+--------------------------------------------------+ ++| PCH | Intel C236 | +++------------------+--------------------------------------------------+ ++| Super I/O | ASPEED AST2400 | +++------------------+--------------------------------------------------+ ++| Coprocessor | Intel SPS (server version of the ME) | +++------------------+--------------------------------------------------+ ++| Coprocessor | ASPEED AST2400 | +++------------------+--------------------------------------------------+ ++``` ++ ++## Extra links ++ ++- [Board manual] ++ ++[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 ++[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf ++[flashrom]: https://flashrom.org/Flashrom ++[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf ++[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf ++[Flashing tutorial]: ../../flash_tutorial/ext_power.md ++[Intel FSP2.0]: ../../soc/intel/fsp/index.md ++[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF +diff --git a/Documentation/mainboard/supermicro/x11ssh_flash.jpg b/Documentation/mainboard/supermicro/x11ssh_flash.jpg +new file mode 100644 +index 0000000..8ab07f2 +--- /dev/null ++++ b/Documentation/mainboard/supermicro/x11ssh_flash.jpg +Binary files differ +diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11ssh/Kconfig +new file mode 100644 +index 0000000..517551f +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/Kconfig +@@ -0,0 +1,76 @@ ++config BOARD_SUPERMICRO_BASEBOARD_X11SSH ++ def_bool n ++ select BOARD_ROMSIZE_KB_16384 ++ select HAVE_ACPI_RESUME ++ select HAVE_ACPI_TABLES ++ select HAVE_OPTION_TABLE ++ select SOC_INTEL_KABYLAKE ++ select SKYLAKE_SOC_PCH_H ++ select MAINBOARD_USES_FSP2_0 ++ select MAINBOARD_HAS_LPC_TPM ++ select DRIVERS_ASPEED_AST2050 ++ select SUPERIO_ASPEED_AST2400 ++ select GENERATE_SMBIOS_TABLES ++ select IPMI_KCS ++ ++if BOARD_SUPERMICRO_BASEBOARD_X11SSH ++ ++config SOC_INTEL_COMMON_BLOCK_SGX ++ bool ++ default y ++ ++config VBOOT ++ select VBOOT_NO_BOARD_SUPPORT ++ select GBB_FLAG_DISABLE_LID_SHUTDOWN ++ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC ++ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC ++ select GBB_FLAG_DISABLE_FWMP ++ ++config VBOOT_SLOTS_RW_AB ++ default y ++ ++config VBOOT_VBNV_OFFSET ++ hex ++ default 0x2a ++ ++config FMDFILE ++ string ++ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB ++ ++config CBFS_SIZE ++ hex ++ default 0x009aa000 if !VBOOT ++ ++config IRQ_SLOT_COUNT ++ int ++ default 18 ++ ++config MAINBOARD_DIR ++ string ++ default "supermicro/x11ssh" ++ ++config VARIANT_DIR ++ string ++ default "tf" if BOARD_SUPERMICRO_X11SSH_PLUS_TF ++ ++config DEVICETREE ++ string ++ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" ++ ++config MAINBOARD_PART_NUMBER ++ string ++ default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_PLUS_TF ++ ++config MAX_CPUS ++ int ++ default 8 ++ ++config SUBSYSTEM_VENDOR_ID ++ hex ++ default 0x8086 ++ ++config CONSOLE_POST ++ bool ++ default y ++ ++endif +diff --git a/src/mainboard/supermicro/x11ssh/Kconfig.name b/src/mainboard/supermicro/x11ssh/Kconfig.name +new file mode 100644 +index 0000000..a9b351b +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/Kconfig.name +@@ -0,0 +1,3 @@ ++config BOARD_SUPERMICRO_X11SSH_PLUS_TF ++ bool "X11SSH+-TF" ++ select BOARD_SUPERMICRO_BASEBOARD_X11SSH +diff --git a/src/mainboard/supermicro/x11ssh/Makefile.inc b/src/mainboard/supermicro/x11ssh/Makefile.inc +new file mode 100644 +index 0000000..3c79bd4 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/Makefile.inc +@@ -0,0 +1,23 @@ ++## ++## This file is part of the coreboot project. ++## ++## Copyright (C) 2013 Google Inc. ++## Copyright (C) 2016 Intel Corporation. ++## ++## This program is free software; you can redistribute it and/or modify ++## it under the terms of the GNU General Public License as published by ++## the Free Software Foundation; version 2 of the License. ++## ++## This program is distributed in the hope that it will be useful, ++## but WITHOUT ANY WARRANTY; without even the implied warranty of ++## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++## GNU General Public License for more details. ++## ++ ++bootblock-y += bootblock.c ++ ++ramstage-y += mainboard.c ++ramstage-y += ramstage.c ++ ++subdirs-y += variants/$(VARIANT_DIR) ++CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +diff --git a/src/mainboard/supermicro/x11ssh/acpi/ec.asl b/src/mainboard/supermicro/x11ssh/acpi/ec.asl +new file mode 100644 +index 0000000..e69de29 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/acpi/ec.asl +diff --git a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl b/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl +new file mode 100644 +index 0000000..e69de29 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl +diff --git a/src/mainboard/supermicro/x11ssh/acpi/superio.asl b/src/mainboard/supermicro/x11ssh/acpi/superio.asl +new file mode 100644 +index 0000000..e69de29 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/acpi/superio.asl +diff --git a/src/mainboard/supermicro/x11ssh/acpi_tables.c b/src/mainboard/supermicro/x11ssh/acpi_tables.c +new file mode 100644 +index 0000000..e69de29 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/acpi_tables.c +diff --git a/src/mainboard/supermicro/x11ssh/board_info.txt b/src/mainboard/supermicro/x11ssh/board_info.txt +new file mode 100644 +index 0000000..029d2a9 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/board_info.txt +@@ -0,0 +1,6 @@ ++Vendor name: Supermicro ++Board name: X11SSH Baseboard ++Category: server ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/supermicro/x11ssh/bootblock.c b/src/mainboard/supermicro/x11ssh/bootblock.c +new file mode 100644 +index 0000000..8bc8ab0 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/bootblock.c +@@ -0,0 +1,48 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright 2016 Google Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include "gpio.h" ++#include ++#include ++#include ++#include ++ ++static void early_config_gpio(void) ++{ ++ /* This is a hack for FSP because it does things in MemoryInit() ++ * which it shouldn't do. We have to prepare certain gpios here ++ * because of the brokenness in FSP. */ ++ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); ++} ++ ++static void early_config_superio(void) ++{ ++ const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); ++ if (CONFIG(CONSOLE_SERIAL)) { ++ aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); ++ /* The serial output is garbeled before this timeout. ++ * FIXME: Find out why and remove delay. ++ */ ++ mdelay(1000); ++ } ++} ++ ++void bootblock_mainboard_early_init(void) ++{ ++ early_config_gpio(); ++ early_config_superio(); ++} +diff --git a/src/mainboard/supermicro/x11ssh/cmos.layout b/src/mainboard/supermicro/x11ssh/cmos.layout +new file mode 100644 +index 0000000..201ca33 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/cmos.layout +@@ -0,0 +1,62 @@ ++## ++## This file is part of the coreboot project. ++## ++## Copyright (C) 2007-2008 coresystems GmbH ++## ++## This program is free software; you can redistribute it and/or modify ++## it under the terms of the GNU General Public License as published by ++## the Free Software Foundation; version 2 of the License. ++## ++## This program is distributed in the hope that it will be useful, ++## but WITHOUT ANY WARRANTY; without even the implied warranty of ++## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++## GNU General Public License for more details. ++## ++ ++# ----------------------------------------------------------------- ++entries ++ ++#start-bit length config config-ID name ++ ++0 120 r 0 reserved_memory ++ ++# ----------------------------------------------------------------- ++# RTC_BOOT_BYTE (coreboot hardcoded) ++384 1 e 4 boot_option ++388 4 h 0 reboot_counter ++ ++# ----------------------------------------------------------------- ++# coreboot config options: console ++395 4 e 6 debug_level ++448 128 r 0 vbnv ++ ++# coreboot config options: check sums ++984 16 h 0 check_sum ++ ++# ----------------------------------------------------------------- ++ ++enumerations ++ ++#ID value text ++1 0 Disable ++1 1 Enable ++2 0 Enable ++2 1 Disable ++4 0 Fallback ++4 1 Normal ++6 0 Emergency ++6 1 Alert ++6 2 Critical ++6 3 Error ++6 4 Warning ++6 5 Notice ++6 6 Info ++6 7 Debug ++6 8 Spew ++7 0 Disable ++7 1 Enable ++7 2 Keep ++# ----------------------------------------------------------------- ++checksums ++ ++checksum 392 415 984 +diff --git a/src/mainboard/supermicro/x11ssh/dsdt.asl b/src/mainboard/supermicro/x11ssh/dsdt.asl +new file mode 100644 +index 0000000..ac929a6 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/dsdt.asl +@@ -0,0 +1,50 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2007-2009 coresystems GmbH ++ * Copyright (C) 2015 Google Inc. ++ * Copyright (C) 2016 Intel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++DefinitionBlock( ++ "dsdt.aml", ++ "DSDT", ++ 0x02, // DSDT revision: ACPI v2.0 and up ++ OEM_ID, ++ ACPI_TABLE_CREATOR, ++ 0x20110725 // OEM revision ++) ++{ ++ // Some generic macros ++ #include ++ ++ // global NVS and variables ++ #include ++ ++ // CPU ++ #include ++ ++ Scope (\_SB) { ++ Device (PCI0) ++ { ++ #include ++ #include ++ } ++ } ++ ++ // Chipset specific sleep states ++ #include ++ ++ // Mainboard specific ++ #include "acpi/mainboard.asl" ++} +diff --git a/src/mainboard/supermicro/x11ssh/gpio.h b/src/mainboard/supermicro/x11ssh/gpio.h +new file mode 100644 +index 0000000..04857c6 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/gpio.h +@@ -0,0 +1,256 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2018 Intel Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _GPIOX11SSHTF_H ++#define _GPIOX11SSHTF_H ++ ++#include ++#include ++ ++ ++/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ ++#define GPE_WLAN_WAKE GPE0_DW0_16 ++ ++/* BIOS Flash Write Protect */ ++#define GPIO_PCH_WP GPP_C23 ++ ++#ifndef __ACPI__ ++/*** XXX TODO XXX */ ++static const struct pad_config gpio_table[] = { ++/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), ++/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), ++/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), ++/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), ++/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), ++/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), ++/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), ++/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), ++/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), ++/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), ++/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), ++/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), ++/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), ++/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), ++/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), ++/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), ++/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), ++/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), ++/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), ++/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), ++/* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), ++/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), ++/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), ++/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), ++/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), ++/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), ++/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), ++/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), ++/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), ++/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), ++/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), ++/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), ++/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), ++/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), ++/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), ++/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), ++/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), ++/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), ++/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), ++/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), ++/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), ++/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), ++/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), ++/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), ++/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), ++/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), ++/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), ++/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), ++/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), ++/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), ++/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), ++/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), ++/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), ++/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), ++/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), ++/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), ++/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), ++/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), ++/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), ++}; ++ ++ ++/*** XXX TODO XXX */ ++/* Early pad configuration in romstage. */ ++static const struct pad_config early_gpio_table[] = { ++/* LPC */ ++ ++/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), ++/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), ++/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), ++/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), ++/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), ++/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), ++/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), ++/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), ++/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), ++}; ++ ++#endif /* __ACPI__ */ ++#endif /* _GPIOX11SSHTF_H */ +diff --git a/src/mainboard/supermicro/x11ssh/mainboard.c b/src/mainboard/supermicro/x11ssh/mainboard.c +new file mode 100644 +index 0000000..d09a373 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/mainboard.c +@@ -0,0 +1,26 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2007-2009 coresystems GmbH ++ * Copyright (C) 2013 Google Inc. ++ * Copyright (C) 2016 Intel Corporation. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++ ++static void mainboard_enable(struct device *dev) ++{ ++} ++ ++struct chip_operations mainboard_ops = { ++ .enable_dev = mainboard_enable, ++}; +diff --git a/src/mainboard/supermicro/x11ssh/ramstage.c b/src/mainboard/supermicro/x11ssh/ramstage.c +new file mode 100644 +index 0000000..2672f73 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/ramstage.c +@@ -0,0 +1,27 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include "gpio.h" ++ ++void mainboard_silicon_init_params(FSP_SIL_UPD *params) ++{ ++ /* Configure pads prior to SiliconInit() in case there's any ++ * dependencies during hardware initialization. */ ++ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); ++ params->CdClock = 3; ++ ++ /* This must be one, otherwise FSP crashes ... */ ++ params->PchHdaVcType = 0x1; ++} +diff --git a/src/mainboard/supermicro/x11ssh/romstage.c b/src/mainboard/supermicro/x11ssh/romstage.c +new file mode 100644 +index 0000000..cb1f105 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/romstage.c +@@ -0,0 +1,37 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++void mainboard_memory_init_params(FSPM_UPD *mupd) ++{ ++ FSP_M_CONFIG *mem_cfg; ++ mem_cfg = &mupd->FspmConfig; ++ ++ struct spd_block blk = { ++ .addr_map = { 0x50, 0x51, 0x52, 0x53, }, ++ }; ++ ++ mem_cfg->DqPinsInterleaved = 1; ++ get_spd_smbus(&blk); ++ mem_cfg->MemorySpdDataLen = blk.len; ++ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; ++ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; ++ mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; ++ mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; ++ mem_cfg->UserBd = BOARD_TYPE_SERVER; ++ ++ mupd->FspmTestConfig.DmiVc1 = 1; ++} +diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt +new file mode 100644 +index 0000000..f3eb3ef +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt +@@ -0,0 +1,6 @@ ++Vendor name: Supermicro ++Board name: X11SSH-TF ++Category: server ++ROM protocol: SPI ++ROM socketed: n ++Flashrom support: y +diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb +new file mode 100644 +index 0000000..dbb589f +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb +@@ -0,0 +1,290 @@ ++chip soc/intel/skylake ++ ++ # Enable deep Sx states ++ register "deep_s5_enable_ac" = "0" ++ register "deep_s5_enable_dc" = "0" ++ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" ++ ++ # GPE configuration ++ # Note that GPE events called out in ASL code rely on this ++ # route. i.e. If this route changes then the affected GPE ++ # offset bits also need to be changed. ++ register "gpe0_dw0" = "GPP_B" ++ register "gpe0_dw1" = "GPP_D" ++ register "gpe0_dw2" = "GPP_E" ++ ++ register "gen1_dec" = "0x007c0a01" # Super IO ++ register "gen2_dec" = "0x000c0ca1" # IPMI KCS ++ register "gen3_dec" = "0x000c03e1" # UART3/4 ++ ++ # Enable "Intel Speed Shift Technology" ++ register "speed_shift_enable" = "1" ++ ++ # FSP Configuration ++ register "SmbusEnable" = "1" ++ register "ScsEmmcEnabled" = "0" ++ register "ScsEmmcHs400Enabled" = "0" ++ register "ScsSdCardEnabled" = "0" ++ register "SkipExtGfxScan" = "1" ++ register "Device4Enable" = "1" ++ register "SaGv" = "SaGv_Enabled" ++ ++ # Disable SGX ++ register "sgx_enable" = "0" # SGX is broken in coreboot ++ register "PrmrrSize" = "128 * MiB" ++ ++ register "pirqa_routing" = "PCH_IRQ11" ++ register "pirqb_routing" = "PCH_IRQ10" ++ register "pirqc_routing" = "PCH_IRQ11" ++ register "pirqd_routing" = "PCH_IRQ11" ++ register "pirqe_routing" = "PCH_IRQ11" ++ register "pirqf_routing" = "PCH_IRQ11" ++ register "pirqg_routing" = "PCH_IRQ11" ++ register "pirqh_routing" = "PCH_IRQ11" ++ ++ register "SataMode" = "0" ++ register "EnableSata" = "1" ++ register "SataSalpSupport" = "1" ++ register "SataPortsEnable" = "{ \ ++ [0] = 1, \ ++ [1] = 1, \ ++ [2] = 1, \ ++ [3] = 1, \ ++ [4] = 1, \ ++ [5] = 1, \ ++ [6] = 1, \ ++ [7] = 1, \ ++ }" ++ ++ register "SataPortsDevSlp" = "{\ ++ [0] = 0, \ ++ [1] = 0, \ ++ [2] = 0, \ ++ [3] = 0, \ ++ [4] = 0, \ ++ [5] = 0, \ ++ [6] = 0, \ ++ [7] = 0, \ ++ }" ++ ++ # USB related ++ register "SsicPortEnable" = "1" ++ ++ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # OTG ++ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Touch Pad ++ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # OTG ++ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # Touch Pad ++ ++ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # OTG ++ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Touch Pad ++ ++ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # OTG ++ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Touch Pad ++ ++ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # OTG ++ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # Touch Pad ++ ++ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # OTG ++ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # Touch Pad ++ ++ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # Touch Pad ++ ++ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB ++ ++ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # OTG ++ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # M.2 WWAN ++ ++ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" # OTG ++ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # M.2 WWAN ++ ++ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" # M.2 WWAN ++ ++ register "serirq_mode" = "SERIRQ_CONTINUOUS" ++ ++ # Enable PCIE slot ++ register "PcieRpEnable[0]" = "1" ++ register "PcieRpClkReqSupport[0]" = "0" ++ ++ # Enable PCIE slot ++ register "PcieRpEnable[2]" = "1" ++ register "PcieRpClkReqSupport[2]" = "0" ++ ++ # Enable PCIE slot ++ register "PcieRpEnable[4]" = "1" ++ register "PcieRpClkReqSupport[4]" = "0" ++ ++ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch ++ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s ++ register "PmConfigSlpS3MinAssert" = "0x02" ++ ++ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s ++ register "PmConfigSlpS4MinAssert" = "0x04" ++ ++ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s ++ register "PmConfigSlpSusMinAssert" = "0x03" ++ ++ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s ++ register "PmConfigSlpAMinAssert" = "0x03" ++ ++ ++ # VR Settings Configuration for 4 Domains ++ #+----------------+-------+-------+-------+-------+ ++ #| Domain/Setting | SA | IA | GTUS | GTS | ++ #+----------------+-------+-------+-------+-------+ ++ #| Psi1Threshold | 20A | 20A | 20A | 20A | ++ #| Psi2Threshold | 5A | 5A | 5A | 5A | ++ #| Psi3Threshold | 1A | 1A | 1A | 1A | ++ #| Psi3Enable | 1 | 1 | 1 | 1 | ++ #| Psi4Enable | 1 | 1 | 1 | 1 | ++ #| ImonSlope | 0 | 0 | 0 | 0 | ++ #| ImonOffset | 0 | 0 | 0 | 0 | ++ #| IccMax | 7A | 34A | 35A | 35A | ++ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | ++ #+----------------+-------+-------+-------+-------+ ++ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ ++ .vr_config_enable = 1, \ ++ .psi1threshold = 0x50, \ ++ .psi2threshold = 0x10, \ ++ .psi3threshold = 0x4, \ ++ .psi3enable = 1, \ ++ .psi4enable = 1, \ ++ .imon_slope = 0x0, \ ++ .imon_offset = 0x0, \ ++ .icc_max = 0x1C, \ ++ .voltage_limit = 0x5F0 \ ++ }" ++ ++ register "domain_vr_config[VR_IA_CORE]" = "{ ++ .vr_config_enable = 1, \ ++ .psi1threshold = 0x50, \ ++ .psi2threshold = 0x14, \ ++ .psi3threshold = 0x4, \ ++ .psi3enable = 1, \ ++ .psi4enable = 1, \ ++ .imon_slope = 0x0, \ ++ .imon_offset = 0x0, \ ++ .icc_max = 0x88, \ ++ .voltage_limit = 0x5F0 \ ++ }" ++ ++ register "domain_vr_config[VR_GT_UNSLICED]" = "{ ++ .vr_config_enable = 1, \ ++ .psi1threshold = 0x50, \ ++ .psi2threshold = 0x14, \ ++ .psi3threshold = 0x4, \ ++ .psi3enable = 1, \ ++ .psi4enable = 1, \ ++ .imon_slope = 0x0, \ ++ .imon_offset = 0x0, \ ++ .icc_max = 0x8C ,\ ++ .voltage_limit = 0x5F0 \ ++ }" ++ ++ register "domain_vr_config[VR_GT_SLICED]" = "{ ++ .vr_config_enable = 1, \ ++ .psi1threshold = 0x50, \ ++ .psi2threshold = 0x14, \ ++ .psi3threshold = 0x4, \ ++ .psi3enable = 1, \ ++ .psi4enable = 1, \ ++ .imon_slope = 0x0, \ ++ .imon_offset = 0x0, \ ++ .icc_max = 0x8C, \ ++ .voltage_limit = 0x5F0 \ ++ }" ++ ++ # Send an extra VR mailbox command for the PS4 exit issue ++ register "SendVrMbxCmd" = "2" ++ ++ # Lock Down ++ register "common_soc_config" = "{ ++ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, ++ }" ++ ++ device cpu_cluster 0 on ++ device lapic 0 on end ++ end ++ device domain 0 on ++ device pci 00.0 on end # Host Bridge ++ device pci 01.0 on end # PCI Slot ++ device pci 01.1 on ++ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" ++ end # PCIE Slot (JPCIE1) ++ device pci 14.0 on end # USB xHCI ++ device pci 14.2 on end # Thermal Subsystem ++ device pci 16.0 on end # Management Engine Interface 1 ++ device pci 16.1 on end # Management Engine Interface 2 ++ device pci 17.0 on end # SATA ++ device pci 1c.0 on ++ smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" ++ end # PCI Express Port 1 (Slot JPCIE1) ++ device pci 1c.2 on ++ device pci 00.0 on ++ device pci 00.0 on end #Aspeed 2400 VGA ++ end ++ end # PCI Express Port 3 ++ device pci 1c.4 on ++ device pci 00.0 on end # 10GBE ++ device pci 00.1 on end # 10GBE ++ end # PCI Express Port 5 ++ device pci 1f.0 on ++ chip drivers/ipmi ++ device pnp ca2.0 on ++ end # IPMI KCS ++ end ++ chip superio/common ++ device pnp 2e.0 on ++ chip superio/aspeed/ast2400 ++ device pnp 2e.0 off end ++ device pnp 2e.2 on # SUART1 ++ io 0x60 = 0x3f8 ++ irq 0x70 = 4 ++ end ++ device pnp 2e.3 on # SUART2 ++ io 0x60 = 0x2f8 ++ irq 0x70 = 3 ++ end ++ device pnp 2e.4 on # SWC ++ io 0x60 = 0xa00 ++ io 0x62 = 0xa10 ++ io 0x64 = 0xa20 ++ io 0x66 = 0xa30 ++ irq 0x70 = 0 ++ end ++ device pnp 2e.5 on # Keyboard ++ io 0x60 = 0x60 ++ io 0x62 = 0x64 ++ irq 0x70 = 1 ++ irq 0x72 = 0xc ++ end ++ device pnp 2e.7 on # GPIO ++ irq 0x70 = 0 ++ end ++ device pnp 2e.b on # SUART3 ++ io 0x60 = 0x3e8 ++ irq 0x70 = 6 ++ end ++ device pnp 2e.c on # SUART4 ++ io 0x60 = 0x2e8 ++ irq 0x70 = 5 ++ end ++ device pnp 2e.d on # iLPC2AHB ++ irq 0x70 = 0 ++ end ++ device pnp 2e.e on # Mailbox ++ io 0x60 = 0xa40 ++ irq 0x70 = 0x00 ++ end ++ end ++ end ++ end ++ chip drivers/pc80/tpm ++ device pnp 0c31.0 on end ++ end ++ end # LPC Interface ++ device pci 1f.1 off end # P2SB ++ device pci 1f.2 on end # Power Management Controller ++ device pci 1f.4 on end # SMBus ++ device pci 1f.5 on end # SPI Controller ++ end ++end +diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd +new file mode 100644 +index 0000000..a295680 +--- /dev/null ++++ b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd +@@ -0,0 +1,36 @@ ++FLASH 16M { ++ SI_ALL@0x0 0x500000 { ++ SI_DESC@0x0 0x1000 ++ SI_ME@0x1000 0x4ff000 ++ } ++ SI_BIOS@0x500000 0xb00000 { ++ RW_SECTION_A@0x0 0x33e000 { ++ VBLOCK_A@0x0 0x20000 ++ FW_MAIN_A(CBFS)@0x20000 0x31dfc0 ++ RW_FWID_A@0x33dfc0 0x40 ++ } ++ RW_SECTION_B@0x33e000 0x33e000 { ++ VBLOCK_B@0x0 0x20000 ++ FW_MAIN_B(CBFS)@0x20000 0x31dfc0 ++ RW_FWID_B@0x33dfc0 0x40 ++ } ++ MISC_RW@0x67d000 0x62000 { ++ UNIFIED_MRC_CACHE@0x0 0x20000 { ++ RECOVERY_MRC_CACHE@0x0 0x10000 ++ RW_MRC_CACHE@0x10000 0x10000 ++ } ++ RW_VPD(PRESERVE)@0x20000 0x2000 ++ SMMSTORE(PRESERVE)@0x22000 0x40000 ++ } ++ WP_RO@0x6df000 0x421000 { ++ RO_VPD(PRESERVE)@0x0 0x4000 ++ RO_SECTION@0x4000 0x41d000 { ++ FMAP@0x0 0x800 ++ RO_FRID@0x800 0x40 ++ RO_FRID_PAD@0x840 0x7c0 ++ GBB@0x1000 0xef000 ++ COREBOOT(CBFS)@0xf0000 0x32d000 ++ } ++ } ++ } ++} From 4d4be41d3f202dc738393790c524ba08394d4e8d Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Sun, 11 Aug 2019 17:01:58 +0200 Subject: [PATCH 3/8] supermicro-x11ssh: igb ethernet and ata drivers --- boards/supermicro-x11ssh/supermicro-x11ssh.config | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/boards/supermicro-x11ssh/supermicro-x11ssh.config b/boards/supermicro-x11ssh/supermicro-x11ssh.config index ef759c02a..4d95b037e 100644 --- a/boards/supermicro-x11ssh/supermicro-x11ssh.config +++ b/boards/supermicro-x11ssh/supermicro-x11ssh.config @@ -17,11 +17,19 @@ CONFIG_POPT=y CONFIG_QRENCODE=y CONFIG_TPMTOTP=y CONFIG_DROPBEAR=y +CONFIG_MSRTOOLS=y # Serial console only, no graphics CONFIG_LINUX_USB=y -CONFIG_LINUX_E1000E=y +CONFIG_LINUX_IGB=y + +CONFIG_LINUX_SCSI_GDTH=y +CONFIG_LINUX_ATA=y +CONFIG_LINUX_AHCI=y +CONFIG_LINUX_NVME=y +CONFIG_LINUX_MEI=y + export CONFIG_TPM=y export CONFIG_BOOTSCRIPT=/bin/ash From 0d9a1e5038c867e6ba27901290e2a5d8d3265399 Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Mon, 12 Aug 2019 14:59:18 +0200 Subject: [PATCH 4/8] initrd: helper to load the SATA modules and mount a partition --- initrd/bin/mount-sata | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100755 initrd/bin/mount-sata diff --git a/initrd/bin/mount-sata b/initrd/bin/mount-sata new file mode 100755 index 000000000..35c1b50bb --- /dev/null +++ b/initrd/bin/mount-sata @@ -0,0 +1,14 @@ +#!/bin/sh +# Setup the devices for SATA +. /etc/functions + +for mod in libata libahci ahci; do + if ! lsmod | grep -q "^$mod " ; then + insmod "/lib/modules/$mod.ko" \ + || die "$mod: Unable to load module" + fi +done + +if [ ! -z "$1" ]; then + exec mount "$@" +fi From 1cb40ada07d8681c738ed65e549e916728b5cf4f Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Mon, 12 Aug 2019 15:09:32 +0200 Subject: [PATCH 5/8] supermicro-x11ssh: drop to a recovery shell --- boards/supermicro-x11ssh/supermicro-x11ssh.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/supermicro-x11ssh/supermicro-x11ssh.config b/boards/supermicro-x11ssh/supermicro-x11ssh.config index 4d95b037e..437169ac1 100644 --- a/boards/supermicro-x11ssh/supermicro-x11ssh.config +++ b/boards/supermicro-x11ssh/supermicro-x11ssh.config @@ -32,7 +32,7 @@ CONFIG_LINUX_MEI=y export CONFIG_TPM=y -export CONFIG_BOOTSCRIPT=/bin/ash +export CONFIG_BOOTSCRIPT=enter-recovery-shell export CONFIG_BOOT_REQ_HASH=n export CONFIG_BOOT_REQ_ROLLBACK=n export CONFIG_BOOT_KERNEL_ADD="intel_iommu=on intel_iommu=igfx_off" From 97c4e7b02e48dd6126c07010580ce14d675c226f Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Thu, 29 Aug 2019 11:39:31 +0200 Subject: [PATCH 6/8] supermicro-x11ssh: IFD compatible with spispy --- blobs/supermicro-x11ssh/ifd.bin | Bin 0 -> 4096 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 blobs/supermicro-x11ssh/ifd.bin diff --git a/blobs/supermicro-x11ssh/ifd.bin b/blobs/supermicro-x11ssh/ifd.bin new file mode 100644 index 0000000000000000000000000000000000000000..d94633527f3daadeb4c72f38ac26abec75afb3ab GIT binary patch literal 4096 zcmeHJJ5Iwu5Ph~|u!A5`6emVPcpA6J)G}K5mT!JQ1E|HQW zIECpVE&DTy(Fvka>Tu8Yr6ubV2+5&UKie?ST2_(meJEFtgQZmYo1Lt$7vn#Id018gF0Pt z?;msgl%{FK&*JP`b#VY64el8Ry!N;!8*t(%qN3OSv+ua={~=zol{GVQ@@+XxpHaXl zU=%P47zK<1MggOMQQ*HS5b=wCKmp}R2QIlZi3jk>r*b_STCyHpseLnQ%Y8EnbX0va z>S`QfNJDxXKf|57^GW<7`AS~OR9~Jbo^o!UsQ$d)MNBc}{ZPe`#v_I4Gn8|7q373` Hx%2-3XQ8N> literal 0 HcmV?d00001 From 8ff038f0c7f3a7b20f83988e3fbb3a79d310f3b7 Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Thu, 29 Aug 2019 11:55:37 +0200 Subject: [PATCH 7/8] supermicro-x11ssh: update patch to c933f4972abb7 --- patches/coreboot/0100-supermicro-x11ssh.patch | 200 +++++++++--------- 1 file changed, 100 insertions(+), 100 deletions(-) diff --git a/patches/coreboot/0100-supermicro-x11ssh.patch b/patches/coreboot/0100-supermicro-x11ssh.patch index 46a66d110..8e9946d60 100644 --- a/patches/coreboot/0100-supermicro-x11ssh.patch +++ b/patches/coreboot/0100-supermicro-x11ssh.patch @@ -1,4 +1,4 @@ -From 2d795267e2fe78af4eb4070e2562aed5fec25dde Mon Sep 17 00:00:00 2001 +From c933f4972abb7acca4981d193cfddd9d4290f3ff Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Fri, 10 May 2019 15:52:00 +0200 Subject: [PATCH] mb/supermicro/x11ssh: Add Supermicro X11SSH-TF @@ -9,7 +9,7 @@ Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC -* PCIe, SATA, USB ports +* PCIe, SATA, USB and M.2 ports * RS232 serial * Native graphics init @@ -44,10 +44,10 @@ index 0f3105f..08689b7 100644 diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11ssh-tf.md new file mode 100644 -index 0000000..e23309d +index 0000000..b35874d --- /dev/null +++ b/Documentation/mainboard/supermicro/x11ssh-tf.md -@@ -0,0 +1,73 @@ +@@ -0,0 +1,74 @@ +# Supermicro X11SSH-TF + +This section details how to run coreboot on the [Supermicro X11SSH-TF]. @@ -76,13 +76,14 @@ index 0000000..e23309d +## Known issues + +- Intel SGX causes secondary APs to crash (disabled for now). -+- MP init causes secondary APs to crash (fix in gerrit). +- Tianocore doesn't work with Aspeed NGI, as it's text mode only. -+- The IPMI driver times out on cold boot (fix in gerrit). ++- After S5 resume coreboot detects more DIMMs than installed, causing FSP-M ++ to fail. + -+## Working ++## Tested and working + -+- USB ++- USB ports ++- M.2 2280 NVMe slot +- 2x 10GB Ethernet +- SATA +- RS232 @@ -841,10 +842,10 @@ index 0000000..f3eb3ef +Flashrom support: y diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb new file mode 100644 -index 0000000..dbb589f +index 0000000..38699ee --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb -@@ -0,0 +1,290 @@ +@@ -0,0 +1,289 @@ +chip soc/intel/skylake + + # Enable deep Sx states @@ -860,9 +861,10 @@ index 0000000..dbb589f + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + -+ register "gen1_dec" = "0x007c0a01" # Super IO ++ register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS -+ register "gen3_dec" = "0x000c03e1" # UART3/4 ++ register "gen3_dec" = "0x000c03e1" # UART3 ++ register "gen4_dec" = "0x000c02e1" # UART4 + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" @@ -874,7 +876,7 @@ index 0000000..dbb589f + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" -+ register "SaGv" = "SaGv_Enabled" ++ register "SaGv" = "SaGv_Disabled" + + # Disable SGX + register "sgx_enable" = "0" # SGX is broken in coreboot @@ -889,7 +891,8 @@ index 0000000..dbb589f + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + -+ register "SataMode" = "0" ++ # SATA configuration ++ register "SataMode" = "0" # AHCI + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ @@ -914,52 +917,56 @@ index 0000000..dbb589f + [7] = 0, \ + }" + -+ # USB related -+ register "SsicPortEnable" = "1" ++ # superspeed_inter-chip_supplement (SSIC) disabled ++ register "SsicPortEnable" = "0" + -+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # OTG -+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Touch Pad -+ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # OTG -+ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # Touch Pad ++ # USB configuration ++ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3 ++ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3 ++ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ? ++ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ? + -+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # OTG -+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Touch Pad ++ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5 ++ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5 + -+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # OTG -+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Touch Pad ++ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1 ++ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1 + -+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # OTG -+ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # Touch Pad ++ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0) ++ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0) ++ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" ++ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + -+ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # OTG -+ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # Touch Pad ++ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0) ++ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0) ++ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" ++ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + -+ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # Touch Pad ++ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0) ++ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + -+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB -+ -+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # OTG -+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # M.2 WWAN -+ -+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" # OTG -+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # M.2 WWAN -+ -+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" # M.2 WWAN ++ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB + ++ # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + -+ # Enable PCIE slot ++ # PCIe configuration ++ # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + -+ # Enable PCIE slot ++ # Enable ASpeed PCI bridge + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + -+ # Enable PCIE slot ++ # Enable X550T + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + ++ # Enable M.2 ++ register "PcieRpEnable[8]" = "1" ++ register "PcieRpClkReqSupport[8]" = "0" ++ + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" @@ -973,75 +980,65 @@ index 0000000..dbb589f + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + -+ + # VR Settings Configuration for 4 Domains -+ #+----------------+-------+-------+-------+-------+ -+ #| Domain/Setting | SA | IA | GTUS | GTS | -+ #+----------------+-------+-------+-------+-------+ -+ #| Psi1Threshold | 20A | 20A | 20A | 20A | -+ #| Psi2Threshold | 5A | 5A | 5A | 5A | -+ #| Psi3Threshold | 1A | 1A | 1A | 1A | -+ #| Psi3Enable | 1 | 1 | 1 | 1 | -+ #| Psi4Enable | 1 | 1 | 1 | 1 | -+ #| ImonSlope | 0 | 0 | 0 | 0 | -+ #| ImonOffset | 0 | 0 | 0 | 0 | -+ #| IccMax | 7A | 34A | 35A | 35A | -+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | -+ #+----------------+-------+-------+-------+-------+ ++ # ICC_MAX = 0 (Auto) ++ # Voltage limit 1.52V (not used on KBL-S and KBL-DT) ++ # Disable PS4 powerstate in S0ix, thus no package C10 support ++ # psi threshold is using FSP default values + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ -+ .psi1threshold = 0x50, \ -+ .psi2threshold = 0x10, \ -+ .psi3threshold = 0x4, \ ++ .psi1threshold = VR_CFG_AMP(20), ++ .psi2threshold = VR_CFG_AMP(5), ++ .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ -+ .psi4enable = 1, \ ++ .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ -+ .icc_max = 0x1C, \ -+ .voltage_limit = 0x5F0 \ ++ .icc_max = 0, \ ++ .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ -+ .psi1threshold = 0x50, \ -+ .psi2threshold = 0x14, \ -+ .psi3threshold = 0x4, \ ++ .psi1threshold = VR_CFG_AMP(20), ++ .psi2threshold = VR_CFG_AMP(5), ++ .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ -+ .psi4enable = 1, \ ++ .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ -+ .icc_max = 0x88, \ -+ .voltage_limit = 0x5F0 \ ++ .icc_max = 0, \ ++ .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ -+ .psi1threshold = 0x50, \ -+ .psi2threshold = 0x14, \ -+ .psi3threshold = 0x4, \ ++ .psi1threshold = VR_CFG_AMP(20), ++ .psi2threshold = VR_CFG_AMP(5), ++ .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ -+ .psi4enable = 1, \ ++ .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ -+ .icc_max = 0x8C ,\ -+ .voltage_limit = 0x5F0 \ ++ .icc_max = 0 ,\ ++ .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ -+ .psi1threshold = 0x50, \ -+ .psi2threshold = 0x14, \ -+ .psi3threshold = 0x4, \ ++ .psi1threshold = VR_CFG_AMP(20), ++ .psi2threshold = VR_CFG_AMP(5), ++ .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ -+ .psi4enable = 1, \ ++ .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ -+ .icc_max = 0x8C, \ -+ .voltage_limit = 0x5F0 \ ++ .icc_max = 0, \ ++ .voltage_limit = 1520 \ + }" + -+ # Send an extra VR mailbox command for the PS4 exit issue -+ register "SendVrMbxCmd" = "2" ++ # No extra VR mailbox command ++ register "SendVrMbxCmd" = "0" + + # Lock Down + register "common_soc_config" = "{ @@ -1052,14 +1049,14 @@ index 0000000..dbb589f + device lapic 0 on end + end + device domain 0 on -+ device pci 00.0 on end # Host Bridge -+ device pci 01.0 on end # PCI Slot ++ device pci 00.0 on end # Host Bridge ++ device pci 01.0 on end # unused + device pci 01.1 on + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" + end # PCIE Slot (JPCIE1) -+ device pci 14.0 on end # USB xHCI -+ device pci 14.2 on end # Thermal Subsystem -+ device pci 16.0 on end # Management Engine Interface 1 ++ device pci 14.0 on end # USB xHCI ++ device pci 14.2 on end # Thermal Subsystem ++ device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 17.0 on end # SATA + device pci 1c.0 on @@ -1067,17 +1064,22 @@ index 0000000..dbb589f + end # PCI Express Port 1 (Slot JPCIE1) + device pci 1c.2 on + device pci 00.0 on -+ device pci 00.0 on end #Aspeed 2400 VGA ++ device pci 00.0 on end # Aspeed 2400 VGA + end + end # PCI Express Port 3 + device pci 1c.4 on -+ device pci 00.0 on end # 10GBE -+ device pci 00.1 on end # 10GBE ++ device pci 00.0 on end # 10GBE ++ device pci 00.1 on end # 10GBE + end # PCI Express Port 5 ++ device pci 1d.0 on ++ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" ++ end # PCI Express Port 9 + device pci 1f.0 on + chip drivers/ipmi -+ device pnp ca2.0 on -+ end # IPMI KCS ++ # On cold boot it takes a while for the BMC to start the IPMI service ++ register "wait_for_bmc" = "1" ++ register "bmc_boot_timeout" = "60" ++ device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on @@ -1096,7 +1098,7 @@ index 0000000..dbb589f + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 -+ irq 0x70 = 0 ++ irq 0x70 = 0xb + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 @@ -1105,18 +1107,16 @@ index 0000000..dbb589f + irq 0x72 = 0xc + end + device pnp 2e.7 on # GPIO -+ irq 0x70 = 0 + end + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 -+ irq 0x70 = 6 ++ irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 -+ irq 0x70 = 5 ++ irq 0x70 = 3 + end + device pnp 2e.d on # iLPC2AHB -+ irq 0x70 = 0 + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 @@ -1129,10 +1129,10 @@ index 0000000..dbb589f + device pnp 0c31.0 on end + end + end # LPC Interface -+ device pci 1f.1 off end # P2SB -+ device pci 1f.2 on end # Power Management Controller -+ device pci 1f.4 on end # SMBus -+ device pci 1f.5 on end # SPI Controller ++ device pci 1f.1 on end # P2SB ++ device pci 1f.2 on end # Power Management Controller ++ device pci 1f.4 on end # SMBus ++ device pci 1f.5 on end # SPI Controller + end +end diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd From 79b6191826cdf3bd75ee7b648d9b5688e38caebc Mon Sep 17 00:00:00 2001 From: Trammell hudson Date: Fri, 30 Aug 2019 10:07:53 +0200 Subject: [PATCH 8/8] supermicro-x11ssh: update to patchset 75 --- patches/coreboot/0100-supermicro-x11ssh.patch | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/patches/coreboot/0100-supermicro-x11ssh.patch b/patches/coreboot/0100-supermicro-x11ssh.patch index 8e9946d60..8daff75a0 100644 --- a/patches/coreboot/0100-supermicro-x11ssh.patch +++ b/patches/coreboot/0100-supermicro-x11ssh.patch @@ -1,4 +1,4 @@ -From c933f4972abb7acca4981d193cfddd9d4290f3ff Mon Sep 17 00:00:00 2001 +From a9d9dc521e5cac7a044a3f238e731265e967bdb0 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Fri, 10 May 2019 15:52:00 +0200 Subject: [PATCH] mb/supermicro/x11ssh: Add Supermicro X11SSH-TF @@ -460,7 +460,7 @@ index 0000000..ac929a6 +} diff --git a/src/mainboard/supermicro/x11ssh/gpio.h b/src/mainboard/supermicro/x11ssh/gpio.h new file mode 100644 -index 0000000..04857c6 +index 0000000..90647b7 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/gpio.h @@ -0,0 +1,256 @@ @@ -514,7 +514,7 @@ index 0000000..04857c6 +/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), @@ -543,14 +543,14 @@ index 0000000..04857c6 +/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), +/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -+/* RESERVED */ _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), ++/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000),