forked from vnmakarov/mir
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathmir-gen.c
4709 lines (4219 loc) · 171 KB
/
mir-gen.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* This file is a part of MIR project.
Copyright (C) 2018-2020 Vladimir Makarov <[email protected]>.
*/
/* Optimization pipeline:
---------------- ----------- ------------------ -------------
MIR --->| Simplify |--->| Build CFG |--->| Common Sub-Expr |--->| Dead Code |
---------------- ----------- | Elimination | | Elimination |
------------------ -------------
|
v
------------- ------------ --------- ----------- ----------------------
| Build Live |<---| Build Live |<---| Finding |<---| Machinize |<--| Sparse Conditional |
| Ranges | | Info | | Loops | ----------- | Constant Propagation |
------------- ------------ --------- ----------------------
|
v
--------- --------- --------- ------------- ---------------
| Assign |-->| Rewrite |-->| Combine |-->| Dead Code |--->| Generate |---> Machine
--------- --------- --------- | Elimination | | machine insns | Insns
------------- ---------------
Simplify: Lowering MIR (in mir.c).
Build CGF: Builing Control Flow Graph (basic blocks and CFG edges).
Common Sub-Expression Elimination: Reusing calculated values
Dead code elimination: Removing insns with unused outputs.
Sparse Conditional Constant Propagation: constant propagation and removing death paths of CFG
Machinize: Machine-dependent code (e.g. in mir-gen-x86_64.c)
transforming MIR for calls ABI, 2-op insns, etc.
Finding Loops: Building loop tree which is used in subsequent register allocation.
Building Live Info: Calculating live in and live out for the basic blocks.
Build Live Ranges: Calculating program point ranges for registers.
Assign: Priority-based assigning hard regs and stack slots to registers.
Rewrite: Transform MIR according to the assign using reserved hard regs.
Combine (code selection): Merging data-depended insns into one.
Dead code elimination: Removing insns with unused outputs.
Generate machine insns: Machine-dependent code (e.g. in
mir-gen-x86_64.c) creating machine insns.
Terminology:
reg - MIR (pseudo-)register (their numbers are in MIR_OP_REG and MIR_OP_MEM)
hard reg - MIR hard register (their numbers are in MIR_OP_HARD_REG and MIR_OP_HARD_REG_MEM)
breg (based reg) - function pseudo registers whose numbers start with zero
var - pseudo and hard register (var numbers for psedo-registers
are based reg numbers + MAX_HARD_REG + 1)
loc - hard register and stack locations (stack slot numbers start with MAX_HARD_REG + 1).
We don't use SSA because the optimization pipeline could use SSA is
short (2 passes) and going into / out of SSA is expensive.
*/
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <assert.h>
#ifdef NDEBUG
static inline int gen_assert (int cond) { return 0 && cond; }
#else
#define gen_assert(cond) assert (cond)
#endif
struct MIR_context;
static void util_error (struct MIR_context *ctx, const char *message);
static void varr_error (const char *message) { util_error (NULL, message); }
#define MIR_VARR_ERROR varr_error
#include "mir.h"
#include "mir-dlist.h"
#include "mir-bitmap.h"
#include "mir-htab.h"
#include "mir-hash.h"
#include "mir-gen.h"
static void MIR_NO_RETURN util_error (MIR_context_t ctx, const char *message) {
(*MIR_get_error_func (ctx)) (MIR_alloc_error, message);
}
static void *gen_malloc (MIR_context_t ctx, size_t size) {
void *res = malloc (size);
if (res == NULL) util_error (ctx, "no memory");
return res;
}
static MIR_reg_t gen_new_temp_reg (MIR_context_t ctx, MIR_type_t type, MIR_func_t func);
static void set_label_disp (MIR_insn_t insn, size_t disp);
static size_t get_label_disp (MIR_insn_t insn);
static void create_new_bb_insns (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t after,
MIR_insn_t insn_for_bb);
static void gen_delete_insn (MIR_context_t ctx, MIR_insn_t insn);
static void gen_add_insn_before (MIR_context_t ctx, MIR_insn_t insn, MIR_insn_t before);
static void gen_add_insn_after (MIR_context_t ctx, MIR_insn_t insn, MIR_insn_t after);
static void setup_call_hard_reg_args (MIR_insn_t call_insn, MIR_reg_t hard_reg);
#ifndef MIR_GEN_DEBUG
#define MIR_GEN_DEBUG 0
#endif
#ifndef MIR_GEN_CALL_TRACE
#define MIR_GEN_CALL_TRACE 0
#endif
typedef struct func_cfg *func_cfg_t;
struct target_ctx;
struct data_flow_ctx;
struct cse_ctx;
struct ccp_ctx;
struct lr_ctx;
struct ra_ctx;
struct selection_ctx;
typedef struct loop_node *loop_node_t;
DEF_VARR (loop_node_t);
struct gen_ctx {
MIR_item_t curr_func_item;
#if MIR_GEN_DEBUG
FILE *debug_file;
#endif
bitmap_t insn_to_consider, temp_bitmap, temp_bitmap2, all_vars;
bitmap_t call_used_hard_regs;
func_cfg_t curr_cfg;
size_t curr_bb_index, curr_loop_node_index;
struct target_ctx *target_ctx;
struct data_flow_ctx *data_flow_ctx;
struct cse_ctx *cse_ctx;
struct ccp_ctx *ccp_ctx;
struct lr_ctx *lr_ctx;
struct ra_ctx *ra_ctx;
struct selection_ctx *selection_ctx;
VARR (loop_node_t) * loop_nodes, *queue_nodes, *loop_entries; /* used in building loop tree */
};
static inline struct gen_ctx **gen_ctx_loc (MIR_context_t ctx) { return (struct gen_ctx **) ctx; }
#define curr_func_item gen_ctx->curr_func_item
#define debug_file gen_ctx->debug_file
#define insn_to_consider gen_ctx->insn_to_consider
#define temp_bitmap gen_ctx->temp_bitmap
#define temp_bitmap2 gen_ctx->temp_bitmap2
#define all_vars gen_ctx->all_vars
#define call_used_hard_regs gen_ctx->call_used_hard_regs
#define curr_cfg gen_ctx->curr_cfg
#define curr_bb_index gen_ctx->curr_bb_index
#define curr_loop_node_index gen_ctx->curr_loop_node_index
#define loop_nodes gen_ctx->loop_nodes
#define queue_nodes gen_ctx->queue_nodes
#define loop_entries gen_ctx->loop_entries
#ifdef __x86_64__
#include "mir-gen-x86_64.c"
#else
#error "undefined or unsupported generation target"
#endif
#define DEFAULT_INIT_BITMAP_BITS_NUM 256
static void make_io_dup_op_insns (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func;
MIR_insn_t insn, next_insn;
MIR_insn_code_t code;
MIR_op_t input, output, temp_op;
MIR_op_mode_t mode;
MIR_type_t type;
size_t i;
int out_p;
gen_assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
for (i = 0; target_io_dup_op_insn_codes[i] != MIR_INSN_BOUND; i++)
bitmap_set_bit_p (insn_to_consider, target_io_dup_op_insn_codes[i]);
if (bitmap_empty_p (insn_to_consider)) return;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (!bitmap_bit_p (insn_to_consider, code)) continue;
gen_assert (MIR_insn_nops (ctx, insn) >= 2 && !MIR_call_code_p (code) && code != MIR_RET);
mode = MIR_insn_op_mode (ctx, insn, 0, &out_p);
gen_assert (out_p && mode == MIR_insn_op_mode (ctx, insn, 1, &out_p) && !out_p);
output = insn->ops[0];
input = insn->ops[1];
gen_assert (input.mode == MIR_OP_REG || input.mode == MIR_OP_HARD_REG
|| output.mode == MIR_OP_REG || output.mode == MIR_OP_HARD_REG);
if (input.mode == output.mode
&& ((input.mode == MIR_OP_HARD_REG && input.u.hard_reg == output.u.hard_reg)
|| (input.mode == MIR_OP_REG && input.u.reg == output.u.reg)))
continue;
if (mode == MIR_OP_FLOAT) {
code = MIR_FMOV;
type = MIR_T_F;
} else if (mode == MIR_OP_DOUBLE) {
code = MIR_DMOV;
type = MIR_T_D;
} else if (mode == MIR_OP_LDOUBLE) {
code = MIR_LDMOV;
type = MIR_T_LD;
} else {
code = MIR_MOV;
type = MIR_T_I64;
}
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, type, func));
gen_add_insn_before (ctx, insn, MIR_new_insn (ctx, code, temp_op, insn->ops[1]));
gen_add_insn_after (ctx, insn, MIR_new_insn (ctx, code, insn->ops[0], temp_op));
insn->ops[0] = insn->ops[1] = temp_op;
}
}
typedef struct dead_var *dead_var_t;
DEF_DLIST_LINK (dead_var_t);
typedef struct bb *bb_t;
DEF_DLIST_LINK (bb_t);
typedef struct bb_insn *bb_insn_t;
DEF_DLIST_LINK (bb_insn_t);
typedef struct edge *edge_t;
typedef edge_t in_edge_t;
typedef edge_t out_edge_t;
DEF_DLIST_LINK (in_edge_t);
DEF_DLIST_LINK (out_edge_t);
struct edge {
bb_t src, dst;
DLIST_LINK (in_edge_t) in_link;
DLIST_LINK (out_edge_t) out_link;
unsigned char back_edge_p;
unsigned char skipped_p; /* used for CCP */
};
DEF_DLIST (in_edge_t, in_link);
DEF_DLIST (out_edge_t, out_link);
struct dead_var {
MIR_reg_t var;
DLIST_LINK (dead_var_t) dead_var_link;
};
DEF_DLIST (dead_var_t, dead_var_link);
struct bb_insn {
MIR_insn_t insn;
unsigned int flag; /* used for CPP */
DLIST_LINK (bb_insn_t) bb_insn_link;
bb_t bb;
DLIST (dead_var_t) dead_vars;
bitmap_t call_hard_reg_args; /* non-null for calls */
size_t label_disp; /* for label */
};
DEF_DLIST (bb_insn_t, bb_insn_link);
struct bb {
size_t index, pre, rpost;
unsigned int flag : 1; /* used for CPP */
DLIST_LINK (bb_t) bb_link;
DLIST (in_edge_t) in_edges;
/* The out edges order: optional fall through bb, optional label bb,
optional exit bb. There is always at least one edge. */
DLIST (out_edge_t) out_edges;
DLIST (bb_insn_t) bb_insns;
size_t freq;
bitmap_t in, out, gen, kill; /* var bitmaps for different data flow problems */
loop_node_t loop_node;
};
DEF_DLIST (bb_t, bb_link);
DEF_DLIST_LINK (loop_node_t);
DEF_DLIST_TYPE (loop_node_t);
struct loop_node {
size_t index;
bb_t bb; /* NULL for internal tree node */
loop_node_t entry;
loop_node_t parent;
DLIST (loop_node_t) children;
DLIST_LINK (loop_node_t) children_link;
};
DEF_DLIST_CODE (loop_node_t, children_link);
DEF_DLIST_LINK (func_cfg_t);
typedef struct mv *mv_t;
typedef mv_t dst_mv_t;
typedef mv_t src_mv_t;
DEF_DLIST_LINK (mv_t);
DEF_DLIST_LINK (dst_mv_t);
DEF_DLIST_LINK (src_mv_t);
struct mv {
bb_insn_t bb_insn;
size_t freq;
DLIST_LINK (mv_t) mv_link;
DLIST_LINK (dst_mv_t) dst_link;
DLIST_LINK (src_mv_t) src_link;
};
DEF_DLIST (mv_t, mv_link);
DEF_DLIST (dst_mv_t, dst_link);
DEF_DLIST (src_mv_t, src_link);
struct reg_info {
long freq;
size_t calls_num;
/* The followd members are defined and used only in RA */
long thread_freq; /* thread accumulated freq, defined for first thread breg */
/* first/next breg of the same thread, MIR_MAX_REG_NUM is end mark */
MIR_reg_t thread_first, thread_next;
size_t live_length; /* # of program points where breg lives */
DLIST (dst_mv_t) dst_moves;
DLIST (src_mv_t) src_moves;
};
typedef struct reg_info reg_info_t;
DEF_VARR (reg_info_t);
typedef struct {
int uns_p;
union {
int64_t i;
uint64_t u;
} u;
} const_t;
#if MIR_GEN_DEBUG
static void print_const (FILE *f, const_t c) {
if (c.uns_p)
fprintf (f, "%" PRIu64, c.u.u);
else
fprintf (f, "%" PRId64, c.u.i);
}
#endif
struct func_cfg {
MIR_reg_t min_reg, max_reg;
size_t non_conflicting_moves; /* # of moves with non-conflicting regs */
VARR (reg_info_t) * breg_info; /* bregs */
DLIST (bb_t) bbs;
DLIST (mv_t) used_moves, free_moves;
loop_node_t root_loop_node;
};
static DLIST (dead_var_t) free_dead_vars;
static void init_dead_vars (void) { DLIST_INIT (dead_var_t, free_dead_vars); }
static void free_dead_var (dead_var_t dv) { DLIST_APPEND (dead_var_t, free_dead_vars, dv); }
static dead_var_t get_dead_var (MIR_context_t ctx) {
dead_var_t dv;
if ((dv = DLIST_HEAD (dead_var_t, free_dead_vars)) == NULL)
return gen_malloc (ctx, sizeof (struct dead_var));
DLIST_REMOVE (dead_var_t, free_dead_vars, dv);
return dv;
}
static void finish_dead_vars (void) {
dead_var_t dv;
while ((dv = DLIST_HEAD (dead_var_t, free_dead_vars)) != NULL) {
DLIST_REMOVE (dead_var_t, free_dead_vars, dv);
free (dv);
}
}
static void add_bb_insn_dead_var (MIR_context_t ctx, bb_insn_t bb_insn, MIR_reg_t var) {
dead_var_t dv;
for (dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL;
dv = DLIST_NEXT (dead_var_t, dv))
if (dv->var == var) return;
dv = get_dead_var (ctx);
dv->var = var;
DLIST_APPEND (dead_var_t, bb_insn->dead_vars, dv);
}
static dead_var_t find_bb_insn_dead_var (bb_insn_t bb_insn, MIR_reg_t var) {
dead_var_t dv;
for (dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL;
dv = DLIST_NEXT (dead_var_t, dv))
if (dv->var == var) return dv;
return NULL;
}
static void clear_bb_insn_dead_vars (bb_insn_t bb_insn) {
dead_var_t dv;
while ((dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars)) != NULL) {
DLIST_REMOVE (dead_var_t, bb_insn->dead_vars, dv);
free_dead_var (dv);
}
}
static void remove_bb_insn_dead_var (bb_insn_t bb_insn, MIR_reg_t hr) {
dead_var_t dv, next_dv;
gen_assert (hr <= MAX_HARD_REG);
for (dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL; dv = next_dv) {
next_dv = DLIST_NEXT (dead_var_t, dv);
if (dv->var != hr) continue;
DLIST_REMOVE (dead_var_t, bb_insn->dead_vars, dv);
free_dead_var (dv);
}
}
static void move_bb_insn_dead_vars (bb_insn_t bb_insn, bb_insn_t from_bb_insn) {
dead_var_t dv;
while ((dv = DLIST_HEAD (dead_var_t, from_bb_insn->dead_vars)) != NULL) {
DLIST_REMOVE (dead_var_t, from_bb_insn->dead_vars, dv);
DLIST_APPEND (dead_var_t, bb_insn->dead_vars, dv);
}
}
static bb_insn_t create_bb_insn (MIR_context_t ctx, MIR_insn_t insn, bb_t bb) {
bb_insn_t bb_insn = gen_malloc (ctx, sizeof (struct bb_insn));
insn->data = bb_insn;
bb_insn->bb = bb;
bb_insn->insn = insn;
bb_insn->flag = FALSE;
bb_insn->call_hard_reg_args = NULL;
DLIST_INIT (dead_var_t, bb_insn->dead_vars);
if (MIR_call_code_p (insn->code)) bb_insn->call_hard_reg_args = bitmap_create2 (MAX_HARD_REG + 1);
return bb_insn;
}
static bb_insn_t add_new_bb_insn (MIR_context_t ctx, MIR_insn_t insn, bb_t bb) {
bb_insn_t bb_insn = create_bb_insn (ctx, insn, bb);
DLIST_APPEND (bb_insn_t, bb->bb_insns, bb_insn);
return bb_insn;
}
static void delete_bb_insn (bb_insn_t bb_insn) {
DLIST_REMOVE (bb_insn_t, bb_insn->bb->bb_insns, bb_insn);
bb_insn->insn->data = NULL;
clear_bb_insn_dead_vars (bb_insn);
if (bb_insn->call_hard_reg_args != NULL) bitmap_destroy (bb_insn->call_hard_reg_args);
free (bb_insn);
}
static void create_new_bb_insns (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t after,
MIR_insn_t insn_for_bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_insn_t insn;
bb_insn_t bb_insn, new_bb_insn;
bb_t bb;
if (insn_for_bb == NULL) /* It should be in the 1st block */
bb = DLIST_EL (bb_t, curr_cfg->bbs, 2); /* Skip entry and exit blocks */
else
bb = ((bb_insn_t) insn_for_bb->data)->bb;
if (before != NULL && (bb_insn = before->data)->bb == bb) {
for (insn = DLIST_NEXT (MIR_insn_t, before); insn != after;
insn = DLIST_NEXT (MIR_insn_t, insn), bb_insn = new_bb_insn) {
new_bb_insn = create_bb_insn (ctx, insn, bb);
DLIST_INSERT_AFTER (bb_insn_t, bb->bb_insns, bb_insn, new_bb_insn);
}
} else {
bb_insn = after->data;
gen_assert (after != NULL);
insn = (before == NULL ? DLIST_HEAD (MIR_insn_t, curr_func_item->u.func->insns)
: DLIST_NEXT (MIR_insn_t, before));
for (; insn != after; insn = DLIST_NEXT (MIR_insn_t, insn)) {
new_bb_insn = create_bb_insn (ctx, insn, bb);
if (bb == bb_insn->bb)
DLIST_INSERT_BEFORE (bb_insn_t, bb->bb_insns, bb_insn, new_bb_insn);
else
DLIST_APPEND (bb_insn_t, bb->bb_insns, new_bb_insn);
}
}
}
static void gen_delete_insn (MIR_context_t ctx, MIR_insn_t insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
delete_bb_insn (insn->data);
MIR_remove_insn (ctx, curr_func_item, insn);
}
static void gen_add_insn_before (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_insert_insn_before (ctx, curr_func_item, before, insn);
create_new_bb_insns (ctx, DLIST_PREV (MIR_insn_t, insn), before, before);
}
static void gen_add_insn_after (MIR_context_t ctx, MIR_insn_t after, MIR_insn_t insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_insert_insn_after (ctx, curr_func_item, after, insn);
create_new_bb_insns (ctx, after, DLIST_NEXT (MIR_insn_t, insn), after);
}
static void setup_call_hard_reg_args (MIR_insn_t call_insn, MIR_reg_t hard_reg) {
bb_insn_t bb_insn = call_insn->data;
gen_assert (MIR_call_code_p (call_insn->code) && hard_reg <= MAX_HARD_REG);
bitmap_set_bit_p (bb_insn->call_hard_reg_args, hard_reg);
}
static void set_label_disp (MIR_insn_t insn, size_t disp) {
gen_assert (insn->code == MIR_LABEL);
((bb_insn_t) insn->data)->label_disp = disp;
}
static size_t get_label_disp (MIR_insn_t insn) {
gen_assert (insn->code == MIR_LABEL);
return ((bb_insn_t) insn->data)->label_disp;
}
static bb_t create_bb (MIR_context_t ctx, MIR_insn_t insn) {
bb_t bb = gen_malloc (ctx, sizeof (struct bb));
bb->pre = bb->rpost = 0;
bb->flag = FALSE;
DLIST_INIT (bb_insn_t, bb->bb_insns);
DLIST_INIT (in_edge_t, bb->in_edges);
DLIST_INIT (out_edge_t, bb->out_edges);
bb->in = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->out = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->gen = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->kill = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
if (insn != NULL) add_new_bb_insn (ctx, insn, bb);
return bb;
}
static void add_bb (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
DLIST_APPEND (bb_t, curr_cfg->bbs, bb);
bb->index = curr_bb_index++;
}
static edge_t create_edge (MIR_context_t ctx, bb_t src, bb_t dst) {
edge_t e = gen_malloc (ctx, sizeof (struct edge));
e->src = src;
e->dst = dst;
DLIST_APPEND (in_edge_t, dst->in_edges, e);
DLIST_APPEND (out_edge_t, src->out_edges, e);
e->back_edge_p = e->skipped_p = FALSE;
return e;
}
static void delete_edge (edge_t e) {
DLIST_REMOVE (out_edge_t, e->src->out_edges, e);
DLIST_REMOVE (in_edge_t, e->dst->in_edges, e);
free (e);
}
static void delete_bb (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e, next_e;
for (e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = next_e) {
next_e = DLIST_NEXT (out_edge_t, e);
delete_edge (e);
}
for (e = DLIST_HEAD (in_edge_t, bb->in_edges); e != NULL; e = next_e) {
next_e = DLIST_NEXT (in_edge_t, e);
delete_edge (e);
}
DLIST_REMOVE (bb_t, curr_cfg->bbs, bb);
bitmap_destroy (bb->in);
bitmap_destroy (bb->out);
bitmap_destroy (bb->gen);
bitmap_destroy (bb->kill);
free (bb);
}
static void DFS (bb_t bb, size_t *pre, size_t *rpost) {
edge_t e;
bb->pre = (*pre)++;
for (e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = DLIST_NEXT (out_edge_t, e))
if (e->dst->pre == 0)
DFS (e->dst, pre, rpost);
else if (e->dst->rpost == 0)
e->back_edge_p = TRUE;
bb->rpost = (*rpost)--;
}
static void enumerate_bbs (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
size_t pre, rpost;
pre = 1;
rpost = DLIST_LENGTH (bb_t, curr_cfg->bbs);
DFS (DLIST_HEAD (bb_t, curr_cfg->bbs), &pre, &rpost);
}
static loop_node_t top_loop_node (bb_t bb) {
for (loop_node_t loop_node = bb->loop_node;; loop_node = loop_node->parent)
if (loop_node->parent == NULL) return loop_node;
}
static loop_node_t create_loop_node (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
loop_node_t loop_node = gen_malloc (ctx, sizeof (struct loop_node));
loop_node->index = curr_loop_node_index++;
loop_node->bb = bb;
if (bb != NULL) bb->loop_node = loop_node;
loop_node->parent = NULL;
loop_node->entry = NULL;
DLIST_INIT (loop_node_t, loop_node->children);
return loop_node;
}
static void process_loop (MIR_context_t ctx, bb_t entry_bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e;
loop_node_t loop_node, new_loop_node, queue_node;
bb_t queue_bb;
VARR_TRUNC (loop_node_t, loop_nodes, 0);
VARR_TRUNC (loop_node_t, queue_nodes, 0);
bitmap_clear (temp_bitmap);
for (e = DLIST_HEAD (in_edge_t, entry_bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e))
if (e->back_edge_p && e->src != entry_bb) {
loop_node = top_loop_node (e->src);
if (!bitmap_set_bit_p (temp_bitmap, loop_node->index)) continue;
VARR_PUSH (loop_node_t, loop_nodes, loop_node);
VARR_PUSH (loop_node_t, queue_nodes, loop_node);
}
while (VARR_LENGTH (loop_node_t, queue_nodes) != 0) {
queue_node = VARR_POP (loop_node_t, queue_nodes);
if ((queue_bb = queue_node->bb) == NULL) queue_bb = queue_node->entry->bb; /* subloop */
/* entry block is achieved which means multiple entry loop -- just ignore */
if (queue_bb == DLIST_HEAD (bb_t, curr_cfg->bbs)) return;
for (e = DLIST_HEAD (in_edge_t, queue_bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e))
if (e->src != entry_bb) {
loop_node = top_loop_node (e->src);
if (!bitmap_set_bit_p (temp_bitmap, loop_node->index)) continue;
VARR_PUSH (loop_node_t, loop_nodes, loop_node);
VARR_PUSH (loop_node_t, queue_nodes, loop_node);
}
}
loop_node = entry_bb->loop_node;
VARR_PUSH (loop_node_t, loop_nodes, loop_node);
new_loop_node = create_loop_node (ctx, NULL);
new_loop_node->entry = loop_node;
while (VARR_LENGTH (loop_node_t, loop_nodes) != 0) {
loop_node = VARR_POP (loop_node_t, loop_nodes);
DLIST_APPEND (loop_node_t, new_loop_node->children, loop_node);
loop_node->parent = new_loop_node;
}
}
static int compare_bb_loop_nodes (const void *p1, const void *p2) {
bb_t bb1 = (*(const loop_node_t *) p1)->bb, bb2 = (*(const loop_node_t *) p2)->bb;
return bb1->rpost > bb2->rpost ? -1 : bb1->rpost < bb2->rpost ? 1 : 0;
}
static void build_loop_tree (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
loop_node_t loop_node;
edge_t e;
curr_loop_node_index = 0;
enumerate_bbs (ctx);
VARR_TRUNC (loop_node_t, loop_entries, 0);
for (bb_t bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb)) {
loop_node = create_loop_node (ctx, bb);
loop_node->entry = loop_node;
for (e = DLIST_HEAD (in_edge_t, bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e))
if (e->back_edge_p) {
VARR_PUSH (loop_node_t, loop_entries, loop_node);
break;
}
}
qsort (VARR_ADDR (loop_node_t, loop_entries), VARR_LENGTH (loop_node_t, loop_entries),
sizeof (loop_node_t), compare_bb_loop_nodes);
for (size_t i = 0; i < VARR_LENGTH (loop_node_t, loop_entries); i++)
process_loop (ctx, VARR_GET (loop_node_t, loop_entries, i)->bb);
curr_cfg->root_loop_node = create_loop_node (ctx, NULL);
for (bb_t bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb))
if ((loop_node = top_loop_node (bb)) != curr_cfg->root_loop_node) {
DLIST_APPEND (loop_node_t, curr_cfg->root_loop_node->children, loop_node);
loop_node->parent = curr_cfg->root_loop_node;
}
}
static void destroy_loop_tree (MIR_context_t ctx, loop_node_t root) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
loop_node_t node, next;
if (root->bb == NULL)
for (node = DLIST_HEAD (loop_node_t, root->children); node != NULL; node = next) {
next = DLIST_NEXT (loop_node_t, node);
destroy_loop_tree (ctx, node);
}
free (root);
}
static void update_min_max_reg (MIR_context_t ctx, MIR_reg_t reg) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
if (reg == 0) return;
if (curr_cfg->max_reg == 0 || curr_cfg->min_reg > reg) curr_cfg->min_reg = reg;
if (curr_cfg->max_reg < reg) curr_cfg->max_reg = reg;
}
static MIR_reg_t gen_new_temp_reg (MIR_context_t ctx, MIR_type_t type, MIR_func_t func) {
MIR_reg_t reg = _MIR_new_temp_reg (ctx, type, func);
update_min_max_reg (ctx, reg);
return reg;
}
static MIR_reg_t reg2breg (struct gen_ctx *gen_ctx, MIR_reg_t reg) {
return reg - curr_cfg->min_reg;
}
static MIR_reg_t breg2reg (struct gen_ctx *gen_ctx, MIR_reg_t breg) {
return breg + curr_cfg->min_reg;
}
static MIR_reg_t reg2var (struct gen_ctx *gen_ctx, MIR_reg_t reg) {
return reg2breg (gen_ctx, reg) + MAX_HARD_REG + 1;
}
static MIR_reg_t var_is_reg_p (MIR_reg_t var) { return var > MAX_HARD_REG; }
static MIR_reg_t var2reg (struct gen_ctx *gen_ctx, MIR_reg_t var) {
gen_assert (var > MAX_HARD_REG);
return breg2reg (gen_ctx, var - MAX_HARD_REG - 1);
}
static MIR_reg_t get_nregs (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
return curr_cfg->max_reg == 0 ? 0 : curr_cfg->max_reg - curr_cfg->min_reg + 1;
}
static MIR_reg_t get_nvars (MIR_context_t ctx) { return get_nregs (ctx) + MAX_HARD_REG + 1; }
static int move_p (MIR_insn_t insn) {
return ((insn->code == MIR_MOV || insn->code == MIR_FMOV || insn->code == MIR_DMOV
|| insn->code == MIR_LDMOV)
&& (insn->ops[0].mode == MIR_OP_REG || insn->ops[0].mode == MIR_OP_HARD_REG)
&& (insn->ops[1].mode == MIR_OP_REG || insn->ops[1].mode == MIR_OP_HARD_REG));
}
static int imm_move_p (MIR_insn_t insn) {
return ((insn->code == MIR_MOV || insn->code == MIR_FMOV || insn->code == MIR_DMOV
|| insn->code == MIR_LDMOV)
&& (insn->ops[0].mode == MIR_OP_REG || insn->ops[0].mode == MIR_OP_HARD_REG)
&& (insn->ops[1].mode == MIR_OP_INT || insn->ops[1].mode == MIR_OP_UINT
|| insn->ops[1].mode == MIR_OP_FLOAT || insn->ops[1].mode == MIR_OP_DOUBLE
|| insn->ops[1].mode == MIR_OP_LDOUBLE || insn->ops[1].mode == MIR_OP_REF));
}
#if MIR_GEN_DEBUG
static void output_in_edges (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e;
fprintf (debug_file, " in edges:");
for (e = DLIST_HEAD (in_edge_t, bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e)) {
fprintf (debug_file, " %3lu", (unsigned long) e->src->index);
if (e->skipped_p) fprintf (debug_file, "(CCP skip)");
}
fprintf (debug_file, "\n");
}
static void output_out_edges (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e;
fprintf (debug_file, " out edges:");
for (e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = DLIST_NEXT (out_edge_t, e)) {
fprintf (debug_file, " %3lu", (unsigned long) e->dst->index);
if (e->skipped_p) fprintf (debug_file, "(CCP skip)");
}
fprintf (debug_file, "\n");
}
static void output_live_element (size_t nel, void *data) {
MIR_context_t ctx = data;
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
fprintf (debug_file, "%3lu", (unsigned long) nel);
if (var_is_reg_p (nel))
fprintf (debug_file, "(%s:%s)",
MIR_type_str (ctx, MIR_reg_type (ctx, var2reg (gen_ctx, nel), curr_func_item->u.func)),
MIR_reg_name (ctx, var2reg (gen_ctx, nel), curr_func_item->u.func));
}
static void output_bitmap (MIR_context_t ctx, const char *head, bitmap_t bm) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
if (bm == NULL || bitmap_empty_p (bm)) return;
fprintf (debug_file, "%s", head);
bitmap_for_each (bm, output_live_element, ctx);
fprintf (debug_file, "\n");
}
static void print_bb_insn (MIR_context_t ctx, bb_insn_t bb_insn, int with_notes_p) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_op_t op;
MIR_output_insn (ctx, debug_file, bb_insn->insn, curr_func_item->u.func, FALSE);
if (with_notes_p) {
for (dead_var_t dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL;
dv = DLIST_NEXT (dead_var_t, dv)) {
if (var_is_reg_p (dv->var)) {
op.mode = MIR_OP_REG;
op.u.reg = var2reg (gen_ctx, dv->var);
} else {
op.mode = MIR_OP_HARD_REG;
op.u.hard_reg = dv->var;
}
fprintf (debug_file, dv == DLIST_HEAD (dead_var_t, bb_insn->dead_vars) ? " # dead: " : " ");
MIR_output_op (ctx, debug_file, op, curr_func_item->u.func);
}
}
fprintf (debug_file, "\n");
}
static void print_CFG (MIR_context_t ctx, int bb_p, int insns_p,
void (*bb_info_print_func) (MIR_context_t, bb_t)) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
for (bb_t bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb)) {
if (bb_p) {
fprintf (debug_file, "BB %3lu:\n", (unsigned long) bb->index);
output_in_edges (ctx, bb);
output_out_edges (ctx, bb);
if (bb_info_print_func != NULL) {
bb_info_print_func (ctx, bb);
fprintf (debug_file, "\n");
}
}
if (insns_p) {
for (bb_insn_t bb_insn = DLIST_HEAD (bb_insn_t, bb->bb_insns); bb_insn != NULL;
bb_insn = DLIST_NEXT (bb_insn_t, bb_insn))
print_bb_insn (ctx, bb_insn, TRUE);
fprintf (debug_file, "\n");
}
}
}
static void print_loop_subtree (MIR_context_t ctx, loop_node_t root, int level) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
for (int i = 0; i < 2 * level + 2; i++) fprintf (debug_file, " ");
if (root->bb != NULL) {
gen_assert (DLIST_HEAD (loop_node_t, root->children) == NULL);
fprintf (debug_file, "BB%-3lu\n", (unsigned long) root->bb->index);
return;
}
fprintf (debug_file, "Loop%-3lu\n", (unsigned long) root->index);
for (loop_node_t node = DLIST_HEAD (loop_node_t, root->children); node != NULL;
node = DLIST_NEXT (loop_node_t, node))
print_loop_subtree (ctx, node, level + 1);
}
static void print_loop_tree (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
fprintf (debug_file, "Loop Tree:\n");
print_loop_subtree (ctx, curr_cfg->root_loop_node, 0);
}
#endif
static mv_t get_free_move (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
mv_t mv;
if ((mv = DLIST_HEAD (mv_t, curr_cfg->free_moves)) != NULL)
DLIST_REMOVE (mv_t, curr_cfg->free_moves, mv);
else
mv = gen_malloc (ctx, sizeof (struct mv));
DLIST_APPEND (mv_t, curr_cfg->used_moves, mv);
return mv;
}
static void free_move (MIR_context_t ctx, mv_t mv) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
DLIST_REMOVE (mv_t, curr_cfg->used_moves, mv);
DLIST_APPEND (mv_t, curr_cfg->free_moves, mv);
}
static void build_func_cfg (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_insn_t insn, next_insn;
bb_insn_t bb_insn, label_bb_insn;
size_t i, nops;
MIR_op_t *op;
MIR_var_t var;
bb_t bb, prev_bb, entry_bb, exit_bb;
DLIST_INIT (bb_t, curr_cfg->bbs);
DLIST_INIT (mv_t, curr_cfg->used_moves);
DLIST_INIT (mv_t, curr_cfg->free_moves);
curr_cfg->max_reg = 0;
curr_cfg->min_reg = 0;
curr_cfg->root_loop_node = NULL;
curr_bb_index = 0;
for (i = 0; i < VARR_LENGTH (MIR_var_t, curr_func_item->u.func->vars); i++) {
var = VARR_GET (MIR_var_t, curr_func_item->u.func->vars, i);
update_min_max_reg (ctx, MIR_reg (ctx, var.name, curr_func_item->u.func));
}
entry_bb = create_bb (ctx, NULL);
add_bb (ctx, entry_bb);
exit_bb = create_bb (ctx, NULL);
add_bb (ctx, exit_bb);
insn = DLIST_HEAD (MIR_insn_t, curr_func_item->u.func->insns);
if (insn != NULL) {
bb = create_bb (ctx, NULL);
add_bb (ctx, bb);
if (insn->code == MIR_LABEL) { /* Create one more BB. First BB will be empty. */
prev_bb = bb;
bb = create_bb (ctx, NULL);
add_bb (ctx, bb);
create_edge (ctx, prev_bb, bb);
}
}
for (; insn != NULL; insn = next_insn) {
next_insn = DLIST_NEXT (MIR_insn_t, insn);
if (insn->data == NULL) add_new_bb_insn (ctx, insn, bb);
nops = MIR_insn_nops (ctx, insn);
if (next_insn != NULL
&& (MIR_branch_code_p (insn->code) || insn->code == MIR_RET || insn->code == MIR_SWITCH
|| next_insn->code == MIR_LABEL)) {
prev_bb = bb;
if (next_insn->code == MIR_LABEL && (label_bb_insn = next_insn->data) != NULL)
bb = label_bb_insn->bb;
else
bb = create_bb (ctx, next_insn);
add_bb (ctx, bb);
if (insn->code != MIR_JMP && insn->code != MIR_RET && insn->code != MIR_SWITCH)
create_edge (ctx, prev_bb, bb);
}
for (i = 0; i < nops; i++)
if ((op = &insn->ops[i])->mode == MIR_OP_LABEL) {
if ((label_bb_insn = op->u.label->data) == NULL) {
create_bb (ctx, op->u.label);
label_bb_insn = op->u.label->data;
}
bb_insn = insn->data;
create_edge (ctx, bb_insn->bb, label_bb_insn->bb);
} else if (op->mode == MIR_OP_REG) {
update_min_max_reg (ctx, op->u.reg);
} else if (op->mode == MIR_OP_MEM) {
update_min_max_reg (ctx, op->u.mem.base);
update_min_max_reg (ctx, op->u.mem.index);
}
}
/* Add additional edges with entry and exit */
for (bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb)) {
if (bb != entry_bb && DLIST_HEAD (in_edge_t, bb->in_edges) == NULL)
create_edge (ctx, entry_bb, bb);
if (bb != exit_bb && DLIST_HEAD (out_edge_t, bb->out_edges) == NULL)
create_edge (ctx, bb, exit_bb);
}
enumerate_bbs (ctx);
VARR_CREATE (reg_info_t, curr_cfg->breg_info, 128);
}
static void destroy_func_cfg (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_insn_t insn;
bb_insn_t bb_insn;
bb_t bb, next_bb;
mv_t mv, next_mv;
gen_assert (curr_func_item->item_type == MIR_func_item && curr_func_item->data != NULL);
for (insn = DLIST_HEAD (MIR_insn_t, curr_func_item->u.func->insns); insn != NULL;
insn = DLIST_NEXT (MIR_insn_t, insn)) {
bb_insn = insn->data;
gen_assert (bb_insn != NULL);
delete_bb_insn (bb_insn);
}
for (bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = next_bb) {
next_bb = DLIST_NEXT (bb_t, bb);
delete_bb (ctx, bb);
}
for (mv = DLIST_HEAD (mv_t, curr_cfg->used_moves); mv != NULL; mv = next_mv) {
next_mv = DLIST_NEXT (mv_t, mv);
free (mv);