diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt new file mode 100644 index 00000000000..34d737e1630 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/arizona.txt @@ -0,0 +1,240 @@ +Wolfson Arizona class audio SoCs + +These devices are audio SoCs with extensive digital capabilites and a range +of analogue I/O. + +Required properties: + + - compatible : One of the following chip-specific strings: + "wlf,wm5102" + "wlf,wm5110" + "wlf,wm8280" + "wlf,wm8281" + "wlf,wm8997" + "wlf,WM8998" + "wlf,wm1814" + "wlf,wm8285" + "wlf,wm1840" + "wlf,wm1831" + "cirrus,cs47l15" + "cirrus,cs47l24" + "cirrus,cs47l85" + "cirrus,cs47l35" + "cirrus,cs47l90" + "cirrus,cs47l91" + + - reg : I2C slave address when connected using I2C, chip select number when + using SPI. + + - interrupts : The interrupt line the /IRQ signal for the device is + connected to. + - interrupt-controller : Arizona class devices contain interrupt controllers + and may provide interrupt services to other devices. + - interrupt-parent : The parent interrupt controller. + - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as the trigger masks from + Documentation/devicetree/bindings/interrupts.txt + + - gpio-controller : Indicates this device is a GPIO controller. + - #gpio-cells : Must be 2. The first cell is the pin number and the + second cell is used to specify optional parameters (currently unused). + + - AVDD-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply (wm5102, wm5110), + DBVDD4-supply (wm8285), CPVDD-supply, SPKVDDL-supply (wm5102, wm5110), + SPKVDDR-supply (wm5102, wm5110), + SPKVDD-supply (wm8997, cs47l15, cs47l24, cs47l35) : + Power supplies for the device, as covered in + Documentation/devicetree/bindings/regulator/regulator.txt + +Optional properties: + + - wlf,reset : GPIO specifier for the GPIO controlling /RESET + - wlf,ldoena : GPIO specifier for the GPIO controlling LDOENA + - wlf,clk32k-src : set input source for codec 32kHz clock. + 0 = default, 1 = MCLK1, 2 = MCLK2, 3 = None + + - wlf,micd-detect-debounce : Additional software microphone detection + debounce specified in milliseconds + - wlf,micd-manual-debounce : Additional software button detection + debounce specified as a number + - wlf,micd-pol-gpio : GPIO specifier for the GPIO controlling the headset + polarity if one exists + - wlf,micd-bias-start-time : Time allowed for MICBIAS to startup prior to + performing microphone detection, specified as per the MICD_BIAS_STARTTIME + bits in the register MIC_DETECT_1 + - wlf,micd-rate : Delay between successive microphone detection measurements, + specified as per the MICD_RATE bits in the register MIC_DETECT_1 + - wlf,micd-dbtime : Microphone detection hardware debounce level, specified + as per the MICD_DBTIME bits in the register MIC_DETECT_1 + - wlf,micd-timeout : Timeout for microphone detection, specified in + milliseconds + - wlf,micd-force-micbias : Force MICBIAS continuously on during microphone + detection and button detection + - wlf,micd-force-micbias-initial : Force MICBIAS continuously on during + microphone detection + - wlf,micd-software-compare : Use a software comparison to determine mic + presence + - wlf,use-jd-gpio : Use GPIO input alongwith JD1 for dual jack detection. For + later arizona chips which have JD1 and JD2, setting this property will use + both JD1 and JD2 for dual jack detect and does not require an additional + GPIO + - wlf,usr-jd-gpio-nopull : Internal pull on GPIO is disabled when used for + jack detection. + - wlf,gpsw : Settings for the general purpose switch, set as per the + SW1_MODE bits in the GP Switch 1 register + - wlf,init-mic-delay : Adds a delay in milliseconds between jack detection + and beginning ramp of MICBIAS. + - wlf,fixed-hpdet-imp : Do not perform any headphone detection, just use + the fixed value specified here as the headphone impedance. + - wlf,hpdet-short-circuit-imp : Specifies the maximum impedance in ohms + that will be considered as a short circuit + - wlf,hpdet-channel : When this property is set then right channel is used + for headphone impedance measurement else the left headphone channel is + used + - wlf,micd-clamp-mode : Specifies the logic of the micdetect clamp block + - wlf,hpd-left-pins : (cs47l15, cs47l90, cs47l91) a 2 cell long field where + the first cell represents the pin that needs to be unclamped when measuring + headphone left channel impedance as per the HPD_OUT_SEL field of + HEADPHONE_DETECT_0 register and the second pin represents the impedance + sense pin as per the HPD_SENSE_SEL field of HEADPHONE_DETECT_0 register + - wlf,hpd-right-pins : See wlf,hpd-left-pins which is for left headphone + channel and this field is similar but for right headphone channel + - wlf,micd-ranges : Microphone detection level and key configuration, this + field can be of variable length but should always be a multiple of 2 cells + long, each two cell group represents one button configuration + The first cell is the maximum impedance for this button in ohms + The second cell the key that should be reported to the input layer + - wlf,micd-configs : Headset polarity configurations, the field can be of + variable length. But is should always be a multiple of + 4 cells long for (cs47l15, cs47l90, cs47l91) + 3 cells long for other Arizona chips + Each two cell group represents one polarity configration + For cs47l15, cs47l90, cs47l91 the first cell is the + accessory detection source as per the MICD_SENSE_SEL field of + MIC_DETECT_1_CONTROL_0 regiser and for other Arizona chips its the accessory + detection source as per the ACCDET_SRC bits in the ACCESSORY_DETECT_MODE_1 register + For cs47l15, cs47l90, cs47l91 the second cell is the accessory + detection ground as per the MICD_GND_SEL field of MIC_DETECT_1_CONTROL_0 regiser + and for other Arizona chips the second cell represents the MICBIAS to be used as + per the MICD_BIAS_SRC bits in the MIC_DETECT_1 register + For cs47l15, cs47l90, cs47l91 the third cell represents + the MICBIAS to be used as per the MICD_BIAS_SRC bits in the MIC_DETECT_1_CONTROL_1 + register and for other Arizona chips the third cell represents the value of the + micd-pol-gpio pin, a non-zero value indicates this should be on + For cs47l15, cs47l90, cs47l91 the fourth cell represents + the value of the micd-pol-gpio pin, a non-zero value indicates this should be on + and for other Arizona chips there are only three cells and fourth cell should + not be specified + - wlf,micbias1 : Configuration for the micbias regulator, number of cells + here will depend on the arizona chip and will be 4 + n (number of + children micbiases). For Marley (cs47l35) n is 2, for cs47l15 n is 3, + for Moon (cs47l90, cs47l91) n is 4 and for other arizona chips n is 1. + The first cell is the output voltage in millivolts + The second cell a non-zero value indicates an external capacitor is fitted + Starting from third cell the next n cells with a non-zero value indicates + the micbias (or children micbiases if n > 1) should be actively discharged + In the (3 + n)'th cell a non-zero value indicates that the micbias should be + brought up slowly to reduce pops + In the (4 + n)'th cell a non-zero value indicates the micbias should be bypassed + and simply output MICVDD + - wlf,micbias2 : See wlf,micbias1 + - wlf,micbias3 : See wlf,micbias1 + - wlf,micbias4 : See wlf,micbias1 + + - wlf,hs-mic: Specify an input to mute during headset button presses and + jack removal: 1 - IN1L, 2 - IN1R, ..., n - IN[n]R + + - wlf,dmic-ref : DMIC reference for each input, must contain four cells if + specified. 0 indicates MICVDD and is the default, 1,2,3 indicate the + respective MICBIAS. + + - wlf,inmode : Input mode for each input, must contain four cells if + specified. 0 indicates Differential, 1 indicates Single Ended and 2 + indicates a digital microphone. + For most codecs the entries map to + wm8998: entries are for + cs47l85, wm8285, cs47l90, cs47l91: entries are for + cs47l15, cs47l35: entries are for + + - wlf,dmic-clksrc : (cs47l15, cs47l90, cs47l91) DMIC clock source for each + input. A value of 0 will source DMIC from internally generated clock within + the ADC subsystem and a value of 1 will source DMIC and External digital + speakers with same clock + + - wlf,gpio-defaults : A list of GPIO configuration register values. Defines + for the appropriate values can found in . If + absent, no configuration of these registers is performed. If any entry has + a value that is out of range for a 16 bit register then the chip default + will be used. + + - wlf,max-channels-clocked : The maximum number of channels to be clocked on + each AIF, useful for I2S systems with multiple data lines being mastered. + Specify one cell for each AIF, specify zero for AIFs that should be handled + normally. + + - wlf,wm5102t-output-pwr : Output power setting (WM5102T only) + + - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if + they are being externally supplied. As covered in + Documentation/devicetree/bindings/regulator/regulator.txt + +Optional subnodes: + - ldo1 : Initial data for the LDO1 regulator, as covered in + Documentation/devicetree/bindings/regulator/regulator.txt + - micvdd : Initial data for the MICVDD regulator, as covered in + Documentation/devicetree/bindings/regulator/regulator.txt + +Example: + +codec: wm5102@1a { + compatible = "wlf,wm5102"; + reg = <0x1a>; + interrupts = <347>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + + gpio-controller; + #gpio-cells = <2>; + + wlf,micd-detect-debounce = <10>; + wlf,micd-bias-start-time = <0x1>; + wlf,micd-rate = <0x1>; + wlf,micd-dbtime = <0x1>; + wlf,micd-timeout = <10>; + wlf,micd-force-micbias; + wlf,micd-ranges = < + 11 0x100 + 28 0x101 + 54 0x102 + 100 0x103 + 186 0x104 + 430 0x105 + >; + wlf,micd-configs = < + 0x1 1 0 + 0x0 2 1 + >; + wlf,fixed-hpdet-imp = <8>; + + wlf,micbias2 = <2600 0 1 1 0>; + wlf,init-mic-delay = <10>; + wlf,micd-clamp-mode = <0xb>; + + wlf,dmic-ref = <0 0 1 0>; + wlf,inmode = <0 0 2 0>; + + wlf,gpsw = <0x3>; + + wlf,gpio-defaults = < + ARIZONA_GP_FN_TXLRCLK + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + >; + + wlf,max-channels-clocked = <2 0 0>; +}; diff --git a/Documentation/sound/alsa/soc/wolfson-arizona.txt b/Documentation/sound/alsa/soc/wolfson-arizona.txt new file mode 100644 index 00000000000..f8195db8642 --- /dev/null +++ b/Documentation/sound/alsa/soc/wolfson-arizona.txt @@ -0,0 +1,195 @@ +This document lists the features of the Cirrus Logic / Wolfson Microelectronics +'Arizona' class SmartCodecs that are supported by the kernel drivers. +Note that some features are covered by other classes of driver (extcon, +regulator, etc.), the list below shows the full set of features related +to sound: + +'-' means not relevant for that audio hub model + + WM8280 +Feature WM8997 WM8998 WM5102 WM8281 CS47L24 CS47L85 CS47L35 +---------------------------------------------------------------------------------------------- +32-bit samples Y Y Y Y Y Y Y +24-bit samples Y Y Y Y Y Y Y +192kHz sample rate Y Y Y Y Y Y Y +Routing controlled via ALSA controls Y Y Y Y Y Y Y +Volume control on all mixer inputs Y Y Y Y Y Y Y +Volume control on all outputs Y Y Y Y Y Y Y +Mute control on all outputs Y Y Y Y Y Y Y +Output DRE control - Y Y Y - Y Y +Output OSR control Y - Y Y Y Y N +Input ramp control Y Y Y Y Y Y Y +Output ramp control Y Y Y Y Y Y Y +Route any audio input to any mixer input Y Y Y Y Y Y Y +Route internal signals to mixer inputs Y Y Y Y Y Y Y +Route audio path through ISRC Y Y Y Y Y Y Y +Route audio path through ASRC - Y Y Y Y Y - +Route audio path through EQs Y Y Y Y Y Y Y +Route audio path through LHPFs Y Y Y Y Y Y Y +Route audio path through DRCs Y Y Y Y Y Y Y +Route audio path through ADSP cores - - Y Y Y Y Y +Set EQ coefficient through ALSA controls Y Y Y Y Y Y Y +Set LHPF coeffs through ALSA controls Y Y Y Y Y Y Y +Set DRC coefficient through ALSA controls Y Y Y Y Y Y Y +Set Noise Gates through ALSA controls Y Y Y Y Y Y Y +Config inputs analogue/digital mode [note 1] Y Y Y Y - Y Y +Input HPF control - Y - Y Y Y Y +Input mux controls [note 8] - Y - - - Y Y +Config analogue inputs as single-ended + or differential [note 1] Y Y Y Y - Y Y +Host I2S routing to any AIF Y Y Y Y Y Y Y +I2S TDM (multi-channel) [note 2] Y Y Y Y Y Y Y +Configure TDM active slots [note 2] Y Y Y Y Y Y Y +Configure TDM slot size [note 2] Y Y Y Y Y Y Y +AEC loopback control Y Y Y Y Y Y Y +ANC block control - - - Y - Y - +Select firmware by ALSA control [note 6] - - Y Y Y Y Y +Load ADSP firmware via DAPM power-up - - Y Y Y Y Y +Load tuning data (.bin) with firmware - - Y Y Y Y Y +Expose firmware controls via ALSA - - Y Y Y Y Y +Set sample-rate domain frequencies [note 4] Y Y Y Y Y Y Y +Auto sample-rate detection N N N N N N N +Codec control over SPI - - Y Y Y Y Y +Codec control over I2C Y Y Y Y - Y Y +DAPM-based power up/down Y Y Y Y Y Y Y +Jack insert detection Y Y Y Y - Y Y +Headset mic detection Y Y Y Y - Y Y +Headset button detection Y Y Y Y - Y Y +Headphone speaker impedance detection Y Y Y Y - Y Y +Codec internal LDOVDD regulator control Y Y Y Y - Y - +Support for external DCVDD regulator Y Y Y Y Y Y Y +Build as loadable module Y Y Y Y Y Y Y +Configure via pdata Y Y Y Y Y Y Y +Configure via device tree [note 7] Y Y Y Y Y Y Y +Configure via ACPI N N N N N N N +Configure SYSCLK rate [note 5] Y Y Y Y Y Y Y +Configure ASYNCCLK rate [note 5] Y Y Y Y Y Y - +Configure analogue mic bias [note 1] Y Y Y Y - Y Y +Configure mapping of headset button + resistance to key event [note 1] Y Y Y Y - Y Y +Configure available firmwares [note 3] - - Y Y Y Y Y +Support SoundClear Control - - N Y Y Y Y + +Notes: +1. Integration-time configuration. Not possible to change at runtime +2. TDM is only possible if host I2S controller and I2S driver support TDM + The set_tdm_slot() function is implemented to enable configuration of the + slot size and which slots the codec will use. Codec channels are mapped in + ascending order to the active slots - for example if the active TX slots in + the I2S frame are 0, 1, and 7 then they will be mapped + 0->AIFTX1 1->AIFTX2 7->AIFTX3 +3. Default firmware list can be overidden by device tree +4. Limited control of domain 2/3 frequency +5. Configured in ASoC machine driver +6. Firmware can be set by host but cannot be changed while ADSP is powered-up, + it must be removed from an active path to power-down and the new + firmware will be loaded when it is next powered-up as part of an + active path +7. Configuration from device tree is work-in-progress so there may be some + pdata settings that have not yet been migrated to device tree +8. See below for a description of the input mux routing. + + +INPUT MUXES +=========== +Some SmartCodecs have input paths with input muxes to select between two +possible external input sources for that path. + +For example on the WM8998: + - The IN1 path can be selected between IN1A or IN1B pins. The left and right + channels have separate mux controls + - The IN2 path can be selected between IN2A or IN2B and is mono + +A diagram of the route through the input muxes on the WM8998 is shown below +(the other SmartCodecs with input muxes are similar): + +Input pin ALSA control Internal signal path +------------------------------------------------------- + + +------------+ +IN1AL ---> "A" | | + | "IN1L Mux" | --> IN1L +IN1BL ---> "B" | | + +------------+ + + +------------+ +IN1AR ---> "A" | | + | "IN1R Mux" | --> IN1R +IN1BR ---> "B" | | + +------------+ + + +------------+ +IN2A ---> "A" | | + | "IN2 Mux" | --> IN2L +IN2B ---> "B" | | + +------------+ + + +WM8998 input muxes +------------------ +IN1A and IN2A can be set as digital. IN1B and IN2B are analogue only. + +It is important to note that although the left and right paths of IN1 have +separate mux controls, these are only separate for analogue paths. The setting +of digital/analogue applies jointly to both channels of IN1. Because of this, +if IN1A is digital _both_ the left and right mux are ganged together and +changing the mux on one channel will automatically change the other. + +The input mode pdata for WM8998 is defined as: + + pdata affects legal values behaviour + inmode[0] IN1 ARIZONA_INMODE_DIFF (0) IN1A and IN1B analogue differential + ARIZONA_INMODE_SE (1) IN1A and IN1B analogue single-ended + ARIZONA_INMODE_DMIC (2) IN1A digital, IN1B analogue differential + ARIZONA_INMODE_DMIC | + ARIZONA_INMODE_SE (3) IN1A digital, IN1B analogue single-ended + + inmode[1] IN2 ARIZONA_INMODE_DIFF (0) IN2A and IN2B analogue differential + ARIZONA_INMODE_SE (1) IN2A and IN2B analogue single-ended + ARIZONA_INMODE_DMIC (2) IN2A digital, IN2B analogue differential + ARIZONA_INMODE_DMIC | + ARIZONA_INMODE_SE (3) IN2A digital, IN2B analogue single-ended + +How firmwares are loaded +======================== +The driver exposes an ALSA control to set the firmware for each ADSP on the +codec. These are named: + + DSP1 Firmware + DSP2 Firmware + ... etc. + +The control is an enumeration of the available firmwares by function. It does +not directly set the actual filename of the firmware to be loaded. The mapping +between control values and actual firmware filename can be found in the file +sound/soc/codecs/wm_adsp.c + +Setting this control tells the driver what firmware to load WHEN THE ADSP IS +NEXT POWERED UP. Setting the control does not force the firmware to be loaded +immediately, nor does it reboot the ADSP if it is currently running a different +firmware. + +To load a firmware, or to reboot the ADSP with different firmware you must: + - Disconnect the ADSP from any active audio path so that it will be powered-down + - Set the firmware control to the firmware you want to load + - Connect the ADSP to an active audio path so it will be powered-up + +Firmware files can have an associated file called a "bin file". This has the +same name as the firmware file, but with the extension .bin, and goes in the +same directory as the firmware file. The bin file contains settings to be +patched in the ADSP memory after the firmware has been loaded. When the driver +loads a firmware it will look for a bin file and if found will apply the patches +from that bin file. + +The purpose of the bin file is to allow tuning data to be applied to the firmware +without the need to rebuild the firmware to include this data. For example, +some audio algorithms must be tuned to the acoustic properties of the enclosure +the microphones or speakers are in - it would be impractical to build a new +firmware for each device with its unique parameters; instead the device is tuned +and the tuning data is put into the bin file. + +The bin file is not intended for setting parameters that are runtime-modifiable, +such as volume controls, since the bin file is a one-shot set of parameters +that are patched when the firmware is loaded. Runtime modifiable controls should +be exposed by the firmware as such and the driver will create ALSA controls for +them. diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index 0c4c9a12a45..154876a254a 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -130,7 +130,7 @@ struct regmap { unsigned long *cache_present; unsigned int cache_present_nbits; - struct reg_default *patch; + struct reg_sequence *patch; int patch_regs; /* if set, converts bulk rw to single rw */ @@ -224,7 +224,7 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg, const void *val, size_t val_len, bool async); int _regmap_raw_multi_reg_write(struct regmap *map, - const struct reg_default *regs, + const struct reg_sequence *regs, size_t num_regs); void regmap_async_complete_cb(struct regmap_async *async, int ret); diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 91de12fe279..90a16a480a6 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -613,10 +613,10 @@ static int regcache_sync_block_raw_multi_reg(struct regmap *map, void *block, unsigned int i, val; unsigned int regtmp = 0; int ret = 0; - struct reg_default *regs; + struct reg_sequence *regs; size_t num_regs = ((end - start) + 1); - regs = kcalloc(num_regs, sizeof(struct reg_default), GFP_KERNEL); + regs = kcalloc(num_regs, sizeof(struct reg_sequence), GFP_KERNEL); if (!regs) return -ENOMEM; diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c index 0c3ceaa8ff0..d8ef007c4d2 100644 --- a/drivers/base/regmap/regmap-debugfs.c +++ b/drivers/base/regmap/regmap-debugfs.c @@ -144,7 +144,7 @@ static unsigned int regmap_debugfs_get_dump_start(struct regmap *map, reg_offset = fpos_offset / map->debugfs_tot_len; *pos = c->min + (reg_offset * map->debugfs_tot_len); mutex_unlock(&map->cache_lock); - return c->base_reg + reg_offset; + return c->base_reg + (reg_offset * map->reg_stride); } *pos = c->max; diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index aadf39bffa0..586b361f045 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -17,6 +17,7 @@ #include #include #include +#include #define CREATE_TRACE_POINTS #include @@ -1328,7 +1329,7 @@ EXPORT_SYMBOL_GPL(regmap_bulk_write); * relative. The page register has been written if that was necessary. */ int _regmap_raw_multi_reg_write(struct regmap *map, - const struct reg_default *regs, + const struct reg_sequence *regs, size_t num_regs) { int ret; @@ -1384,17 +1385,19 @@ static unsigned int _regmap_register_page(struct regmap *map, } static int _regmap_range_multi_paged_reg_write(struct regmap *map, - struct reg_default *regs, + struct reg_sequence *regs, size_t num_regs) { int ret; int i, n; - struct reg_default *base; + struct reg_sequence *base; unsigned int this_page; + unsigned int page_change = 0; /* * the set of registers are not neccessarily in order, but * since the order of write must be preserved this algorithm - * chops the set each time the page changes + * chops the set each time the page changes. This also applies + * if there is a delay required at any point in the sequence. */ base = regs; for (i = 0, n = 0; i < num_regs; i++, n++) { @@ -1410,15 +1413,42 @@ static int _regmap_range_multi_paged_reg_write(struct regmap *map, this_page = win_page; if (win_page != this_page) { this_page = win_page; - ret = _regmap_raw_multi_reg_write(map, base, n); - if (ret != 0) - return ret; - base += n; - n = 0; + page_change = 1; } - ret = _regmap_select_page(map, &base[n].reg, range, 1); + } + + /* If we have both a page change and a delay make sure to + * write the regs and apply the delay before we change the + * page. + */ + + if (page_change || regs[i].delay_us) { + /* For situations where the first write requires + * a delay we need to make sure we don't call + * raw_multi_reg_write with n=0 + * This can't occur with page breaks as we + * never write on the first iteration + */ + if (regs[i].delay_us && i == 0) + n = 1; + ret = _regmap_raw_multi_reg_write(map, base, n); if (ret != 0) return ret; + + if (regs[i].delay_us) + udelay(regs[i].delay_us); + + base += n; + n = 0; + if (page_change) { + ret = _regmap_select_page(map, + &base[n].reg, + range, 1); + if (ret != 0) + return ret; + + page_change = 0; + } } } if (n > 0) @@ -1428,7 +1458,7 @@ static int _regmap_range_multi_paged_reg_write(struct regmap *map, static int _regmap_multi_reg_write(struct regmap *map, - const struct reg_default *regs, + const struct reg_sequence *regs, size_t num_regs) { int i; @@ -1439,6 +1469,9 @@ static int _regmap_multi_reg_write(struct regmap *map, ret = _regmap_write(map, regs[i].reg, regs[i].def); if (ret != 0) return ret; + + if (regs[i].delay_us) + udelay(regs[i].delay_us); } return 0; } @@ -1482,10 +1515,13 @@ static int _regmap_multi_reg_write(struct regmap *map, unsigned int reg = regs[i].reg; struct regmap_range_node *range; + /* Coalesce all the writes between a page break or a delay + * in a sequence + */ range = _regmap_range_lookup(map, reg); - if (range) { - size_t len = sizeof(struct reg_default)*num_regs; - struct reg_default *base = kmemdup(regs, len, + if (range || regs[i].delay_us) { + size_t len = sizeof(struct reg_sequence)*num_regs; + struct reg_sequence *base = kmemdup(regs, len, GFP_KERNEL); if (!base) return -ENOMEM; @@ -1518,7 +1554,7 @@ static int _regmap_multi_reg_write(struct regmap *map, * A value of zero will be returned on success, a negative errno will be * returned in error cases. */ -int regmap_multi_reg_write(struct regmap *map, const struct reg_default *regs, +int regmap_multi_reg_write(struct regmap *map, const struct reg_sequence *regs, int num_regs) { int ret; @@ -1551,7 +1587,7 @@ EXPORT_SYMBOL(regmap_multi_reg_write); * be returned in error cases. */ int regmap_multi_reg_write_bypassed(struct regmap *map, - const struct reg_default *regs, + const struct reg_sequence *regs, int num_regs) { int ret; @@ -2002,7 +2038,7 @@ EXPORT_SYMBOL_GPL(regmap_async_complete); * corrections to be applied to the device defaults on startup, such * as the updates some vendors provide to undocumented registers. */ -int regmap_register_patch(struct regmap *map, const struct reg_default *regs, +int regmap_register_patch(struct regmap *map, const struct reg_sequence *regs, int num_regs) { int i, ret; @@ -2028,10 +2064,10 @@ int regmap_register_patch(struct regmap *map, const struct reg_default *regs, } } - map->patch = kcalloc(num_regs, sizeof(struct reg_default), GFP_KERNEL); + map->patch = kcalloc(num_regs, sizeof(struct reg_sequence), GFP_KERNEL); if (map->patch != NULL) { memcpy(map->patch, regs, - num_regs * sizeof(struct reg_default)); + num_regs * sizeof(struct reg_sequence)); map->patch_regs = num_regs; } else { ret = -ENOMEM; diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c index 7a1b4a7791b..6714aa2db22 100644 --- a/drivers/extcon/extcon-arizona.c +++ b/drivers/extcon/extcon-arizona.c @@ -1,7 +1,7 @@ /* * extcon-arizona.c - Extcon driver Wolfson Arizona devices * - * Copyright (C) 2012 Wolfson Microelectronics plc + * Copyright (C) 2012-2014 Wolfson Microelectronics plc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,6 +26,9 @@ #include #include #include +#include +#include +#include #include @@ -38,12 +41,35 @@ #define ARIZONA_ACCDET_MODE_MIC 0 #define ARIZONA_ACCDET_MODE_HPL 1 #define ARIZONA_ACCDET_MODE_HPR 2 +#define ARIZONA_ACCDET_MODE_HPM 4 +#define ARIZONA_ACCDET_MODE_ADC 7 + +#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4 +#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5 + +/* GP5 is analogous to JD2 (for systems without a dedicated second JD pin) */ +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5L 0x8 +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9 +#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb #define ARIZONA_HPDET_MAX 10000 #define HPDET_DEBOUNCE 500 #define DEFAULT_MICD_TIMEOUT 2000 +#define QUICK_HEADPHONE_MAX_OHM 3 +#define MICROPHONE_MIN_OHM 1257 +#define MICROPHONE_MAX_OHM 30000 + +#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \ + ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \ + ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \ + ARIZONA_MICD_LVL_7) + +#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7) + +#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8) + struct arizona_extcon_info { struct device *dev; struct arizona *arizona; @@ -80,14 +106,14 @@ struct arizona_extcon_info { bool detecting; int jack_flips; - int hpdet_ip; + int hpdet_ip_version; struct extcon_dev edev; }; static const struct arizona_micd_config micd_default_modes[] = { - { ARIZONA_ACCDET_SRC, 1 << ARIZONA_MICD_BIAS_SRC_SHIFT, 0 }, - { 0, 2 << ARIZONA_MICD_BIAS_SRC_SHIFT, 1 }, + { ARIZONA_ACCDET_SRC, 1, 0 }, + { 0, 2, 1 }, }; static const struct arizona_micd_range micd_default_ranges[] = { @@ -99,12 +125,15 @@ static const struct arizona_micd_range micd_default_ranges[] = { { .max = 430, .key = BTN_5 }, }; +/* The number of levels in arizona_micd_levels valid for button thresholds */ +#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64 + static const int arizona_micd_levels[] = { 3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46, 49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100, 105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245, 270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071, - 1257, + 1257, 30000, }; #define ARIZONA_CABLE_MECHANICAL 0 @@ -120,20 +149,56 @@ static const char *arizona_cable[] = { NULL, }; +static ssize_t arizona_extcon_show(struct device *dev, + struct device_attribute *attr, + char *buf); +DEVICE_ATTR(hp_impedance, S_IRUGO, arizona_extcon_show, NULL); + static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info); -static void arizona_extcon_do_magic(struct arizona_extcon_info *info, - unsigned int magic) +static void arizona_extcon_hp_clamp(struct arizona_extcon_info *info, + bool clamp) { struct arizona *arizona = info->arizona; + unsigned int mask, val = 0; + unsigned int ep_sel = 0; int ret; - mutex_lock(&arizona->dapm->card->dapm_mutex); + mutex_lock_nested(&arizona->dapm->card->dapm_mutex, + SND_SOC_DAPM_CLASS_RUNTIME); + - arizona->hpdet_magic = magic; + switch (arizona->type) { + case WM5102: + case WM8997: + mask = ARIZONA_RMV_SHRT_HP1L; + if (clamp) + val = ARIZONA_RMV_SHRT_HP1L; + break; + case WM8280: + case WM5110: + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) + val = ARIZONA_HP1L_SHRTO; + else + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + break; + case CS47L35: + /* check whether audio is routed to EPOUT, do not disable OUT1 + * in that case */ + regmap_read(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, &ep_sel); + ep_sel &= ARIZONA_EP_SEL_MASK; + /* fall through to next step to set common variables */ + default: + mask = 0; + break; + }; - /* Keep the HP output stages disabled while doing the magic */ - if (magic) { + arizona->hpdet_clamp = clamp; + + /* Keep the HP output stages disabled while doing the clamp */ + if (clamp && !ep_sel) { ret = regmap_update_bits(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT1L_ENA | @@ -144,20 +209,22 @@ static void arizona_extcon_do_magic(struct arizona_extcon_info *info, ret); } - ret = regmap_update_bits(arizona->regmap, 0x225, 0x4000, - magic); - if (ret != 0) - dev_warn(arizona->dev, "Failed to do magic: %d\n", - ret); + if (mask) { + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1L, + ARIZONA_RMV_SHRT_HP1L, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); - ret = regmap_update_bits(arizona->regmap, 0x226, 0x4000, - magic); - if (ret != 0) - dev_warn(arizona->dev, "Failed to do magic: %d\n", - ret); + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1R, + ARIZONA_RMV_SHRT_HP1R, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + } - /* Restore the desired state while not doing the magic */ - if (!magic) { + /* Restore the desired state while not doing the clamp */ + if (!clamp && !ep_sel) { ret = regmap_update_bits(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT1L_ENA | @@ -182,7 +249,8 @@ static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) info->micd_modes[mode].gpio); regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, ARIZONA_MICD_BIAS_SRC_MASK, - info->micd_modes[mode].bias); + info->micd_modes[mode].bias << + ARIZONA_MICD_BIAS_SRC_SHIFT); regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, ARIZONA_ACCDET_SRC, info->micd_modes[mode].src); @@ -193,15 +261,33 @@ static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) static const char *arizona_extcon_get_micbias(struct arizona_extcon_info *info) { - switch (info->micd_modes[0].bias >> ARIZONA_MICD_BIAS_SRC_SHIFT) { - case 1: - return "MICBIAS1"; - case 2: - return "MICBIAS2"; - case 3: - return "MICBIAS3"; + struct arizona *arizona = info->arizona; + + switch (arizona->type) { + case CS47L35: + switch (info->micd_modes[0].bias) { + case 1: + return "MICBIAS1A"; + case 2: + return "MICBIAS1B"; + case 3: + return "MICBIAS2A"; + default: + return "MICVDD"; + } default: - return "MICVDD"; + switch (info->micd_modes[0].bias) { + case 1: + return "MICBIAS1"; + case 2: + return "MICBIAS2"; + case 3: + return "MICBIAS3"; + case 4: + return "MICBIAS4"; + default: + return "MICVDD"; + } } } @@ -242,6 +328,7 @@ static void arizona_start_mic(struct arizona_extcon_info *info) struct arizona *arizona = info->arizona; bool change; int ret; + unsigned int mode; /* Microphone detection can't use idle mode */ pm_runtime_get(info->dev); @@ -267,9 +354,14 @@ static void arizona_start_mic(struct arizona_extcon_info *info) regmap_write(arizona->regmap, 0x80, 0x0); } + if (info->detecting && arizona->pdata.micd_software_compare) + mode = ARIZONA_ACCDET_MODE_ADC; + else + mode = ARIZONA_ACCDET_MODE_MIC; + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, - ARIZONA_ACCDET_MODE_MASK, ARIZONA_ACCDET_MODE_MIC); + ARIZONA_ACCDET_MODE_MASK, mode); arizona_extcon_pulse_micbias(info); @@ -326,14 +418,17 @@ static void arizona_stop_mic(struct arizona_extcon_info *info) } static struct { + unsigned int threshold; unsigned int factor_a; unsigned int factor_b; } arizona_hpdet_b_ranges[] = { - { 5528, 362464 }, - { 11084, 6186851 }, - { 11065, 65460395 }, + { 100, 5528, 362464 }, + { 169, 11084, 6186851 }, + { 169, 11065, 65460395 }, }; +#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb + static struct { int min; int max; @@ -357,7 +452,7 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info) return ret; } - switch (info->hpdet_ip) { + switch (info->hpdet_ip_version) { case 0: if (!(val & ARIZONA_HP_DONE)) { dev_err(arizona->dev, "HPDET did not complete: %x\n", @@ -388,7 +483,8 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info) >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 && - (val < 100 || val > 0x3fb)) { + (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX)) { range++; dev_dbg(arizona->dev, "Moving to HPDET range %d\n", range); @@ -401,7 +497,8 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info) } /* If we go out of range report top of range */ - if (val < 100 || val > 0x3fb) { + if (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX) { dev_dbg(arizona->dev, "Measurement out of range\n"); return ARIZONA_HPDET_MAX; } @@ -416,7 +513,7 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info) default: dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", - info->hpdet_ip); + info->hpdet_ip_version); case 2: if (!(val & ARIZONA_HP_DONE_B)) { dev_err(arizona->dev, "HPDET did not complete: %x\n", @@ -425,26 +522,15 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info) } val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to ohms, the value is in 0.5 ohm increments */ + val /= 2; regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, &range); range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; - /* Skip up or down a range? */ - if (range && (val < arizona_hpdet_c_ranges[range].min)) { - range--; - dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", - arizona_hpdet_c_ranges[range].min, - arizona_hpdet_c_ranges[range].max); - regmap_update_bits(arizona->regmap, - ARIZONA_HEADPHONE_DETECT_1, - ARIZONA_HP_IMPEDANCE_RANGE_MASK, - range << - ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); - return -EAGAIN; - } - + /* Skip up a range, or report? */ if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 && (val >= arizona_hpdet_c_ranges[range].max)) { range++; @@ -458,8 +544,15 @@ static int arizona_hpdet_read(struct arizona_extcon_info *info) ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); return -EAGAIN; } + + if (range && (val < arizona_hpdet_c_ranges[range].min)) { + dev_dbg(arizona->dev, "Reporting range boundary %d\n", + arizona_hpdet_c_ranges[range].min); + val = arizona_hpdet_c_ranges[range].min; + } } + arizona->hp_impedance = val; dev_dbg(arizona->dev, "HP impedance %d ohms\n", val); return val; } @@ -514,7 +607,7 @@ static int arizona_hpdet_do_id(struct arizona_extcon_info *info, int *reading, } /* - * If we measure the mic as + * If we measure the mic as high impedance */ if (!id_gpio || info->hpdet_res[1] > 50) { dev_dbg(arizona->dev, "Detected mic\n"); @@ -564,11 +657,10 @@ static irqreturn_t arizona_hpdet_irq(int irq, void *data) } ret = arizona_hpdet_read(info); - if (ret == -EAGAIN) { + if (ret == -EAGAIN) goto out; - } else if (ret < 0) { + else if (ret < 0) goto done; - } reading = ret; /* Reset back to starting range */ @@ -578,11 +670,10 @@ static irqreturn_t arizona_hpdet_irq(int irq, void *data) 0); ret = arizona_hpdet_do_id(info, &reading, &mic); - if (ret == -EAGAIN) { + if (ret == -EAGAIN) goto out; - } else if (ret < 0) { + else if (ret < 0) goto done; - } /* Report high impedence cables as line outputs */ if (reading >= 5000) @@ -595,9 +686,15 @@ static irqreturn_t arizona_hpdet_irq(int irq, void *data) dev_err(arizona->dev, "Failed to report HP/line: %d\n", ret); - arizona_extcon_do_magic(info, 0); - done: + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + arizona_extcon_hp_clamp(info, false); + if (id_gpio) gpio_set_value_cansleep(id_gpio, 0); @@ -641,7 +738,7 @@ static void arizona_identify_headphone(struct arizona_extcon_info *info) if (info->mic) arizona_stop_mic(info); - arizona_extcon_do_magic(info, 0x4000); + arizona_extcon_hp_clamp(info, true); ret = regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, @@ -667,9 +764,8 @@ static void arizona_identify_headphone(struct arizona_extcon_info *info) ARIZONA_ACCDET_MODE_MASK, ARIZONA_ACCDET_MODE_MIC); /* Just report headphone */ - ret = extcon_update_state(&info->edev, - 1 << ARIZONA_CABLE_HEADPHONE, - 1 << ARIZONA_CABLE_HEADPHONE); + ret = extcon_set_cable_state_(&info->edev, + ARIZONA_CABLE_HEADPHONE, true); if (ret != 0) dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); @@ -693,7 +789,7 @@ static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) info->hpdet_active = true; - arizona_extcon_do_magic(info, 0x4000); + arizona_extcon_hp_clamp(info, true); ret = regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, @@ -726,9 +822,8 @@ static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) ARIZONA_ACCDET_MODE_MASK, ARIZONA_ACCDET_MODE_MIC); /* Just report headphone */ - ret = extcon_update_state(&info->edev, - 1 << ARIZONA_CABLE_HEADPHONE, - 1 << ARIZONA_CABLE_HEADPHONE); + ret = extcon_set_cable_state_(&info->edev, + ARIZONA_CABLE_HEADPHONE, true); if (ret != 0) dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); @@ -738,8 +833,8 @@ static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) static void arizona_micd_timeout_work(struct work_struct *work) { struct arizona_extcon_info *info = container_of(work, - struct arizona_extcon_info, - micd_timeout_work.work); + struct arizona_extcon_info, + micd_timeout_work.work); mutex_lock(&info->lock); @@ -756,8 +851,8 @@ static void arizona_micd_timeout_work(struct work_struct *work) static void arizona_micd_detect(struct work_struct *work) { struct arizona_extcon_info *info = container_of(work, - struct arizona_extcon_info, - micd_detect_work.work); + struct arizona_extcon_info, + micd_detect_work.work); struct arizona *arizona = info->arizona; unsigned int val = 0, lvl; int ret, i, key; @@ -766,10 +861,55 @@ static void arizona_micd_detect(struct work_struct *work) mutex_lock(&info->lock); - for (i = 0; i < 10 && !(val & 0x7fc); i++) { + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_cable_state_(&info->edev, ARIZONA_CABLE_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + mutex_unlock(&info->lock); + return; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n"); + mutex_unlock(&info->lock); + return; + } + + if (info->detecting && arizona->pdata.micd_software_compare) { + /* Must disable MICD before we read the ADCVAL */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET_ADCVAL: %d\n", + ret); + mutex_unlock(&info->lock); + return; + } + + dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val); + + val &= ARIZONA_MICDET_ADCVAL_MASK; + if (val < ARRAY_SIZE(arizona_micd_levels)) + val = arizona_micd_levels[val]; + else + val = INT_MAX; + + if (val <= QUICK_HEADPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0; + else if (val <= MICROPHONE_MIN_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1; + else if (val <= MICROPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8; + else + val = ARIZONA_MICD_LVL_8; + } + + for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); if (ret != 0) { - dev_err(arizona->dev, "Failed to read MICDET: %d\n", ret); + dev_err(arizona->dev, + "Failed to read MICDET: %d\n", ret); mutex_unlock(&info->lock); return; } @@ -777,13 +917,14 @@ static void arizona_micd_detect(struct work_struct *work) dev_dbg(arizona->dev, "MICDET: %x\n", val); if (!(val & ARIZONA_MICD_VALID)) { - dev_warn(arizona->dev, "Microphone detection state invalid\n"); + dev_warn(arizona->dev, + "Microphone detection state invalid\n"); mutex_unlock(&info->lock); return; } } - if (i == 10 && !(val & 0x7fc)) { + if (i == 10 && !(val & MICD_LVL_0_TO_8)) { dev_err(arizona->dev, "Failed to get valid MICDET value\n"); mutex_unlock(&info->lock); return; @@ -792,24 +933,36 @@ static void arizona_micd_detect(struct work_struct *work) /* Due to jack detect this should never happen */ if (!(val & ARIZONA_MICD_STS)) { dev_warn(arizona->dev, "Detected open circuit\n"); + info->mic = arizona->pdata.micd_open_circuit_declare; + if (!info->mic) { + arizona_stop_mic(info); + } else { + /* Don't need to regulate for button detection */ + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to bypass MICVDD: %d\n", + ret); + } + } + arizona_identify_headphone(info); info->detecting = false; goto handled; } /* If we got a high impedence we should have a headset, report it. */ - if (info->detecting && (val & 0x400)) { + if (info->detecting && (val & ARIZONA_MICD_LVL_8)) { arizona_identify_headphone(info); - ret = extcon_update_state(&info->edev, - 1 << ARIZONA_CABLE_MICROPHONE, - 1 << ARIZONA_CABLE_MICROPHONE); + ret = extcon_set_cable_state_(&info->edev, + ARIZONA_CABLE_MICROPHONE, true); if (ret != 0) dev_err(arizona->dev, "Headset report failed: %d\n", ret); /* Don't need to regulate for button detection */ - ret = regulator_allow_bypass(info->micvdd, false); + ret = regulator_allow_bypass(info->micvdd, true); if (ret != 0) { dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", ret); @@ -826,7 +979,7 @@ static void arizona_micd_detect(struct work_struct *work) * plain headphones. If both polarities report a low * impedence then give up and report headphones. */ - if (info->detecting && (val & 0x3f8)) { + if (info->detecting && (val & MICD_LVL_1_TO_7)) { if (info->jack_flips >= info->micd_num_modes * 10) { dev_dbg(arizona->dev, "Detected HP/line\n"); arizona_identify_headphone(info); @@ -850,7 +1003,7 @@ static void arizona_micd_detect(struct work_struct *work) * If we're still detecting and we detect a short then we've * got a headphone. Otherwise it's a button press. */ - if (val & 0x3fc) { + if (val & MICD_LVL_0_TO_7) { if (info->mic) { dev_dbg(arizona->dev, "Mic button detected\n"); @@ -889,9 +1042,16 @@ static void arizona_micd_detect(struct work_struct *work) } handled: - if (info->detecting) + if (info->detecting) { + if (arizona->pdata.micd_software_compare) + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, + ARIZONA_MICD_ENA); + schedule_delayed_work(&info->micd_timeout_work, msecs_to_jiffies(info->micd_timeout)); + } pm_runtime_mark_last_busy(info->dev); mutex_unlock(&info->lock); @@ -923,8 +1083,8 @@ static irqreturn_t arizona_micdet(int irq, void *data) static void arizona_hpdet_work(struct work_struct *work) { struct arizona_extcon_info *info = container_of(work, - struct arizona_extcon_info, - hpdet_work.work); + struct arizona_extcon_info, + hpdet_work.work); mutex_lock(&info->lock); arizona_start_hpdet_acc_id(info); @@ -935,7 +1095,7 @@ static irqreturn_t arizona_jackdet(int irq, void *data) { struct arizona_extcon_info *info = data; struct arizona *arizona = info->arizona; - unsigned int val, present, mask; + unsigned int reg, val, present, mask; bool cancelled_hp, cancelled_mic; int ret, i; @@ -946,15 +1106,43 @@ static irqreturn_t arizona_jackdet(int irq, void *data) mutex_lock(&info->lock); - if (arizona->pdata.jd_gpio5) { - mask = ARIZONA_MICD_CLAMP_STS; - present = 0; - } else { - mask = ARIZONA_JD1_STS; - present = ARIZONA_JD1_STS; + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + if (arizona->pdata.jd_gpio5) { + mask = ARIZONA_MICD_CLAMP_STS; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + reg = ARIZONA_AOD_IRQ_RAW_STATUS; + break; + default: + if (arizona->pdata.jd_gpio5) { + mask = CLEARWATER_MICD_CLAMP_RISE_STS1; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + reg = CLEARWATER_IRQ1_RAW_STATUS_7; + break; } - ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val); + ret = regmap_read(arizona->regmap, reg, &val); if (ret != 0) { dev_err(arizona->dev, "Failed to read jackdet status: %d\n", ret); @@ -970,14 +1158,33 @@ static irqreturn_t arizona_jackdet(int irq, void *data) schedule_delayed_work(&info->hpdet_work, msecs_to_jiffies(HPDET_DEBOUNCE)); - if (cancelled_mic) + if (cancelled_mic) { + int micd_timeout = info->micd_timeout; + schedule_delayed_work(&info->micd_timeout_work, - msecs_to_jiffies(info->micd_timeout)); + msecs_to_jiffies(micd_timeout)); + } goto out; } info->last_jackdet = val; + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + reg = ARIZONA_JACK_DETECT_DEBOUNCE; + mask = ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB; + break; + default: + reg = CLEARWATER_INTERRUPT_DEBOUNCE_7; + mask = CLEARWATER_MICD_CLAMP_DB | CLEARWATER_JD1_DB; + break; + } + if (info->last_jackdet == present) { dev_dbg(arizona->dev, "Detected jack\n"); ret = extcon_set_cable_state_(&info->edev, @@ -992,15 +1199,16 @@ static irqreturn_t arizona_jackdet(int irq, void *data) info->mic = false; info->jack_flips = 0; + if (arizona->pdata.init_mic_delay) + msleep(arizona->pdata.init_mic_delay); + arizona_start_mic(info); } else { schedule_delayed_work(&info->hpdet_work, msecs_to_jiffies(HPDET_DEBOUNCE)); } - regmap_update_bits(arizona->regmap, - ARIZONA_JACK_DETECT_DEBOUNCE, - ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB, 0); + regmap_update_bits(arizona->regmap, reg, mask, 0); } else { dev_dbg(arizona->dev, "Detected jack removal\n"); @@ -1012,6 +1220,7 @@ static irqreturn_t arizona_jackdet(int irq, void *data) info->mic = false; info->hpdet_done = false; info->hpdet_retried = false; + arizona->hp_impedance = 0; for (i = 0; i < info->num_micd_ranges; i++) input_report_key(info->input, @@ -1023,10 +1232,7 @@ static irqreturn_t arizona_jackdet(int irq, void *data) dev_err(arizona->dev, "Removal report failed: %d\n", ret); - regmap_update_bits(arizona->regmap, - ARIZONA_JACK_DETECT_DEBOUNCE, - ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB, - ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB); + regmap_update_bits(arizona->regmap, reg, mask, mask); } if (arizona->pdata.micd_timeout) @@ -1034,14 +1240,25 @@ static irqreturn_t arizona_jackdet(int irq, void *data) else info->micd_timeout = DEFAULT_MICD_TIMEOUT; - /* Clear trig_sts to make sure DCVDD is not forced up */ - regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, - ARIZONA_MICD_CLAMP_FALL_TRIG_STS | - ARIZONA_MICD_CLAMP_RISE_TRIG_STS | - ARIZONA_JD1_FALL_TRIG_STS | - ARIZONA_JD1_RISE_TRIG_STS); - out: + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + /* Clear trig_sts to make sure DCVDD is not forced up */ + regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, + ARIZONA_MICD_CLAMP_FALL_TRIG_STS | + ARIZONA_MICD_CLAMP_RISE_TRIG_STS | + ARIZONA_JD1_FALL_TRIG_STS | + ARIZONA_JD1_RISE_TRIG_STS); + break; + default: + break; + } + mutex_unlock(&info->lock); pm_runtime_mark_last_busy(info->dev); @@ -1070,32 +1287,212 @@ static void arizona_micd_set_level(struct arizona *arizona, int index, regmap_update_bits(arizona->regmap, reg, mask, level); } +#ifdef CONFIG_OF +static int arizona_extcon_of_get_pdata(struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + + arizona_of_read_s32(arizona, "wlf,micd-detect-debounce", false, + &pdata->micd_detect_debounce); + + pdata->micd_pol_gpio = arizona_of_get_named_gpio(arizona, + "wlf,micd-pol-gpio", + false); + + arizona_of_read_s32(arizona, "wlf,micd-bias-start-time", false, + &pdata->micd_bias_start_time); + + arizona_of_read_s32(arizona, "wlf,micd-rate", false, + &pdata->micd_rate); + + arizona_of_read_s32(arizona, "wlf,micd-dbtime", false, + &pdata->micd_dbtime); + + arizona_of_read_s32(arizona, "wlf,micd-timeout", false, + &pdata->micd_timeout); + + pdata->micd_force_micbias = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-force-micbias"); + + pdata->micd_software_compare = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-software-compare"); + + pdata->micd_open_circuit_declare = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-open-circuit-declare"); + + pdata->jd_gpio5 = of_property_read_bool(arizona->dev->of_node, + "wlf,use-jd-gpio"); + + pdata->jd_gpio5_nopull = of_property_read_bool(arizona->dev->of_node, + "wlf,jd-gpio-nopull"); + + pdata->jd_invert = of_property_read_bool(arizona->dev->of_node, + "wlf,jd-invert"); + + arizona_of_read_u32(arizona, "wlf,gpsw", false, &pdata->gpsw); + + arizona_of_read_s32(arizona, "wlf,init-mic-delay", false, + &pdata->init_mic_delay); + + arizona_of_read_u32(arizona, "wlf,micd-clamp-mode", false, + &pdata->micd_clamp_mode); + + return 0; +} +#else +static inline int arizona_extcon_of_get_pdata(struct arizona *arizona) +{ + return 0; +} +#endif + +static ssize_t arizona_extcon_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + + return scnprintf(buf, PAGE_SIZE, "%d\n", info->arizona->hp_impedance); +} + +static void arizona_extcon_set_micd_clamp_mode(struct arizona *arizona) +{ + unsigned int clamp_ctrl_reg, clamp_ctrl_mask, clamp_ctrl_val; + unsigned int clamp_db_reg, clamp_db_mask, clamp_db_val; + int val; + + /* Set up the regs */ + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + case WM5110: + clamp_ctrl_reg = ARIZONA_MICD_CLAMP_CONTROL; + clamp_ctrl_mask = ARIZONA_MICD_CLAMP_MODE_MASK; + + clamp_db_reg = ARIZONA_JACK_DETECT_DEBOUNCE; + clamp_db_mask = ARIZONA_MICD_CLAMP_DB; + clamp_db_val = ARIZONA_MICD_CLAMP_DB; + break; + default: + clamp_ctrl_reg = CLEARWATER_MICD_CLAMP_CONTROL; + clamp_ctrl_mask = ARIZONA_MICD_CLAMP_MODE_MASK; + + clamp_db_reg = CLEARWATER_INTERRUPT_DEBOUNCE_7; + clamp_db_mask = CLEARWATER_MICD_CLAMP_DB; + clamp_db_val = CLEARWATER_MICD_CLAMP_DB; + + regmap_update_bits(arizona->regmap, + CLEARWATER_MICD_CLAMP_CONTROL, + 0x10, 0); + break; + } + + /* If the user has supplied a micd_clamp_mode, assume they know + * what they are doing and just write it out + */ + if (arizona->pdata.micd_clamp_mode) { + clamp_ctrl_val = arizona->pdata.micd_clamp_mode; + goto out; + } + + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + case WM5110: + if (arizona->pdata.jd_gpio5) { + /* Put the GPIO into input mode with optional pull */ + val = 0xc101; + if (arizona->pdata.jd_gpio5_nopull) + val &= ~ARIZONA_GPN_PU; + + regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, + val); + + if (arizona->pdata.jd_invert) + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDL_GP5H; + } else { + if (arizona->pdata.jd_invert) + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDL; + } + break; + default: + if (arizona->pdata.jd_gpio5) { + if (arizona->pdata.jd_invert) + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDL_GP5L; + } else { + if (arizona->pdata.jd_invert) + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDL; + } + break; + } + +out: + regmap_update_bits(arizona->regmap, + clamp_ctrl_reg, + clamp_ctrl_mask, + clamp_ctrl_val); + + regmap_update_bits(arizona->regmap, + clamp_db_reg, + clamp_db_mask, + clamp_db_val); +} + static int arizona_extcon_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); - struct arizona_pdata *pdata; + struct arizona_pdata *pdata = &arizona->pdata; struct arizona_extcon_info *info; - unsigned int val; + unsigned int reg, debounce_reg, debounce_val, analog_val; int jack_irq_fall, jack_irq_rise; int ret, mode, i, j; if (!arizona->dapm || !arizona->dapm->card) return -EPROBE_DEFER; - pdata = dev_get_platdata(arizona->dev); - info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); - if (!info) { - dev_err(&pdev->dev, "Failed to allocate memory\n"); - ret = -ENOMEM; - goto err; + if (!info) + return -ENOMEM; + + if (IS_ENABLED(CONFIG_OF)) { + if (!dev_get_platdata(arizona->dev)) { + ret = arizona_extcon_of_get_pdata(arizona); + if (ret < 0) + return ret; + } } - info->micvdd = devm_regulator_get(arizona->dev, "MICVDD"); + /* Set of_node to parent from the SPI device to allow + * location regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + info->micvdd = devm_regulator_get(&pdev->dev, "MICVDD"); if (IS_ERR(info->micvdd)) { ret = PTR_ERR(info->micvdd); dev_err(arizona->dev, "Failed to get MICVDD: %d\n", ret); - goto err; + return ret; } mutex_init(&info->lock); @@ -1115,11 +1512,27 @@ static int arizona_extcon_probe(struct platform_device *pdev) break; default: info->micd_clamp = true; - info->hpdet_ip = 1; + info->hpdet_ip_version = 1; break; } break; + case WM8280: + case WM5110: + switch (arizona->rev) { + case 0 ... 2: + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + } + break; + case CS47L35: + arizona->pdata.micd_force_micbias = true; + /* fall through to default case to set common properties */ default: + info->micd_clamp = true; + info->hpdet_ip_version = 2; break; } @@ -1130,7 +1543,7 @@ static int arizona_extcon_probe(struct platform_device *pdev) if (ret < 0) { dev_err(arizona->dev, "extcon_dev_register() failed: %d\n", ret); - goto err; + return ret; } info->input = devm_input_allocate_device(&pdev->dev); @@ -1142,7 +1555,6 @@ static int arizona_extcon_probe(struct platform_device *pdev) info->input->name = "Headset"; info->input->phys = "arizona/extcon"; - info->input->dev.parent = &pdev->dev; if (pdata->num_micd_configs) { info->micd_modes = pdata->micd_configs; @@ -1152,6 +1564,26 @@ static int arizona_extcon_probe(struct platform_device *pdev) info->micd_num_modes = ARRAY_SIZE(micd_default_modes); } + switch (arizona->type) { + case WM8997: + case WM5102: + case WM1814: + case WM8998: + case WM8280: + case WM5110: + reg = ARIZONA_GP_SWITCH_1; + break; + default: + reg = CLEARWATER_GP_SWITCH_1; + break; + } + + if (arizona->pdata.gpsw > 0) + regmap_update_bits(arizona->regmap, + reg, + ARIZONA_SW1_MODE_MASK, + arizona->pdata.gpsw); + if (arizona->pdata.micd_pol_gpio > 0) { if (info->micd_modes[0].gpio) mode = GPIOF_OUT_INIT_HIGH; @@ -1199,7 +1631,8 @@ static int arizona_extcon_probe(struct platform_device *pdev) arizona->pdata.micd_dbtime << ARIZONA_MICD_DBTIME_SHIFT); - BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) != 0x40); + BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) < + ARIZONA_NUM_MICD_BUTTON_LEVELS); if (arizona->pdata.num_micd_ranges) { info->micd_ranges = pdata->micd_ranges; @@ -1232,11 +1665,11 @@ static int arizona_extcon_probe(struct platform_device *pdev) /* Set up all the buttons the user specified */ for (i = 0; i < info->num_micd_ranges; i++) { - for (j = 0; j < ARRAY_SIZE(arizona_micd_levels); j++) + for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++) if (arizona_micd_levels[j] >= info->micd_ranges[i].max) break; - if (j == ARRAY_SIZE(arizona_micd_levels)) { + if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) { dev_err(arizona->dev, "Unsupported MICD level %d\n", info->micd_ranges[i].max); ret = -EINVAL; @@ -1263,30 +1696,8 @@ static int arizona_extcon_probe(struct platform_device *pdev) * If we have a clamp use it, activating in conjunction with * GPIO5 if that is connected for jack detect operation. */ - if (info->micd_clamp) { - if (arizona->pdata.jd_gpio5) { - /* Put the GPIO into input mode with optional pull */ - val = 0xc101; - if (arizona->pdata.jd_gpio5_nopull) - val &= ~ARIZONA_GPN_PU; - - regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, - val); - - regmap_update_bits(arizona->regmap, - ARIZONA_MICD_CLAMP_CONTROL, - ARIZONA_MICD_CLAMP_MODE_MASK, 0x9); - } else { - regmap_update_bits(arizona->regmap, - ARIZONA_MICD_CLAMP_CONTROL, - ARIZONA_MICD_CLAMP_MODE_MASK, 0x4); - } - - regmap_update_bits(arizona->regmap, - ARIZONA_JACK_DETECT_DEBOUNCE, - ARIZONA_MICD_CLAMP_DB, - ARIZONA_MICD_CLAMP_DB); - } + if (info->micd_clamp) + arizona_extcon_set_micd_clamp_mode(arizona); arizona_extcon_set_mode(info, 0); @@ -1345,11 +1756,34 @@ static int arizona_extcon_probe(struct platform_device *pdev) goto err_micdet; } - arizona_clk32k_enable(arizona); - regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_DEBOUNCE, - ARIZONA_JD1_DB, ARIZONA_JD1_DB); + switch (arizona->type) { + case WM8997: + case WM5102: + case WM1814: + case WM8998: + case WM8280: + case WM5110: + debounce_reg = ARIZONA_JACK_DETECT_DEBOUNCE; + debounce_val = ARIZONA_JD1_DB; + analog_val = ARIZONA_JD1_ENA; + break; + default: + debounce_reg = CLEARWATER_INTERRUPT_DEBOUNCE_7; + + if (arizona->pdata.jd_gpio5) { + debounce_val = CLEARWATER_JD1_DB | CLEARWATER_JD2_DB; + analog_val = ARIZONA_JD1_ENA | ARIZONA_JD2_ENA; + } else { + debounce_val = CLEARWATER_JD1_DB; + analog_val = ARIZONA_JD1_ENA; + } + break; + } + + regmap_update_bits(arizona->regmap, debounce_reg, + debounce_val, debounce_val); regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, - ARIZONA_JD1_ENA, ARIZONA_JD1_ENA); + analog_val, analog_val); ret = regulator_allow_bypass(info->micvdd, true); if (ret != 0) @@ -1364,6 +1798,12 @@ static int arizona_extcon_probe(struct platform_device *pdev) goto err_hpdet; } + ret = device_create_file(&pdev->dev, &dev_attr_hp_impedance); + if (ret != 0) + dev_err(&pdev->dev, + "Failed to create sysfs node for hp_impedance %d\n", + ret); + return 0; err_hpdet: @@ -1381,8 +1821,8 @@ static int arizona_extcon_probe(struct platform_device *pdev) err_input: err_register: pm_runtime_disable(&pdev->dev); - extcon_dev_unregister(&info->edev); -err: + extcon_dev_unregister(info->edev); + return ret; } @@ -1394,9 +1834,21 @@ static int arizona_extcon_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); - regmap_update_bits(arizona->regmap, - ARIZONA_MICD_CLAMP_CONTROL, - ARIZONA_MICD_CLAMP_MODE_MASK, 0); + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + case WM5110: + regmap_update_bits(arizona->regmap, ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + break; + default: + regmap_update_bits(arizona->regmap, CLEARWATER_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + break; + } if (arizona->pdata.jd_gpio5) { jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; @@ -1415,7 +1867,8 @@ static int arizona_extcon_remove(struct platform_device *pdev) cancel_delayed_work_sync(&info->hpdet_work); regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, ARIZONA_JD1_ENA, 0); - arizona_clk32k_disable(arizona); + + device_remove_file(&pdev->dev, &dev_attr_hp_impedance); extcon_dev_unregister(&info->edev); return 0; diff --git a/drivers/extcon/extcon-class.c b/drivers/extcon/extcon-class.c index 60adc04b056..2c7858339f6 100644 --- a/drivers/extcon/extcon-class.c +++ b/drivers/extcon/extcon-class.c @@ -470,7 +470,8 @@ int extcon_register_interest(struct extcon_specific_cable_nb *obj, if (!obj->edev) return -ENODEV; - obj->cable_index = extcon_find_cable_index(obj->edev, cable_name); + obj->cable_index = extcon_find_cable_index(obj->edev, + cable_name); if (obj->cable_index < 0) return obj->cable_index; @@ -478,7 +479,8 @@ int extcon_register_interest(struct extcon_specific_cable_nb *obj, obj->internal_nb.notifier_call = _call_per_cable; - return raw_notifier_chain_register(&obj->edev->nh, &obj->internal_nb); + return raw_notifier_chain_register(&obj->edev->nh, + &obj->internal_nb); } else { struct class_dev_iter iter; struct extcon_dev *extd; diff --git a/drivers/extcon/extcon-max77693.c b/drivers/extcon/extcon-max77693.c index 9966fc0a527..5ba0dda2b4b 100644 --- a/drivers/extcon/extcon-max77693.c +++ b/drivers/extcon/extcon-max77693.c @@ -189,14 +189,17 @@ enum max77693_muic_acc_type { /* The below accessories have same ADC value so ADCLow and ADC1K bit is used to separate specific accessory */ - MAX77693_MUIC_GND_USB_OTG = 0x100, /* ADC:0x0, VBVolot:0, ADCLow:0, ADC1K:0 */ - MAX77693_MUIC_GND_USB_OTG_VB = 0x104, /* ADC:0x0, VBVolot:1, ADCLow:0, ADC1K:0 */ - MAX77693_MUIC_GND_AV_CABLE_LOAD = 0x102,/* ADC:0x0, VBVolot:0, ADCLow:1, ADC1K:0 */ - MAX77693_MUIC_GND_MHL = 0x103, /* ADC:0x0, VBVolot:0, ADCLow:1, ADC1K:1 */ - MAX77693_MUIC_GND_MHL_VB = 0x107, /* ADC:0x0, VBVolot:1, ADCLow:1, ADC1K:1 */ + /* ADC|VBVolot|ADCLow|ADC1K| */ + MAX77693_MUIC_GND_USB_OTG = 0x100, /* 0x0| 0| 0| 0| */ + MAX77693_MUIC_GND_USB_OTG_VB = 0x104, /* 0x0| 1| 0| 0| */ + MAX77693_MUIC_GND_AV_CABLE_LOAD = 0x102,/* 0x0| 0| 1| 0| */ + MAX77693_MUIC_GND_MHL = 0x103, /* 0x0| 0| 1| 1| */ + MAX77693_MUIC_GND_MHL_VB = 0x107, /* 0x0| 1| 1| 1| */ }; -/* MAX77693 MUIC device support below list of accessories(external connector) */ +/* + * MAX77693 MUIC device support below list of accessories(external connector) + */ enum { EXTCON_CABLE_USB = 0, EXTCON_CABLE_USB_HOST, @@ -395,12 +398,12 @@ static int max77693_muic_get_cable_type(struct max77693_muic_info *info, vbvolt >>= STATUS2_VBVOLT_SHIFT; /** - * [0x1][VBVolt][ADCLow][ADC1K] - * [0x1 0 0 0 ] : USB_OTG - * [0x1 1 0 0 ] : USB_OTG_VB - * [0x1 0 1 0 ] : Audio Video Cable with load - * [0x1 0 1 1 ] : MHL without charging connector - * [0x1 1 1 1 ] : MHL with charging connector + * [0x1|VBVolt|ADCLow|ADC1K] + * [0x1| 0| 0| 0] USB_OTG + * [0x1| 1| 0| 0] USB_OTG_VB + * [0x1| 0| 1| 0] Audio Video cable with load + * [0x1| 0| 1| 1] MHL without charging cable + * [0x1| 1| 1| 1] MHL with charging cable */ cable_type = ((0x1 << 8) | (vbvolt << 2) @@ -723,11 +726,11 @@ static int max77693_muic_adc_handler(struct max77693_muic_info *info) if (ret < 0) return ret; break; - case MAX77693_MUIC_ADC_REMOTE_S3_BUTTON: /* DOCK_KEY_PREV */ - case MAX77693_MUIC_ADC_REMOTE_S7_BUTTON: /* DOCK_KEY_NEXT */ - case MAX77693_MUIC_ADC_REMOTE_S9_BUTTON: /* DOCK_VOL_DOWN */ - case MAX77693_MUIC_ADC_REMOTE_S10_BUTTON: /* DOCK_VOL_UP */ - case MAX77693_MUIC_ADC_REMOTE_S12_BUTTON: /* DOCK_KEY_PLAY_PAUSE */ + case MAX77693_MUIC_ADC_REMOTE_S3_BUTTON: /* DOCK_KEY_PREV */ + case MAX77693_MUIC_ADC_REMOTE_S7_BUTTON: /* DOCK_KEY_NEXT */ + case MAX77693_MUIC_ADC_REMOTE_S9_BUTTON: /* DOCK_VOL_DOWN */ + case MAX77693_MUIC_ADC_REMOTE_S10_BUTTON: /* DOCK_VOL_UP */ + case MAX77693_MUIC_ADC_REMOTE_S12_BUTTON: /* DOCK_KEY_PLAY_PAUSE */ /* * Button of DOCK device * - the Prev/Next/Volume Up/Volume Down/Play-Pause button @@ -815,19 +818,21 @@ static int max77693_muic_chg_handler(struct max77693_muic_info *info) case MAX77693_MUIC_GND_MHL_VB: /* * MHL cable with MHL_TA(USB/TA) cable - * - MHL cable include two port(HDMI line and separate micro- - * usb port. When the target connect MHL cable, extcon driver - * check whether MHL_TA(USB/TA) cable is connected. If MHL_TA - * cable is connected, extcon driver notify state to notifiee - * for charging battery. + * - MHL cable include two port(HDMI line and separate + * micro-usb port. When the target connect MHL cable, + * extcon driver check whether MHL_TA(USB/TA) cable is + * connected. If MHL_TA cable is connected, extcon + * driver notify state to notifiee for charging battery. * * Features of 'MHL_TA(USB/TA) with MHL cable' * - Support MHL - * - Support charging through micro-usb port without data connection + * - Support charging through micro-usb port without + * data connection */ extcon_set_cable_state(info->edev, "MHL_TA", attached); if (!cable_attached) - extcon_set_cable_state(info->edev, "MHL", cable_attached); + extcon_set_cable_state(info->edev, + "MHL", cable_attached); break; } @@ -839,47 +844,51 @@ static int max77693_muic_chg_handler(struct max77693_muic_info *info) case MAX77693_MUIC_ADC_AV_CABLE_NOLOAD: /* Dock-Audio */ /* * Dock-Audio device with USB/TA cable - * - Dock device include two port(Dock-Audio and micro-usb - * port). When the target connect Dock-Audio device, extcon - * driver check whether USB/TA cable is connected. If USB/TA - * cable is connected, extcon driver notify state to notifiee - * for charging battery. + * - Dock device include two port(Dock-Audio and micro- + * usb port). When the target connect Dock-Audio device, + * extcon driver check whether USB/TA cable is connected + * or not. If USB/TA cable is connected, extcon driver + * notify state to notifiee for charging battery. * * Features of 'USB/TA cable with Dock-Audio device' * - Support external output feature of audio. - * - Support charging through micro-usb port without data - * connection. + * - Support charging through micro-usb port without + * data connection. */ extcon_set_cable_state(info->edev, "USB", attached); if (!cable_attached) - extcon_set_cable_state(info->edev, "Dock-Audio", cable_attached); + extcon_set_cable_state(info->edev, "Dock-Audio", + cable_attached); break; case MAX77693_MUIC_ADC_RESERVED_ACC_3: /* Dock-Smart */ /* * Dock-Smart device with USB/TA cable * - Dock-Desk device include three type of cable which * are HDMI, USB for mouse/keyboard and micro-usb port - * for USB/TA cable. Dock-Smart device need always exteranl - * power supply(USB/TA cable through micro-usb cable). Dock- - * Smart device support screen output of target to separate - * monitor and mouse/keyboard for desktop mode. + * for USB/TA cable. Dock-Smart device need always + * exteranl power supply(USB/TA cable through micro-usb + * cable). Dock-Smart device support screen output of + * target to separate monitor and mouse/keyboard for + * desktop mode. * * Features of 'USB/TA cable with Dock-Smart device' * - Support MHL * - Support external output feature of audio - * - Support charging through micro-usb port without data - * connection if TA cable is connected to target. - * - Support charging and data connection through micro-usb port - * if USB cable is connected between target and host - * device. + * - Support charging through micro-usb port without + * data connection if TA cable is connected to target. + * - Support charging and data connection through micro- + * usb port if USB cable is connected between target + * and host device * - Support OTG device (Mouse/Keyboard) */ - ret = max77693_muic_set_path(info, info->path_usb, attached); + ret = max77693_muic_set_path(info, info->path_usb, + attached); if (ret < 0) return ret; - extcon_set_cable_state(info->edev, "Dock-Smart", attached); + extcon_set_cable_state(info->edev, "Dock-Smart", + attached); extcon_set_cable_state(info->edev, "MHL", attached); break; @@ -889,25 +898,28 @@ static int max77693_muic_chg_handler(struct max77693_muic_info *info) switch (chg_type) { case MAX77693_CHARGER_TYPE_NONE: /* - * When MHL(with USB/TA cable) or Dock-Audio with USB/TA cable - * is attached, muic device happen below two interrupt. - * - 'MAX77693_MUIC_IRQ_INT1_ADC' for detecting MHL/Dock-Audio. - * - 'MAX77693_MUIC_IRQ_INT2_CHGTYP' for detecting USB/TA cable - * connected to MHL or Dock-Audio. - * Always, happen eariler MAX77693_MUIC_IRQ_INT1_ADC interrupt - * than MAX77693_MUIC_IRQ_INT2_CHGTYP interrupt. + * When MHL(with USB/TA cable) or Dock-Audio with USB/TA + * cable is attached, muic device happen below two irq. + * - 'MAX77693_MUIC_IRQ_INT1_ADC' for detecting + * MHL/Dock-Audio. + * - 'MAX77693_MUIC_IRQ_INT2_CHGTYP' for detecting + * USB/TA cable connected to MHL or Dock-Audio. + * Always, happen eariler MAX77693_MUIC_IRQ_INT1_ADC + * irq than MAX77693_MUIC_IRQ_INT2_CHGTYP irq. * - * If user attach MHL (with USB/TA cable and immediately detach - * MHL with USB/TA cable before MAX77693_MUIC_IRQ_INT2_CHGTYP - * interrupt is happened, USB/TA cable remain connected state to - * target. But USB/TA cable isn't connected to target. The user - * be face with unusual action. So, driver should check this - * situation in spite of, that previous charger type is N/A. + * If user attach MHL (with USB/TA cable and immediately + * detach MHL with USB/TA cable before MAX77693_MUIC_IRQ + * _INT2_CHGTYP irq is happened, USB/TA cable remain + * connected state to target. But USB/TA cable isn't + * connected to target. The user be face with unusual + * action. So, driver should check this situation in + * spite of, that previous charger type is N/A. */ break; case MAX77693_CHARGER_TYPE_USB: /* Only USB cable, PATH:AP_USB */ - ret = max77693_muic_set_path(info, info->path_usb, attached); + ret = max77693_muic_set_path(info, info->path_usb, + attached); if (ret < 0) return ret; diff --git a/drivers/extcon/extcon-max8997.c b/drivers/extcon/extcon-max8997.c index 09f4a9374cf..18f53e6f306 100644 --- a/drivers/extcon/extcon-max8997.c +++ b/drivers/extcon/extcon-max8997.c @@ -426,7 +426,8 @@ static int max8997_muic_adc_handler(struct max8997_muic_info *info) break; case MAX8997_MUIC_ADC_FACTORY_MODE_USB_OFF: case MAX8997_MUIC_ADC_FACTORY_MODE_USB_ON: - ret = max8997_muic_handle_usb(info, MAX8997_USB_DEVICE, attached); + ret = max8997_muic_handle_usb(info, + MAX8997_USB_DEVICE, attached); if (ret < 0) return ret; break; @@ -504,7 +505,8 @@ static int max8997_muic_chg_handler(struct max8997_muic_info *info) } break; case MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT: - extcon_set_cable_state(info->edev, "Charge-downstream", attached); + extcon_set_cable_state(info->edev, + "Charge-downstream", attached); break; case MAX8997_CHARGER_TYPE_DEDICATED_CHG: extcon_set_cable_state(info->edev, "TA", attached); diff --git a/drivers/gpio/gpio-arizona.c b/drivers/gpio/gpio-arizona.c index 0ea853f68db..4a682a34016 100644 --- a/drivers/gpio/gpio-arizona.c +++ b/drivers/gpio/gpio-arizona.c @@ -1,6 +1,7 @@ /* * gpiolib support for Wolfson Arizona class devices * + * Copyright 2014 CirrusLogic, Inc. * Copyright 2012 Wolfson Microelectronics PLC. * * Author: Mark Brown @@ -18,6 +19,7 @@ #include #include #include +#include #include #include @@ -84,6 +86,139 @@ static void arizona_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ARIZONA_GPN_LVL, value); } +static int clearwater_gpio_direction_in(struct gpio_chip *chip, unsigned offset) +{ + struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip); + struct arizona *arizona = arizona_gpio->arizona; + + offset *= 2; + + return regmap_update_bits(arizona->regmap, CLEARWATER_GPIO1_CTRL_2 + offset, + ARIZONA_GPN_DIR, ARIZONA_GPN_DIR); +} + +static int clearwater_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip); + struct arizona *arizona = arizona_gpio->arizona; + unsigned int val; + int ret; + + offset *= 2; + + pm_runtime_get_sync(arizona->dev); + + ret = regmap_read(arizona->regmap, CLEARWATER_GPIO1_CTRL_1 + offset, &val); + if (ret < 0) + goto err; + + ret = val & CLEARWATER_GPN_LVL ? 1 : 0; + +err: + pm_runtime_put_sync(arizona->dev); + return ret; +} + +static int clearwater_gpio_direction_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip); + struct arizona *arizona = arizona_gpio->arizona; + int ret; + unsigned int old_val, new_val; + + offset *= 2; + + if (value) + value = CLEARWATER_GPN_LVL; + + pm_runtime_get_sync(arizona->dev); + + ret = regmap_update_bits(arizona->regmap, CLEARWATER_GPIO1_CTRL_2 + offset, + ARIZONA_GPN_DIR, 0); + if (ret < 0) + goto err; + + ret = regmap_read(arizona->regmap, CLEARWATER_GPIO1_CTRL_1 + offset, &old_val); + if (ret == 0) { + new_val = (old_val) & (~CLEARWATER_GPN_LVL); + new_val |= value; + if (new_val != old_val) { + regmap_write(arizona->regmap, CLEARWATER_GPIO1_CTRL_1 + offset, new_val); + arizona->pdata.gpio_defaults[offset] = new_val; + } + } + +err: + pm_runtime_put_sync(arizona->dev); + return ret; +} + +static void clearwater_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip); + struct arizona *arizona = arizona_gpio->arizona; + unsigned int old_val, new_val; + int ret; + + offset *= 2; + + if (value) + value = CLEARWATER_GPN_LVL; + + pm_runtime_get_sync(arizona->dev); + + ret = regmap_read(arizona->regmap, CLEARWATER_GPIO1_CTRL_1 + offset, &old_val); + if (ret == 0) { + new_val = (old_val) & (~CLEARWATER_GPN_LVL); + new_val |= value; + if (new_val != old_val) { + regmap_write(arizona->regmap, CLEARWATER_GPIO1_CTRL_1 + offset, new_val); + arizona->pdata.gpio_defaults[offset] = new_val; + } + } + + pm_runtime_put_sync(arizona->dev); +} + +static int clearwater_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct arizona_gpio *arizona_gpio = to_arizona_gpio(chip); + struct arizona *arizona = arizona_gpio->arizona; + int irq; + + switch (offset) { + case 0: + irq = ARIZONA_IRQ_GP1; + break; + case 1: + irq = ARIZONA_IRQ_GP2; + break; + case 2: + irq = ARIZONA_IRQ_GP3; + break; + case 3: + irq = ARIZONA_IRQ_GP4; + break; + case 4: + irq = ARIZONA_IRQ_GP5; + break; + case 5: + irq = ARIZONA_IRQ_GP6; + break; + case 6: + irq = ARIZONA_IRQ_GP7; + break; + case 7: + irq = ARIZONA_IRQ_GP8; + break; + default: + return -EINVAL; + } + + return arizona_map_irq(arizona, irq); +} + static struct gpio_chip template_chip = { .label = "arizona", .owner = THIS_MODULE, @@ -109,12 +244,68 @@ static int arizona_gpio_probe(struct platform_device *pdev) arizona_gpio->arizona = arizona; arizona_gpio->gpio_chip = template_chip; arizona_gpio->gpio_chip.dev = &pdev->dev; +#ifdef CONFIG_OF_GPIO + arizona_gpio->gpio_chip.of_node = arizona->dev->of_node; +#endif switch (arizona->type) { case WM5102: + case WM8280: case WM5110: + case WM8997: + case WM8998: + case WM1814: arizona_gpio->gpio_chip.ngpio = 5; break; + case WM8285: + case WM1840: + arizona_gpio->gpio_chip.direction_input = + clearwater_gpio_direction_in; + arizona_gpio->gpio_chip.get = clearwater_gpio_get; + arizona_gpio->gpio_chip.direction_output = + clearwater_gpio_direction_out; + arizona_gpio->gpio_chip.set = clearwater_gpio_set; + + arizona_gpio->gpio_chip.ngpio = CLEARWATER_NUM_GPIOS; + break; + case WM1831: + case CS47L24: + arizona_gpio->gpio_chip.ngpio = 2; + break; + case CS47L35: + arizona_gpio->gpio_chip.direction_input = + clearwater_gpio_direction_in; + arizona_gpio->gpio_chip.get = clearwater_gpio_get; + arizona_gpio->gpio_chip.direction_output = + clearwater_gpio_direction_out; + arizona_gpio->gpio_chip.set = clearwater_gpio_set; + arizona_gpio->gpio_chip.to_irq = clearwater_gpio_to_irq; + + arizona_gpio->gpio_chip.ngpio = MARLEY_NUM_GPIOS; + break; + case CS47L90: + case CS47L91: + arizona_gpio->gpio_chip.direction_input = + clearwater_gpio_direction_in; + arizona_gpio->gpio_chip.get = clearwater_gpio_get; + arizona_gpio->gpio_chip.direction_output = + clearwater_gpio_direction_out; + arizona_gpio->gpio_chip.set = clearwater_gpio_set; + arizona_gpio->gpio_chip.to_irq = clearwater_gpio_to_irq; + + arizona_gpio->gpio_chip.ngpio = MOON_NUM_GPIOS; + break; + case CS47L15: + arizona_gpio->gpio_chip.direction_input = + clearwater_gpio_direction_in; + arizona_gpio->gpio_chip.get = clearwater_gpio_get; + arizona_gpio->gpio_chip.direction_output = + clearwater_gpio_direction_out; + arizona_gpio->gpio_chip.set = clearwater_gpio_set; + arizona_gpio->gpio_chip.to_irq = clearwater_gpio_to_irq; + + arizona_gpio->gpio_chip.ngpio = CS47L15_NUM_GPIOS; + break; default: dev_err(&pdev->dev, "Unknown chip variant %d\n", arizona->type); diff --git a/drivers/input/misc/arizona-haptics.c b/drivers/input/misc/arizona-haptics.c index e7e12a5f5c2..8dc2814ab3f 100644 --- a/drivers/input/misc/arizona-haptics.c +++ b/drivers/input/misc/arizona-haptics.c @@ -37,7 +37,7 @@ static void arizona_haptics_work(struct work_struct *work) struct arizona_haptics, work); struct arizona *arizona = haptics->arizona; - struct mutex *dapm_mutex = &arizona->dapm->card->dapm_mutex; + struct mutex *dapm_mutex; int ret; if (!haptics->arizona->dapm) { @@ -45,6 +45,8 @@ static void arizona_haptics_work(struct work_struct *work) return; } + dapm_mutex = &arizona->dapm->card->dapm_mutex; + if (haptics->intensity) { ret = regmap_update_bits(arizona->regmap, ARIZONA_HAPTICS_PHASE_2_INTENSITY, @@ -68,12 +70,12 @@ static void arizona_haptics_work(struct work_struct *work) } mutex_lock_nested(dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); - ret = snd_soc_dapm_enable_pin(arizona->dapm, "HAPTICS"); + mutex_unlock(dapm_mutex); + if (ret != 0) { dev_err(arizona->dev, "Failed to start HAPTICS: %d\n", ret); - mutex_unlock(dapm_mutex); return; } @@ -88,12 +90,12 @@ static void arizona_haptics_work(struct work_struct *work) } else { /* This disable sequence will be a noop if already enabled */ mutex_lock_nested(dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); - ret = snd_soc_dapm_disable_pin(arizona->dapm, "HAPTICS"); + mutex_unlock(dapm_mutex); + if (ret != 0) { dev_err(arizona->dev, "Failed to disable HAPTICS: %d\n", ret); - mutex_unlock(dapm_mutex); return; } @@ -108,8 +110,7 @@ static void arizona_haptics_work(struct work_struct *work) ret = regmap_update_bits(arizona->regmap, ARIZONA_HAPTICS_CONTROL_1, - ARIZONA_HAP_CTRL_MASK, - 1 << ARIZONA_HAP_CTRL_SHIFT); + ARIZONA_HAP_CTRL_MASK, 0); if (ret != 0) { dev_err(arizona->dev, "Failed to stop haptics: %d\n", ret); @@ -152,16 +153,16 @@ static int arizona_haptics_play(struct input_dev *input, void *data, static void arizona_haptics_close(struct input_dev *input) { struct arizona_haptics *haptics = input_get_drvdata(input); - struct mutex *dapm_mutex = &haptics->arizona->dapm->card->dapm_mutex; + struct mutex *dapm_mutex; cancel_work_sync(&haptics->work); - mutex_lock_nested(dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); - - if (haptics->arizona->dapm) + if (haptics->arizona->dapm) { + dapm_mutex = &haptics->arizona->dapm->card->dapm_mutex; + mutex_lock_nested(dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); snd_soc_dapm_disable_pin(haptics->arizona->dapm, "HAPTICS"); - - mutex_unlock(dapm_mutex); + mutex_unlock(dapm_mutex); + } } static int arizona_haptics_probe(struct platform_device *pdev) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a4776603a0e..1748b137e85 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -783,9 +783,6 @@ config MFD_TPS65217 charger, wled and other features that are often used in portable devices. - This driver can also be built as a module. If so, the module - will be called tps65217. - config MFD_TPS6586X bool "TI TPS6586x Power Management chips" depends on I2C=y @@ -1036,11 +1033,60 @@ config MFD_WM5102 help Support for Wolfson Microelectronics WM5102 low power audio SoC -config MFD_WM5110 - bool "Wolfson Microelectronics WM5110" +config MFD_FLORIDA + bool "Wolfson Microelectronics Florida class codecs" + depends on MFD_ARIZONA + help + Support for Wolfson Microelectronics Florida class low power audio SoC + such as the WM8280 + +config MFD_VEGAS + bool "Support Wolfson Microelectronics Vegas" + depends on MFD_ARIZONA + help + Support for Wolfson Microelectronics Vegas low power audio SoC + +config MFD_WM8997 + bool "Wolfson Microelectronics WM8997" + depends on MFD_ARIZONA + help + Support for Wolfson Microelectronics WM8997 low power audio SoC + +config MFD_CLEARWATER + bool "Cirrus Logic ClearWater class codecs" + depends on MFD_ARIZONA + help + Support for Cirrus Logic ClearWater class low power audio SoC + +config MFD_MOON + bool "Cirrus Logic Moon class codecs" + depends on MFD_ARIZONA + help + Support for Cirrus Logic Moon class low power audio SoC + such as the CS47L90. This driver provides common support + for accessing the device, additional drivers must be + enabled in order to use the functionality of the device. + +config MFD_LARGO + bool "Cirrus Logic Largo" + depends on MFD_ARIZONA + help + Support for Cirrus Logic Largo low power audio SoC + +config MFD_MARLEY + bool "Cirrus Logic Marley" + depends on MFD_ARIZONA + help + Support for Cirrus Logic Marley low power audio SoC + +config MFD_CS47L15 + bool "Cirrus Logic CS47L15" depends on MFD_ARIZONA help - Support for Wolfson Microelectronics WM5110 low power audio SoC + Support for Cirrus Logic CS47L15 low power audio SoC. + This driver provides common support for accessing the codec. + Additional drivers must be enabled in order to use the + functionality of the codec. config MFD_WM8400 bool "Wolfson Microelectronics WM8400" diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 44217e83d61..afb61ca1642 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -37,11 +37,32 @@ obj-$(CONFIG_MFD_ARIZONA) += arizona-core.o obj-$(CONFIG_MFD_ARIZONA) += arizona-irq.o obj-$(CONFIG_MFD_ARIZONA_I2C) += arizona-i2c.o obj-$(CONFIG_MFD_ARIZONA_SPI) += arizona-spi.o -ifneq ($(CONFIG_MFD_WM5102),n) +ifeq ($(CONFIG_MFD_WM5102),y) obj-$(CONFIG_MFD_ARIZONA) += wm5102-tables.o endif -ifneq ($(CONFIG_MFD_WM5110),n) -obj-$(CONFIG_MFD_ARIZONA) += wm5110-tables.o +ifeq ($(CONFIG_MFD_FLORIDA),y) +obj-$(CONFIG_MFD_ARIZONA) += florida-tables.o +endif +ifeq ($(CONFIG_MFD_WM8997),y) +obj-$(CONFIG_MFD_ARIZONA) += wm8997-tables.o +endif +ifeq ($(CONFIG_MFD_VEGAS),y) +obj-$(CONFIG_MFD_ARIZONA) += vegas-tables.o +endif +ifeq ($(CONFIG_MFD_CLEARWATER),y) +obj-$(CONFIG_MFD_ARIZONA) += clearwater-tables.o +endif +ifeq ($(CONFIG_MFD_MARLEY),y) +obj-$(CONFIG_MFD_ARIZONA) += marley-tables.o +endif +ifeq ($(CONFIG_MFD_LARGO),y) +obj-$(CONFIG_MFD_ARIZONA) += largo-tables.o +endif +ifeq ($(CONFIG_MFD_MOON), y) +obj-$(CONFIG_MFD_ARIZONA) += moon-tables.o +endif +ifeq ($(CONFIG_MFD_CS47L15),y) +obj-$(CONFIG_MFD_ARIZONA) += cs47l15-tables.o endif obj-$(CONFIG_MFD_WM8400) += wm8400-core.o wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index 6ab03043fd6..3b219c9917d 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -1,6 +1,7 @@ /* * Arizona core driver * + * Copyright 2014 CirrusLogic, Inc. * Copyright 2012 Wolfson Microelectronics plc * * Author: Mark Brown @@ -16,9 +17,14 @@ #include #include #include +#include +#include +#include +#include #include #include #include +#include #include #include @@ -119,6 +125,8 @@ static irqreturn_t arizona_underclocked(int irq, void *data) dev_err(arizona->dev, "AIF2 underclocked\n"); if (val & ARIZONA_AIF1_UNDERCLOCKED_STS) dev_err(arizona->dev, "AIF1 underclocked\n"); + if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS) + dev_err(arizona->dev, "ISRC3 underclocked\n"); if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS) dev_err(arizona->dev, "ISRC2 underclocked\n"); if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS) @@ -140,17 +148,28 @@ static irqreturn_t arizona_underclocked(int irq, void *data) static irqreturn_t arizona_overclocked(int irq, void *data) { struct arizona *arizona = data; - unsigned int val[2]; + unsigned int val[3]; int ret; - + ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6, - &val[0], 2); + &val[0], 3); if (ret != 0) { dev_err(arizona->dev, "Failed to read overclock status: %d\n", ret); return IRQ_NONE; } + switch (arizona->type) { + case WM8998: + case WM1814: + val[0] = ((val[0] & 0x60e0) >> 1) | + ((val[0] & 0x1e00) >> 2) | + (val[0] & 0x000f); + break; + default: + break; + } + if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS) dev_err(arizona->dev, "PWM overclocked\n"); if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS) @@ -188,11 +207,16 @@ static irqreturn_t arizona_overclocked(int irq, void *data) dev_err(arizona->dev, "ASRC sync WARP overclocked\n"); if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS) dev_err(arizona->dev, "DSP1 overclocked\n"); + if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS) + dev_err(arizona->dev, "ISRC3 overclocked\n"); if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS) dev_err(arizona->dev, "ISRC2 overclocked\n"); if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS) dev_err(arizona->dev, "ISRC1 overclocked\n"); + if (val[2] & ARIZONA_SPDIF_OVERCLOCKED_STS) + dev_err(arizona->dev, "SPDIF overclocked\n"); + return IRQ_HANDLED; } @@ -230,34 +254,83 @@ static int arizona_wait_for_boot(struct arizona *arizona) * we won't race with the interrupt handler as it'll be blocked on * runtime resume. */ - ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5, - ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS); + switch (arizona->type) { + case WM5102: + case WM8997: + case WM1814: + case WM8998: + case WM5110: + case WM8280: + case WM1831: + case CS47L24: + ret = arizona_poll_reg(arizona, 5, + ARIZONA_INTERRUPT_RAW_STATUS_5, + ARIZONA_BOOT_DONE_STS, + ARIZONA_BOOT_DONE_STS); + if (!ret) + regmap_write(arizona->regmap, + ARIZONA_INTERRUPT_STATUS_5, + ARIZONA_BOOT_DONE_STS); + break; + default: + ret = arizona_poll_reg(arizona, 5, CLEARWATER_IRQ1_RAW_STATUS_1, + CLEARWATER_BOOT_DONE_STS1, + CLEARWATER_BOOT_DONE_STS1); - if (!ret) - regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5, - ARIZONA_BOOT_DONE_STS); + if (!ret) + regmap_write(arizona->regmap, CLEARWATER_IRQ1_STATUS_1, + CLEARWATER_BOOT_DONE_EINT1); + break; + } pm_runtime_mark_last_busy(arizona->dev); return ret; } -static int arizona_apply_hardware_patch(struct arizona* arizona) +static inline void arizona_enable_reset(struct arizona *arizona) { - unsigned int fll, sysclk; - int ret, err; + if (arizona->pdata.reset) + gpio_set_value_cansleep(arizona->pdata.reset, 0); +} + +static void arizona_disable_reset(struct arizona *arizona) +{ + if (arizona->pdata.reset) { + switch (arizona->type) { + case WM5110: + case WM8280: + msleep(5); + break; + default: + break; + } + + gpio_set_value_cansleep(arizona->pdata.reset, 1); + msleep(1); + } +} + +struct arizona_sysclk_state { + unsigned int fll; + unsigned int sysclk; +}; - regcache_cache_bypass(arizona->regmap, true); +static int arizona_enable_freerun_sysclk(struct arizona *arizona, + struct arizona_sysclk_state *state) +{ + int ret, err; /* Cache existing FLL and SYSCLK settings */ - ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll); - if (ret != 0) { + ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &state->fll); + if (ret) { dev_err(arizona->dev, "Failed to cache FLL settings: %d\n", ret); return ret; } - ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk); - if (ret != 0) { + ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, + &state->sysclk); + if (ret) { dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n", ret); return ret; @@ -266,7 +339,7 @@ static int arizona_apply_hardware_patch(struct arizona* arizona) /* Start up SYSCLK using the FLL in free running mode */ ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN); - if (ret != 0) { + if (ret) { dev_err(arizona->dev, "Failed to start FLL in freerunning mode: %d\n", ret); @@ -275,65 +348,199 @@ static int arizona_apply_hardware_patch(struct arizona* arizona) ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5, ARIZONA_FLL1_CLOCK_OK_STS, ARIZONA_FLL1_CLOCK_OK_STS); - if (ret != 0) { + if (ret) { ret = -ETIMEDOUT; goto err_fll; } ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144); - if (ret != 0) { + if (ret) { dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret); goto err_fll; } + return 0; + +err_fll: + err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll); + if (err) + dev_err(arizona->dev, + "Failed to re-apply old FLL settings: %d\n", err); + + return ret; +} + +static int arizona_disable_freerun_sysclk(struct arizona *arizona, + struct arizona_sysclk_state *state) +{ + int ret; + + ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, + state->sysclk); + if (ret) { + dev_err(arizona->dev, + "Failed to re-apply old SYSCLK settings: %d\n", ret); + return ret; + } + + ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll); + if (ret) { + dev_err(arizona->dev, + "Failed to re-apply old FLL settings: %d\n", ret); + return ret; + } + + return 0; +} + +static int wm5102_apply_hardware_patch(struct arizona *arizona) +{ + struct arizona_sysclk_state state; + int err, ret; + + ret = arizona_enable_freerun_sysclk(arizona, &state); + if (ret) + return ret; + /* Start the write sequencer and wait for it to finish */ ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0, ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160); - if (ret != 0) { + if (ret) { dev_err(arizona->dev, "Failed to start write sequencer: %d\n", ret); - goto err_sysclk; + goto err; } + ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1, ARIZONA_WSEQ_BUSY, 0); - if (ret != 0) { + if (ret) { regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0, - ARIZONA_WSEQ_ABORT); + ARIZONA_WSEQ_ABORT); ret = -ETIMEDOUT; } -err_sysclk: - err = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk); - if (err != 0) { - dev_err(arizona->dev, - "Failed to re-apply old SYSCLK settings: %d\n", - err); - } +err: + err = arizona_disable_freerun_sysclk(arizona, &state); -err_fll: - err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll); - if (err != 0) { - dev_err(arizona->dev, - "Failed to re-apply old FLL settings: %d\n", - err); - } + return ret ?: err; +} + +/* + * Register patch to some of the CODECs internal write sequences + * to ensure a clean exit from the low power sleep state. + */ +static const struct reg_sequence wm5110_sleep_patch[] = { + { 0x337A, 0xC100 }, + { 0x337B, 0x0041 }, + { 0x3300, 0xA210 }, + { 0x3301, 0x050C }, +}; - regcache_cache_bypass(arizona->regmap, false); +static int wm5110_apply_sleep_patch(struct arizona *arizona) +{ + struct arizona_sysclk_state state; + int err, ret; - if (ret != 0) + ret = arizona_enable_freerun_sysclk(arizona, &state); + if (ret) + return ret; + + ret = regmap_multi_reg_write_bypassed(arizona->regmap, + wm5110_sleep_patch, + ARRAY_SIZE(wm5110_sleep_patch)); + + err = arizona_disable_freerun_sysclk(arizona, &state); + + if (ret) return ret; else return err; } +static int wm5102_clear_write_sequencer(struct arizona *arizona) +{ + int ret; + + ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_3, + 0x0); + if (ret) { + dev_err(arizona->dev, + "Failed to clear write sequencer state: %d\n", ret); + return ret; + } + + arizona_enable_reset(arizona); + regulator_disable(arizona->dcvdd); + + msleep(20); + + ret = regulator_enable(arizona->dcvdd); + if (ret) { + dev_err(arizona->dev, "Failed to re-enable DCVDD: %d\n", ret); + return ret; + } + arizona_disable_reset(arizona); + + return 0; +} + +static int arizona_soft_reset(struct arizona *arizona) +{ + int ret; + + ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0); + if (ret != 0) { + dev_err(arizona->dev, "Failed to reset device: %d\n", ret); + goto err; + } + msleep(1); + +err: + return ret; +} + #ifdef CONFIG_PM_RUNTIME +static int arizona_dcvdd_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct arizona *arizona = container_of(nb, struct arizona, + dcvdd_notifier); + + dev_dbg(arizona->dev, "DCVDD notify %lx\n", action); + + if (action & REGULATOR_EVENT_DISABLE) + msleep(20); + + return NOTIFY_DONE; +} + static int arizona_runtime_resume(struct device *dev) { struct arizona *arizona = dev_get_drvdata(dev); int ret; + unsigned int offset, num_gpios = 0; dev_dbg(arizona->dev, "Leaving AoD mode\n"); + switch (arizona->type) { + case WM5110: + case WM8280: + if (arizona->rev == 3) + arizona_enable_reset(arizona); + break; + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM1831: + case CS47L24: + break; + default: + if (arizona->external_dcvdd) + arizona_enable_reset(arizona); + break; + }; + ret = regulator_enable(arizona->dcvdd); if (ret != 0) { dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret); @@ -341,9 +548,22 @@ static int arizona_runtime_resume(struct device *dev) } regcache_cache_only(arizona->regmap, false); + if (arizona->regmap_32bit) + regcache_cache_only(arizona->regmap_32bit, false); switch (arizona->type) { case WM5102: + if (arizona->external_dcvdd) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ISOLATION_CONTROL, + ARIZONA_ISOLATE_DCVDD1, 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to connect DCVDD: %d\n", ret); + goto err; + } + } + ret = wm5102_patch(arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to apply patch: %d\n", @@ -351,33 +571,154 @@ static int arizona_runtime_resume(struct device *dev) goto err; } - ret = arizona_apply_hardware_patch(arizona); - if (ret != 0) { + ret = wm5102_apply_hardware_patch(arizona); + if (ret) { dev_err(arizona->dev, "Failed to apply hardware patch: %d\n", ret); goto err; } break; + case WM5110: + case WM8280: + if (arizona->rev == 3) { + if (!arizona->pdata.reset) { + ret = arizona_soft_reset(arizona); + if (ret != 0) + goto err; + } else { + arizona_disable_reset(arizona); + } + } + + ret = arizona_wait_for_boot(arizona); + if (ret) + goto err; + + if (arizona->external_dcvdd) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ISOLATION_CONTROL, + ARIZONA_ISOLATE_DCVDD1, 0); + if (ret) { + dev_err(arizona->dev, + "Failed to connect DCVDD: %d\n", ret); + goto err; + } + } else { + /* + * As this is only called for the internal regulator + * (where we know voltage ranges available) it is ok + * to request an exact range. + */ + ret = regulator_set_voltage(arizona->dcvdd, + 1200000, 1200000); + if (ret < 0) { + dev_err(arizona->dev, + "Failed to set resume voltage: %d\n", + ret); + goto err; + } + } + break; + case WM8997: + case WM8998: + case WM1814: + ret = arizona_wait_for_boot(arizona); + if (ret != 0) { + goto err; + } + + if (arizona->external_dcvdd) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ISOLATION_CONTROL, + ARIZONA_ISOLATE_DCVDD1, 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to connect DCVDD: %d\n", ret); + goto err; + } + } + break; + case WM1831: + case CS47L24: + ret = arizona_wait_for_boot(arizona); + if (ret != 0) { + goto err; + } + break; default: + if (arizona->external_dcvdd) + arizona_disable_reset(arizona); + ret = arizona_wait_for_boot(arizona); if (ret != 0) { goto err; } + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + ret = regcache_sync_region(arizona->regmap, CLEARWATER_CP_MODE, + CLEARWATER_CP_MODE); + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + + if (ret != 0) { + dev_err(arizona->dev, "Failed to restore keyed cache\n"); + goto err; + } + break; + } + + switch (arizona->type) { + case WM8285: + case WM1840: + num_gpios = CLEARWATER_NUM_GPIOS; + break; + case CS47L35: + num_gpios = MARLEY_NUM_GPIOS; + break; + case CS47L90: + case CS47L91: + num_gpios = MOON_NUM_GPIOS; + break; + case CS47L15: + num_gpios = CS47L15_NUM_GPIOS; break; + default: + break; + } + + /* sync the gpio registers */ + for (offset = 0; offset < num_gpios; offset++) { + if (!arizona->pdata.gpio_defaults[offset * 2]) + continue; + regmap_write(arizona->regmap, + CLEARWATER_GPIO1_CTRL_1 + (offset * 2), + arizona->pdata.gpio_defaults[offset * 2]); } ret = regcache_sync(arizona->regmap); if (ret != 0) { - dev_err(arizona->dev, "Failed to restore register cache\n"); + dev_err(arizona->dev, + "Failed to restore 16-bit register cache\n"); goto err; } + if (arizona->regmap_32bit) { + ret = regcache_sync(arizona->regmap_32bit); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to restore 32-bit register cache\n"); + goto err; + } + } + return 0; err: regcache_cache_only(arizona->regmap, true); + if (arizona->regmap_32bit) + regcache_cache_only(arizona->regmap_32bit, true); regulator_disable(arizona->dcvdd); return ret; } @@ -385,18 +726,100 @@ static int arizona_runtime_resume(struct device *dev) static int arizona_runtime_suspend(struct device *dev) { struct arizona *arizona = dev_get_drvdata(dev); + int ret; dev_dbg(arizona->dev, "Entering AoD mode\n"); - regulator_disable(arizona->dcvdd); + if (arizona->external_dcvdd) { + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ISOLATION_CONTROL, + ARIZONA_ISOLATE_DCVDD1, + ARIZONA_ISOLATE_DCVDD1); + if (ret != 0) { + dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n", + ret); + return ret; + } + break; + default: + break; + } + } else { + switch (arizona->type) { + case WM5110: + case WM8280: + /* + * As this is only called for the internal regulator + * (where we know voltage ranges available) it is ok + * to request an exact range. + */ + ret = regulator_set_voltage(arizona->dcvdd, + 1175000, + 1175000); + if (ret < 0) { + dev_err(arizona->dev, + "Failed to set suspend voltage: %d\n", + ret); + return ret; + } + break; + default: + break; + } + } + regcache_cache_only(arizona->regmap, true); regcache_mark_dirty(arizona->regmap); + if (arizona->regmap_32bit) { + regcache_cache_only(arizona->regmap_32bit, true); + regcache_mark_dirty(arizona->regmap_32bit); + } + regulator_disable(arizona->dcvdd); return 0; } +#else +static inline int arizona_dcvdd_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + return 0; +} #endif #ifdef CONFIG_PM_SLEEP +static int arizona_suspend_noirq(struct device *dev) +{ + struct arizona *arizona = dev_get_drvdata(dev); + + dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n"); + + if (arizona->irq_sem) { + enable_irq(arizona->irq); + arizona->irq_sem = 0; + } + + return 0; +} + +static int arizona_suspend(struct device *dev) +{ + struct arizona *arizona = dev_get_drvdata(dev); + + dev_dbg(arizona->dev, "Early suspend, disabling IRQ\n"); + + disable_irq(arizona->irq); + arizona->irq_sem = 1; + + return 0; +} + static int arizona_resume_noirq(struct device *dev) { struct arizona *arizona = dev_get_drvdata(dev); @@ -404,6 +827,8 @@ static int arizona_resume_noirq(struct device *dev) dev_dbg(arizona->dev, "Early resume, disabling IRQ\n"); disable_irq(arizona->irq); + arizona->irq_sem = 1; + return 0; } @@ -411,66 +836,807 @@ static int arizona_resume(struct device *dev) { struct arizona *arizona = dev_get_drvdata(dev); - dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n"); - enable_irq(arizona->irq); + dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n"); + if (arizona->irq_sem) { + enable_irq(arizona->irq); + arizona->irq_sem = 0; + } + + return 0; +} +#endif + +const struct dev_pm_ops arizona_pm_ops = { + SET_RUNTIME_PM_OPS(arizona_runtime_suspend, + arizona_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume) +#ifdef CONFIG_PM_SLEEP + .suspend_noirq = arizona_suspend_noirq, + .resume_noirq = arizona_resume_noirq, +#endif +}; +EXPORT_SYMBOL_GPL(arizona_pm_ops); + +#ifdef CONFIG_OF +unsigned long arizona_of_get_type(struct device *dev) +{ + const struct of_device_id *id = of_match_device(arizona_of_match, dev); + + if (id) + return (unsigned long)id->data; + else + return 0; +} +EXPORT_SYMBOL_GPL(arizona_of_get_type); + +int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop, + bool mandatory) +{ + int gpio; + + gpio = of_get_named_gpio(arizona->dev->of_node, prop, 0); + if (gpio < 0) { + if (mandatory) + dev_err(arizona->dev, + "Mandatory DT gpio %s missing/malformed: %d\n", + prop, gpio); + + gpio = 0; + } + + return gpio; +} +EXPORT_SYMBOL_GPL(arizona_of_get_named_gpio); + +int arizona_of_read_u32_array(struct arizona *arizona, + const char *prop, bool mandatory, + u32 *data, size_t num) +{ + int ret; + + ret = of_property_read_u32_array(arizona->dev->of_node, prop, + data, num); + + if (ret >= 0) + return 0; + + switch (ret) { + case -EINVAL: + if (mandatory) + dev_err(arizona->dev, + "Mandatory DT property %s is missing\n", + prop); + break; + default: + dev_err(arizona->dev, + "DT property %s is malformed: %d\n", + prop, ret); + } + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_of_read_u32_array); + +int arizona_of_read_u32(struct arizona *arizona, + const char* prop, bool mandatory, + u32 *data) +{ + return arizona_of_read_u32_array(arizona, prop, mandatory, data, 1); +} +EXPORT_SYMBOL_GPL(arizona_of_read_u32); + +static int arizona_of_get_max_channels(struct arizona *arizona, + const char *prop) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct device_node *np = arizona->dev->of_node; + struct property *tempprop; + const __be32 *cur; + u32 val; + int i; + + i = 0; + of_property_for_each_u32(np, prop, tempprop, cur, val) { + if (i == ARRAY_SIZE(pdata->max_channels_clocked)) + break; + + pdata->max_channels_clocked[i++] = val; + } + + return 0; +} + +static int arizona_of_get_inmode(struct arizona *arizona, + const char *prop) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct device_node *np = arizona->dev->of_node; + struct property *tempprop; + const __be32 *cur; + u32 val; + int i; + + i = 0; + of_property_for_each_u32(np, prop, tempprop, cur, val) { + if (i == ARRAY_SIZE(pdata->inmode)) + break; + + pdata->inmode[i++] = val; + } + + return 0; +} + +static int arizona_of_get_lrclk_adv(struct arizona *arizona, + const char *prop) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct device_node *np = arizona->dev->of_node; + struct property *tempprop; + const __be32 *cur; + u32 val; + int i; + + i = 0; + of_property_for_each_u32(np, prop, tempprop, cur, val) { + if (i == ARRAY_SIZE(pdata->lrclk_adv)) + break; + + pdata->lrclk_adv[i++] = val; + } + + return 0; +} + +static int arizona_of_get_dmicref(struct arizona *arizona, + const char *prop) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct device_node *np = arizona->dev->of_node; + struct property *tempprop; + const __be32 *cur; + u32 val; + int i; + + i = 0; + of_property_for_each_u32(np, prop, tempprop, cur, val) { + if (i == ARRAY_SIZE(pdata->dmic_ref)) + break; + + pdata->dmic_ref[i++] = val; + } + + return 0; +} + +static int arizona_of_get_dmic_clksrc(struct arizona *arizona, + const char *prop) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct device_node *np = arizona->dev->of_node; + struct property *tempprop; + const __be32 *cur; + u32 val; + int i; + + i = 0; + of_property_for_each_u32(np, prop, tempprop, cur, val) { + if (i == ARRAY_SIZE(pdata->dmic_clksrc)) + break; + + pdata->dmic_clksrc[i++] = val; + } + + return 0; +} + +static int arizona_of_get_gpio_defaults(struct arizona *arizona, + const char *prop) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct device_node *np = arizona->dev->of_node; + struct property *tempprop; + const __be32 *cur; + u32 val; + int i; + + i = 0; + of_property_for_each_u32(np, prop, tempprop, cur, val) { + if (i == ARRAY_SIZE(pdata->gpio_defaults)) + break; + + pdata->gpio_defaults[i++] = val; + } + + /* + * All values are literal except out of range values + * which are chip default, translate into platform + * data which uses 0 as chip default and out of range + * as zero. + */ + while (i > 0) { + --i; + if (pdata->gpio_defaults[i] > 0xffff) + pdata->gpio_defaults[i] = 0; + else if (pdata->gpio_defaults[i] == 0) + pdata->gpio_defaults[i] = 0x10000; + } + + return 0; +} + +static int arizona_of_get_u32_num_groups(struct arizona *arizona, + const char *prop, + int group_size) +{ + int len_prop; + int num_groups; + + if (!of_get_property(arizona->dev->of_node, prop, &len_prop)) + return -EINVAL; + + num_groups = len_prop / (group_size * sizeof(u32)); + + if (num_groups * group_size * sizeof(u32) != len_prop) { + dev_err(arizona->dev, + "DT property %s is malformed: %d\n", + prop, -EOVERFLOW); + return -EOVERFLOW; + } + + return num_groups; +} + +static int arizona_of_get_micd_ranges(struct arizona *arizona, + const char *prop) +{ + int nranges; + int i, j; + int ret = 0; + u32 value; + struct arizona_micd_range *micd_ranges; + + nranges = arizona_of_get_u32_num_groups(arizona, prop, 2); + if (nranges < 0) + return nranges; + + micd_ranges = devm_kzalloc(arizona->dev, + nranges * sizeof(struct arizona_micd_range), + GFP_KERNEL); + + for (i = 0, j = 0; i < nranges; ++i) { + ret = of_property_read_u32_index(arizona->dev->of_node, + prop, j++, &value); + if (ret < 0) + goto error; + micd_ranges[i].max = value; + + ret = of_property_read_u32_index(arizona->dev->of_node, + prop, j++, &value); + if (ret < 0) + goto error; + micd_ranges[i].key = value; + } + + arizona->pdata.micd_ranges = micd_ranges; + arizona->pdata.num_micd_ranges = nranges; + + return ret; + +error: + devm_kfree(arizona->dev, micd_ranges); + dev_err(arizona->dev, "DT property %s is malformed: %d\n", prop, ret); + return ret; +} + +static int arizona_of_get_micd_configs(struct arizona *arizona, + const char *prop) +{ + int nconfigs; + int i, j, group_size; + int ret = 0; + u32 value; + struct arizona_micd_config *micd_configs; + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + case CS47L35: + group_size = 3; + break; + default: + group_size = 4; + break; + } + + nconfigs = arizona_of_get_u32_num_groups(arizona, prop, group_size); + if (nconfigs < 0) + return nconfigs; + + micd_configs = devm_kzalloc(arizona->dev, + nconfigs * + sizeof(struct arizona_micd_config), + GFP_KERNEL); + + for (i = 0, j = 0; i < nconfigs; ++i) { + ret = of_property_read_u32_index(arizona->dev->of_node, + prop, j++, &value); + if (ret < 0) + goto error; + micd_configs[i].src = value; + + if (group_size == 4) { + ret = of_property_read_u32_index(arizona->dev->of_node, + prop, j++, &value); + if (ret < 0) + goto error; + micd_configs[i].gnd = value; + } + + ret = of_property_read_u32_index(arizona->dev->of_node, + prop, j++, &value); + if (ret < 0) + goto error; + micd_configs[i].bias = value; + + ret = of_property_read_u32_index(arizona->dev->of_node, + prop, j++, &value); + if (ret < 0) + goto error; + micd_configs[i].gpio = value; + } + + arizona->pdata.micd_configs = micd_configs; + arizona->pdata.num_micd_configs = nconfigs; + + return ret; + +error: + devm_kfree(arizona->dev, micd_configs); + dev_err(arizona->dev, "DT property %s is malformed: %d\n", prop, ret); + + return ret; +} + +static int arizona_of_get_micbias(struct arizona *arizona, + const char *prop, int index, + int num_micbias_outputs) +{ + int ret, i; + int j = 0; + u32 micbias_config[4 + ARIZONA_MAX_CHILD_MICBIAS] = {0}; + + ret = arizona_of_read_u32_array(arizona, prop, false, + micbias_config, + 4 + num_micbias_outputs); + + if (ret >= 0) { + arizona->pdata.micbias[index].mV = micbias_config[j++]; + arizona->pdata.micbias[index].ext_cap = micbias_config[j++]; + for (i = 0; i < num_micbias_outputs; i++) + arizona->pdata.micbias[index].discharge[i] = + micbias_config[j++]; + arizona->pdata.micbias[index].soft_start = micbias_config[j++]; + arizona->pdata.micbias[index].bypass = micbias_config[j++]; + } + + return ret; +} + +static int arizona_of_get_core_pdata(struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + u32 out_mono[ARIZONA_MAX_OUTPUT]; + int i, num_micbias_outputs; + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + num_micbias_outputs = 1; + break; + case CS47L15: + num_micbias_outputs = CS47L15_NUM_CHILD_MICBIAS; + break; + case CS47L35: + num_micbias_outputs = MARLEY_NUM_CHILD_MICBIAS; + break; + default: + num_micbias_outputs = MOON_NUM_CHILD_MICBIAS; + break; + } + + memset(&out_mono, 0, sizeof(out_mono)); + + pdata->reset = arizona_of_get_named_gpio(arizona, "wlf,reset", true); + + arizona_of_read_s32(arizona, "wlf,clk32k-src", false, + &pdata->clk32k_src); + + arizona_of_get_micd_ranges(arizona, "wlf,micd-ranges"); + arizona_of_get_micd_configs(arizona, "wlf,micd-configs"); + + arizona_of_get_micbias(arizona, "wlf,micbias1", 0, num_micbias_outputs); + arizona_of_get_micbias(arizona, "wlf,micbias2", 1, num_micbias_outputs); + arizona_of_get_micbias(arizona, "wlf,micbias3", 2, num_micbias_outputs); + arizona_of_get_micbias(arizona, "wlf,micbias4", 3, num_micbias_outputs); + + arizona_of_get_gpio_defaults(arizona, "wlf,gpio-defaults"); + + arizona_of_get_max_channels(arizona, "wlf,max-channels-clocked"); + + arizona_of_get_dmicref(arizona, "wlf,dmic-ref"); + + arizona_of_get_inmode(arizona, "wlf,inmode"); + + arizona_of_get_dmic_clksrc(arizona, "wlf,dmic-clksrc"); + + arizona_of_read_u32_array(arizona, "wlf,out-mono", false, + out_mono, ARRAY_SIZE(out_mono)); + for (i = 0; i < ARRAY_SIZE(out_mono); ++i) + pdata->out_mono[i] = !!out_mono[i]; + + arizona_of_read_u32(arizona, "wlf,wm5102t-output-pwr", false, + &pdata->wm5102t_output_pwr); + + arizona_of_read_s32(arizona, "wlf,hpdet-ext-res", false, + &pdata->hpdet_ext_res); + + pdata->rev_specific_fw = of_property_read_bool(arizona->dev->of_node, + "wlf,rev-specific-fw"); + + arizona_of_get_lrclk_adv(arizona, "wlf,aif-lrclk-advance"); + + return 0; +} + +const struct of_device_id arizona_of_match[] = { + { .compatible = "wlf,wm5102", .data = (void *)WM5102 }, + { .compatible = "wlf,wm8280", .data = (void *)WM8280 }, + { .compatible = "wlf,wm5110", .data = (void *)WM5110 }, + { .compatible = "wlf,wm8997", .data = (void *)WM8997 }, + { .compatible = "wlf,wm8998", .data = (void *)WM8998 }, + { .compatible = "wlf,wm1814", .data = (void *)WM1814 }, + { .compatible = "wlf,wm8285", .data = (void *)WM8285 }, + { .compatible = "wlf,wm1840", .data = (void *)WM1840 }, + { .compatible = "wlf,wm1831", .data = (void *)WM1831 }, + { .compatible = "cirrus,cs47l15", .data = (void *)CS47L15 }, + { .compatible = "cirrus,cs47l24", .data = (void *)CS47L24 }, + { .compatible = "cirrus,cs47l35", .data = (void *)CS47L35 }, + { .compatible = "cirrus,cs47l85", .data = (void *)WM8285 }, + { .compatible = "cirrus,cs47l90", .data = (void *)CS47L90 }, + { .compatible = "cirrus,cs47l91", .data = (void *)CS47L91 }, + {}, +}; +EXPORT_SYMBOL_GPL(arizona_of_match); +#else +static inline int arizona_of_get_core_pdata(struct arizona *arizona) +{ + return 0; +} +#endif + +static struct mfd_cell early_devs[] = { + { .name = "arizona-ldo1" }, +}; + +static struct mfd_cell wm5102_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "wm5102-codec" }, +}; + +static struct mfd_cell florida_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "florida-codec" }, +}; + +static struct mfd_cell largo_devs[] = { + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "largo-codec" }, +}; + +static struct mfd_cell wm8997_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "wm8997-codec" }, +}; + +static struct mfd_cell vegas_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "vegas-codec" }, +}; + +static struct mfd_cell clearwater_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "clearwater-codec" }, +}; + +static struct mfd_cell marley_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "marley-codec" }, +}; + +static struct mfd_cell moon_devs[] = { + { .name = "arizona-micsupp" }, + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "moon-codec" }, +}; + +static struct mfd_cell cs47l15_devs[] = { + { .name = "arizona-extcon" }, + { .name = "arizona-gpio" }, + { .name = "arizona-haptics" }, + { .name = "arizona-pwm" }, + { .name = "cs47l15-codec" }, +}; + +static const struct { + unsigned int enable; + unsigned int conf_reg; + unsigned int vol_reg; + unsigned int adc_reg; +} arizona_florida_channel_defs[] = { + { + ARIZONA_IN1R_ENA, ARIZONA_IN1L_CONTROL, + ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_ADC_VCO_CAL_5 + }, + { + ARIZONA_IN1L_ENA, ARIZONA_IN1L_CONTROL, + ARIZONA_ADC_DIGITAL_VOLUME_1L, ARIZONA_ADC_VCO_CAL_4 + }, + { + ARIZONA_IN2R_ENA, ARIZONA_IN2L_CONTROL, + ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_ADC_VCO_CAL_7 + }, + { + ARIZONA_IN2L_ENA, ARIZONA_IN2L_CONTROL, + ARIZONA_ADC_DIGITAL_VOLUME_2L, ARIZONA_ADC_VCO_CAL_6 + }, + { + ARIZONA_IN3R_ENA, ARIZONA_IN3L_CONTROL, + ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_ADC_VCO_CAL_9 + }, + { + ARIZONA_IN3L_ENA, ARIZONA_IN3L_CONTROL, + ARIZONA_ADC_DIGITAL_VOLUME_3L, ARIZONA_ADC_VCO_CAL_8 + }, +}; + +void arizona_florida_mute_analog(struct arizona* arizona, + unsigned int mute) +{ + unsigned int val, chans; + int i; + + regmap_read(arizona->regmap, ARIZONA_INPUT_ENABLES_STATUS, &chans); + + for (i = 0; i < ARRAY_SIZE(arizona_florida_channel_defs); ++i) { + if (!(chans & arizona_florida_channel_defs[i].enable)) + continue; + + /* Check for analogue input */ + regmap_read(arizona->regmap, + arizona_florida_channel_defs[i].conf_reg, + &val); + if (val & 0x0400) + continue; + + regmap_update_bits(arizona->regmap, + arizona_florida_channel_defs[i].vol_reg, + ARIZONA_IN1L_MUTE, + mute); + } +} +EXPORT_SYMBOL_GPL(arizona_florida_mute_analog); + +static bool arizona_florida_get_input_state(struct arizona* arizona) +{ + unsigned int val, chans; + int count, i, j; + + regmap_read(arizona->regmap, ARIZONA_INPUT_ENABLES_STATUS, &chans); + + for (i = 0; i < ARRAY_SIZE(arizona_florida_channel_defs); ++i) { + if (!(chans & arizona_florida_channel_defs[i].enable)) + continue; + + /* Check for analogue input */ + regmap_read(arizona->regmap, + arizona_florida_channel_defs[i].conf_reg, + &val); + if (val & 0x0400) + continue; + + count = 0; + + for (j = 0; j < 4; ++j) { + regmap_read(arizona->regmap, + arizona_florida_channel_defs[i].adc_reg, + &val); + val &= ARIZONA_ADC1L_COUNT_RD_MASK; + val >>= ARIZONA_ADC1L_COUNT_RD_SHIFT; + + dev_dbg(arizona->dev, "ADC Count: %d\n", val); + + if (val > 78 || val < 54) + count++; + } + + if (count == j) + return true; + } + + return false; +} + +void arizona_florida_clear_input(struct arizona *arizona) +{ + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + + if (arizona_florida_get_input_state(arizona)) { + arizona_florida_mute_analog(arizona, ARIZONA_IN1L_MUTE); + + regmap_write(arizona->regmap, 0x3A6, 0x5555); + regmap_write(arizona->regmap, 0x3A5, 0x3); + msleep(10); + regmap_write(arizona->regmap, 0x3A5, 0x0); + + if (arizona_florida_get_input_state(arizona)) { + regmap_write(arizona->regmap, 0x3A6, 0xAAAA); + regmap_write(arizona->regmap, 0x3A5, 0x5); + msleep(10); + regmap_write(arizona->regmap, 0x3A5, 0x0); + } + + regmap_write(arizona->regmap, 0x3A6, 0x0); + + msleep(5); + + arizona_florida_mute_analog(arizona, 0); + } + + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); +} +EXPORT_SYMBOL_GPL(arizona_florida_clear_input); + +int arizona_get_num_micbias(struct arizona *arizona, + unsigned int *micbiases, unsigned int *child_micbiases) +{ + unsigned int num_micbiases, num_child_micbiases; + + if (!arizona) + return -EINVAL; + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + num_micbiases = WM5102_NUM_MICBIAS; + num_child_micbiases = 0; + break; + case WM1831: + case CS47L24: + num_micbiases = LARGO_NUM_MICBIAS; + num_child_micbiases = 0; + break; + case WM8285: + case WM1840: + num_micbiases = CLEARWATER_NUM_MICBIAS; + num_child_micbiases = 0; + break; + case CS47L15: + num_micbiases = CS47L15_NUM_MICBIAS; + num_child_micbiases = CS47L15_NUM_CHILD_MICBIAS; + break; + case CS47L35: + num_micbiases = MARLEY_NUM_MICBIAS; + num_child_micbiases = MARLEY_NUM_CHILD_MICBIAS; + break; + default: + num_micbiases = MOON_NUM_MICBIAS; + num_child_micbiases = MOON_NUM_CHILD_MICBIAS; + break; + } + + if (micbiases) + *micbiases = num_micbiases; + if (child_micbiases) + *child_micbiases = num_child_micbiases; return 0; } -#endif - -const struct dev_pm_ops arizona_pm_ops = { - SET_RUNTIME_PM_OPS(arizona_runtime_suspend, - arizona_runtime_resume, - NULL) - SET_SYSTEM_SLEEP_PM_OPS(NULL, arizona_resume) -#ifdef CONFIG_PM_SLEEP - .resume_noirq = arizona_resume_noirq, -#endif -}; -EXPORT_SYMBOL_GPL(arizona_pm_ops); - -static struct mfd_cell early_devs[] = { - { .name = "arizona-ldo1" }, -}; - -static struct mfd_cell wm5102_devs[] = { - { .name = "arizona-micsupp" }, - { .name = "arizona-extcon" }, - { .name = "arizona-gpio" }, - { .name = "arizona-haptics" }, - { .name = "arizona-pwm" }, - { .name = "wm5102-codec" }, -}; - -static struct mfd_cell wm5110_devs[] = { - { .name = "arizona-micsupp" }, - { .name = "arizona-extcon" }, - { .name = "arizona-gpio" }, - { .name = "arizona-haptics" }, - { .name = "arizona-pwm" }, - { .name = "wm5110-codec" }, -}; +EXPORT_SYMBOL_GPL(arizona_get_num_micbias); int arizona_dev_init(struct arizona *arizona) { struct device *dev = arizona->dev; - const char *type_name; - unsigned int reg, val; + const char *type_name = "Unknown"; + unsigned int reg, val, mask; int (*apply_patch)(struct arizona *) = NULL; - int ret, i; + int ret, i, max_inputs, j; + unsigned int max_micbias = 0, num_child_micbias = 0; + unsigned int num_dmic_clksrc = 0; dev_set_drvdata(arizona->dev, arizona); mutex_init(&arizona->clk_lock); + mutex_init(&arizona->reg_setting_lock); + mutex_init(&arizona->rate_lock); + mutex_init(&arizona->dspclk_ena_lock); if (dev_get_platdata(arizona->dev)) memcpy(&arizona->pdata, dev_get_platdata(arizona->dev), sizeof(arizona->pdata)); + else + arizona_of_get_core_pdata(arizona); regcache_cache_only(arizona->regmap, true); + if (arizona->regmap_32bit) + regcache_cache_only(arizona->regmap_32bit, true); switch (arizona->type) { case WM5102: case WM5110: + case WM8280: + case WM8997: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L15: + case CS47L24: + case CS47L35: + case CS47L90: + case CS47L91: for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++) arizona->core_supplies[i].supply = wm5102_core_supplies[i]; @@ -482,11 +1648,25 @@ int arizona_dev_init(struct arizona *arizona) return -EINVAL; } - ret = mfd_add_devices(arizona->dev, -1, early_devs, - ARRAY_SIZE(early_devs), NULL, 0, NULL); - if (ret != 0) { - dev_err(dev, "Failed to add early children: %d\n", ret); - return ret; + /* Mark DCVDD as external, LDO1 driver will clear if internal */ + arizona->external_dcvdd = true; + + switch (arizona->type) { + case WM1831: + case CS47L15: + case CS47L24: + case CS47L35: + case CS47L90: + case CS47L91: + break; + default: + ret = mfd_add_devices(arizona->dev, -1, early_devs, + ARRAY_SIZE(early_devs), NULL, 0, NULL); + if (ret != 0) { + dev_err(dev, "Failed to add early children: %d\n", ret); + return ret; + } + break; } ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies, @@ -497,30 +1677,47 @@ int arizona_dev_init(struct arizona *arizona) goto err_early; } - arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD"); + /** + * Don't use devres here because the only device we have to get + * against is the MFD device and DCVDD will likely be supplied by + * one of its children. Meaning that the regulator will be + * destroyed by the time devres calls regulator put. + */ + arizona->dcvdd = regulator_get(arizona->dev, "DCVDD"); if (IS_ERR(arizona->dcvdd)) { ret = PTR_ERR(arizona->dcvdd); dev_err(dev, "Failed to request DCVDD: %d\n", ret); goto err_early; } + arizona->dcvdd_notifier.notifier_call = arizona_dcvdd_notify; + ret = regulator_register_notifier(arizona->dcvdd, + &arizona->dcvdd_notifier); + if (ret < 0) { + dev_err(dev, "Failed to register DCVDD notifier %d\n", ret); + goto err_dcvdd; + } + if (arizona->pdata.reset) { /* Start out with /RESET low to put the chip into reset */ - ret = gpio_request_one(arizona->pdata.reset, - GPIOF_DIR_OUT | GPIOF_INIT_LOW, - "arizona /RESET"); + ret = devm_gpio_request_one(arizona->dev, arizona->pdata.reset, + GPIOF_DIR_OUT | GPIOF_INIT_LOW, + "arizona /RESET"); if (ret != 0) { dev_err(dev, "Failed to request /RESET: %d\n", ret); - goto err_early; + goto err_notifier; } } + /* Ensure period of reset asserted before we apply the supplies */ + msleep(20); + ret = regulator_bulk_enable(arizona->num_core_supplies, arizona->core_supplies); if (ret != 0) { dev_err(dev, "Failed to enable core supplies: %d\n", ret); - goto err_early; + goto err_notifier; } ret = regulator_enable(arizona->dcvdd); @@ -529,13 +1726,68 @@ int arizona_dev_init(struct arizona *arizona) goto err_enable; } - if (arizona->pdata.reset) { - gpio_set_value_cansleep(arizona->pdata.reset, 1); - msleep(1); - } + arizona_disable_reset(arizona); regcache_cache_only(arizona->regmap, false); + if (arizona->regmap_32bit) + regcache_cache_only(arizona->regmap_32bit, false); + + /* Verify that this is a chip we know about */ + ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®); + if (ret != 0) { + dev_err(dev, "Failed to read ID register: %d\n", ret); + goto err_reset; + } + + switch (reg) { + case 0x5102: + case 0x5110: + case 0x6349: + case 0x6363: + case 0x8997: + case 0x6338: + case 0x6360: + case 0x6364: + case 0x6370: + break; + default: + dev_err(arizona->dev, "Unknown device ID: %x\n", reg); + goto err_reset; + } + + /* If we have a /RESET GPIO we'll already be reset */ + if (!arizona->pdata.reset) { + ret = arizona_soft_reset(arizona); + if (ret != 0) + goto err_reset; + } + + /* Ensure device startup is complete */ + switch (arizona->type) { + case WM5102: + ret = regmap_read(arizona->regmap, + ARIZONA_WRITE_SEQUENCER_CTRL_3, &val); + if (ret) { + dev_err(dev, + "Failed to check write sequencer state: %d\n", + ret); + } else if (val & 0x01) { + ret = wm5102_clear_write_sequencer(arizona); + if (ret) + return ret; + } + break; + default: + break; + } + + ret = arizona_wait_for_boot(arizona); + if (ret) { + dev_err(arizona->dev, "Device failed initial boot: %d\n", ret); + goto err_reset; + } + /* Read the device ID information & do device specific stuff */ ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®); if (ret != 0) { dev_err(dev, "Failed to read ID register: %d\n", ret); @@ -563,63 +1815,160 @@ int arizona_dev_init(struct arizona *arizona) arizona->rev &= 0x7; break; #endif -#ifdef CONFIG_MFD_WM5110 +#ifdef CONFIG_MFD_FLORIDA case 0x5110: - type_name = "WM5110"; - if (arizona->type != WM5110) { - dev_err(arizona->dev, "WM5110 registered as %d\n", + switch (arizona->type) { + case WM8280: + if (arizona->rev >= 0x5) + type_name = "WM8281"; + else + type_name = "WM8280"; + break; + + case WM5110: + type_name = "WM5110"; + break; + + default: + dev_err(arizona->dev, "Florida codec registered as %d\n", arizona->type); - arizona->type = WM5110; + arizona->type = WM8280; + type_name = "Florida"; + break; } - apply_patch = wm5110_patch; + apply_patch = florida_patch; break; #endif - default: - dev_err(arizona->dev, "Unknown device ID %x\n", reg); - goto err_reset; - } +#ifdef CONFIG_MFD_LARGO + case 0x6363: + switch (arizona->type) { + case CS47L24: + type_name = "CS47L24"; + break; - dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A'); + case WM1831: + type_name = "WM1831"; + break; - /* If we have a /RESET GPIO we'll already be reset */ - if (!arizona->pdata.reset) { - regcache_mark_dirty(arizona->regmap); + default: + dev_err(arizona->dev, "Largo codec registered as %d\n", + arizona->type); + arizona->type = CS47L24; + type_name = "Largo"; + break; + } + apply_patch = largo_patch; + break; +#endif +#ifdef CONFIG_MFD_WM8997 + case 0x8997: + type_name = "WM8997"; + if (arizona->type != WM8997) { + dev_err(arizona->dev, "WM8997 registered as %d\n", + arizona->type); + arizona->type = WM8997; + } + apply_patch = wm8997_patch; + break; +#endif +#ifdef CONFIG_MFD_VEGAS + case 0x6349: + switch (arizona->type) { + case WM8998: + type_name = "WM8998"; + break; - ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0); - if (ret != 0) { - dev_err(dev, "Failed to reset device: %d\n", ret); - goto err_reset; + case WM1814: + type_name = "WM1814"; + break; + + default: + dev_err(arizona->dev, + "Unknown Vegas codec registered as WM8998\n"); + arizona->type = WM8998; } - msleep(1); + apply_patch = vegas_patch; + break; +#endif +#ifdef CONFIG_MFD_CLEARWATER + case 0x6338: + switch (arizona->type) { + case WM8285: + type_name = "CS47L85"; + break; - ret = regcache_sync(arizona->regmap); - if (ret != 0) { - dev_err(dev, "Failed to sync device: %d\n", ret); - goto err_reset; + case WM1840: + type_name = "WM1840"; + break; + + default: + dev_err(arizona->dev, + "Unknown Clearwater codec registered as CS47L85\n"); + arizona->type = WM8285; } - } - switch (arizona->type) { - case WM5102: - ret = regmap_read(arizona->regmap, 0x19, &val); - if (ret != 0) - dev_err(dev, - "Failed to check write sequencer state: %d\n", - ret); - else if (val & 0x01) + apply_patch = clearwater_patch; + break; +#endif +#ifdef CONFIG_MFD_MARLEY + case 0x6360: + switch (arizona->type) { + case CS47L35: + type_name = "CS47L35"; break; - /* Fall through */ - default: - ret = arizona_wait_for_boot(arizona); - if (ret != 0) { + + default: dev_err(arizona->dev, - "Device failed initial boot: %d\n", ret); - goto err_reset; + "Unknown Marley codec registered as CS47L35\n"); + arizona->type = CS47L35; + } + + apply_patch = marley_patch; + break; +#endif +#ifdef CONFIG_MFD_MOON + case 0x6364: + switch (arizona->type) { + case CS47L90: + type_name = "CS47L90"; + break; + case CS47L91: + type_name = "CS47L91"; + break; + default: + dev_err(arizona->dev, + "Unknown Moon codec registered as CS47L90\n"); + arizona->type = CS47L90; + } + + apply_patch = moon_patch; + break; +#endif +#ifdef CONFIG_MFD_CS47L15 + case 0x6370: + switch (arizona->type) { + case CS47L15: + type_name = "CS47L15"; + break; + default: + arizona->type = CS47L15; + dev_err(arizona->dev, + "CS47L15 codec registered as %d\n", + arizona->type); + break; } + + apply_patch = cs47l15_patch; break; +#endif + default: + dev_err(arizona->dev, "Unknown device ID %x\n", reg); + goto err_reset; } + dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A'); + if (apply_patch) { ret = apply_patch(arizona); if (ret != 0) { @@ -630,31 +1979,57 @@ int arizona_dev_init(struct arizona *arizona) switch (arizona->type) { case WM5102: - ret = arizona_apply_hardware_patch(arizona); - if (ret != 0) { + ret = wm5102_apply_hardware_patch(arizona); + if (ret) { dev_err(arizona->dev, "Failed to apply hardware patch: %d\n", ret); goto err_reset; } break; + case WM5110: + case WM8280: + ret = wm5110_apply_sleep_patch(arizona); + if (ret) { + dev_err(arizona->dev, + "Failed to apply sleep patch: %d\n", + ret); + goto err_reset; + } + break; default: break; } } - for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { - if (!arizona->pdata.gpio_defaults[i]) - continue; + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8280: + case WM8997: + case WM8998: + case WM1814: + case WM1831: + case CS47L24: + for (i = 0; i < ARIZONA_MAX_GPIO_REGS; i++) { + if (!arizona->pdata.gpio_defaults[i]) + continue; + + regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i, + arizona->pdata.gpio_defaults[i]); + } + break; + default: + for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { + if (!arizona->pdata.gpio_defaults[i]) + continue; - regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i, - arizona->pdata.gpio_defaults[i]); + regmap_write(arizona->regmap, CLEARWATER_GPIO1_CTRL_1 + i, + arizona->pdata.gpio_defaults[i]); + } + break; } - pm_runtime_set_autosuspend_delay(arizona->dev, 100); - pm_runtime_use_autosuspend(arizona->dev); - pm_runtime_enable(arizona->dev); - /* Chip default */ if (!arizona->pdata.clk32k_src) arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2; @@ -678,7 +2053,9 @@ int arizona_dev_init(struct arizona *arizona) goto err_reset; } - for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) { + arizona_get_num_micbias(arizona, &max_micbias, &num_child_micbias); + + for (i = 0; i < max_micbias; i++) { if (!arizona->pdata.micbias[i].mV && !arizona->pdata.micbias[i].bypass) continue; @@ -689,38 +2066,149 @@ int arizona_dev_init(struct arizona *arizona) val = (arizona->pdata.micbias[i].mV - 1500) / 100; + mask = ARIZONA_MICB1_LVL_MASK | ARIZONA_MICB1_EXT_CAP | + ARIZONA_MICB1_BYPASS | ARIZONA_MICB1_RATE; + val <<= ARIZONA_MICB1_LVL_SHIFT; if (arizona->pdata.micbias[i].ext_cap) val |= ARIZONA_MICB1_EXT_CAP; - if (arizona->pdata.micbias[i].discharge) - val |= ARIZONA_MICB1_DISCH; + if (num_child_micbias == 0) { + mask |= ARIZONA_MICB1_DISCH; + if (arizona->pdata.micbias[i].discharge[0]) + val |= ARIZONA_MICB1_DISCH; + } - if (arizona->pdata.micbias[i].fast_start) + if (arizona->pdata.micbias[i].soft_start) val |= ARIZONA_MICB1_RATE; if (arizona->pdata.micbias[i].bypass) val |= ARIZONA_MICB1_BYPASS; regmap_update_bits(arizona->regmap, - ARIZONA_MIC_BIAS_CTRL_1 + i, - ARIZONA_MICB1_LVL_MASK | - ARIZONA_MICB1_DISCH | - ARIZONA_MICB1_BYPASS | - ARIZONA_MICB1_RATE, val); + ARIZONA_MIC_BIAS_CTRL_1 + i, + mask, val); + + if (num_child_micbias) { + val = 0; + mask = 0; + for (j = 0; j < num_child_micbias; j++) { + mask |= (ARIZONA_MICB1A_DISCH << j*4); + if (arizona->pdata.micbias[i].discharge[j]) + val |= (ARIZONA_MICB1A_DISCH << j*4); + } + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_BIAS_CTRL_5 + i*2, + mask, val); + } + } + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8280: + /* These arizona chips have 4 inputs and + settings for INxL and INxR are same*/ + max_inputs = 4; + break; + case WM8997: + case WM1831: + case CS47L24: + case WM8998: + case WM1814: + case CS47L35: + max_inputs = 2; + break; + case WM8285: + case WM1840: + /* DMIC Ref for IN4-6 is fixed for WM8285/1840 and + settings for INxL and INxR are different*/ + max_inputs = 3; + break; + case CS47L15: + max_inputs = 2; + break; + default: + /*DMIC Ref for IN3-5 is fixed for CS47L90 and + settings for INxL and INxR are different*/ + max_inputs = 2; + /* For CS47L90/91 dmic clk src can be set same as + pdm speaker clock this is used when pdm speaker + feedsback IV data via pdm input */ + num_dmic_clksrc = 5; + break; + } + + for (i = 0; i < num_dmic_clksrc; i++) { + regmap_update_bits(arizona->regmap, + ARIZONA_IN1R_CONTROL + (i * 8), + MOON_IN1_DMICCLK_SRC_MASK, + (arizona->pdata.dmic_clksrc[i]) + << MOON_IN1_DMICCLK_SRC_SHIFT); } - for (i = 0; i < ARIZONA_MAX_INPUT; i++) { - /* Default for both is 0 so noop with defaults */ - val = arizona->pdata.dmic_ref[i] - << ARIZONA_IN1_DMIC_SUP_SHIFT; - val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT; + for (i = 0; i < max_inputs; i++) { + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM1831: + case CS47L24: + val = arizona->pdata.dmic_ref[i] + << ARIZONA_IN1_DMIC_SUP_SHIFT; + val |= (arizona->pdata.inmode[i] & 2) + << (ARIZONA_IN1_MODE_SHIFT - 1); + val |= (arizona->pdata.inmode[i] & 1) + << ARIZONA_IN1_SINGLE_ENDED_SHIFT; + mask = ARIZONA_IN1_DMIC_SUP_MASK | + ARIZONA_IN1_MODE_MASK | + ARIZONA_IN1_SINGLE_ENDED_MASK; + break; + case WM8998: + case WM1814: + case CS47L15: + case CS47L35: + val = arizona->pdata.dmic_ref[i] + << ARIZONA_IN1_DMIC_SUP_SHIFT; + val |= (arizona->pdata.inmode[i] & 2) + << (ARIZONA_IN1_MODE_SHIFT - 1); + mask = ARIZONA_IN1_DMIC_SUP_MASK | + ARIZONA_IN1_MODE_MASK; + regmap_update_bits(arizona->regmap, + ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 8), + ARIZONA_IN1L_SRC_SE_MASK, + (arizona->pdata.inmode[i] & 1) + << ARIZONA_IN1L_SRC_SE_SHIFT); + regmap_update_bits(arizona->regmap, + ARIZONA_ADC_DIGITAL_VOLUME_1R + (i * 8), + ARIZONA_IN1R_SRC_SE_MASK, + (arizona->pdata.inmode[i] & 1) + << ARIZONA_IN1R_SRC_SE_SHIFT); + break; + default: + val = arizona->pdata.dmic_ref[i] + << ARIZONA_IN1_DMIC_SUP_SHIFT; + val |= (arizona->pdata.inmode[2*i] & 2) + << (ARIZONA_IN1_MODE_SHIFT - 1); + mask = ARIZONA_IN1_DMIC_SUP_MASK | + ARIZONA_IN1_MODE_MASK; + regmap_update_bits(arizona->regmap, + ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 8), + ARIZONA_IN1L_SRC_SE_MASK, + (arizona->pdata.inmode[2*i] & 1) + << ARIZONA_IN1L_SRC_SE_SHIFT); + regmap_update_bits(arizona->regmap, + ARIZONA_ADC_DIGITAL_VOLUME_1R + (i * 8), + ARIZONA_IN1R_SRC_SE_MASK, + (arizona->pdata.inmode[(2*i) + 1] & 1) + << ARIZONA_IN1R_SRC_SE_SHIFT); + break; + } regmap_update_bits(arizona->regmap, - ARIZONA_IN1L_CONTROL + (i * 8), - ARIZONA_IN1_DMIC_SUP_MASK | - ARIZONA_IN1_MODE_MASK, val); + ARIZONA_IN1L_CONTROL + (i * 8), mask, val); } for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) { @@ -750,11 +2238,17 @@ int arizona_dev_init(struct arizona *arizona) arizona->pdata.spk_fmt[i]); } + pm_runtime_set_active(arizona->dev); + pm_runtime_enable(arizona->dev); + /* Set up for interrupts */ ret = arizona_irq_init(arizona); if (ret != 0) goto err_reset; + pm_runtime_set_autosuspend_delay(arizona->dev, 100); + pm_runtime_use_autosuspend(arizona->dev); + arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error", arizona_clkgen_err, arizona); arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked", @@ -762,14 +2256,53 @@ int arizona_dev_init(struct arizona *arizona) arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked", arizona_underclocked, arizona); + /** + * Give us a sane default for the headphone impedance in case the + * extcon driver is not used + */ + arizona->hp_impedance_x100 = 3200; + switch (arizona->type) { case WM5102: ret = mfd_add_devices(arizona->dev, -1, wm5102_devs, ARRAY_SIZE(wm5102_devs), NULL, 0, NULL); break; + case WM8280: case WM5110: - ret = mfd_add_devices(arizona->dev, -1, wm5110_devs, - ARRAY_SIZE(wm5110_devs), NULL, 0, NULL); + ret = mfd_add_devices(arizona->dev, -1, florida_devs, + ARRAY_SIZE(florida_devs), NULL, 0, NULL); + break; + case WM1831: + case CS47L24: + ret = mfd_add_devices(arizona->dev, -1, largo_devs, + ARRAY_SIZE(largo_devs), NULL, 0, NULL); + break; + case WM8997: + ret = mfd_add_devices(arizona->dev, -1, wm8997_devs, + ARRAY_SIZE(wm8997_devs), NULL, 0, NULL); + break; + case WM8998: + case WM1814: + ret = mfd_add_devices(arizona->dev, -1, vegas_devs, + ARRAY_SIZE(vegas_devs), NULL, 0, NULL); + break; + case WM8285: + case WM1840: + ret = mfd_add_devices(arizona->dev, -1, clearwater_devs, + ARRAY_SIZE(clearwater_devs), NULL, 0, NULL); + break; + case CS47L15: + ret = mfd_add_devices(arizona->dev, -1, cs47l15_devs, + ARRAY_SIZE(cs47l15_devs), NULL, 0, NULL); + break; + case CS47L35: + ret = mfd_add_devices(arizona->dev, -1, marley_devs, + ARRAY_SIZE(marley_devs), NULL, 0, NULL); + break; + case CS47L90: + case CS47L91: + ret = mfd_add_devices(arizona->dev, -1, moon_devs, + ARRAY_SIZE(moon_devs), NULL, 0, NULL); break; } @@ -778,23 +2311,20 @@ int arizona_dev_init(struct arizona *arizona) goto err_irq; } -#ifdef CONFIG_PM_RUNTIME - regulator_disable(arizona->dcvdd); -#endif - return 0; err_irq: arizona_irq_exit(arizona); err_reset: - if (arizona->pdata.reset) { - gpio_set_value_cansleep(arizona->pdata.reset, 0); - gpio_free(arizona->pdata.reset); - } + arizona_enable_reset(arizona); regulator_disable(arizona->dcvdd); err_enable: regulator_bulk_disable(arizona->num_core_supplies, arizona->core_supplies); +err_notifier: + regulator_unregister_notifier(arizona->dcvdd, &arizona->dcvdd_notifier); +err_dcvdd: + regulator_put(arizona->dcvdd); err_early: mfd_remove_devices(dev); return ret; @@ -803,12 +2333,22 @@ EXPORT_SYMBOL_GPL(arizona_dev_init); int arizona_dev_exit(struct arizona *arizona) { + pm_runtime_disable(arizona->dev); + disable_irq(arizona->irq); + + regulator_disable(arizona->dcvdd); + regulator_unregister_notifier(arizona->dcvdd, &arizona->dcvdd_notifier); + regulator_put(arizona->dcvdd); + mfd_remove_devices(arizona->dev); arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona); arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona); arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona); - pm_runtime_disable(arizona->dev); arizona_irq_exit(arizona); + arizona_enable_reset(arizona); + + regulator_bulk_disable(arizona->num_core_supplies, + arizona->core_supplies); return 0; } EXPORT_SYMBOL_GPL(arizona_dev_exit); diff --git a/drivers/mfd/arizona-i2c.c b/drivers/mfd/arizona-i2c.c index 44a1bb96984..fe211f2f1f7 100644 --- a/drivers/mfd/arizona-i2c.c +++ b/drivers/mfd/arizona-i2c.c @@ -23,26 +23,70 @@ #include "arizona.h" static int arizona_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { struct arizona *arizona; const struct regmap_config *regmap_config; + const struct regmap_config *regmap_32bit_config = NULL; + unsigned long type; int ret; - switch (id->driver_data) { + if (i2c->dev.of_node) + type = arizona_of_get_type(&i2c->dev); + else + type = id->driver_data; + + switch (type) { #ifdef CONFIG_MFD_WM5102 case WM5102: regmap_config = &wm5102_i2c_regmap; break; #endif -#ifdef CONFIG_MFD_WM5110 +#ifdef CONFIG_MFD_FLORIDA + case WM8280: case WM5110: - regmap_config = &wm5110_i2c_regmap; + regmap_config = &florida_i2c_regmap; + break; +#endif +#ifdef CONFIG_MFD_WM8997 + case WM8997: + regmap_config = &wm8997_i2c_regmap; + break; +#endif +#ifdef CONFIG_MFD_VEGAS + case WM8998: + case WM1814: + regmap_config = &vegas_i2c_regmap; + break; +#endif +#ifdef CONFIG_MFD_CLEARWATER + case WM8285: + case WM1840: + regmap_config = &clearwater_16bit_i2c_regmap; + regmap_32bit_config = &clearwater_32bit_i2c_regmap; + break; +#endif +#ifdef CONFIG_MFD_MARLEY + case CS47L35: + regmap_config = &marley_16bit_i2c_regmap; + regmap_32bit_config = &marley_32bit_i2c_regmap; + break; +#endif +#ifdef CONFIG_MFD_MOON + case CS47L90: + case CS47L91: + regmap_config = &moon_16bit_i2c_regmap; + regmap_32bit_config = &moon_32bit_i2c_regmap; + break; +#endif +#ifdef CONFIG_MFD_CS47L15 + case CS47L15: + regmap_config = &cs47l15_16bit_i2c_regmap; + regmap_32bit_config = &cs47l15_32bit_i2c_regmap; break; #endif default: - dev_err(&i2c->dev, "Unknown device type %ld\n", - id->driver_data); + dev_err(&i2c->dev, "Unknown device type %ld\n", type); return -EINVAL; } @@ -58,7 +102,19 @@ static int arizona_i2c_probe(struct i2c_client *i2c, return ret; } - arizona->type = id->driver_data; + if (regmap_32bit_config) { + arizona->regmap_32bit = devm_regmap_init_i2c(i2c, + regmap_32bit_config); + if (IS_ERR(arizona->regmap_32bit)) { + ret = PTR_ERR(arizona->regmap_32bit); + dev_err(&i2c->dev, + "Failed to allocate dsp register map: %d\n", + ret); + return ret; + } + } + + arizona->type = type; arizona->dev = &i2c->dev; arizona->irq = i2c->irq; @@ -74,7 +130,19 @@ static int arizona_i2c_remove(struct i2c_client *i2c) static const struct i2c_device_id arizona_i2c_id[] = { { "wm5102", WM5102 }, + { "wm8280", WM8280 }, + { "wm8281", WM8280 }, { "wm5110", WM5110 }, + { "wm8997", WM8997 }, + { "wm8998", WM8998 }, + { "wm1814", WM1814 }, + { "wm8285", WM8285 }, + { "wm1840", WM1840 }, + { "cs47l15", CS47L15 }, + { "cs47l35", CS47L35 }, + { "cs47l85", WM8285 }, + { "cs47l90", CS47L90 }, + { "cs47l91", CS47L91 }, { } }; MODULE_DEVICE_TABLE(i2c, arizona_i2c_id); @@ -84,6 +152,7 @@ static struct i2c_driver arizona_i2c_driver = { .name = "arizona", .owner = THIS_MODULE, .pm = &arizona_pm_ops, + .of_match_table = of_match_ptr(arizona_of_match), }, .probe = arizona_i2c_probe, .remove = arizona_i2c_remove, diff --git a/drivers/mfd/arizona-irq.c b/drivers/mfd/arizona-irq.c index 64cd9b6dac9..b034f98682a 100644 --- a/drivers/mfd/arizona-irq.c +++ b/drivers/mfd/arizona-irq.c @@ -1,6 +1,7 @@ /* * Arizona interrupt support * + * Copyright 2014 CirrusLogic, Inc. * Copyright 2012 Wolfson Microelectronics plc * * Author: Mark Brown @@ -26,18 +27,24 @@ #include "arizona.h" -static int arizona_map_irq(struct arizona *arizona, int irq) +int arizona_map_irq(struct arizona *arizona, int irq) { int ret; - ret = regmap_irq_get_virq(arizona->aod_irq_chip, irq); - if (ret < 0) - ret = regmap_irq_get_virq(arizona->irq_chip, irq); + if (arizona->aod_irq_chip) { + ret = regmap_irq_get_virq(arizona->aod_irq_chip, irq); + if (ret >= 0) + return ret; + } - return ret; + if (arizona->irq_chip) + return regmap_irq_get_virq(arizona->irq_chip, irq); + + return -EINVAL; } +EXPORT_SYMBOL_GPL(arizona_map_irq); -int arizona_request_irq(struct arizona *arizona, int irq, char *name, +int arizona_request_irq(struct arizona *arizona, int irq, const char *name, irq_handler_t handler, void *data) { irq = arizona_map_irq(arizona, irq); @@ -91,11 +98,30 @@ static irqreturn_t arizona_ctrlif_err(int irq, void *data) return IRQ_HANDLED; } +/* + * Examine the IRQ pin status to see if we're really done + * if the interrupt controller can't do it for us. + */ +static bool arizona_irq_still_pending(struct arizona *arizona) +{ + bool still_pending = false; + + if (arizona->pdata.irq_gpio) { + if (arizona->pdata.irq_flags & IRQF_TRIGGER_RISING && + gpio_get_value_cansleep(arizona->pdata.irq_gpio)) { + still_pending = true; + } else if (arizona->pdata.irq_flags & IRQF_TRIGGER_FALLING && + !gpio_get_value_cansleep(arizona->pdata.irq_gpio)) { + still_pending = true; + } + } + return still_pending; +} + static irqreturn_t arizona_irq_thread(int irq, void *data) { struct arizona *arizona = data; - bool poll; - unsigned int val; + unsigned int val, nest_irq; int ret; ret = pm_runtime_get_sync(arizona->dev); @@ -105,38 +131,36 @@ static irqreturn_t arizona_irq_thread(int irq, void *data) } do { - poll = false; - - /* Always handle the AoD domain */ - handle_nested_irq(irq_find_mapping(arizona->virq, 0)); - - /* - * Check if one of the main interrupts is asserted and only - * check that domain if it is. - */ - ret = regmap_read(arizona->regmap, ARIZONA_IRQ_PIN_STATUS, - &val); - if (ret == 0 && val & ARIZONA_IRQ1_STS) { + if (arizona->aod_irq_chip && arizona->irq_chip) { + /* Only handle each domain if it has triggered an IRQ */ + ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ1, + &val); + if (ret == 0 && val != 0) { + nest_irq = irq_find_mapping(arizona->virq, 0); + handle_nested_irq(nest_irq); + } else if (ret != 0) { + dev_err(arizona->dev, + "Failed to read AOD IRQ1 %d\n", + ret); + } + + ret = regmap_read(arizona->regmap, + ARIZONA_IRQ_PIN_STATUS, + &val); + if (ret == 0 && val & ARIZONA_IRQ1_STS) { + nest_irq = irq_find_mapping(arizona->virq, 1); + handle_nested_irq(nest_irq); + } else if (ret != 0) { + dev_err(arizona->dev, + "Failed to read main IRQ status: %d\n", + ret); + } + } else if (arizona->aod_irq_chip) { + handle_nested_irq(irq_find_mapping(arizona->virq, 0)); + } else if (arizona->irq_chip) { handle_nested_irq(irq_find_mapping(arizona->virq, 1)); - } else if (ret != 0) { - dev_err(arizona->dev, - "Failed to read main IRQ status: %d\n", ret); } - - /* - * Poll the IRQ pin status to see if we're really done - * if the interrupt controller can't do it for us. - */ - if (!arizona->pdata.irq_gpio) { - break; - } else if (arizona->pdata.irq_flags & IRQF_TRIGGER_RISING && - gpio_get_value_cansleep(arizona->pdata.irq_gpio)) { - poll = true; - } else if (arizona->pdata.irq_flags & IRQF_TRIGGER_FALLING && - !gpio_get_value_cansleep(arizona->pdata.irq_gpio)) { - poll = true; - } - } while (poll); + } while (arizona_irq_still_pending(arizona)); pm_runtime_mark_last_busy(arizona->dev); pm_runtime_put_autosuspend(arizona->dev); @@ -144,27 +168,37 @@ static irqreturn_t arizona_irq_thread(int irq, void *data) return IRQ_HANDLED; } -static void arizona_irq_enable(struct irq_data *data) +static void arizona_irq_dummy(struct irq_data *data) { } -static void arizona_irq_disable(struct irq_data *data) +static int arizona_irq_set_wake(struct irq_data *data, unsigned int on) { + struct arizona *arizona = irq_data_get_irq_chip_data(data); + + return irq_set_irq_wake(arizona->irq, on); } static struct irq_chip arizona_irq_chip = { .name = "arizona", - .irq_disable = arizona_irq_disable, - .irq_enable = arizona_irq_enable, + .irq_disable = arizona_irq_dummy, + .irq_enable = arizona_irq_dummy, + .irq_ack = arizona_irq_dummy, + .irq_mask = arizona_irq_dummy, + .irq_unmask = arizona_irq_dummy, + .irq_set_wake = arizona_irq_set_wake, }; +static struct lock_class_key arizona_irq_lock_class; + static int arizona_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { - struct regmap_irq_chip_data *data = h->host_data; + struct arizona *data = h->host_data; irq_set_chip_data(virq, data); - irq_set_chip_and_handler(virq, &arizona_irq_chip, handle_edge_irq); + irq_set_lockdep_class(virq, &arizona_irq_lock_class); + irq_set_chip_and_handler(virq, &arizona_irq_chip, handle_simple_irq); irq_set_nested_thread(virq, 1); /* ARM needs us to explicitly flag the IRQ as valid @@ -190,6 +224,7 @@ int arizona_irq_init(struct arizona *arizona) const struct regmap_irq_chip *aod, *irq; bool ctrlif_error = true; struct irq_data *irq_data; + unsigned int irq_ctrl_reg = ARIZONA_IRQ_CTRL_1; switch (arizona->type) { #ifdef CONFIG_MFD_WM5102 @@ -200,21 +235,105 @@ int arizona_irq_init(struct arizona *arizona) ctrlif_error = false; break; #endif -#ifdef CONFIG_MFD_WM5110 +#ifdef CONFIG_MFD_FLORIDA + case WM8280: case WM5110: - aod = &wm5110_aod; - irq = &wm5110_irq; + aod = &florida_aod; + + switch (arizona->rev) { + case 0 ... 2: + irq = &florida_irq; + break; + default: + irq = &florida_revd_irq; + break; + } ctrlif_error = false; break; +#endif +#ifdef CONFIG_MFD_CLEARWATER + case WM8285: + case WM1840: + aod = &clearwater_irq; + irq = NULL; + + ctrlif_error = false; + irq_ctrl_reg = CLEARWATER_IRQ1_CTRL; + break; +#endif +#ifdef CONFIG_MFD_LARGO + case WM1831: + case CS47L24: + aod = NULL; + irq = &largo_irq; + + ctrlif_error = false; + break; +#endif +#ifdef CONFIG_MFD_WM8997 + case WM8997: + aod = &wm8997_aod; + irq = &wm8997_irq; + + ctrlif_error = false; + break; +#endif +#ifdef CONFIG_MFD_VEGAS + case WM8998: + case WM1814: + aod = &vegas_aod; + irq = &vegas_irq; + + ctrlif_error = false; + break; +#endif +#ifdef CONFIG_MFD_MARLEY + case CS47L35: + aod = &marley_irq; + irq = NULL; + + ctrlif_error = false; + irq_ctrl_reg = CLEARWATER_IRQ1_CTRL; + break; +#endif +#ifdef CONFIG_MFD_MOON + case CS47L90: + case CS47L91: + aod = &moon_irq; + irq = NULL; + + ctrlif_error = false; + irq_ctrl_reg = CLEARWATER_IRQ1_CTRL; + break; +#endif +#ifdef CONFIG_MFD_CS47L15 + case CS47L15: + aod = &cs47l15_irq; + irq = NULL; + + ctrlif_error = false; + irq_ctrl_reg = CLEARWATER_IRQ1_CTRL; + break; #endif default: BUG_ON("Unknown Arizona class device" == NULL); return -EINVAL; } - /* Disable all wake sources by default */ - regmap_write(arizona->regmap, ARIZONA_WAKE_CONTROL, 0); + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + /* Disable all wake sources by default */ + regmap_write(arizona->regmap, ARIZONA_WAKE_CONTROL, 0); + break; + default: + break; + } /* Read the flags from the interrupt controller if not specified */ if (!arizona->pdata.irq_flags) { @@ -243,7 +362,7 @@ int arizona_irq_init(struct arizona *arizona) if (arizona->pdata.irq_flags & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_RISING)) { - ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ_CTRL_1, + ret = regmap_update_bits(arizona->regmap, irq_ctrl_reg, ARIZONA_IRQ_POL, 0); if (ret != 0) { dev_err(arizona->dev, "Couldn't set IRQ polarity: %d\n", @@ -263,45 +382,26 @@ int arizona_irq_init(struct arizona *arizona) goto err; } - ret = regmap_add_irq_chip(arizona->regmap, - irq_create_mapping(arizona->virq, 0), - IRQF_ONESHOT, -1, aod, - &arizona->aod_irq_chip); - if (ret != 0) { - dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret); - goto err_domain; - } - - ret = regmap_add_irq_chip(arizona->regmap, - irq_create_mapping(arizona->virq, 1), - IRQF_ONESHOT, -1, irq, - &arizona->irq_chip); - if (ret != 0) { - dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret); - goto err_aod; - } - - /* Make sure the boot done IRQ is unmasked for resumes */ - i = arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE); - ret = request_threaded_irq(i, NULL, arizona_boot_done, IRQF_ONESHOT, - "Boot done", arizona); - if (ret != 0) { - dev_err(arizona->dev, "Failed to request boot done %d: %d\n", - arizona->irq, ret); - goto err_boot_done; + if (aod) { + ret = regmap_add_irq_chip(arizona->regmap, + irq_create_mapping(arizona->virq, 0), + IRQF_ONESHOT, 0, aod, + &arizona->aod_irq_chip); + if (ret != 0) { + dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", + ret); + goto err; + } } - /* Handle control interface errors in the core */ - if (ctrlif_error) { - i = arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR); - ret = request_threaded_irq(i, NULL, arizona_ctrlif_err, - IRQF_ONESHOT, - "Control interface error", arizona); + if (irq) { + ret = regmap_add_irq_chip(arizona->regmap, + irq_create_mapping(arizona->virq, 1), + IRQF_ONESHOT, 0, irq, + &arizona->irq_chip); if (ret != 0) { - dev_err(arizona->dev, - "Failed to request CTRLIF_ERR %d: %d\n", - arizona->irq, ret); - goto err_ctrlif; + dev_err(arizona->dev, "Failed to add main IRQs: %d\n", ret); + goto err_aod; } } @@ -334,19 +434,42 @@ int arizona_irq_init(struct arizona *arizona) goto err_main_irq; } + /* Make sure the boot done IRQ is unmasked for resumes */ + i = arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE); + ret = request_threaded_irq(i, NULL, arizona_boot_done, IRQF_ONESHOT, + "Boot done", arizona); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request boot done %d: %d\n", + arizona->irq, ret); + goto err_boot_done; + } + + /* Handle control interface errors in the core */ + if (ctrlif_error) { + i = arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR); + ret = request_threaded_irq(i, NULL, arizona_ctrlif_err, + IRQF_ONESHOT, + "Control interface error", arizona); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to request CTRLIF_ERR %d: %d\n", + arizona->irq, ret); + goto err_ctrlif; + } + } + return 0; -err_main_irq: - free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR), arizona); err_ctrlif: free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona); err_boot_done: + free_irq(arizona->irq, arizona); +err_main_irq: regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1), arizona->irq_chip); err_aod: regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0), arizona->aod_irq_chip); -err_domain: err: return ret; } diff --git a/drivers/mfd/arizona-spi.c b/drivers/mfd/arizona-spi.c index b57e642d2b4..6c7cc08ded1 100644 --- a/drivers/mfd/arizona-spi.c +++ b/drivers/mfd/arizona-spi.c @@ -1,6 +1,7 @@ /* * arizona-spi.c -- Arizona SPI bus interface * + * Copyright 2014 Cirrus Logic * Copyright 2012 Wolfson Microelectronics plc * * Author: Mark Brown @@ -27,22 +28,61 @@ static int arizona_spi_probe(struct spi_device *spi) const struct spi_device_id *id = spi_get_device_id(spi); struct arizona *arizona; const struct regmap_config *regmap_config; + const struct regmap_config *regmap_32bit_config = NULL; + unsigned long type; int ret; - switch (id->driver_data) { + if (spi->dev.of_node) + type = arizona_of_get_type(&spi->dev); + else + type = id->driver_data; + + switch (type) { #ifdef CONFIG_MFD_WM5102 case WM5102: regmap_config = &wm5102_spi_regmap; break; #endif -#ifdef CONFIG_MFD_WM5110 +#ifdef CONFIG_MFD_FLORIDA + case WM8280: case WM5110: - regmap_config = &wm5110_spi_regmap; + regmap_config = &florida_spi_regmap; + break; +#endif +#ifdef CONFIG_MFD_CLEARWATER + case WM8285: + case WM1840: + regmap_config = &clearwater_16bit_spi_regmap; + regmap_32bit_config = &clearwater_32bit_spi_regmap; + break; +#endif +#ifdef CONFIG_MFD_LARGO + case WM1831: + case CS47L24: + regmap_config = &largo_spi_regmap; + break; +#endif +#ifdef CONFIG_MFD_MARLEY + case CS47L35: + regmap_config = &marley_16bit_spi_regmap; + regmap_32bit_config = &marley_32bit_spi_regmap; + break; +#endif +#ifdef CONFIG_MFD_MOON + case CS47L90: + case CS47L91: + regmap_config = &moon_16bit_spi_regmap; + regmap_32bit_config = &moon_32bit_spi_regmap; + break; +#endif +#ifdef CONFIG_MFD_CS47L15 + case CS47L15: + regmap_config = &cs47l15_16bit_spi_regmap; + regmap_32bit_config = &cs47l15_32bit_spi_regmap; break; #endif default: - dev_err(&spi->dev, "Unknown device type %ld\n", - id->driver_data); + dev_err(&spi->dev, "Unknown device type %ld\n", type); return -EINVAL; } @@ -58,7 +98,19 @@ static int arizona_spi_probe(struct spi_device *spi) return ret; } - arizona->type = id->driver_data; + if (regmap_32bit_config) { + arizona->regmap_32bit = devm_regmap_init_spi(spi, + regmap_32bit_config); + if (IS_ERR(arizona->regmap_32bit)) { + ret = PTR_ERR(arizona->regmap_32bit); + dev_err(&spi->dev, + "Failed to allocate dsp register map: %d\n", + ret); + return ret; + } + } + + arizona->type = type; arizona->dev = &spi->dev; arizona->irq = spi->irq; @@ -74,7 +126,18 @@ static int arizona_spi_remove(struct spi_device *spi) static const struct spi_device_id arizona_spi_ids[] = { { "wm5102", WM5102 }, + { "wm8280", WM8280 }, + { "wm8281", WM8280 }, { "wm5110", WM5110 }, + { "wm8285", WM8285 }, + { "wm1840", WM1840 }, + { "wm1831", WM1831 }, + { "cs47l15", CS47L15 }, + { "cs47l24", CS47L24 }, + { "cs47l35", CS47L35 }, + { "cs47l85", WM8285 }, + { "cs47l90", CS47L90 }, + { "cs47l91", CS47L91 }, { }, }; MODULE_DEVICE_TABLE(spi, arizona_spi_ids); @@ -84,6 +147,7 @@ static struct spi_driver arizona_spi_driver = { .name = "arizona", .owner = THIS_MODULE, .pm = &arizona_pm_ops, + .of_match_table = of_match_ptr(arizona_of_match), }, .probe = arizona_spi_probe, .remove = arizona_spi_remove, diff --git a/drivers/mfd/arizona.h b/drivers/mfd/arizona.h index 9798ae5da67..9a54d089d7c 100644 --- a/drivers/mfd/arizona.h +++ b/drivers/mfd/arizona.h @@ -1,6 +1,7 @@ /* - * wm5102.h -- WM5102 MFD internals + * arizona.h -- WM5102 MFD internals * + * Copyright 2014 Cirrus Logic * Copyright 2012 Wolfson Microelectronics plc * * Author: Mark Brown @@ -10,9 +11,10 @@ * published by the Free Software Foundation. */ -#ifndef _WM5102_H -#define _WM5102_H +#ifndef _ARIZONA_H +#define _ARIZONA_H +#include #include #include @@ -21,20 +23,72 @@ struct wm_arizona; extern const struct regmap_config wm5102_i2c_regmap; extern const struct regmap_config wm5102_spi_regmap; -extern const struct regmap_config wm5110_i2c_regmap; -extern const struct regmap_config wm5110_spi_regmap; +extern const struct regmap_config florida_i2c_regmap; +extern const struct regmap_config florida_spi_regmap; + +extern const struct regmap_config clearwater_16bit_i2c_regmap; +extern const struct regmap_config clearwater_16bit_spi_regmap; +extern const struct regmap_config clearwater_32bit_spi_regmap; +extern const struct regmap_config clearwater_32bit_i2c_regmap; + +extern const struct regmap_config cs47l15_16bit_i2c_regmap; +extern const struct regmap_config cs47l15_16bit_spi_regmap; +extern const struct regmap_config cs47l15_32bit_spi_regmap; +extern const struct regmap_config cs47l15_32bit_i2c_regmap; + +extern const struct regmap_config marley_16bit_i2c_regmap; +extern const struct regmap_config marley_16bit_spi_regmap; +extern const struct regmap_config marley_32bit_spi_regmap; +extern const struct regmap_config marley_32bit_i2c_regmap; + +extern const struct regmap_config moon_16bit_i2c_regmap; +extern const struct regmap_config moon_16bit_spi_regmap; +extern const struct regmap_config moon_32bit_spi_regmap; +extern const struct regmap_config moon_32bit_i2c_regmap; + +extern const struct regmap_config wm8997_i2c_regmap; + +extern const struct regmap_config vegas_i2c_regmap; + +extern const struct regmap_config largo_spi_regmap; extern const struct dev_pm_ops arizona_pm_ops; +extern const struct of_device_id arizona_of_match[]; + extern const struct regmap_irq_chip wm5102_aod; extern const struct regmap_irq_chip wm5102_irq; -extern const struct regmap_irq_chip wm5110_aod; -extern const struct regmap_irq_chip wm5110_irq; +extern const struct regmap_irq_chip florida_aod; +extern const struct regmap_irq_chip florida_irq; +extern const struct regmap_irq_chip florida_revd_irq; + +extern const struct regmap_irq_chip cs47l15_irq; +extern const struct regmap_irq_chip clearwater_irq; +extern const struct regmap_irq_chip moon_irq; + +extern const struct regmap_irq_chip wm8997_aod; +extern const struct regmap_irq_chip wm8997_irq; + +extern struct regmap_irq_chip vegas_aod; +extern struct regmap_irq_chip vegas_irq; + +extern const struct regmap_irq_chip largo_irq; + +extern const struct regmap_irq_chip marley_irq; int arizona_dev_init(struct arizona *arizona); int arizona_dev_exit(struct arizona *arizona); int arizona_irq_init(struct arizona *arizona); int arizona_irq_exit(struct arizona *arizona); +#ifdef CONFIG_OF +unsigned long arizona_of_get_type(struct device *dev); +#else +static inline unsigned long arizona_of_get_type(struct device *dev) +{ + return 0; +} +#endif + #endif diff --git a/drivers/mfd/clearwater-tables.c b/drivers/mfd/clearwater-tables.c new file mode 100644 index 00000000000..17a255fdc56 --- /dev/null +++ b/drivers/mfd/clearwater-tables.c @@ -0,0 +1,3378 @@ +/* + * clearwater-tables.c -- data tables for CLEARWATER class codecs + * + * Copyright 2014 Wolfson Microelectronics plc + * + * Author: Nariman Poushin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include + +#include "arizona.h" + +static const struct reg_sequence clearwater_reva_16_patch[] = { + { 0x80, 0x0003 }, + { 0x213, 0x03E4 }, + { 0x177, 0x0281 }, + { 0x197, 0x0281 }, + { 0x1B7, 0x0281 }, + { 0x4B1, 0x010A }, + { 0x4CF, 0x0933 }, + { 0x36C, 0x011B }, + { 0x4B8, 0x1120 }, + { 0x4A0, 0x3280 }, + { 0x4A1, 0x3200 }, + { 0x4A2, 0x3200 }, + { 0x441, 0xC050 }, + { 0x4A4, 0x000B }, + { 0x4A5, 0x000B }, + { 0x4A6, 0x000B }, + { 0x4E2, 0x1E1D }, + { 0x4E3, 0x1E1D }, + { 0x4E4, 0x1E1D }, + { 0x293, 0x0080 }, + { 0x17D, 0x0303 }, + { 0x19D, 0x0303 }, + { 0x27E, 0x0000 }, + { 0x80, 0x0000 }, + { 0x80, 0x0000 }, + { 0x448, 0x003f }, +}; + +static const struct reg_sequence clearwater_revc_16_patch[] = { + { 0x27E, 0x0000 }, + { 0x2C2, 0x5 }, + { 0x448, 0x003f }, +}; + +/* this patch is required for EDRE on RevA*/ +static const struct reg_sequence clearwater_reva_32_patch[] = { + { 0x3000, 0xC2253632}, + { 0x3002, 0xC2300001}, + { 0x3004, 0x8225100E}, + { 0x3006, 0x22251803}, + { 0x3008, 0x82310B00}, + { 0x300A, 0xE231023B}, + { 0x300C, 0x2313B01}, + { 0x300E, 0x62300000}, + { 0x3010, 0xE2314288}, + { 0x3012, 0x2310B00}, + { 0x3014, 0x2310B00}, + { 0x3016, 0x4050100}, + { 0x3018, 0x42310C02}, + { 0x301A, 0xE2310227}, + { 0x301C, 0x2313B01}, + { 0x301E, 0xE2314266}, + { 0x3020, 0xE2315294}, + { 0x3022, 0x2310B00}, + { 0x3024, 0x2310B00}, + { 0x3026, 0x2251100}, + { 0x3028, 0x2251401}, + { 0x302A, 0x2250200}, + { 0x302C, 0x2251001}, + { 0x302E, 0x2250200}, + { 0x3030, 0xE2310266}, + { 0x3032, 0x82314B15}, + { 0x3034, 0x82310B15}, + { 0x3036, 0xE2315294}, + { 0x3038, 0x2310B00}, + { 0x303A, 0x8225160D}, + { 0x303C, 0x225F501}, + { 0x303E, 0x8225061C}, + { 0x3040, 0x2251000}, + { 0x3042, 0x4051101}, + { 0x3044, 0x2251800}, + { 0x3046, 0x42251203}, + { 0x3048, 0x2251101}, + { 0x304A, 0xC2251300}, + { 0x304C, 0x2225FB02}, + { 0x3050, 0xC2263632}, + { 0x3052, 0xC2300001}, + { 0x3054, 0x8226100E}, + { 0x3056, 0x22261803}, + { 0x3058, 0x82310B02}, + { 0x305A, 0xE231023B}, + { 0x305C, 0x2313B01}, + { 0x305E, 0x62300000}, + { 0x3060, 0xE2314288}, + { 0x3062, 0x2310B00}, + { 0x3064, 0x2310B00}, + { 0x3066, 0x4050000}, + { 0x3068, 0x42310C03}, + { 0x306A, 0xE2310227}, + { 0x306C, 0x2313B01}, + { 0x306E, 0xE2314266}, + { 0x3070, 0xE2315294}, + { 0x3072, 0x2310B00}, + { 0x3074, 0x2310B00}, + { 0x3076, 0x2261100}, + { 0x3078, 0x2261401}, + { 0x307A, 0x2260200}, + { 0x307C, 0x2261001}, + { 0x307E, 0x2260200}, + { 0x3080, 0xE2310266}, + { 0x3082, 0x82314B17}, + { 0x3084, 0x82310B17}, + { 0x3086, 0xE2315294}, + { 0x3088, 0x2310B00}, + { 0x308A, 0x8226160D}, + { 0x308C, 0x226F501}, + { 0x308E, 0x8226061C}, + { 0x3090, 0x2261000}, + { 0x3092, 0x4051101}, + { 0x3094, 0x2261800}, + { 0x3096, 0x42261203}, + { 0x3098, 0x2261101}, + { 0x309A, 0xC2261300}, + { 0x309C, 0x2226FB02}, + { 0x309E, 0xF000}, + { 0x30A0, 0xC2273632}, + { 0x30A2, 0xC2400001}, + { 0x30A4, 0x8227100E}, + { 0x30A6, 0x22271803}, + { 0x30A8, 0x82410B00}, + { 0x30AA, 0xE241023B}, + { 0x30AC, 0x2413B01}, + { 0x30AE, 0x62400000}, + { 0x30B0, 0xE2414288}, + { 0x30B2, 0x2410B00}, + { 0x30B4, 0x2410B00}, + { 0x30B6, 0x4050300}, + { 0x30B8, 0x42410C02}, + { 0x30BA, 0xE2410227}, + { 0x30BC, 0x2413B01}, + { 0x30BE, 0xE2414266}, + { 0x30C0, 0xE2415294}, + { 0x30C2, 0x2410B00}, + { 0x30C4, 0x2410B00}, + { 0x30C6, 0x2271100}, + { 0x30C8, 0x2271401}, + { 0x30CA, 0x2270200}, + { 0x30CC, 0x2271001}, + { 0x30CE, 0x2270200}, + { 0x30D0, 0xE2410266}, + { 0x30D2, 0x82414B15}, + { 0x30D4, 0x82410B15}, + { 0x30D6, 0xE2415294}, + { 0x30D8, 0x2410B00}, + { 0x30DA, 0x8227160D}, + { 0x30DC, 0x227F501}, + { 0x30DE, 0x8227061C}, + { 0x30E0, 0x2271000}, + { 0x30E2, 0x4051101}, + { 0x30E4, 0x2271800}, + { 0x30E6, 0x42271203}, + { 0x30E8, 0x2271101}, + { 0x30EA, 0xC2271300}, + { 0x30EC, 0x2227FB02}, + { 0x30F0, 0xC2283632}, + { 0x30F2, 0xC2400001}, + { 0x30F4, 0x8228100E}, + { 0x30F6, 0x22281803}, + { 0x30F8, 0x82410B02}, + { 0x30FA, 0xE241023B}, + { 0x30FC, 0x2413B01}, + { 0x30FE, 0x62400000}, + { 0x3100, 0xE2414288}, + { 0x3102, 0x2410B00}, + { 0x3104, 0x2410B00}, + { 0x3106, 0x4050200}, + { 0x3108, 0x42410C03}, + { 0x310A, 0xE2410227}, + { 0x310C, 0x2413B01}, + { 0x310E, 0xE2414266}, + { 0x3110, 0xE2415294}, + { 0x3112, 0x2410B00}, + { 0x3114, 0x2410B00}, + { 0x3116, 0x2281100}, + { 0x3118, 0x2281401}, + { 0x311A, 0x2280200}, + { 0x311C, 0x2281001}, + { 0x311E, 0x2280200}, + { 0x3120, 0xE2410266}, + { 0x3122, 0x82414B17}, + { 0x3124, 0x82410B17}, + { 0x3126, 0xE2415294}, + { 0x3128, 0x2410B00}, + { 0x312A, 0x8228160D}, + { 0x312C, 0x228F501}, + { 0x312E, 0x8228061C}, + { 0x3130, 0x2281000}, + { 0x3132, 0x4051101}, + { 0x3134, 0x2281800}, + { 0x3136, 0x42281203}, + { 0x3138, 0x2281101}, + { 0x313A, 0xC2281300}, + { 0x313C, 0x2228FB02}, + { 0x3140, 0xC2293632}, + { 0x3142, 0xC2500001}, + { 0x3144, 0x8229100E}, + { 0x3146, 0x22291803}, + { 0x3148, 0x82510B00}, + { 0x314A, 0xE251023B}, + { 0x314C, 0x2513B01}, + { 0x314E, 0x62500000}, + { 0x3150, 0xE2514288}, + { 0x3152, 0x2510B00}, + { 0x3154, 0x2510B00}, + { 0x3156, 0x4050500}, + { 0x3158, 0x42510C02}, + { 0x315A, 0xE2510227}, + { 0x315C, 0x2513B01}, + { 0x315E, 0xE2514266}, + { 0x3160, 0xE2515294}, + { 0x3162, 0x2510B00}, + { 0x3164, 0x2510B00}, + { 0x3166, 0x2291100}, + { 0x3168, 0x2291401}, + { 0x316A, 0x2290200}, + { 0x316C, 0x2291001}, + { 0x316E, 0x2290200}, + { 0x3170, 0xE2510266}, + { 0x3172, 0x82514B15}, + { 0x3174, 0x82510B15}, + { 0x3176, 0xE2515294}, + { 0x3178, 0x2510B00}, + { 0x317A, 0x8229160D}, + { 0x317C, 0x229F501}, + { 0x317E, 0x8229061C}, + { 0x3180, 0x2291000}, + { 0x3182, 0x4051101}, + { 0x3184, 0x2291800}, + { 0x3186, 0x42291203}, + { 0x3188, 0x2291101}, + { 0x318A, 0xC2291300}, + { 0x318C, 0x2229FB02}, + { 0x3190, 0xC22A3632}, + { 0x3192, 0xC2500001}, + { 0x3194, 0x822A100E}, + { 0x3196, 0x222A1803}, + { 0x3198, 0x82510B02}, + { 0x319A, 0xE251023B}, + { 0x319C, 0x2513B01}, + { 0x319E, 0x62500000}, + { 0x31A0, 0xE2514288}, + { 0x31A2, 0x2510B00}, + { 0x31A4, 0x2510B00}, + { 0x31A6, 0x4050400}, + { 0x31A8, 0x42510C03}, + { 0x31AA, 0xE2510227}, + { 0x31AC, 0x2513B01}, + { 0x31AE, 0xE2514266}, + { 0x31B0, 0xE2515294}, + { 0x31B2, 0x2510B00}, + { 0x31B4, 0x2510B00}, + { 0x31B6, 0x22A1100}, + { 0x31B8, 0x22A1401}, + { 0x31BA, 0x22A0200}, + { 0x31BC, 0x22A1001}, + { 0x31BE, 0x22A0200}, + { 0x31C0, 0xE2510266}, + { 0x31C2, 0x82514B17}, + { 0x31C4, 0x82510B17}, + { 0x31C6, 0xE2515294}, + { 0x31C8, 0x2510B00}, + { 0x31CA, 0x822A160D}, + { 0x31CC, 0x22AF501}, + { 0x31CE, 0x822A061C}, + { 0x31D0, 0x22A1000}, + { 0x31D2, 0x4051101}, + { 0x31D4, 0x22A1800}, + { 0x31D6, 0x422A1203}, + { 0x31D8, 0x22A1101}, + { 0x31DA, 0xC22A1300}, + { 0x31DC, 0x222AFB02}, +}; + +static const struct reg_sequence clearwater_revc_32_patch[] = { + { 0x3380, 0xE4103066 }, + { 0x3382, 0xE4103070 }, + { 0x3384, 0xE4103078 }, + { 0x3386, 0xE4103080 }, + { 0x3388, 0xE410F080 }, + { 0x338A, 0xE4143066 }, + { 0x338C, 0xE4143070 }, + { 0x338E, 0xE4143078 }, + { 0x3390, 0xE4143080 }, + { 0x3392, 0xE414F080 }, + { 0x3394, 0xE4103078 }, + { 0x3396, 0xE4103070 }, + { 0x3398, 0xE4103066 }, + { 0x339A, 0xE410F056 }, + { 0x339C, 0xE4143078 }, + { 0x339E, 0xE4143070 }, + { 0x33A0, 0xE4143066 }, + { 0x33A2, 0xE414F056 }, +}; + +/* We use a function so we can use ARRAY_SIZE() */ +int clearwater_patch(struct arizona *arizona) +{ + int ret = 0; + const struct reg_default *patch16 = NULL; + const struct reg_default *patch32 = NULL; + unsigned int num16, num32; + + switch (arizona->rev) { + case 0: + case 1: + patch16 = clearwater_reva_16_patch; + num16 = ARRAY_SIZE(clearwater_reva_16_patch); + + patch32 = clearwater_reva_32_patch; + num32 = ARRAY_SIZE(clearwater_reva_32_patch); + break; + default: + patch16 = clearwater_revc_16_patch; + num16 = ARRAY_SIZE(clearwater_revc_16_patch); + + patch32 = clearwater_revc_32_patch; + num32 = ARRAY_SIZE(clearwater_revc_32_patch); + break; + } + + if (patch16) { + ret = regmap_register_patch(arizona->regmap, patch16, num16); + if (ret < 0) { + dev_err(arizona->dev, + "Error in applying 16-bit patch: %d\n", ret); + return ret; + } + } + + if (patch32) { + ret = regmap_register_patch(arizona->regmap_32bit, + patch32, num32); + if (ret < 0) { + dev_err(arizona->dev, + "Error in applying 32-bit patch: %d\n", ret); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(clearwater_patch); + +static const struct regmap_irq clearwater_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_BOOT_DONE] = { .reg_offset = 0, + .mask = CLEARWATER_BOOT_DONE_EINT1 }, + [ARIZONA_IRQ_CTRLIF_ERR] = { .reg_offset = 0, + .mask = CLEARWATER_CTRLIF_ERR_EINT1 }, + + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL1_LOCK_EINT1 }, + [ARIZONA_IRQ_FLL2_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL2_LOCK_EINT1}, + [ARIZONA_IRQ_FLL3_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL3_LOCK_EINT1}, + + [ARIZONA_IRQ_MICDET] = { .reg_offset = 5, + .mask = CLEARWATER_MICDET_EINT1 }, + [ARIZONA_IRQ_HPDET] = { .reg_offset = 5, + .mask = CLEARWATER_HPDET_EINT1}, + + [ARIZONA_IRQ_MICD_CLAMP_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_RISE_EINT1 }, + [ARIZONA_IRQ_MICD_CLAMP_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_FALL_EINT1 }, + [ARIZONA_IRQ_JD_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_FALL_EINT1 }, + [ARIZONA_IRQ_JD_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_RISE_EINT1 }, + + [ARIZONA_IRQ_ASRC2_LOCK] = { .reg_offset = 8, + .mask = CLEARWATER_ASRC2_IN1_LOCK_EINT1 }, + [ARIZONA_IRQ_ASRC1_LOCK] = { .reg_offset = 8, + .mask = CLEARWATER_ASRC1_IN1_LOCK_EINT1 }, + [ARIZONA_IRQ_DRC2_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC2_SIG_DET_EINT1 }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC1_SIG_DET_EINT1 }, + + [ARIZONA_IRQ_DSP_IRQ1] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ1_EINT1}, + [ARIZONA_IRQ_DSP_IRQ2] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ2_EINT1}, + [ARIZONA_IRQ_DSP_IRQ3] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ3_EINT1}, + [ARIZONA_IRQ_DSP_IRQ4] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ4_EINT1}, + [ARIZONA_IRQ_DSP_IRQ5] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ5_EINT1}, + [ARIZONA_IRQ_DSP_IRQ6] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ6_EINT1}, + [ARIZONA_IRQ_DSP_IRQ7] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ7_EINT1}, + [ARIZONA_IRQ_DSP_IRQ8] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ8_EINT1}, + + [ARIZONA_IRQ_HP3R_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP3R_SC_EINT1}, + [ARIZONA_IRQ_HP3L_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP3L_SC_EINT1}, + [ARIZONA_IRQ_HP2R_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP2R_SC_EINT1}, + [ARIZONA_IRQ_HP2L_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP2L_SC_EINT1}, + [ARIZONA_IRQ_HP1R_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP1R_SC_EINT1}, + [ARIZONA_IRQ_HP1L_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP1L_SC_EINT1}, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { .reg_offset = 14, + .mask = CLEARWATER_SPK_OVERHEAT_WARN_EINT1}, + [ARIZONA_IRQ_SPK_OVERHEAT] = { .reg_offset = 14, + .mask = CLEARWATER_SPK_SHUTDOWN_EINT1}, +}; + +const struct regmap_irq_chip clearwater_irq = { + .name = "clearwater IRQ", + .status_base = CLEARWATER_IRQ1_STATUS_1, + .mask_base = CLEARWATER_IRQ1_MASK_1, + .ack_base = CLEARWATER_IRQ1_STATUS_1, + .num_regs = 15, + .irqs = clearwater_irqs, + .num_irqs = ARRAY_SIZE(clearwater_irqs), +}; +EXPORT_SYMBOL_GPL(clearwater_irq); + +static const struct reg_default clearwater_reg_default[] = { + { 0x00000008, 0x0309 }, /* R8 - Ctrl IF CFG 1 */ + { 0x00000009, 0x0200 }, /* R9 - Ctrl IF CFG 2 */ + { 0x0000000A, 0x0309 }, /* R10 - Ctrl IF CFG 3 */ + { 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */ + { 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */ + { 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */ + { 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */ + { 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */ + { 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */ + { 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */ + { 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */ + { 0x00000041, 0x0000 }, /* R65 (0x41) - Sequence control */ + { 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */ + { 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */ + { 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */ + { 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */ + { 0x00000066, 0x01ff }, + { 0x00000067, 0x01ff }, + { 0x00000068, 0x01ff }, /* R104 (0x68) - Always On Triggers Sequence Select 1 */ + { 0x00000069, 0x01ff }, /* R105 (0x69) - Always On Triggers Sequence Select 2 */ + { 0x0000006a, 0x01ff }, /* R106 (0x6A) - Always On Triggers Sequence Select 3 */ + { 0x0000006b, 0x01ff }, /* R107 (0x6B) - Always On Triggers Sequence Select 4 */ + { 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */ + { 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics phase 1 intensity */ + { 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics phase 1 duration */ + { 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics phase 2 intensity */ + { 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics phase 2 duration */ + { 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics phase 3 intensity */ + { 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics phase 3 duration */ + { 0x000000A0, 0x0000 }, /* R160 (0xA0) - Clearwater Comfort Noise Generator */ + { 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */ + { 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */ + { 0x00000102, 0x0011 }, /* R258 (0x102) - Sample rate 1 */ + { 0x00000103, 0x0011 }, /* R259 (0x103) - Sample rate 2 */ + { 0x00000104, 0x0011 }, /* R260 (0x104) - Sample rate 3 */ + { 0x00000112, 0x0305 }, /* R274 (0x112) - Async clock 1 */ + { 0x00000113, 0x0011 }, /* R275 (0x113) - Async sample rate 1 */ + { 0x00000114, 0x0011 }, /* R276 (0x114) - Async sample rate 2 */ + { 0x00000120, 0x0305 }, + { 0x00000122, 0x0000 }, + { 0x00000149, 0x0000 }, /* R329 (0x149) - Output system clock */ + { 0x0000014a, 0x0000 }, /* R330 (0x14A) - Output async clock */ + { 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */ + { 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */ + { 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */ + { 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */ + { 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */ + { 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */ + { 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */ + { 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */ + { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ + { 0x00000175, 0x0000 }, /* R373 - FLL1 Control 5 */ + { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ + { 0x00000177, 0x0281 }, /* R375 (0x177) - FLL1 Loop Filter Test 1 */ + { 0x00000178, 0x0000 }, + { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ + { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */ + { 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */ + { 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */ + { 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */ + { 0x00000185, 0x0000 }, /* R389 (0x185) - FLL1 Synchroniser 5 */ + { 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */ + { 0x00000187, 0x0001 }, /* R391 (0x187) - FLL1 Synchroniser 7 */ + { 0x00000189, 0x0000 }, /* R393 (0x189) - FLL1 Spread Spectrum */ + { 0x0000018a, 0x000c }, /* R394 (0x18A) - FLL1 GPIO Clock */ + { 0x00000191, 0x0002 }, /* R401 (0x191) - FLL2 Control 1 */ + { 0x00000192, 0x0008 }, /* R402 (0x192) - FLL2 Control 2 */ + { 0x00000193, 0x0018 }, /* R403 (0x193) - FLL2 Control 3 */ + { 0x00000194, 0x007d }, /* R404 (0x194) - FLL2 Control 4 */ + { 0x00000195, 0x0000 }, /* R405 - FLL2 Control 5 */ + { 0x00000196, 0x0000 }, /* R406 (0x196) - FLL2 Control 6 */ + { 0x00000197, 0x0281 }, /* R407 (0x197) - FLL2 Loop Filter Test 1 */ + { 0x00000198, 0x0000 }, + { 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 7 */ + { 0x000001a1, 0x0000 }, /* R417 (0x1A1) - FLL2 Synchroniser 1 */ + { 0x000001a2, 0x0000 }, /* R418 (0x1A2) - FLL2 Synchroniser 2 */ + { 0x000001a3, 0x0000 }, /* R419 (0x1A3) - FLL2 Synchroniser 3 */ + { 0x000001a4, 0x0000 }, /* R420 (0x1A4) - FLL2 Synchroniser 4 */ + { 0x000001a5, 0x0000 }, /* R421 (0x1A5) - FLL2 Synchroniser 5 */ + { 0x000001a6, 0x0000 }, /* R422 (0x1A6) - FLL2 Synchroniser 6 */ + { 0x000001a7, 0x0001 }, /* R423 (0x1A7) - FLL2 Synchroniser 7 */ + { 0x000001a9, 0x0000 }, /* R425 (0x1A9) - FLL2 Spread Spectrum */ + { 0x000001aa, 0x000c }, /* R426 (0x1AA) - FLL2 GPIO Clock */ + { 0x000001B1, 0x0002 }, /* R433 - FLL3 Control 1 */ + { 0x000001B2, 0x0008 }, /* R434 - FLL3 Control 2 */ + { 0x000001B3, 0x0018 }, /* R435 - FLL3 Control 3 */ + { 0x000001B4, 0x007D }, /* R436 - FLL3 Control 4 */ + { 0x000001B5, 0x0000 }, /* R437 - FLL3 Control 5 */ + { 0x000001B6, 0x0000 }, /* R438 - FLL3 Control 6 */ + { 0x000001B7, 0x0281 }, /* R439 - FLL3 Loop Filter Test 1 */ + { 0x000001B8, 0x0000 }, /* R440 - FLL3 NCO Test 0 */ + { 0x000001B9, 0x0000 }, /* R441 - FLL3 Control 7 */ + { 0x000001C1, 0x0000 }, /* R449 - FLL3 Synchroniser 1 */ + { 0x000001C2, 0x0000 }, /* R450 - FLL3 Synchroniser 2 */ + { 0x000001C3, 0x0000 }, /* R451 - FLL3 Synchroniser 3 */ + { 0x000001C4, 0x0000 }, /* R452 - FLL3 Synchroniser 4 */ + { 0x000001C5, 0x0000 }, /* R453 - FLL3 Synchroniser 5 */ + { 0x000001C6, 0x0000 }, /* R454 - FLL3 Synchroniser 6 */ + { 0x000001C7, 0x0001 }, /* R455 - FLL3 Synchroniser 7 */ + { 0x000001C9, 0x0000 }, /* R457 - FLL3 Spread Spectrum */ + { 0x000001CA, 0x000C }, /* R458 - FLL3 GPIO Clock */ + { 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */ + { 0x0000020B, 0x0400 }, + { 0x00000210, 0x0184 }, /* R528 (0x210) - LDO1 Control 1 */ + { 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */ + { 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */ + { 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */ + { 0x0000021a, 0x00e6 }, /* R538 (0x21A) - Mic Bias Ctrl 3 */ + { 0x0000021B, 0x00e6 }, /* R539 - Mic Bias Ctrl 4 */ + { 0x0000027e, 0x0000 }, /* R638 (0x27E) - Clearwater EDRE HP stereo control */ + { 0x00000293, 0x0000 }, /* R659 (0x293) - Accessory Detect Mode 1 */ + { 0x0000029b, 0x0000 }, /* R667 (0x29B) - Headphone Detect 1 */ + { 0x000002a3, 0x1102 }, /* R675 (0x2A3) - Mic Detect 1 */ + { 0x000002a4, 0x009f }, /* R676 (0x2A4) - Mic Detect 2 */ + { 0x000002a6, 0x3737 }, + { 0x000002a7, 0x2c37 }, + { 0x000002a8, 0x1422 }, + { 0x000002a9, 0x030a }, + { 0x000002c3, 0x0000 }, /* R707 (0x2C3) - Mic noise mix control 1 */ + { 0x000002c6, 0x0010 }, + { 0x000002c8, 0x0000 }, /* R712 (0x2C8) - GP switch 1 */ + { 0x000002d3, 0x0000 }, /* R723 (0x2D3) - Jack detect analogue */ + { 0x00000300, 0x0000 }, /* R768 - Input Enables */ + { 0x00000308, 0x0000 }, /* R776 (0x308) - Input Rate */ + { 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */ + { 0x0000030c, 0x0002 }, /* R780 (0x30C) - HPF Control */ + { 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */ + { 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */ + { 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */ + { 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */ + { 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */ + { 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */ + { 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */ + { 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */ + { 0x0000031a, 0x0500 }, /* R794 (0x31A) - DMIC2L Control */ + { 0x0000031c, 0x0080 }, /* R796 (0x31C) - IN2R Control */ + { 0x0000031d, 0x0180 }, /* R797 (0x31D) - ADC Digital Volume 2R */ + { 0x0000031e, 0x0000 }, /* R798 (0x31E) - DMIC2R Control */ + { 0x00000320, 0x0080 }, /* R800 (0x320) - IN3L Control */ + { 0x00000321, 0x0180 }, /* R801 (0x321) - ADC Digital Volume 3L */ + { 0x00000322, 0x0500 }, /* R802 (0x322) - DMIC3L Control */ + { 0x00000324, 0x0080 }, /* R804 (0x324) - IN3R Control */ + { 0x00000325, 0x0180 }, /* R805 (0x325) - ADC Digital Volume 3R */ + { 0x00000326, 0x0000 }, /* R806 (0x326) - DMIC3R Control */ + { 0x00000328, 0x0000 }, /* R808 (0x328) - IN4 Control */ + { 0x00000329, 0x0180 }, /* R809 (0x329) - ADC Digital Volume 4L */ + { 0x0000032a, 0x0500 }, /* R810 (0x32A) - DMIC4L Control */ + { 0x0000032c, 0x0000 }, /* R812 (0x32C) - IN4R Control */ + { 0x0000032d, 0x0180 }, /* R813 (0x32D) - ADC Digital Volume 4R */ + { 0x0000032e, 0x0000 }, /* R814 (0x32E) - DMIC4R Control */ + { 0x00000330, 0x0000 }, /* R816 - IN5L Control */ + { 0x00000331, 0x0180 }, /* R817 - ADC Digital Volume 5L */ + { 0x00000332, 0x0500 }, /* R818 - DMIC5L Control */ + { 0x00000334, 0x0000 }, /* R820 - IN5R Control */ + { 0x00000335, 0x0180 }, /* R821 - ADC Digital Volume 5R */ + { 0x00000336, 0x0000 }, /* R822 - DMIC5R Control */ + { 0x00000338, 0x0000 }, /* R824 - IN6L Control */ + { 0x00000339, 0x0180 }, /* R825 - ADC Digital Volume 6L */ + { 0x0000033A, 0x0500 }, /* R826 - DMIC6L Control */ + { 0x0000033C, 0x0000 }, /* R828 - IN6R Control */ + { 0x0000033D, 0x0180 }, /* R829 - ADC Digital Volume 6R */ + { 0x0000033E, 0x0000 }, /* R830 - DMIC6R Control */ + { 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */ + { 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */ + { 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */ + { 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */ + { 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */ + { 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */ + { 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */ + { 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */ + { 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */ + { 0x00000418, 0x0080 }, /* R1048 (0x418) - Output Path Config 2L */ + { 0x00000419, 0x0180 }, /* R1049 (0x419) - DAC Digital Volume 2L */ + { 0x0000041b, 0x0004 }, /* R1051 (0x41B) - Noise Gate Select 2L */ + { 0x0000041c, 0x0080 }, /* R1052 (0x41C) - Output Path Config 2R */ + { 0x0000041d, 0x0180 }, /* R1053 (0x41D) - DAC Digital Volume 2R */ + { 0x0000041f, 0x0008 }, /* R1055 (0x41F) - Noise Gate Select 2R */ + { 0x00000420, 0x0080 }, /* R1056 (0x420) - Output Path Config 3L */ + { 0x00000421, 0x0180 }, /* R1057 (0x421) - DAC Digital Volume 3L */ + { 0x00000423, 0x0010 }, /* R1059 (0x423) - Noise Gate Select 3L */ + { 0x00000424, 0x0080 }, /* R1060 (0x424) - Output Path Config 3R */ + { 0x00000425, 0x0180 }, /* R1061 (0x425) - DAC Digital Volume 3R */ + { 0x00000427, 0x0020 }, + { 0x00000428, 0x0000 }, /* R1064 (0x428) - Output Path Config 4L */ + { 0x00000429, 0x0180 }, /* R1065 (0x429) - DAC Digital Volume 4L */ + { 0x0000042b, 0x0040 }, /* R1067 (0x42B) - Noise Gate Select 4L */ + { 0x0000042c, 0x0000 }, /* R1068 (0x42C) - Output Path Config 4R */ + { 0x0000042d, 0x0180 }, /* R1069 (0x42D) - DAC Digital Volume 4R */ + { 0x0000042f, 0x0080 }, /* R1071 (0x42F) - Noise Gate Select 4R */ + { 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */ + { 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */ + { 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */ + { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ + { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ + { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ + { 0x00000438, 0x0000 }, /* R1080 (0x438) - Output Path Config 6L */ + { 0x00000439, 0x0180 }, /* R1081 (0x439) - DAC Digital Volume 6L */ + { 0x0000043b, 0x0400 }, /* R1083 (0x43B) - Noise Gate Select 6L */ + { 0x0000043c, 0x0000 }, /* R1084 (0x43C) - Output Path Config 6R */ + { 0x0000043d, 0x0180 }, /* R1085 (0x43D) - DAC Digital Volume 6R */ + { 0x0000043f, 0x0800 }, /* R1087 (0x43F) - Noise Gate Select 6R */ + { 0x00000440, 0x003f }, /* R1088 (0x440) - DRE Enable */ + { 0x00000448, 0x003f }, /* R1096 (0x448) - eDRE Enable */ + { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ + { 0x00000451, 0x0000 }, /* R1105 - DAC AEC Control 2 */ + { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ + { 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 CTRL 1 */ + { 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */ + { 0x00000492, 0x0069 }, /* R1170 (0x492) - PDM SPK2 CTRL 1 */ + { 0x00000493, 0x0000 }, /* R1171 (0x493) - PDM SPK2 CTRL 2 */ + { 0x000004A0, 0x3210 }, /* R1184 - HP1 Short Circuit Ctrl */ + { 0x000004A1, 0x3200 }, /* R1185 - HP2 Short Circuit Ctrl */ + { 0x000004A2, 0x3200 }, /* R1186 - HP3 Short Circuit Ctrl */ + { 0x000004A8, 0x7020 }, /* R1192 - HP Test Ctrl 5 */ + { 0x000004A9, 0x7020 }, /* R1193 - HP Test Ctrl 6 */ + { 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */ + { 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */ + { 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */ + { 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */ + { 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */ + { 0x00000505, 0x0040 }, /* R1285 (0x505) - AIF1 Tx BCLK Rate */ + { 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */ + { 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */ + { 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */ + { 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */ + { 0x0000050a, 0x0001 }, /* R1290 (0x50A) - AIF1 Frame Ctrl 4 */ + { 0x0000050b, 0x0002 }, /* R1291 (0x50B) - AIF1 Frame Ctrl 5 */ + { 0x0000050c, 0x0003 }, /* R1292 (0x50C) - AIF1 Frame Ctrl 6 */ + { 0x0000050d, 0x0004 }, /* R1293 (0x50D) - AIF1 Frame Ctrl 7 */ + { 0x0000050e, 0x0005 }, /* R1294 (0x50E) - AIF1 Frame Ctrl 8 */ + { 0x0000050f, 0x0006 }, /* R1295 (0x50F) - AIF1 Frame Ctrl 9 */ + { 0x00000510, 0x0007 }, /* R1296 (0x510) - AIF1 Frame Ctrl 10 */ + { 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */ + { 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */ + { 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */ + { 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */ + { 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */ + { 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */ + { 0x00000517, 0x0006 }, /* R1303 (0x517) - AIF1 Frame Ctrl 17 */ + { 0x00000518, 0x0007 }, /* R1304 (0x518) - AIF1 Frame Ctrl 18 */ + { 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */ + { 0x0000051a, 0x0000 }, /* R1306 (0x51A) - AIF1 Rx Enables */ + { 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */ + { 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */ + { 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */ + { 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */ + { 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */ + { 0x00000545, 0x0040 }, /* R1349 (0x545) - AIF2 Tx BCLK Rate */ + { 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */ + { 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */ + { 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */ + { 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */ + { 0x0000054a, 0x0001 }, /* R1354 (0x54A) - AIF2 Frame Ctrl 4 */ + { 0x0000054b, 0x0002 }, /* R1355 (0x54B) - AIF2 Frame Ctrl 5 */ + { 0x0000054c, 0x0003 }, /* R1356 (0x54C) - AIF2 Frame Ctrl 6 */ + { 0x0000054d, 0x0004 }, /* R1357 (0x54D) - AIF2 Frame Ctrl 7 */ + { 0x0000054e, 0x0005 }, /* R1358 (0x54E) - AIF2 Frame Ctrl 8 */ + { 0x0000054F, 0x0006 }, /* R1359 - AIF2 Frame Ctrl 9 */ + { 0x00000550, 0x0007 }, /* R1360 - AIF2 Frame Ctrl 10 */ + { 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */ + { 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */ + { 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */ + { 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */ + { 0x00000555, 0x0004 }, /* R1365 (0x555) - AIF2 Frame Ctrl 15 */ + { 0x00000556, 0x0005 }, /* R1366 (0x556) - AIF2 Frame Ctrl 16 */ + { 0x00000557, 0x0006 }, /* R1367 - AIF2 Frame Ctrl 17 */ + { 0x00000558, 0x0007 }, /* R1368 - AIF2 Frame Ctrl 18 */ + { 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */ + { 0x0000055a, 0x0000 }, /* R1370 (0x55A) - AIF2 Rx Enables */ + { 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */ + { 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */ + { 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */ + { 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */ + { 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */ + { 0x00000585, 0x0040 }, /* R1413 (0x585) - AIF3 Tx BCLK Rate */ + { 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */ + { 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */ + { 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */ + { 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */ + { 0x0000058a, 0x0001 }, /* R1418 (0x58A) - AIF3 Frame Ctrl 4 */ + { 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */ + { 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */ + { 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */ + { 0x0000059a, 0x0000 }, /* R1434 (0x59A) - AIF3 Rx Enables */ + { 0x000005a0, 0x000c }, /* R1440 - AIF4 BCLK Ctrl */ + { 0x000005a1, 0x0000 }, /* R1441 - AIF4 Tx Pin Ctrl */ + { 0x000005a2, 0x0000 }, /* R1442 - AIF4 Rx Pin Ctrl */ + { 0x000005a3, 0x0000 }, /* R1443 - AIF4 Rate Ctrl */ + { 0x000005a4, 0x0000 }, /* R1444 - AIF4 Format */ + { 0x000005a5, 0x0040 }, /* R1445 - AIF4 Tx BCLK Rate */ + { 0x000005a6, 0x0040 }, /* R1446 - AIF4 Rx BCLK Rate */ + { 0x000005a7, 0x1818 }, /* R1447 - AIF4 Frame Ctrl 1 */ + { 0x000005a8, 0x1818 }, /* R1448 - AIF4 Frame Ctrl 2 */ + { 0x000005a9, 0x0000 }, /* R1449 - AIF4 Frame Ctrl 3 */ + { 0x000005aa, 0x0001 }, /* R1450 - AIF4 Frame Ctrl 4 */ + { 0x000005b1, 0x0000 }, /* R1457 - AIF4 Frame Ctrl 11 */ + { 0x000005b2, 0x0001 }, /* R1458 - AIF4 Frame Ctrl 12 */ + { 0x000005b9, 0x0000 }, /* R1465 - AIF4 Tx Enables */ + { 0x000005ba, 0x0000 }, /* R1466 - AIF4 Rx Enables */ + { 0x000005C2, 0x0000 }, /* R1474 - SPD1 TX Control */ + { 0x000005e3, 0x0000 }, /* R1507 (0x5E3) - SLIMbus Framer Ref Gear */ + { 0x000005e5, 0x0000 }, /* R1509 (0x5E5) - SLIMbus Rates 1 */ + { 0x000005e6, 0x0000 }, /* R1510 (0x5E6) - SLIMbus Rates 2 */ + { 0x000005e7, 0x0000 }, /* R1511 (0x5E7) - SLIMbus Rates 3 */ + { 0x000005e8, 0x0000 }, /* R1512 (0x5E8) - SLIMbus Rates 4 */ + { 0x000005e9, 0x0000 }, /* R1513 (0x5E9) - SLIMbus Rates 5 */ + { 0x000005ea, 0x0000 }, /* R1514 (0x5EA) - SLIMbus Rates 6 */ + { 0x000005eb, 0x0000 }, /* R1515 (0x5EB) - SLIMbus Rates 7 */ + { 0x000005ec, 0x0000 }, /* R1516 (0x5EC) - SLIMbus Rates 8 */ + { 0x000005f5, 0x0000 }, /* R1525 (0x5F5) - SLIMbus RX Channel Enable */ + { 0x000005f6, 0x0000 }, /* R1526 (0x5F6) - SLIMbus TX Channel Enable */ + { 0x00000640, 0x0000 }, + { 0x00000641, 0x0080 }, + { 0x00000642, 0x0000 }, + { 0x00000643, 0x0080 }, + { 0x00000644, 0x0000 }, + { 0x00000645, 0x0080 }, + { 0x00000646, 0x0000 }, + { 0x00000647, 0x0080 }, + { 0x00000648, 0x0000 }, + { 0x00000649, 0x0080 }, + { 0x0000064a, 0x0000 }, + { 0x0000064b, 0x0080 }, + { 0x0000064c, 0x0000 }, + { 0x0000064d, 0x0080 }, + { 0x0000064e, 0x0000 }, + { 0x0000064f, 0x0080 }, + { 0x00000680, 0x0000 }, + { 0x00000681, 0x0080 }, + { 0x00000682, 0x0000 }, + { 0x00000683, 0x0080 }, + { 0x00000684, 0x0000 }, + { 0x00000685, 0x0080 }, + { 0x00000686, 0x0000 }, + { 0x00000687, 0x0080 }, + { 0x00000688, 0x0000 }, + { 0x00000689, 0x0080 }, + { 0x0000068a, 0x0000 }, + { 0x0000068b, 0x0080 }, + { 0x0000068c, 0x0000 }, + { 0x0000068d, 0x0080 }, + { 0x0000068e, 0x0000 }, + { 0x0000068f, 0x0080 }, + { 0x00000690, 0x0000 }, + { 0x00000691, 0x0080 }, + { 0x00000692, 0x0000 }, + { 0x00000693, 0x0080 }, + { 0x00000694, 0x0000 }, + { 0x00000695, 0x0080 }, + { 0x00000696, 0x0000 }, + { 0x00000697, 0x0080 }, + { 0x00000698, 0x0000 }, + { 0x00000699, 0x0080 }, + { 0x0000069a, 0x0000 }, + { 0x0000069b, 0x0080 }, + { 0x0000069c, 0x0000 }, + { 0x0000069d, 0x0080 }, + { 0x0000069e, 0x0000 }, + { 0x0000069f, 0x0080 }, + { 0x000006a0, 0x0000 }, + { 0x000006a1, 0x0080 }, + { 0x000006a2, 0x0000 }, + { 0x000006a3, 0x0080 }, + { 0x000006a4, 0x0000 }, + { 0x000006a5, 0x0080 }, + { 0x000006a6, 0x0000 }, + { 0x000006a7, 0x0080 }, + { 0x000006a8, 0x0000 }, + { 0x000006a9, 0x0080 }, + { 0x000006aa, 0x0000 }, + { 0x000006ab, 0x0080 }, + { 0x000006ac, 0x0000 }, + { 0x000006ad, 0x0080 }, + { 0x000006ae, 0x0000 }, + { 0x000006af, 0x0080 }, + { 0x000006b0, 0x0000 }, + { 0x000006b1, 0x0080 }, + { 0x000006b2, 0x0000 }, + { 0x000006b3, 0x0080 }, + { 0x000006b4, 0x0000 }, + { 0x000006b5, 0x0080 }, + { 0x000006b6, 0x0000 }, + { 0x000006b7, 0x0080 }, + { 0x000006b8, 0x0000 }, + { 0x000006b9, 0x0080 }, + { 0x000006ba, 0x0000 }, + { 0x000006bb, 0x0080 }, + { 0x000006bc, 0x0000 }, + { 0x000006bd, 0x0080 }, + { 0x000006be, 0x0000 }, + { 0x000006bf, 0x0080 }, + { 0x000006c0, 0x0000 }, + { 0x000006c1, 0x0080 }, + { 0x000006c2, 0x0000 }, + { 0x000006c3, 0x0080 }, + { 0x000006c4, 0x0000 }, + { 0x000006c5, 0x0080 }, + { 0x000006c6, 0x0000 }, + { 0x000006c7, 0x0080 }, + { 0x000006c8, 0x0000 }, + { 0x000006c9, 0x0080 }, + { 0x000006ca, 0x0000 }, + { 0x000006cb, 0x0080 }, + { 0x000006cc, 0x0000 }, + { 0x000006cd, 0x0080 }, + { 0x000006ce, 0x0000 }, + { 0x000006cf, 0x0080 }, + { 0x000006d0, 0x0000 }, + { 0x000006d1, 0x0080 }, + { 0x000006d2, 0x0000 }, + { 0x000006d3, 0x0080 }, + { 0x000006d4, 0x0000 }, + { 0x000006d5, 0x0080 }, + { 0x000006d6, 0x0000 }, + { 0x000006d7, 0x0080 }, + { 0x000006d8, 0x0000 }, + { 0x000006d9, 0x0080 }, + { 0x000006da, 0x0000 }, + { 0x000006db, 0x0080 }, + { 0x000006dc, 0x0000 }, + { 0x000006dd, 0x0080 }, + { 0x000006de, 0x0000 }, + { 0x000006df, 0x0080 }, + { 0x00000700, 0x0000 }, + { 0x00000701, 0x0080 }, + { 0x00000702, 0x0000 }, + { 0x00000703, 0x0080 }, + { 0x00000704, 0x0000 }, + { 0x00000705, 0x0080 }, + { 0x00000706, 0x0000 }, + { 0x00000707, 0x0080 }, + { 0x00000708, 0x0000 }, + { 0x00000709, 0x0080 }, + { 0x0000070a, 0x0000 }, + { 0x0000070b, 0x0080 }, + { 0x0000070c, 0x0000 }, + { 0x0000070d, 0x0080 }, + { 0x0000070e, 0x0000 }, + { 0x0000070f, 0x0080 }, + { 0x00000710, 0x0000 }, + { 0x00000711, 0x0080 }, + { 0x00000712, 0x0000 }, + { 0x00000713, 0x0080 }, + { 0x00000714, 0x0000 }, + { 0x00000715, 0x0080 }, + { 0x00000716, 0x0000 }, + { 0x00000717, 0x0080 }, + { 0x00000718, 0x0000 }, + { 0x00000719, 0x0080 }, + { 0x0000071a, 0x0000 }, + { 0x0000071b, 0x0080 }, + { 0x0000071c, 0x0000 }, + { 0x0000071d, 0x0080 }, + { 0x0000071e, 0x0000 }, + { 0x0000071f, 0x0080 }, + { 0x00000720, 0x0000 }, + { 0x00000721, 0x0080 }, + { 0x00000722, 0x0000 }, + { 0x00000723, 0x0080 }, + { 0x00000724, 0x0000 }, + { 0x00000725, 0x0080 }, + { 0x00000726, 0x0000 }, + { 0x00000727, 0x0080 }, + { 0x00000728, 0x0000 }, + { 0x00000729, 0x0080 }, + { 0x0000072a, 0x0000 }, + { 0x0000072b, 0x0080 }, + { 0x0000072c, 0x0000 }, + { 0x0000072d, 0x0080 }, + { 0x0000072e, 0x0000 }, + { 0x0000072f, 0x0080 }, + { 0x00000730, 0x0000 }, + { 0x00000731, 0x0080 }, + { 0x00000732, 0x0000 }, + { 0x00000733, 0x0080 }, + { 0x00000734, 0x0000 }, + { 0x00000735, 0x0080 }, + { 0x00000736, 0x0000 }, + { 0x00000737, 0x0080 }, + { 0x00000738, 0x0000 }, + { 0x00000739, 0x0080 }, + { 0x0000073a, 0x0000 }, + { 0x0000073b, 0x0080 }, + { 0x0000073c, 0x0000 }, + { 0x0000073d, 0x0080 }, + { 0x0000073e, 0x0000 }, + { 0x0000073f, 0x0080 }, + { 0x00000740, 0x0000 }, + { 0x00000741, 0x0080 }, + { 0x00000742, 0x0000 }, + { 0x00000743, 0x0080 }, + { 0x00000744, 0x0000 }, + { 0x00000745, 0x0080 }, + { 0x00000746, 0x0000 }, + { 0x00000747, 0x0080 }, + { 0x00000748, 0x0000 }, + { 0x00000749, 0x0080 }, + { 0x0000074a, 0x0000 }, + { 0x0000074b, 0x0080 }, + { 0x0000074c, 0x0000 }, + { 0x0000074d, 0x0080 }, + { 0x0000074e, 0x0000 }, + { 0x0000074f, 0x0080 }, + { 0x00000750, 0x0000 }, + { 0x00000751, 0x0080 }, + { 0x00000752, 0x0000 }, + { 0x00000753, 0x0080 }, + { 0x00000754, 0x0000 }, + { 0x00000755, 0x0080 }, + { 0x00000756, 0x0000 }, + { 0x00000757, 0x0080 }, + { 0x00000758, 0x0000 }, + { 0x00000759, 0x0080 }, + { 0x0000075a, 0x0000 }, + { 0x0000075b, 0x0080 }, + { 0x0000075c, 0x0000 }, + { 0x0000075d, 0x0080 }, + { 0x0000075e, 0x0000 }, + { 0x0000075f, 0x0080 }, + { 0x00000760, 0x0000 }, + { 0x00000761, 0x0080 }, + { 0x00000762, 0x0000 }, + { 0x00000763, 0x0080 }, + { 0x00000764, 0x0000 }, + { 0x00000765, 0x0080 }, + { 0x00000766, 0x0000 }, + { 0x00000767, 0x0080 }, + { 0x00000768, 0x0000 }, + { 0x00000769, 0x0080 }, + { 0x0000076a, 0x0000 }, + { 0x0000076b, 0x0080 }, + { 0x0000076c, 0x0000 }, + { 0x0000076d, 0x0080 }, + { 0x0000076e, 0x0000 }, + { 0x0000076f, 0x0080 }, + { 0x00000770, 0x0000 }, /* R1904 - AIF2TX7MIX Input 1 Source */ + { 0x00000771, 0x0080 }, /* R1905 - AIF2TX7MIX Input 1 Volume */ + { 0x00000772, 0x0000 }, /* R1906 - AIF2TX7MIX Input 2 Source */ + { 0x00000773, 0x0080 }, /* R1907 - AIF2TX7MIX Input 2 Volume */ + { 0x00000774, 0x0000 }, /* R1908 - AIF2TX7MIX Input 3 Source */ + { 0x00000775, 0x0080 }, /* R1909 - AIF2TX7MIX Input 3 Volume */ + { 0x00000776, 0x0000 }, /* R1910 - AIF2TX7MIX Input 4 Source */ + { 0x00000777, 0x0080 }, /* R1911 - AIF2TX7MIX Input 4 Volume */ + { 0x00000778, 0x0000 }, /* R1912 - AIF2TX8MIX Input 1 Source */ + { 0x00000779, 0x0080 }, /* R1913 - AIF2TX8MIX Input 1 Volume */ + { 0x0000077a, 0x0000 }, /* R1914 - AIF2TX8MIX Input 2 Source */ + { 0x0000077b, 0x0080 }, /* R1915 - AIF2TX8MIX Input 2 Volume */ + { 0x0000077c, 0x0000 }, /* R1916 - AIF2TX8MIX Input 3 Source */ + { 0x0000077d, 0x0080 }, /* R1917 - AIF2TX8MIX Input 3 Volume */ + { 0x0000077e, 0x0000 }, /* R1918 - AIF2TX8MIX Input 4 Source */ + { 0x0000077f, 0x0080 }, /* R1919 - AIF2TX8MIX Input 4 Volume */ + { 0x00000780, 0x0000 }, + { 0x00000781, 0x0080 }, + { 0x00000782, 0x0000 }, + { 0x00000783, 0x0080 }, + { 0x00000784, 0x0000 }, + { 0x00000785, 0x0080 }, + { 0x00000786, 0x0000 }, + { 0x00000787, 0x0080 }, + { 0x00000788, 0x0000 }, + { 0x00000789, 0x0080 }, + { 0x0000078a, 0x0000 }, + { 0x0000078b, 0x0080 }, + { 0x0000078c, 0x0000 }, + { 0x0000078d, 0x0080 }, + { 0x0000078e, 0x0000 }, + { 0x0000078f, 0x0080 }, + { 0x000007a0, 0x0000 }, /* R1952 - AIF4TX1MIX Input 1 Source */ + { 0x000007a1, 0x0080 }, /* R1953 - AIF4TX1MIX Input 1 Volume */ + { 0x000007a2, 0x0000 }, /* R1954 - AIF4TX1MIX Input 2 Source */ + { 0x000007a3, 0x0080 }, /* R1955 - AIF4TX1MIX Input 2 Volume */ + { 0x000007a4, 0x0000 }, /* R1956 - AIF4TX1MIX Input 3 Source */ + { 0x000007a5, 0x0080 }, /* R1957 - AIF4TX1MIX Input 3 Volume */ + { 0x000007a6, 0x0000 }, /* R1958 - AIF4TX1MIX Input 4 Source */ + { 0x000007a7, 0x0080 }, /* R1959 - AIF4TX1MIX Input 4 Volume */ + { 0x000007a8, 0x0000 }, /* R1960 - AIF4TX2MIX Input 1 Source */ + { 0x000007a9, 0x0080 }, /* R1961 - AIF4TX2MIX Input 1 Volume */ + { 0x000007aa, 0x0000 }, /* R1962 - AIF4TX2MIX Input 2 Source */ + { 0x000007ab, 0x0080 }, /* R1963 - AIF4TX2MIX Input 2 Volume */ + { 0x000007ac, 0x0000 }, /* R1964 - AIF4TX2MIX Input 3 Source */ + { 0x000007ad, 0x0080 }, /* R1965 - AIF4TX2MIX Input 3 Volume */ + { 0x000007ae, 0x0000 }, /* R1966 - AIF4TX2MIX Input 4 Source */ + { 0x000007af, 0x0080 }, /* R1967 - AIF4TX2MIX Input 4 Volume */ + { 0x000007c0, 0x0000 }, + { 0x000007c1, 0x0080 }, + { 0x000007c2, 0x0000 }, + { 0x000007c3, 0x0080 }, + { 0x000007c4, 0x0000 }, + { 0x000007c5, 0x0080 }, + { 0x000007c6, 0x0000 }, + { 0x000007c7, 0x0080 }, + { 0x000007c8, 0x0000 }, + { 0x000007c9, 0x0080 }, + { 0x000007ca, 0x0000 }, + { 0x000007cb, 0x0080 }, + { 0x000007cc, 0x0000 }, + { 0x000007cd, 0x0080 }, + { 0x000007ce, 0x0000 }, + { 0x000007cf, 0x0080 }, + { 0x000007d0, 0x0000 }, + { 0x000007d1, 0x0080 }, + { 0x000007d2, 0x0000 }, + { 0x000007d3, 0x0080 }, + { 0x000007d4, 0x0000 }, + { 0x000007d5, 0x0080 }, + { 0x000007d6, 0x0000 }, + { 0x000007d7, 0x0080 }, + { 0x000007d8, 0x0000 }, + { 0x000007d9, 0x0080 }, + { 0x000007da, 0x0000 }, + { 0x000007db, 0x0080 }, + { 0x000007dc, 0x0000 }, + { 0x000007dd, 0x0080 }, + { 0x000007de, 0x0000 }, + { 0x000007df, 0x0080 }, + { 0x000007e0, 0x0000 }, + { 0x000007e1, 0x0080 }, + { 0x000007e2, 0x0000 }, + { 0x000007e3, 0x0080 }, + { 0x000007e4, 0x0000 }, + { 0x000007e5, 0x0080 }, + { 0x000007e6, 0x0000 }, + { 0x000007e7, 0x0080 }, + { 0x000007e8, 0x0000 }, + { 0x000007e9, 0x0080 }, + { 0x000007ea, 0x0000 }, + { 0x000007eb, 0x0080 }, + { 0x000007ec, 0x0000 }, + { 0x000007ed, 0x0080 }, + { 0x000007ee, 0x0000 }, + { 0x000007ef, 0x0080 }, + { 0x000007f0, 0x0000 }, + { 0x000007f1, 0x0080 }, + { 0x000007f2, 0x0000 }, + { 0x000007f3, 0x0080 }, + { 0x000007f4, 0x0000 }, + { 0x000007f5, 0x0080 }, + { 0x000007f6, 0x0000 }, + { 0x000007f7, 0x0080 }, + { 0x000007f8, 0x0000 }, + { 0x000007f9, 0x0080 }, + { 0x000007fa, 0x0000 }, + { 0x000007fb, 0x0080 }, + { 0x000007fc, 0x0000 }, + { 0x000007fd, 0x0080 }, + { 0x000007fe, 0x0000 }, + { 0x000007ff, 0x0080 }, + { 0x00000800, 0x0000 }, + { 0x00000801, 0x0080 }, + { 0x00000808, 0x0000 }, + { 0x00000809, 0x0080 }, + { 0x00000880, 0x0000 }, + { 0x00000881, 0x0080 }, + { 0x00000882, 0x0000 }, + { 0x00000883, 0x0080 }, + { 0x00000884, 0x0000 }, + { 0x00000885, 0x0080 }, + { 0x00000886, 0x0000 }, + { 0x00000887, 0x0080 }, + { 0x00000888, 0x0000 }, + { 0x00000889, 0x0080 }, + { 0x0000088a, 0x0000 }, + { 0x0000088b, 0x0080 }, + { 0x0000088c, 0x0000 }, + { 0x0000088d, 0x0080 }, + { 0x0000088e, 0x0000 }, + { 0x0000088f, 0x0080 }, + { 0x00000890, 0x0000 }, + { 0x00000891, 0x0080 }, + { 0x00000892, 0x0000 }, + { 0x00000893, 0x0080 }, + { 0x00000894, 0x0000 }, + { 0x00000895, 0x0080 }, + { 0x00000896, 0x0000 }, + { 0x00000897, 0x0080 }, + { 0x00000898, 0x0000 }, + { 0x00000899, 0x0080 }, + { 0x0000089a, 0x0000 }, + { 0x0000089b, 0x0080 }, + { 0x0000089c, 0x0000 }, + { 0x0000089d, 0x0080 }, + { 0x0000089e, 0x0000 }, + { 0x0000089f, 0x0080 }, + { 0x000008c0, 0x0000 }, + { 0x000008c1, 0x0080 }, + { 0x000008c2, 0x0000 }, + { 0x000008c3, 0x0080 }, + { 0x000008c4, 0x0000 }, + { 0x000008c5, 0x0080 }, + { 0x000008c6, 0x0000 }, + { 0x000008c7, 0x0080 }, + { 0x000008c8, 0x0000 }, + { 0x000008c9, 0x0080 }, + { 0x000008ca, 0x0000 }, + { 0x000008cb, 0x0080 }, + { 0x000008cc, 0x0000 }, + { 0x000008cd, 0x0080 }, + { 0x000008ce, 0x0000 }, + { 0x000008cf, 0x0080 }, + { 0x000008d0, 0x0000 }, + { 0x000008d1, 0x0080 }, + { 0x000008d2, 0x0000 }, + { 0x000008d3, 0x0080 }, + { 0x000008d4, 0x0000 }, + { 0x000008d5, 0x0080 }, + { 0x000008d6, 0x0000 }, + { 0x000008d7, 0x0080 }, + { 0x000008d8, 0x0000 }, + { 0x000008d9, 0x0080 }, + { 0x000008da, 0x0000 }, + { 0x000008db, 0x0080 }, + { 0x000008dc, 0x0000 }, + { 0x000008dd, 0x0080 }, + { 0x000008de, 0x0000 }, + { 0x000008df, 0x0080 }, + { 0x00000900, 0x0000 }, + { 0x00000901, 0x0080 }, + { 0x00000902, 0x0000 }, + { 0x00000903, 0x0080 }, + { 0x00000904, 0x0000 }, + { 0x00000905, 0x0080 }, + { 0x00000906, 0x0000 }, + { 0x00000907, 0x0080 }, + { 0x00000908, 0x0000 }, + { 0x00000909, 0x0080 }, + { 0x0000090a, 0x0000 }, + { 0x0000090b, 0x0080 }, + { 0x0000090c, 0x0000 }, + { 0x0000090d, 0x0080 }, + { 0x0000090e, 0x0000 }, + { 0x0000090f, 0x0080 }, + { 0x00000910, 0x0000 }, + { 0x00000911, 0x0080 }, + { 0x00000912, 0x0000 }, + { 0x00000913, 0x0080 }, + { 0x00000914, 0x0000 }, + { 0x00000915, 0x0080 }, + { 0x00000916, 0x0000 }, + { 0x00000917, 0x0080 }, + { 0x00000918, 0x0000 }, + { 0x00000919, 0x0080 }, + { 0x0000091a, 0x0000 }, + { 0x0000091b, 0x0080 }, + { 0x0000091c, 0x0000 }, + { 0x0000091d, 0x0080 }, + { 0x0000091e, 0x0000 }, + { 0x0000091f, 0x0080 }, + { 0x00000940, 0x0000 }, + { 0x00000941, 0x0080 }, + { 0x00000942, 0x0000 }, + { 0x00000943, 0x0080 }, + { 0x00000944, 0x0000 }, + { 0x00000945, 0x0080 }, + { 0x00000946, 0x0000 }, + { 0x00000947, 0x0080 }, + { 0x00000948, 0x0000 }, + { 0x00000949, 0x0080 }, + { 0x0000094a, 0x0000 }, + { 0x0000094b, 0x0080 }, + { 0x0000094c, 0x0000 }, + { 0x0000094d, 0x0080 }, + { 0x0000094e, 0x0000 }, + { 0x0000094f, 0x0080 }, + { 0x00000950, 0x0000 }, + { 0x00000958, 0x0000 }, + { 0x00000960, 0x0000 }, + { 0x00000968, 0x0000 }, + { 0x00000970, 0x0000 }, + { 0x00000978, 0x0000 }, + { 0x00000980, 0x0000 }, + { 0x00000981, 0x0080 }, + { 0x00000982, 0x0000 }, + { 0x00000983, 0x0080 }, + { 0x00000984, 0x0000 }, + { 0x00000985, 0x0080 }, + { 0x00000986, 0x0000 }, + { 0x00000987, 0x0080 }, + { 0x00000988, 0x0000 }, + { 0x00000989, 0x0080 }, + { 0x0000098a, 0x0000 }, + { 0x0000098b, 0x0080 }, + { 0x0000098c, 0x0000 }, + { 0x0000098d, 0x0080 }, + { 0x0000098e, 0x0000 }, + { 0x0000098f, 0x0080 }, + { 0x00000990, 0x0000 }, + { 0x00000998, 0x0000 }, + { 0x000009a0, 0x0000 }, + { 0x000009a8, 0x0000 }, + { 0x000009b0, 0x0000 }, + { 0x000009b8, 0x0000 }, + { 0x000009c0, 0x0000 }, + { 0x000009c1, 0x0080 }, + { 0x000009c2, 0x0000 }, + { 0x000009c3, 0x0080 }, + { 0x000009c4, 0x0000 }, + { 0x000009c5, 0x0080 }, + { 0x000009c6, 0x0000 }, + { 0x000009c7, 0x0080 }, + { 0x000009c8, 0x0000 }, + { 0x000009c9, 0x0080 }, + { 0x000009ca, 0x0000 }, + { 0x000009cb, 0x0080 }, + { 0x000009cc, 0x0000 }, + { 0x000009cd, 0x0080 }, + { 0x000009ce, 0x0000 }, + { 0x000009cf, 0x0080 }, + { 0x000009d0, 0x0000 }, + { 0x000009d8, 0x0000 }, + { 0x000009e0, 0x0000 }, + { 0x000009e8, 0x0000 }, + { 0x000009f0, 0x0000 }, + { 0x000009f8, 0x0000 }, + { 0x00000a00, 0x0000 }, + { 0x00000a01, 0x0080 }, + { 0x00000a02, 0x0000 }, + { 0x00000a03, 0x0080 }, + { 0x00000a04, 0x0000 }, + { 0x00000a05, 0x0080 }, + { 0x00000a06, 0x0000 }, + { 0x00000a07, 0x0080 }, + { 0x00000a08, 0x0000 }, + { 0x00000a09, 0x0080 }, + { 0x00000a0a, 0x0000 }, + { 0x00000a0b, 0x0080 }, + { 0x00000a0c, 0x0000 }, + { 0x00000a0d, 0x0080 }, + { 0x00000a0e, 0x0000 }, + { 0x00000a0f, 0x0080 }, + { 0x00000a10, 0x0000 }, + { 0x00000a18, 0x0000 }, + { 0x00000a20, 0x0000 }, + { 0x00000a28, 0x0000 }, + { 0x00000a30, 0x0000 }, + { 0x00000a38, 0x0000 }, + { 0x00000a40, 0x0000 }, + { 0x00000a41, 0x0080 }, + { 0x00000a42, 0x0000 }, + { 0x00000a43, 0x0080 }, + { 0x00000a44, 0x0000 }, + { 0x00000a45, 0x0080 }, + { 0x00000a46, 0x0000 }, + { 0x00000a47, 0x0080 }, + { 0x00000a48, 0x0000 }, + { 0x00000a49, 0x0080 }, + { 0x00000a4a, 0x0000 }, + { 0x00000a4b, 0x0080 }, + { 0x00000a4c, 0x0000 }, + { 0x00000a4d, 0x0080 }, + { 0x00000a4e, 0x0000 }, + { 0x00000a4f, 0x0080 }, + { 0x00000a50, 0x0000 }, + { 0x00000a58, 0x0000 }, + { 0x00000a60, 0x0000 }, + { 0x00000a68, 0x0000 }, + { 0x00000a70, 0x0000 }, + { 0x00000a78, 0x0000 }, + { 0x00000a80, 0x0000 }, + { 0x00000a88, 0x0000 }, + { 0x00000a90, 0x0000 }, + { 0x00000a98, 0x0000 }, + { 0x00000aa0, 0x0000 }, + { 0x00000aa8, 0x0000 }, + { 0x00000ab0, 0x0000 }, + { 0x00000ab8, 0x0000 }, + { 0x00000b00, 0x0000 }, + { 0x00000b08, 0x0000 }, + { 0x00000b10, 0x0000 }, + { 0x00000b18, 0x0000 }, + { 0x00000b20, 0x0000 }, + { 0x00000b28, 0x0000 }, + { 0x00000b30, 0x0000 }, + { 0x00000b38, 0x0000 }, + { 0x00000b40, 0x0000 }, + { 0x00000b48, 0x0000 }, + { 0x00000b50, 0x0000 }, + { 0x00000b58, 0x0000 }, + { 0x00000b60, 0x0000 }, + { 0x00000b68, 0x0000 }, + { 0x00000b70, 0x0000 }, + { 0x00000b78, 0x0000 }, + { 0x00000b80, 0x0000 }, + { 0x00000b88, 0x0000 }, + { 0x00000ba0, 0x0000 }, + { 0x00000ba8, 0x0000 }, + { 0x00000bc0, 0x0000 }, /* R3008 - ISRC4DEC1MIX Input 1 Source */ + { 0x00000bc8, 0x0000 }, /* R3016 - ISRC4DEC2MIX Input 1 Source */ + { 0x00000be0, 0x0000 }, /* R3040 - ISRC4INT1MIX Input 1 Source */ + { 0x00000be8, 0x0000 }, /* R3048 - ISRC4INT2MIX Input 1 Source */ + { 0x00000c00, 0x0000 }, + { 0x00000c01, 0x0080 }, + { 0x00000c02, 0x0000 }, + { 0x00000c03, 0x0080 }, + { 0x00000c04, 0x0000 }, + { 0x00000c05, 0x0080 }, + { 0x00000c06, 0x0000 }, + { 0x00000c07, 0x0080 }, + { 0x00000c08, 0x0000 }, + { 0x00000c09, 0x0080 }, + { 0x00000c0a, 0x0000 }, + { 0x00000c0b, 0x0080 }, + { 0x00000c0c, 0x0000 }, + { 0x00000c0d, 0x0080 }, + { 0x00000c0e, 0x0000 }, + { 0x00000c0f, 0x0080 }, + { 0x00000c10, 0x0000 }, /* R3088 (0xC10) - DSP6AUX1MIX Input 1 */ + { 0x00000c18, 0x0000 }, /* R3088 (0xC18) - DSP6AUX2MIX Input 1 */ + { 0x00000c20, 0x0000 }, /* R3088 (0xC20) - DSP6AUX3MIX Input 1 */ + { 0x00000c28, 0x0000 }, /* R3088 (0xC28) - DSP6AUX4MIX Input 1 */ + { 0x00000c30, 0x0000 }, /* R3088 (0xC30) - DSP6AUX5MIX Input 1 */ + { 0x00000c38, 0x0000 }, /* R3088 (0xC38) - DSP6AUX6MIX Input 1 */ + { 0x00000c40, 0x0000 }, + { 0x00000c41, 0x0080 }, + { 0x00000c42, 0x0000 }, + { 0x00000c43, 0x0080 }, + { 0x00000c44, 0x0000 }, + { 0x00000c45, 0x0080 }, + { 0x00000c46, 0x0000 }, + { 0x00000c47, 0x0080 }, + { 0x00000c48, 0x0000 }, + { 0x00000c49, 0x0080 }, + { 0x00000c4a, 0x0000 }, + { 0x00000c4b, 0x0080 }, + { 0x00000c4c, 0x0000 }, + { 0x00000c4d, 0x0080 }, + { 0x00000c4e, 0x0000 }, + { 0x00000c4f, 0x0080 }, + { 0x00000c50, 0x0000 }, + { 0x00000c58, 0x0000 }, + { 0x00000c60, 0x0000 }, + { 0x00000c68, 0x0000 }, + { 0x00000c70, 0x0000 }, + { 0x00000c78, 0x0000 }, + { 0x00000e00, 0x0000 }, /* R3584 (0xE00) - FX_Ctrl1 */ + { 0x00000e10, 0x6318 }, /* R3600 (0xE10) - EQ1_1 */ + { 0x00000e11, 0x6300 }, /* R3601 (0xE11) - EQ1_2 */ + { 0x00000e12, 0x0fc8 }, /* R3602 (0xE12) - EQ1_3 */ + { 0x00000e13, 0x03fe }, /* R3603 (0xE13) - EQ1_4 */ + { 0x00000e14, 0x00e0 }, /* R3604 (0xE14) - EQ1_5 */ + { 0x00000e15, 0x1ec4 }, /* R3605 (0xE15) - EQ1_6 */ + { 0x00000e16, 0xf136 }, /* R3606 (0xE16) - EQ1_7 */ + { 0x00000e17, 0x0409 }, /* R3607 (0xE17) - EQ1_8 */ + { 0x00000e18, 0x04cc }, /* R3608 (0xE18) - EQ1_9 */ + { 0x00000e19, 0x1c9b }, /* R3609 (0xE19) - EQ1_10 */ + { 0x00000e1a, 0xf337 }, /* R3610 (0xE1A) - EQ1_11 */ + { 0x00000e1b, 0x040b }, /* R3611 (0xE1B) - EQ1_12 */ + { 0x00000e1c, 0x0cbb }, /* R3612 (0xE1C) - EQ1_13 */ + { 0x00000e1d, 0x16f8 }, /* R3613 (0xE1D) - EQ1_14 */ + { 0x00000e1e, 0xf7d9 }, /* R3614 (0xE1E) - EQ1_15 */ + { 0x00000e1f, 0x040a }, /* R3615 (0xE1F) - EQ1_16 */ + { 0x00000e20, 0x1f14 }, /* R3616 (0xE20) - EQ1_17 */ + { 0x00000e21, 0x058c }, /* R3617 (0xE21) - EQ1_18 */ + { 0x00000e22, 0x0563 }, /* R3618 (0xE22) - EQ1_19 */ + { 0x00000e23, 0x4000 }, /* R3619 (0xE23) - EQ1_20 */ + { 0x00000e24, 0x0b75 }, /* R3620 (0xE24) - EQ1_21 */ + { 0x00000e26, 0x6318 }, /* R3622 (0xE26) - EQ2_1 */ + { 0x00000e27, 0x6300 }, /* R3623 (0xE27) - EQ2_2 */ + { 0x00000e28, 0x0fc8 }, /* R3624 (0xE28) - EQ2_3 */ + { 0x00000e29, 0x03fe }, /* R3625 (0xE29) - EQ2_4 */ + { 0x00000e2a, 0x00e0 }, /* R3626 (0xE2A) - EQ2_5 */ + { 0x00000e2b, 0x1ec4 }, /* R3627 (0xE2B) - EQ2_6 */ + { 0x00000e2c, 0xf136 }, /* R3628 (0xE2C) - EQ2_7 */ + { 0x00000e2d, 0x0409 }, /* R3629 (0xE2D) - EQ2_8 */ + { 0x00000e2e, 0x04cc }, /* R3630 (0xE2E) - EQ2_9 */ + { 0x00000e2f, 0x1c9b }, /* R3631 (0xE2F) - EQ2_10 */ + { 0x00000e30, 0xf337 }, /* R3632 (0xE30) - EQ2_11 */ + { 0x00000e31, 0x040b }, /* R3633 (0xE31) - EQ2_12 */ + { 0x00000e32, 0x0cbb }, /* R3634 (0xE32) - EQ2_13 */ + { 0x00000e33, 0x16f8 }, /* R3635 (0xE33) - EQ2_14 */ + { 0x00000e34, 0xf7d9 }, /* R3636 (0xE34) - EQ2_15 */ + { 0x00000e35, 0x040a }, /* R3637 (0xE35) - EQ2_16 */ + { 0x00000e36, 0x1f14 }, /* R3638 (0xE36) - EQ2_17 */ + { 0x00000e37, 0x058c }, /* R3639 (0xE37) - EQ2_18 */ + { 0x00000e38, 0x0563 }, /* R3640 (0xE38) - EQ2_19 */ + { 0x00000e39, 0x4000 }, /* R3641 (0xE39) - EQ2_20 */ + { 0x00000e3a, 0x0b75 }, /* R3642 (0xE3A) - EQ2_21 */ + { 0x00000e3c, 0x6318 }, /* R3644 (0xE3C) - EQ3_1 */ + { 0x00000e3d, 0x6300 }, /* R3645 (0xE3D) - EQ3_2 */ + { 0x00000e3e, 0x0fc8 }, /* R3646 (0xE3E) - EQ3_3 */ + { 0x00000e3f, 0x03fe }, /* R3647 (0xE3F) - EQ3_4 */ + { 0x00000e40, 0x00e0 }, /* R3648 (0xE40) - EQ3_5 */ + { 0x00000e41, 0x1ec4 }, /* R3649 (0xE41) - EQ3_6 */ + { 0x00000e42, 0xf136 }, /* R3650 (0xE42) - EQ3_7 */ + { 0x00000e43, 0x0409 }, /* R3651 (0xE43) - EQ3_8 */ + { 0x00000e44, 0x04cc }, /* R3652 (0xE44) - EQ3_9 */ + { 0x00000e45, 0x1c9b }, /* R3653 (0xE45) - EQ3_10 */ + { 0x00000e46, 0xf337 }, /* R3654 (0xE46) - EQ3_11 */ + { 0x00000e47, 0x040b }, /* R3655 (0xE47) - EQ3_12 */ + { 0x00000e48, 0x0cbb }, /* R3656 (0xE48) - EQ3_13 */ + { 0x00000e49, 0x16f8 }, /* R3657 (0xE49) - EQ3_14 */ + { 0x00000e4a, 0xf7d9 }, /* R3658 (0xE4A) - EQ3_15 */ + { 0x00000e4b, 0x040a }, /* R3659 (0xE4B) - EQ3_16 */ + { 0x00000e4c, 0x1f14 }, /* R3660 (0xE4C) - EQ3_17 */ + { 0x00000e4d, 0x058c }, /* R3661 (0xE4D) - EQ3_18 */ + { 0x00000e4e, 0x0563 }, /* R3662 (0xE4E) - EQ3_19 */ + { 0x00000e4f, 0x4000 }, /* R3663 (0xE4F) - EQ3_20 */ + { 0x00000e50, 0x0b75 }, /* R3664 (0xE50) - EQ3_21 */ + { 0x00000e52, 0x6318 }, /* R3666 (0xE52) - EQ4_1 */ + { 0x00000e53, 0x6300 }, /* R3667 (0xE53) - EQ4_2 */ + { 0x00000e54, 0x0fc8 }, /* R3668 (0xE54) - EQ4_3 */ + { 0x00000e55, 0x03fe }, /* R3669 (0xE55) - EQ4_4 */ + { 0x00000e56, 0x00e0 }, /* R3670 (0xE56) - EQ4_5 */ + { 0x00000e57, 0x1ec4 }, /* R3671 (0xE57) - EQ4_6 */ + { 0x00000e58, 0xf136 }, /* R3672 (0xE58) - EQ4_7 */ + { 0x00000e59, 0x0409 }, /* R3673 (0xE59) - EQ4_8 */ + { 0x00000e5a, 0x04cc }, /* R3674 (0xE5A) - EQ4_9 */ + { 0x00000e5b, 0x1c9b }, /* R3675 (0xE5B) - EQ4_10 */ + { 0x00000e5c, 0xf337 }, /* R3676 (0xE5C) - EQ4_11 */ + { 0x00000e5d, 0x040b }, /* R3677 (0xE5D) - EQ4_12 */ + { 0x00000e5e, 0x0cbb }, /* R3678 (0xE5E) - EQ4_13 */ + { 0x00000e5f, 0x16f8 }, /* R3679 (0xE5F) - EQ4_14 */ + { 0x00000e60, 0xf7d9 }, /* R3680 (0xE60) - EQ4_15 */ + { 0x00000e61, 0x040a }, /* R3681 (0xE61) - EQ4_16 */ + { 0x00000e62, 0x1f14 }, /* R3682 (0xE62) - EQ4_17 */ + { 0x00000e63, 0x058c }, /* R3683 (0xE63) - EQ4_18 */ + { 0x00000e64, 0x0563 }, /* R3684 (0xE64) - EQ4_19 */ + { 0x00000e65, 0x4000 }, /* R3685 (0xE65) - EQ4_20 */ + { 0x00000e66, 0x0b75 }, /* R3686 (0xE66) - EQ4_21 */ + { 0x00000e80, 0x0018 }, /* R3712 (0xE80) - DRC1 ctrl1 */ + { 0x00000e81, 0x0933 }, /* R3713 (0xE81) - DRC1 ctrl2 */ + { 0x00000e82, 0x0018 }, /* R3714 (0xE82) - DRC1 ctrl3 */ + { 0x00000e83, 0x0000 }, /* R3715 (0xE83) - DRC1 ctrl4 */ + { 0x00000e84, 0x0000 }, /* R3716 (0xE84) - DRC1 ctrl5 */ + { 0x00000e88, 0x0933 }, /* R3720 (0xE88) - DRC2 ctrl1 */ + { 0x00000e89, 0x0018 }, /* R3721 (0xE89) - DRC2 ctrl2 */ + { 0x00000e8a, 0x0000 }, /* R3722 (0xE8A) - DRC2 ctrl3 */ + { 0x00000e8b, 0x0000 }, /* R3723 (0xE8B) - DRC2 ctrl4 */ + { 0x00000e8c, 0x0040 }, /* R3724 (0xE8C) - DRC2 ctrl5 */ + { 0x00000ec0, 0x0000 }, /* R3776 (0xEC0) - HPLPF1_1 */ + { 0x00000ec1, 0x0000 }, /* R3777 (0xEC1) - HPLPF1_2 */ + { 0x00000ec4, 0x0000 }, /* R3780 (0xEC4) - HPLPF2_1 */ + { 0x00000ec5, 0x0000 }, /* R3781 (0xEC5) - HPLPF2_2 */ + { 0x00000ec8, 0x0000 }, /* R3784 (0xEC8) - HPLPF3_1 */ + { 0x00000ec9, 0x0000 }, /* R3785 (0xEC9) - HPLPF3_2 */ + { 0x00000ecc, 0x0000 }, /* R3788 (0xECC) - HPLPF4_1 */ + { 0x00000ecd, 0x0000 }, /* R3789 (0xECD) - HPLPF4_2 */ + { 0x00000ed0, 0x0000 }, /* R3792 (0xED0) - ASRC2_ENABLE */ + { 0x00000ed2, 0x0000 }, /* R3794 (0xED2) - ASRC2_RATE1 */ + { 0x00000ed3, 0x4000 }, /* R3795 (0xED3) - ASRC2_RATE2 */ + { 0x00000ee0, 0x0000 }, /* R3808 (0xEE0) - ASRC1_ENABLE */ + { 0x00000ee2, 0x0000 }, /* R3810 (0xEE2) - ASRC1_RATE1 */ + { 0x00000ee3, 0x4000 }, /* R3811 (0xEE3) - ASRC1_RATE2 */ + { 0x00000ef0, 0x0000 }, /* R3824 (0xEF0) - ISRC 1 CTRL 1 */ + { 0x00000ef1, 0x0001 }, /* R3825 (0xEF1) - ISRC 1 CTRL 2 */ + { 0x00000ef2, 0x0000 }, /* R3826 (0xEF2) - ISRC 1 CTRL 3 */ + { 0x00000ef3, 0x0000 }, /* R3827 (0xEF3) - ISRC 2 CTRL 1 */ + { 0x00000ef4, 0x0001 }, /* R3828 (0xEF4) - ISRC 2 CTRL 2 */ + { 0x00000ef5, 0x0000 }, /* R3829 (0xEF5) - ISRC 2 CTRL 3 */ + { 0x00000ef6, 0x0000 }, /* R3830 (0xEF6) - ISRC 3 CTRL 1 */ + { 0x00000ef7, 0x0001 }, /* R3831 (0xEF7) - ISRC 3 CTRL 2 */ + { 0x00000ef8, 0x0000 }, /* R3832 (0xEF8) - ISRC 3 CTRL 3 */ + { 0x00000ef9, 0x0000 }, /* R3833 - ISRC 4 CTRL 1 */ + { 0x00000efa, 0x0001 }, /* R3834 - ISRC 4 CTRL 2 */ + { 0x00000efb, 0x0000 }, /* R3835 - ISRC 4 CTRL 3 */ + { 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */ + { 0x00000F02, 0x0000 }, /* R3842 - Arizona DSP Status */ + { 0x00000F08, 0x001c }, /* R3848 - ANC Coefficient */ + { 0x00000F09, 0x0000 }, /* R3849 - ANC Coefficient */ + { 0x00000F0A, 0x0000 }, /* R3850 - ANC Coefficient */ + { 0x00000F0B, 0x0000 }, /* R3851 - ANC Coefficient */ + { 0x00000F0C, 0x0000 }, /* R3852 - ANC Coefficient */ + { 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */ + { 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */ + { 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */ + { 0x00000F10, 0x0000 }, /* R3856 - ANC Coefficient */ + { 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */ + { 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */ + { 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */ + { 0x00000F17, 0x0004 }, /* R3863 - FCL ADC Reformatter Control */ + { 0x00000F18, 0x0004 }, /* R3864 - ANC Coefficient */ + { 0x00000F19, 0x0002 }, /* R3865 - ANC Coefficient */ + { 0x00000F1A, 0x0000 }, /* R3866 - ANC Coefficient */ + { 0x00000F1B, 0x0010 }, /* R3867 - ANC Coefficient */ + { 0x00000F1C, 0x0000 }, /* R3868 - ANC Coefficient */ + { 0x00000F1D, 0x0000 }, /* R3869 - ANC Coefficient */ + { 0x00000F1E, 0x0000 }, /* R3870 - ANC Coefficient */ + { 0x00000F1F, 0x0000 }, /* R3871 - ANC Coefficient */ + { 0x00000F20, 0x0000 }, /* R3872 - ANC Coefficient */ + { 0x00000F21, 0x0000 }, /* R3873 - ANC Coefficient */ + { 0x00000F22, 0x0000 }, /* R3874 - ANC Coefficient */ + { 0x00000F23, 0x0000 }, /* R3875 - ANC Coefficient */ + { 0x00000F24, 0x0000 }, /* R3876 - ANC Coefficient */ + { 0x00000F25, 0x0000 }, /* R3877 - ANC Coefficient */ + { 0x00000F26, 0x0000 }, /* R3878 - ANC Coefficient */ + { 0x00000F27, 0x0000 }, /* R3879 - ANC Coefficient */ + { 0x00000F28, 0x0000 }, /* R3880 - ANC Coefficient */ + { 0x00000F29, 0x0000 }, /* R3881 - ANC Coefficient */ + { 0x00000F2A, 0x0000 }, /* R3882 - ANC Coefficient */ + { 0x00000F2B, 0x0000 }, /* R3883 - ANC Coefficient */ + { 0x00000F2C, 0x0000 }, /* R3884 - ANC Coefficient */ + { 0x00000F2D, 0x0000 }, /* R3885 - ANC Coefficient */ + { 0x00000F2E, 0x0000 }, /* R3886 - ANC Coefficient */ + { 0x00000F2F, 0x0000 }, /* R3887 - ANC Coefficient */ + { 0x00000F30, 0x0000 }, /* R3888 - ANC Coefficient */ + { 0x00000F31, 0x0000 }, /* R3889 - ANC Coefficient */ + { 0x00000F32, 0x0000 }, /* R3890 - ANC Coefficient */ + { 0x00000F33, 0x0000 }, /* R3891 - ANC Coefficient */ + { 0x00000F34, 0x0000 }, /* R3892 - ANC Coefficient */ + { 0x00000F35, 0x0000 }, /* R3893 - ANC Coefficient */ + { 0x00000F36, 0x0000 }, /* R3894 - ANC Coefficient */ + { 0x00000F37, 0x0000 }, /* R3895 - ANC Coefficient */ + { 0x00000F38, 0x0000 }, /* R3896 - ANC Coefficient */ + { 0x00000F39, 0x0000 }, /* R3897 - ANC Coefficient */ + { 0x00000F3A, 0x0000 }, /* R3898 - ANC Coefficient */ + { 0x00000F3B, 0x0000 }, /* R3899 - ANC Coefficient */ + { 0x00000F3C, 0x0000 }, /* R3900 - ANC Coefficient */ + { 0x00000F3D, 0x0000 }, /* R3901 - ANC Coefficient */ + { 0x00000F3E, 0x0000 }, /* R3902 - ANC Coefficient */ + { 0x00000F3F, 0x0000 }, /* R3903 - ANC Coefficient */ + { 0x00000F40, 0x0000 }, /* R3904 - ANC Coefficient */ + { 0x00000F41, 0x0000 }, /* R3905 - ANC Coefficient */ + { 0x00000F42, 0x0000 }, /* R3906 - ANC Coefficient */ + { 0x00000F43, 0x0000 }, /* R3907 - ANC Coefficient */ + { 0x00000F44, 0x0000 }, /* R3908 - ANC Coefficient */ + { 0x00000F45, 0x0000 }, /* R3909 - ANC Coefficient */ + { 0x00000F46, 0x0000 }, /* R3910 - ANC Coefficient */ + { 0x00000F47, 0x0000 }, /* R3911 - ANC Coefficient */ + { 0x00000F48, 0x0000 }, /* R3912 - ANC Coefficient */ + { 0x00000F49, 0x0000 }, /* R3913 - ANC Coefficient */ + { 0x00000F4A, 0x0000 }, /* R3914 - ANC Coefficient */ + { 0x00000F4B, 0x0000 }, /* R3915 - ANC Coefficient */ + { 0x00000F4C, 0x0000 }, /* R3916 - ANC Coefficient */ + { 0x00000F4D, 0x0000 }, /* R3917 - ANC Coefficient */ + { 0x00000F4E, 0x0000 }, /* R3918 - ANC Coefficient */ + { 0x00000F4F, 0x0000 }, /* R3919 - ANC Coefficient */ + { 0x00000F50, 0x0000 }, /* R3920 - ANC Coefficient */ + { 0x00000F51, 0x0000 }, /* R3921 - ANC Coefficient */ + { 0x00000F52, 0x0000 }, /* R3922 - ANC Coefficient */ + { 0x00000F53, 0x0000 }, /* R3923 - ANC Coefficient */ + { 0x00000F54, 0x0000 }, /* R3924 - ANC Coefficient */ + { 0x00000F55, 0x0000 }, /* R3925 - ANC Coefficient */ + { 0x00000F56, 0x0000 }, /* R3926 - ANC Coefficient */ + { 0x00000F57, 0x0000 }, /* R3927 - ANC Coefficient */ + { 0x00000F58, 0x0000 }, /* R3928 - ANC Coefficient */ + { 0x00000F59, 0x0000 }, /* R3929 - ANC Coefficient */ + { 0x00000F5A, 0x0000 }, /* R3930 - ANC Coefficient */ + { 0x00000F5B, 0x0000 }, /* R3931 - ANC Coefficient */ + { 0x00000F5C, 0x0000 }, /* R3932 - ANC Coefficient */ + { 0x00000F5D, 0x0000 }, /* R3933 - ANC Coefficient */ + { 0x00000F5E, 0x0000 }, /* R3934 - ANC Coefficient */ + { 0x00000F5F, 0x0000 }, /* R3935 - ANC Coefficient */ + { 0x00000F60, 0x0000 }, /* R3936 - ANC Coefficient */ + { 0x00000F61, 0x0000 }, /* R3937 - ANC Coefficient */ + { 0x00000F62, 0x0000 }, /* R3938 - ANC Coefficient */ + { 0x00000F63, 0x0000 }, /* R3939 - ANC Coefficient */ + { 0x00000F64, 0x0000 }, /* R3940 - ANC Coefficient */ + { 0x00000F65, 0x0000 }, /* R3941 - ANC Coefficient */ + { 0x00000F66, 0x0000 }, /* R3942 - ANC Coefficient */ + { 0x00000F67, 0x0000 }, /* R3943 - ANC Coefficient */ + { 0x00000F68, 0x0000 }, /* R3944 - ANC Coefficient */ + { 0x00000F69, 0x0000 }, /* R3945 - ANC Coefficient */ + { 0x00000F71, 0x0000 }, /* R3953 - FCR Filter Control */ + { 0x00000F73, 0x0004 }, /* R3955 - FCR ADC Reformatter Control */ + { 0x00000F74, 0x0004 }, /* R3956 - ANC Coefficient */ + { 0x00000F75, 0x0002 }, /* R3957 - ANC Coefficient */ + { 0x00000F76, 0x0000 }, /* R3958 - ANC Coefficient */ + { 0x00000F77, 0x0010 }, /* R3959 - ANC Coefficient */ + { 0x00000F78, 0x0000 }, /* R3960 - ANC Coefficient */ + { 0x00000F79, 0x0000 }, /* R3961 - ANC Coefficient */ + { 0x00000F7A, 0x0000 }, /* R3962 - ANC Coefficient */ + { 0x00000F7B, 0x0000 }, /* R3963 - ANC Coefficient */ + { 0x00000F7C, 0x0000 }, /* R3964 - ANC Coefficient */ + { 0x00000F7D, 0x0000 }, /* R3965 - ANC Coefficient */ + { 0x00000F7E, 0x0000 }, /* R3966 - ANC Coefficient */ + { 0x00000F7F, 0x0000 }, /* R3967 - ANC Coefficient */ + { 0x00000F80, 0x0000 }, /* R3968 - ANC Coefficient */ + { 0x00000F81, 0x0000 }, /* R3969 - ANC Coefficient */ + { 0x00000F82, 0x0000 }, /* R3970 - ANC Coefficient */ + { 0x00000F83, 0x0000 }, /* R3971 - ANC Coefficient */ + { 0x00000F84, 0x0000 }, /* R3972 - ANC Coefficient */ + { 0x00000F85, 0x0000 }, /* R3973 - ANC Coefficient */ + { 0x00000F86, 0x0000 }, /* R3974 - ANC Coefficient */ + { 0x00000F87, 0x0000 }, /* R3975 - ANC Coefficient */ + { 0x00000F88, 0x0000 }, /* R3976 - ANC Coefficient */ + { 0x00000F89, 0x0000 }, /* R3977 - ANC Coefficient */ + { 0x00000F8A, 0x0000 }, /* R3978 - ANC Coefficient */ + { 0x00000F8B, 0x0000 }, /* R3979 - ANC Coefficient */ + { 0x00000F8C, 0x0000 }, /* R3980 - ANC Coefficient */ + { 0x00000F8D, 0x0000 }, /* R3981 - ANC Coefficient */ + { 0x00000F8E, 0x0000 }, /* R3982 - ANC Coefficient */ + { 0x00000F8F, 0x0000 }, /* R3983 - ANC Coefficient */ + { 0x00000F90, 0x0000 }, /* R3984 - ANC Coefficient */ + { 0x00000F91, 0x0000 }, /* R3985 - ANC Coefficient */ + { 0x00000F92, 0x0000 }, /* R3986 - ANC Coefficient */ + { 0x00000F93, 0x0000 }, /* R3987 - ANC Coefficient */ + { 0x00000F94, 0x0000 }, /* R3988 - ANC Coefficient */ + { 0x00000F95, 0x0000 }, /* R3989 - ANC Coefficient */ + { 0x00000F96, 0x0000 }, /* R3990 - ANC Coefficient */ + { 0x00000F97, 0x0000 }, /* R3991 - ANC Coefficient */ + { 0x00000F98, 0x0000 }, /* R3992 - ANC Coefficient */ + { 0x00000F99, 0x0000 }, /* R3993 - ANC Coefficient */ + { 0x00000F9A, 0x0000 }, /* R3994 - ANC Coefficient */ + { 0x00000F9B, 0x0000 }, /* R3995 - ANC Coefficient */ + { 0x00000F9C, 0x0000 }, /* R3996 - ANC Coefficient */ + { 0x00000F9D, 0x0000 }, /* R3997 - ANC Coefficient */ + { 0x00000F9E, 0x0000 }, /* R3998 - ANC Coefficient */ + { 0x00000F9F, 0x0000 }, /* R3999 - ANC Coefficient */ + { 0x00000FA0, 0x0000 }, /* R4000 - ANC Coefficient */ + { 0x00000FA1, 0x0000 }, /* R4001 - ANC Coefficient */ + { 0x00000FA2, 0x0000 }, /* R4002 - ANC Coefficient */ + { 0x00000FA3, 0x0000 }, /* R4003 - ANC Coefficient */ + { 0x00000FA4, 0x0000 }, /* R4004 - ANC Coefficient */ + { 0x00000FA5, 0x0000 }, /* R4005 - ANC Coefficient */ + { 0x00000FA6, 0x0000 }, /* R4006 - ANC Coefficient */ + { 0x00000FA7, 0x0000 }, /* R4007 - ANC Coefficient */ + { 0x00000FA8, 0x0000 }, /* R4008 - ANC Coefficient */ + { 0x00000FA9, 0x0000 }, /* R4009 - ANC Coefficient */ + { 0x00000FAA, 0x0000 }, /* R4010 - ANC Coefficient */ + { 0x00000FAB, 0x0000 }, /* R4011 - ANC Coefficient */ + { 0x00000FAC, 0x0000 }, /* R4012 - ANC Coefficient */ + { 0x00000FAD, 0x0000 }, /* R4013 - ANC Coefficient */ + { 0x00000FAE, 0x0000 }, /* R4014 - ANC Coefficient */ + { 0x00000FAF, 0x0000 }, /* R4015 - ANC Coefficient */ + { 0x00000FB0, 0x0000 }, /* R4016 - ANC Coefficient */ + { 0x00000FB1, 0x0000 }, /* R4017 - ANC Coefficient */ + { 0x00000FB2, 0x0000 }, /* R4018 - ANC Coefficient */ + { 0x00000FB3, 0x0000 }, /* R4019 - ANC Coefficient */ + { 0x00000FB4, 0x0000 }, /* R4020 - ANC Coefficient */ + { 0x00000FB5, 0x0000 }, /* R4021 - ANC Coefficient */ + { 0x00000FB6, 0x0000 }, /* R4022 - ANC Coefficient */ + { 0x00000FB7, 0x0000 }, /* R4023 - ANC Coefficient */ + { 0x00000FB8, 0x0000 }, /* R4024 - ANC Coefficient */ + { 0x00000FB9, 0x0000 }, /* R4025 - ANC Coefficient */ + { 0x00000FBA, 0x0000 }, /* R4026 - ANC Coefficient */ + { 0x00000FBB, 0x0000 }, /* R4027 - ANC Coefficient */ + { 0x00000FBC, 0x0000 }, /* R4028 - ANC Coefficient */ + { 0x00000FBD, 0x0000 }, /* R4029 - ANC Coefficient */ + { 0x00000FBE, 0x0000 }, /* R4030 - ANC Coefficient */ + { 0x00000FBF, 0x0000 }, /* R4031 - ANC Coefficient */ + { 0x00000FC0, 0x0000 }, /* R4032 - ANC Coefficient */ + { 0x00000FC1, 0x0000 }, /* R4033 - ANC Coefficient */ + { 0x00000FC2, 0x0000 }, /* R4034 - ANC Coefficient */ + { 0x00000FC3, 0x0000 }, /* R4035 - ANC Coefficient */ + { 0x00000FC4, 0x0000 }, /* R4036 - ANC Coefficient */ + { 0x00000FC5, 0x0000 }, /* R4037 - ANC Coefficient */ + { 0x00001300, 0x0000 }, /* R4864 - DAC Comp 1 */ + { 0x00001302, 0x0000 }, /* R4866 - DAC Comp 2 */ + { 0x00001380, 0x0000 }, + { 0x00001381, 0x0000 }, + { 0x00001382, 0x0000 }, + { 0x00001383, 0x0000 }, + { 0x00001390, 0x0000 }, + { 0x00001391, 0x0000 }, + { 0x00001392, 0x0000 }, + { 0x00001393, 0x0000 }, + { 0x000013a0, 0x0000 }, + { 0x000013a1, 0x0000 }, + { 0x000013a2, 0x0000 }, + { 0x000013a3, 0x0000 }, + { 0x000013b0, 0x0000 }, + { 0x000013b1, 0x0000 }, + { 0x000013b2, 0x0000 }, + { 0x000013b3, 0x0000 }, + { 0x000013c0, 0x0000 }, + { 0x000013c1, 0x0000 }, + { 0x000013c2, 0x0000 }, + { 0x000013c3, 0x0000 }, + { 0x000013d0, 0x0000 }, + { 0x000013d1, 0x0000 }, + { 0x000013d2, 0x0000 }, + { 0x000013d3, 0x0000 }, + { 0x000013e0, 0x0000 }, + { 0x000013e1, 0x0000 }, + { 0x000013e2, 0x0000 }, + { 0x000013e3, 0x0000 }, + { 0x000013f0, 0x0000 }, + { 0x000013f1, 0x0000 }, + { 0x000013f2, 0x0000 }, + { 0x000013f3, 0x0000 }, + { 0x00001400, 0x0000 }, + { 0x00001401, 0x0000 }, + { 0x00001402, 0x0000 }, + { 0x00001403, 0x0000 }, + { 0x00001410, 0x0000 }, + { 0x00001411, 0x0000 }, + { 0x00001412, 0x0000 }, + { 0x00001413, 0x0000 }, + { 0x00001420, 0x0000 }, + { 0x00001421, 0x0000 }, + { 0x00001422, 0x0000 }, + { 0x00001423, 0x0000 }, + { 0x00001430, 0x0000 }, + { 0x00001431, 0x0000 }, + { 0x00001432, 0x0000 }, + { 0x00001433, 0x0000 }, + { 0x00001701, 0xE000 }, /* R5889 - GPIO1 Control 2 */ + { 0x00001703, 0xE000 }, /* R5891 - GPIO2 Control 2 */ + { 0x00001705, 0xE000 }, /* R5893 - GPIO3 Control 2 */ + { 0x00001707, 0xE000 }, /* R5895 - GPIO4 Control 2 */ + { 0x00001709, 0xE000 }, /* R5897 - GPIO5 Control 2 */ + { 0x0000170B, 0xE000 }, /* R5899 - GPIO6 Control 2 */ + { 0x0000170D, 0xE000 }, /* R5901 - GPIO7 Control 2 */ + { 0x0000170F, 0xE000 }, /* R5903 - GPIO8 Control 2 */ + { 0x00001711, 0xE000 }, /* R5905 - GPIO9 Control 2 */ + { 0x00001713, 0xE000 }, /* R5907 - GPIO10 Control 2 */ + { 0x00001715, 0xE000 }, /* R5909 - GPIO11 Control 2 */ + { 0x00001717, 0xE000 }, /* R5911 - GPIO12 Control 2 */ + { 0x00001719, 0xE000 }, /* R5913 - GPIO13 Control 2 */ + { 0x0000171B, 0xE000 }, /* R5915 - GPIO14 Control 2 */ + { 0x0000171D, 0xE000 }, /* R5917 - GPIO15 Control 2 */ + { 0x0000171F, 0xE000 }, /* R5919 - GPIO16 Control 2 */ + { 0x00001721, 0xE000 }, /* R5921 - GPIO17 Control 2 */ + { 0x00001723, 0xE000 }, /* R5923 - GPIO18 Control 2 */ + { 0x00001725, 0xE000 }, /* R5925 - GPIO19 Control 2 */ + { 0x00001727, 0xE000 }, /* R5927 - GPIO20 Control 2 */ + { 0x00001729, 0xE000 }, /* R5929 - GPIO21 Control 2 */ + { 0x0000172B, 0xE000 }, /* R5931 - GPIO22 Control 2 */ + { 0x0000172D, 0xE000 }, /* R5933 - GPIO23 Control 2 */ + { 0x0000172F, 0xE000 }, /* R5935 - GPIO24 Control 2 */ + { 0x00001731, 0xE000 }, /* R5937 - GPIO25 Control 2 */ + { 0x00001733, 0xE000 }, /* R5939 - GPIO26 Control 2 */ + { 0x00001735, 0xE000 }, /* R5941 - GPIO27 Control 2 */ + { 0x00001737, 0xE000 }, /* R5943 - GPIO28 Control 2 */ + { 0x00001739, 0xE000 }, /* R5945 - GPIO29 Control 2 */ + { 0x0000173B, 0xE000 }, /* R5947 - GPIO30 Control 2 */ + { 0x0000173D, 0xE000 }, /* R5949 - GPIO31 Control 2 */ + { 0x0000173F, 0xE000 }, /* R5951 - GPIO32 Control 2 */ + { 0x00001741, 0xE000 }, /* R5953 - GPIO33 Control 2 */ + { 0x00001743, 0xE000 }, /* R5955 - GPIO34 Control 2 */ + { 0x00001745, 0xE000 }, /* R5957 - GPIO35 Control 2 */ + { 0x00001747, 0xE000 }, /* R5959 - GPIO36 Control 2 */ + { 0x00001749, 0xE000 }, /* R5961 - GPIO37 Control 2 */ + { 0x0000174B, 0xE000 }, /* R5963 - GPIO38 Control 2 */ + { 0x0000174D, 0xE000 }, /* R5965 - GPIO39 Control 2 */ + { 0x0000174F, 0xE000 }, /* R5967 - GPIO40 Control 2 */ + { 0x00001802, 0x0000 }, + { 0x00001803, 0x0000 }, + { 0x00001804, 0x0000 }, + { 0x00001807, 0x0000 }, + { 0x00001809, 0x0000 }, + { 0x0000180F, 0x0000 }, + { 0x00001813, 0x0000 }, + { 0x00001819, 0x0000 }, + { 0x0000181C, 0x0000 }, + { 0x00001840, 0xFFFF }, /* R6208 - IRQ1 Mask 1 */ + { 0x00001841, 0xFFFF }, /* R6209 - IRQ1 Mask 2 */ + { 0x00001842, 0xFFFF }, /* R6210 - IRQ1 Mask 3 */ + { 0x00001843, 0xFFFF }, /* R6211 - IRQ1 Mask 4 */ + { 0x00001844, 0xFFFF }, /* R6212 - IRQ1 Mask 5 */ + { 0x00001845, 0xFFFF }, /* R6213 - IRQ1 Mask 6 */ + { 0x00001846, 0xFFFF }, /* R6214 - IRQ1 Mask 7 */ + { 0x00001847, 0xFFFF }, /* R6215 - IRQ1 Mask 8 */ + { 0x00001848, 0xFFFF }, /* R6216 - IRQ1 Mask 9 */ + { 0x00001849, 0xFFFF }, /* R6217 - IRQ1 Mask 10 */ + { 0x0000184A, 0xFFFF }, /* R6218 - IRQ1 Mask 11 */ + { 0x0000184B, 0xFFFF }, /* R6219 - IRQ1 Mask 12 */ + { 0x0000184C, 0xFFFF }, /* R6220 - IRQ1 Mask 13 */ + { 0x0000184D, 0xFFFF }, /* R6221 - IRQ1 Mask 14 */ + { 0x0000184E, 0xFFFF }, /* R6222 - IRQ1 Mask 15 */ + { 0x00001948, 0xFFFF }, /* R6472 - IRQ2 Mask 9 */ + { 0x00001A06, 0x0000 }, /* R6662 - Interrupt Debounce 7 */ + { 0x00001A80, 0x4400 }, /* R6784 - IRQ1 CTRL */ +}; + +static bool clearwater_is_adsp_memory(struct device *dev, unsigned int reg) +{ + if ((reg >= 0x080000 && reg <= 0x085ffe) || + (reg >= 0x0a0000 && reg <= 0x0a7ffe) || + (reg >= 0x0c0000 && reg <= 0x0c1ffe) || + (reg >= 0x0e0000 && reg <= 0x0e1ffe) || + (reg >= 0x100000 && reg <= 0x10effe) || + (reg >= 0x120000 && reg <= 0x12bffe) || + (reg >= 0x136000 && reg <= 0x137ffe) || + (reg >= 0x140000 && reg <= 0x14bffe) || + (reg >= 0x160000 && reg <= 0x161ffe) || + (reg >= 0x180000 && reg <= 0x18effe) || + (reg >= 0x1a0000 && reg <= 0x1b1ffe) || + (reg >= 0x1b6000 && reg <= 0x1b7ffe) || + (reg >= 0x1c0000 && reg <= 0x1cbffe) || + (reg >= 0x1e0000 && reg <= 0x1e1ffe) || + (reg >= 0x200000 && reg <= 0x208ffe) || + (reg >= 0x220000 && reg <= 0x231ffe) || + (reg >= 0x240000 && reg <= 0x24bffe) || + (reg >= 0x260000 && reg <= 0x261ffe) || + (reg >= 0x280000 && reg <= 0x288ffe) || + (reg >= 0x2a0000 && reg <= 0x2a9ffe) || + (reg >= 0x2c0000 && reg <= 0x2c3ffe) || + (reg >= 0x2e0000 && reg <= 0x2e1ffe) || + (reg >= 0x300000 && reg <= 0x305ffe) || + (reg >= 0x320000 && reg <= 0x333ffe) || + (reg >= 0x340000 && reg <= 0x34bffe) || + (reg >= 0x360000 && reg <= 0x361ffe) || + (reg >= 0x380000 && reg <= 0x388ffe) || + (reg >= 0x3a0000 && reg <= 0x3a7ffe) || + (reg >= 0x3c0000 && reg <= 0x3c1ffe) || + (reg >= 0x3e0000 && reg <= 0x3e1ffe)) + return true; + else + return false; +} + +static bool clearwater_16bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x2C2: + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_SPI_CFG_1: + case ARIZONA_CTRL_IF_I2C1_CFG_1: + case ARIZONA_CTRL_IF_I2C2_CFG_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case CLEARWATER_COMFORT_NOISE_GENERATOR: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_CLOCK_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case CLEARWATER_DSP_CLOCK_1: + case CLEARWATER_DSP_CLOCK_2: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_OUTPUT_ASYNC_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_CONTROL_7: + case ARIZONA_FLL1_LOOP_FILTER_TEST_1: + case ARIZONA_FLL1_NCO_TEST_0: + case ARIZONA_FLL1_SYNCHRONISER_1: + case ARIZONA_FLL1_SYNCHRONISER_2: + case ARIZONA_FLL1_SYNCHRONISER_3: + case ARIZONA_FLL1_SYNCHRONISER_4: + case ARIZONA_FLL1_SYNCHRONISER_5: + case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SYNCHRONISER_7: + case ARIZONA_FLL1_SPREAD_SPECTRUM: + case ARIZONA_FLL1_GPIO_CLOCK: + case ARIZONA_FLL2_CONTROL_1: + case ARIZONA_FLL2_CONTROL_2: + case ARIZONA_FLL2_CONTROL_3: + case ARIZONA_FLL2_CONTROL_4: + case ARIZONA_FLL2_CONTROL_5: + case ARIZONA_FLL2_CONTROL_6: + case ARIZONA_FLL2_CONTROL_7: + case ARIZONA_FLL2_LOOP_FILTER_TEST_1: + case ARIZONA_FLL2_NCO_TEST_0: + case ARIZONA_FLL2_SYNCHRONISER_1: + case ARIZONA_FLL2_SYNCHRONISER_2: + case ARIZONA_FLL2_SYNCHRONISER_3: + case ARIZONA_FLL2_SYNCHRONISER_4: + case ARIZONA_FLL2_SYNCHRONISER_5: + case ARIZONA_FLL2_SYNCHRONISER_6: + case ARIZONA_FLL2_SYNCHRONISER_7: + case ARIZONA_FLL2_SPREAD_SPECTRUM: + case ARIZONA_FLL2_GPIO_CLOCK: + case ARIZONA_FLL3_CONTROL_1: + case ARIZONA_FLL3_CONTROL_2: + case ARIZONA_FLL3_CONTROL_3: + case ARIZONA_FLL3_CONTROL_4: + case ARIZONA_FLL3_CONTROL_5: + case ARIZONA_FLL3_CONTROL_6: + case ARIZONA_FLL3_CONTROL_7: + case ARIZONA_FLL3_LOOP_FILTER_TEST_1: + case ARIZONA_FLL3_NCO_TEST_0: + case ARIZONA_FLL3_SYNCHRONISER_1: + case ARIZONA_FLL3_SYNCHRONISER_2: + case ARIZONA_FLL3_SYNCHRONISER_3: + case ARIZONA_FLL3_SYNCHRONISER_4: + case ARIZONA_FLL3_SYNCHRONISER_5: + case ARIZONA_FLL3_SYNCHRONISER_6: + case ARIZONA_FLL3_SYNCHRONISER_7: + case ARIZONA_FLL3_SPREAD_SPECTRUM: + case ARIZONA_FLL3_GPIO_CLOCK: + case ARIZONA_MIC_CHARGE_PUMP_1: + case CLEARWATER_CP_MODE: + case ARIZONA_LDO1_CONTROL_1: + case ARIZONA_LDO2_CONTROL_1: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_2: + case ARIZONA_MIC_BIAS_CTRL_3: + case ARIZONA_MIC_BIAS_CTRL_4: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HP_CTRL_2L: + case ARIZONA_HP_CTRL_2R: + case ARIZONA_HP_CTRL_3L: + case ARIZONA_HP_CTRL_3R: + case ARIZONA_DCS_HP1L_CONTROL: + case ARIZONA_DCS_HP1R_CONTROL: + case CLEARWATER_EDRE_HP_STEREO_CONTROL: + case ARIZONA_ACCESSORY_DETECT_MODE_1: + case ARIZONA_HEADPHONE_DETECT_1: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case CLEARWATER_MICD_CLAMP_CONTROL: + case ARIZONA_MIC_DETECT_1: + case ARIZONA_MIC_DETECT_2: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_MIC_DETECT_LEVEL_1: + case ARIZONA_MIC_DETECT_LEVEL_2: + case ARIZONA_MIC_DETECT_LEVEL_3: + case ARIZONA_MIC_DETECT_LEVEL_4: + case ARIZONA_MIC_NOISE_MIX_CONTROL_1: + case CLEARWATER_GP_SWITCH_1: + case ARIZONA_JACK_DETECT_ANALOGUE: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case ARIZONA_IN2R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2R: + case ARIZONA_DMIC2R_CONTROL: + case ARIZONA_IN3L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_3L: + case ARIZONA_DMIC3L_CONTROL: + case ARIZONA_IN3R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_3R: + case ARIZONA_DMIC3R_CONTROL: + case ARIZONA_IN4L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_4L: + case ARIZONA_DMIC4L_CONTROL: + case ARIZONA_IN4R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_4R: + case ARIZONA_DMIC4R_CONTROL: + case ARIZONA_IN5L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_5L: + case ARIZONA_DMIC5L_CONTROL: + case ARIZONA_IN5R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_5R: + case ARIZONA_DMIC5R_CONTROL: + case ARIZONA_IN6L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_6L: + case ARIZONA_DMIC6L_CONTROL: + case ARIZONA_IN6R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_6R: + case ARIZONA_DMIC6R_CONTROL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_OUTPUT_PATH_CONFIG_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case ARIZONA_OUTPUT_PATH_CONFIG_2L: + case ARIZONA_DAC_DIGITAL_VOLUME_2L: + case ARIZONA_NOISE_GATE_SELECT_2L: + case ARIZONA_OUTPUT_PATH_CONFIG_2R: + case ARIZONA_DAC_DIGITAL_VOLUME_2R: + case ARIZONA_NOISE_GATE_SELECT_2R: + case ARIZONA_OUTPUT_PATH_CONFIG_3L: + case ARIZONA_DAC_DIGITAL_VOLUME_3L: + case ARIZONA_NOISE_GATE_SELECT_3L: + case ARIZONA_OUTPUT_PATH_CONFIG_3R: + case ARIZONA_DAC_DIGITAL_VOLUME_3R: + case ARIZONA_NOISE_GATE_SELECT_3R: + case ARIZONA_OUTPUT_PATH_CONFIG_4L: + case ARIZONA_DAC_DIGITAL_VOLUME_4L: + case ARIZONA_NOISE_GATE_SELECT_4L: + case ARIZONA_OUTPUT_PATH_CONFIG_4R: + case ARIZONA_DAC_DIGITAL_VOLUME_4R: + case ARIZONA_NOISE_GATE_SELECT_4R: + case ARIZONA_OUTPUT_PATH_CONFIG_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5L: + case ARIZONA_NOISE_GATE_SELECT_5L: + case ARIZONA_OUTPUT_PATH_CONFIG_5R: + case ARIZONA_DAC_DIGITAL_VOLUME_5R: + case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_OUTPUT_PATH_CONFIG_6L: + case ARIZONA_DAC_DIGITAL_VOLUME_6L: + case ARIZONA_NOISE_GATE_SELECT_6L: + case ARIZONA_OUTPUT_PATH_CONFIG_6R: + case ARIZONA_DAC_DIGITAL_VOLUME_6R: + case ARIZONA_NOISE_GATE_SELECT_6R: + case ARIZONA_DRE_ENABLE: + case CLEARWATER_EDRE_ENABLE: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_DAC_AEC_CONTROL_2: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_PDM_SPK1_CTRL_1: + case ARIZONA_PDM_SPK1_CTRL_2: + case ARIZONA_PDM_SPK2_CTRL_1: + case ARIZONA_PDM_SPK2_CTRL_2: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP2_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP3_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP_TEST_CTRL_5: + case ARIZONA_HP_TEST_CTRL_6: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_TX_BCLK_RATE: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_9: + case ARIZONA_AIF1_FRAME_CTRL_10: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_FRAME_CTRL_17: + case ARIZONA_AIF1_FRAME_CTRL_18: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_TX_BCLK_RATE: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_5: + case ARIZONA_AIF2_FRAME_CTRL_6: + case ARIZONA_AIF2_FRAME_CTRL_7: + case ARIZONA_AIF2_FRAME_CTRL_8: + case ARIZONA_AIF2_FRAME_CTRL_9: + case ARIZONA_AIF2_FRAME_CTRL_10: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_FRAME_CTRL_13: + case ARIZONA_AIF2_FRAME_CTRL_14: + case ARIZONA_AIF2_FRAME_CTRL_15: + case ARIZONA_AIF2_FRAME_CTRL_16: + case ARIZONA_AIF2_FRAME_CTRL_17: + case ARIZONA_AIF2_FRAME_CTRL_18: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_AIF3_BCLK_CTRL: + case ARIZONA_AIF3_TX_PIN_CTRL: + case ARIZONA_AIF3_RX_PIN_CTRL: + case ARIZONA_AIF3_RATE_CTRL: + case ARIZONA_AIF3_FORMAT: + case ARIZONA_AIF3_TX_BCLK_RATE: + case ARIZONA_AIF3_RX_BCLK_RATE: + case ARIZONA_AIF3_FRAME_CTRL_1: + case ARIZONA_AIF3_FRAME_CTRL_2: + case ARIZONA_AIF3_FRAME_CTRL_3: + case ARIZONA_AIF3_FRAME_CTRL_4: + case ARIZONA_AIF3_FRAME_CTRL_11: + case ARIZONA_AIF3_FRAME_CTRL_12: + case ARIZONA_AIF3_TX_ENABLES: + case ARIZONA_AIF3_RX_ENABLES: + case ARIZONA_AIF4_BCLK_CTRL: + case ARIZONA_AIF4_TX_PIN_CTRL: + case ARIZONA_AIF4_RX_PIN_CTRL: + case ARIZONA_AIF4_RATE_CTRL: + case ARIZONA_AIF4_FORMAT: + case ARIZONA_AIF4_TX_BCLK_RATE: + case ARIZONA_AIF4_RX_BCLK_RATE: + case ARIZONA_AIF4_FRAME_CTRL_1: + case ARIZONA_AIF4_FRAME_CTRL_2: + case ARIZONA_AIF4_FRAME_CTRL_3: + case ARIZONA_AIF4_FRAME_CTRL_4: + case ARIZONA_AIF4_FRAME_CTRL_11: + case ARIZONA_AIF4_FRAME_CTRL_12: + case ARIZONA_AIF4_TX_ENABLES: + case ARIZONA_AIF4_RX_ENABLES: + case ARIZONA_SPD1_TX_CONTROL: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_FRAMER_REF_GEAR: + case ARIZONA_SLIMBUS_RATES_1: + case ARIZONA_SLIMBUS_RATES_2: + case ARIZONA_SLIMBUS_RATES_3: + case ARIZONA_SLIMBUS_RATES_4: + case ARIZONA_SLIMBUS_RATES_5: + case ARIZONA_SLIMBUS_RATES_6: + case ARIZONA_SLIMBUS_RATES_7: + case ARIZONA_SLIMBUS_RATES_8: + case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT6LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT6LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT6LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT6LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT6LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT6LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT6LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT6LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT6RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT6RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT6RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT6RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT6RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT6RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT6RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT6RMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME: + case ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_2_SOURCE: + case ARIZONA_EQ1MIX_INPUT_2_VOLUME: + case ARIZONA_EQ1MIX_INPUT_3_SOURCE: + case ARIZONA_EQ1MIX_INPUT_3_VOLUME: + case ARIZONA_EQ1MIX_INPUT_4_SOURCE: + case ARIZONA_EQ1MIX_INPUT_4_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_2_SOURCE: + case ARIZONA_EQ2MIX_INPUT_2_VOLUME: + case ARIZONA_EQ2MIX_INPUT_3_SOURCE: + case ARIZONA_EQ2MIX_INPUT_3_VOLUME: + case ARIZONA_EQ2MIX_INPUT_4_SOURCE: + case ARIZONA_EQ2MIX_INPUT_4_VOLUME: + case ARIZONA_EQ3MIX_INPUT_1_SOURCE: + case ARIZONA_EQ3MIX_INPUT_1_VOLUME: + case ARIZONA_EQ3MIX_INPUT_2_SOURCE: + case ARIZONA_EQ3MIX_INPUT_2_VOLUME: + case ARIZONA_EQ3MIX_INPUT_3_SOURCE: + case ARIZONA_EQ3MIX_INPUT_3_VOLUME: + case ARIZONA_EQ3MIX_INPUT_4_SOURCE: + case ARIZONA_EQ3MIX_INPUT_4_VOLUME: + case ARIZONA_EQ4MIX_INPUT_1_SOURCE: + case ARIZONA_EQ4MIX_INPUT_1_VOLUME: + case ARIZONA_EQ4MIX_INPUT_2_SOURCE: + case ARIZONA_EQ4MIX_INPUT_2_VOLUME: + case ARIZONA_EQ4MIX_INPUT_3_SOURCE: + case ARIZONA_EQ4MIX_INPUT_3_VOLUME: + case ARIZONA_EQ4MIX_INPUT_4_SOURCE: + case ARIZONA_EQ4MIX_INPUT_4_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_4_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP4LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP4LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP4LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP5LMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP5LMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP5LMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP5AUX1MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX3MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX4MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX5MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX6MIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_1RMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_2RMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_1RMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_2RMIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4INT2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP6LMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP6LMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP6LMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP6AUX1MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX3MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX4MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX5MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX6MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP7LMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP7LMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP7LMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP7AUX1MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX3MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX4MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX5MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_EQ3_1: + case ARIZONA_EQ3_2: + case ARIZONA_EQ3_3: + case ARIZONA_EQ3_4: + case ARIZONA_EQ3_5: + case ARIZONA_EQ3_6: + case ARIZONA_EQ3_7: + case ARIZONA_EQ3_8: + case ARIZONA_EQ3_9: + case ARIZONA_EQ3_10: + case ARIZONA_EQ3_11: + case ARIZONA_EQ3_12: + case ARIZONA_EQ3_13: + case ARIZONA_EQ3_14: + case ARIZONA_EQ3_15: + case ARIZONA_EQ3_16: + case ARIZONA_EQ3_17: + case ARIZONA_EQ3_18: + case ARIZONA_EQ3_19: + case ARIZONA_EQ3_20: + case ARIZONA_EQ3_21: + case ARIZONA_EQ4_1: + case ARIZONA_EQ4_2: + case ARIZONA_EQ4_3: + case ARIZONA_EQ4_4: + case ARIZONA_EQ4_5: + case ARIZONA_EQ4_6: + case ARIZONA_EQ4_7: + case ARIZONA_EQ4_8: + case ARIZONA_EQ4_9: + case ARIZONA_EQ4_10: + case ARIZONA_EQ4_11: + case ARIZONA_EQ4_12: + case ARIZONA_EQ4_13: + case ARIZONA_EQ4_14: + case ARIZONA_EQ4_15: + case ARIZONA_EQ4_16: + case ARIZONA_EQ4_17: + case ARIZONA_EQ4_18: + case ARIZONA_EQ4_19: + case ARIZONA_EQ4_20: + case ARIZONA_EQ4_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case CLEARWATER_DRC2_CTRL1: + case CLEARWATER_DRC2_CTRL2: + case CLEARWATER_DRC2_CTRL3: + case CLEARWATER_DRC2_CTRL4: + case CLEARWATER_DRC2_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case CLEARWATER_ASRC1_ENABLE: + case CLEARWATER_ASRC1_STATUS: + case CLEARWATER_ASRC1_RATE1: + case CLEARWATER_ASRC1_RATE2: + case CLEARWATER_ASRC2_ENABLE: + case CLEARWATER_ASRC2_STATUS: + case CLEARWATER_ASRC2_RATE1: + case CLEARWATER_ASRC2_RATE2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + case ARIZONA_ISRC_3_CTRL_1: + case ARIZONA_ISRC_3_CTRL_2: + case ARIZONA_ISRC_3_CTRL_3: + case ARIZONA_ISRC_4_CTRL_1: + case ARIZONA_ISRC_4_CTRL_2: + case ARIZONA_ISRC_4_CTRL_3: + case ARIZONA_CLOCK_CONTROL: + case ARIZONA_ANC_SRC: + case ARIZONA_DSP_STATUS: + case ARIZONA_ANC_COEFF_START ... ARIZONA_ANC_COEFF_END: + case ARIZONA_FCL_FILTER_CONTROL: + case ARIZONA_FCL_ADC_REFORMATTER_CONTROL: + case ARIZONA_FCL_COEFF_START ... ARIZONA_FCL_COEFF_END: + case CLEARWATER_FCR_FILTER_CONTROL: + case CLEARWATER_FCR_ADC_REFORMATTER_CONTROL: + case CLEARWATER_FCR_COEFF_START ... CLEARWATER_FCR_COEFF_END: + case CLEARWATER_DAC_COMP_1: + case CLEARWATER_DAC_COMP_2: + case CLEARWATER_FRF_COEFFICIENT_1L_1: + case CLEARWATER_FRF_COEFFICIENT_1L_2: + case CLEARWATER_FRF_COEFFICIENT_1L_3: + case CLEARWATER_FRF_COEFFICIENT_1L_4: + case CLEARWATER_FRF_COEFFICIENT_1R_1: + case CLEARWATER_FRF_COEFFICIENT_1R_2: + case CLEARWATER_FRF_COEFFICIENT_1R_3: + case CLEARWATER_FRF_COEFFICIENT_1R_4: + case CLEARWATER_FRF_COEFFICIENT_2L_1: + case CLEARWATER_FRF_COEFFICIENT_2L_2: + case CLEARWATER_FRF_COEFFICIENT_2L_3: + case CLEARWATER_FRF_COEFFICIENT_2L_4: + case CLEARWATER_FRF_COEFFICIENT_2R_1: + case CLEARWATER_FRF_COEFFICIENT_2R_2: + case CLEARWATER_FRF_COEFFICIENT_2R_3: + case CLEARWATER_FRF_COEFFICIENT_2R_4: + case CLEARWATER_FRF_COEFFICIENT_3L_1: + case CLEARWATER_FRF_COEFFICIENT_3L_2: + case CLEARWATER_FRF_COEFFICIENT_3L_3: + case CLEARWATER_FRF_COEFFICIENT_3L_4: + case CLEARWATER_FRF_COEFFICIENT_3R_1: + case CLEARWATER_FRF_COEFFICIENT_3R_2: + case CLEARWATER_FRF_COEFFICIENT_3R_3: + case CLEARWATER_FRF_COEFFICIENT_3R_4: + case CLEARWATER_FRF_COEFFICIENT_4L_1: + case CLEARWATER_FRF_COEFFICIENT_4L_2: + case CLEARWATER_FRF_COEFFICIENT_4L_3: + case CLEARWATER_FRF_COEFFICIENT_4L_4: + case CLEARWATER_FRF_COEFFICIENT_4R_1: + case CLEARWATER_FRF_COEFFICIENT_4R_2: + case CLEARWATER_FRF_COEFFICIENT_4R_3: + case CLEARWATER_FRF_COEFFICIENT_4R_4: + case CLEARWATER_FRF_COEFFICIENT_5L_1: + case CLEARWATER_FRF_COEFFICIENT_5L_2: + case CLEARWATER_FRF_COEFFICIENT_5L_3: + case CLEARWATER_FRF_COEFFICIENT_5L_4: + case CLEARWATER_FRF_COEFFICIENT_5R_1: + case CLEARWATER_FRF_COEFFICIENT_5R_2: + case CLEARWATER_FRF_COEFFICIENT_5R_3: + case CLEARWATER_FRF_COEFFICIENT_5R_4: + case CLEARWATER_FRF_COEFFICIENT_6L_1: + case CLEARWATER_FRF_COEFFICIENT_6L_2: + case CLEARWATER_FRF_COEFFICIENT_6L_3: + case CLEARWATER_FRF_COEFFICIENT_6L_4: + case CLEARWATER_FRF_COEFFICIENT_6R_1: + case CLEARWATER_FRF_COEFFICIENT_6R_2: + case CLEARWATER_FRF_COEFFICIENT_6R_3: + case CLEARWATER_FRF_COEFFICIENT_6R_4: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO1_CTRL_2: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO2_CTRL_2: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO3_CTRL_2: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO4_CTRL_2: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO5_CTRL_2: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO6_CTRL_2: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO7_CTRL_2: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO8_CTRL_2: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO9_CTRL_2: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO10_CTRL_2: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO11_CTRL_2: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO12_CTRL_2: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO13_CTRL_2: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO14_CTRL_2: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO15_CTRL_2: + case CLEARWATER_GPIO16_CTRL_1: + case CLEARWATER_GPIO16_CTRL_2: + case CLEARWATER_GPIO17_CTRL_1: + case CLEARWATER_GPIO17_CTRL_2: + case CLEARWATER_GPIO18_CTRL_1: + case CLEARWATER_GPIO18_CTRL_2: + case CLEARWATER_GPIO19_CTRL_1: + case CLEARWATER_GPIO19_CTRL_2: + case CLEARWATER_GPIO20_CTRL_1: + case CLEARWATER_GPIO20_CTRL_2: + case CLEARWATER_GPIO21_CTRL_1: + case CLEARWATER_GPIO21_CTRL_2: + case CLEARWATER_GPIO22_CTRL_1: + case CLEARWATER_GPIO22_CTRL_2: + case CLEARWATER_GPIO23_CTRL_1: + case CLEARWATER_GPIO23_CTRL_2: + case CLEARWATER_GPIO24_CTRL_1: + case CLEARWATER_GPIO24_CTRL_2: + case CLEARWATER_GPIO25_CTRL_1: + case CLEARWATER_GPIO25_CTRL_2: + case CLEARWATER_GPIO26_CTRL_1: + case CLEARWATER_GPIO26_CTRL_2: + case CLEARWATER_GPIO27_CTRL_1: + case CLEARWATER_GPIO27_CTRL_2: + case CLEARWATER_GPIO28_CTRL_1: + case CLEARWATER_GPIO28_CTRL_2: + case CLEARWATER_GPIO29_CTRL_1: + case CLEARWATER_GPIO29_CTRL_2: + case CLEARWATER_GPIO30_CTRL_1: + case CLEARWATER_GPIO30_CTRL_2: + case CLEARWATER_GPIO31_CTRL_1: + case CLEARWATER_GPIO31_CTRL_2: + case CLEARWATER_GPIO32_CTRL_1: + case CLEARWATER_GPIO32_CTRL_2: + case CLEARWATER_GPIO33_CTRL_1: + case CLEARWATER_GPIO33_CTRL_2: + case CLEARWATER_GPIO34_CTRL_1: + case CLEARWATER_GPIO34_CTRL_2: + case CLEARWATER_GPIO35_CTRL_1: + case CLEARWATER_GPIO35_CTRL_2: + case CLEARWATER_GPIO36_CTRL_1: + case CLEARWATER_GPIO36_CTRL_2: + case CLEARWATER_GPIO37_CTRL_1: + case CLEARWATER_GPIO37_CTRL_2: + case CLEARWATER_GPIO38_CTRL_1: + case CLEARWATER_GPIO38_CTRL_2: + case CLEARWATER_GPIO39_CTRL_1: + case CLEARWATER_GPIO39_CTRL_2: + case CLEARWATER_GPIO40_CTRL_1: + case CLEARWATER_GPIO40_CTRL_2: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_3: + case CLEARWATER_IRQ1_STATUS_4: + case CLEARWATER_IRQ1_STATUS_5: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_8: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_10: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_16: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_20: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_26: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_29: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case CLEARWATER_IRQ1_MASK_1: + case CLEARWATER_IRQ1_MASK_2: + case CLEARWATER_IRQ1_MASK_3: + case CLEARWATER_IRQ1_MASK_4: + case CLEARWATER_IRQ1_MASK_5: + case CLEARWATER_IRQ1_MASK_6: + case CLEARWATER_IRQ1_MASK_7: + case CLEARWATER_IRQ1_MASK_8: + case CLEARWATER_IRQ1_MASK_9: + case CLEARWATER_IRQ1_MASK_10: + case CLEARWATER_IRQ1_MASK_11: + case CLEARWATER_IRQ1_MASK_12: + case CLEARWATER_IRQ1_MASK_13: + case CLEARWATER_IRQ1_MASK_14: + case CLEARWATER_IRQ1_MASK_15: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_11: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_18: + case CLEARWATER_IRQ1_RAW_STATUS_19: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_MASK_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + case CLEARWATER_INTERRUPT_DEBOUNCE_7: + case CLEARWATER_IRQ1_CTRL: + return true; + default: + return false; + } +} + +static bool clearwater_16bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x2C2: + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HP_CTRL_2L: + case ARIZONA_HP_CTRL_2R: + case ARIZONA_HP_CTRL_3L: + case ARIZONA_HP_CTRL_3R: + case ARIZONA_DCS_HP1L_CONTROL: + case ARIZONA_DCS_HP1R_CONTROL: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_FX_CTRL2: + case CLEARWATER_ASRC2_STATUS: + case CLEARWATER_ASRC1_STATUS: + case ARIZONA_CLOCK_CONTROL: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO16_CTRL_1: + case CLEARWATER_GPIO17_CTRL_1: + case CLEARWATER_GPIO18_CTRL_1: + case CLEARWATER_GPIO19_CTRL_1: + case CLEARWATER_GPIO20_CTRL_1: + case CLEARWATER_GPIO21_CTRL_1: + case CLEARWATER_GPIO22_CTRL_1: + case CLEARWATER_GPIO23_CTRL_1: + case CLEARWATER_GPIO24_CTRL_1: + case CLEARWATER_GPIO25_CTRL_1: + case CLEARWATER_GPIO26_CTRL_1: + case CLEARWATER_GPIO27_CTRL_1: + case CLEARWATER_GPIO28_CTRL_1: + case CLEARWATER_GPIO29_CTRL_1: + case CLEARWATER_GPIO30_CTRL_1: + case CLEARWATER_GPIO31_CTRL_1: + case CLEARWATER_GPIO32_CTRL_1: + case CLEARWATER_GPIO33_CTRL_1: + case CLEARWATER_GPIO34_CTRL_1: + case CLEARWATER_GPIO35_CTRL_1: + case CLEARWATER_GPIO36_CTRL_1: + case CLEARWATER_GPIO37_CTRL_1: + case CLEARWATER_GPIO38_CTRL_1: + case CLEARWATER_GPIO39_CTRL_1: + case CLEARWATER_GPIO40_CTRL_1: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_11: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_18: + case CLEARWATER_IRQ1_RAW_STATUS_19: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + return true; + default: + return false; + } +} + +static bool clearwater_32bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_508: + case CLEARWATER_OTP_HPDET_CALIB_1 ... CLEARWATER_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... CLEARWATER_DSP1_SCRATCH_2_3: + case CLEARWATER_DSP2_CONFIG ... CLEARWATER_DSP2_SCRATCH_2_3: + case CLEARWATER_DSP3_CONFIG ... CLEARWATER_DSP3_SCRATCH_2_3: + case CLEARWATER_DSP4_CONFIG ... CLEARWATER_DSP4_SCRATCH_2_3: + case CLEARWATER_DSP5_CONFIG ... CLEARWATER_DSP5_SCRATCH_2_3: + case CLEARWATER_DSP6_CONFIG ... CLEARWATER_DSP6_SCRATCH_2_3: + case CLEARWATER_DSP7_CONFIG ... CLEARWATER_DSP7_SCRATCH_2_3: + return true; + default: + return clearwater_is_adsp_memory(dev, reg); + } +} + +static bool clearwater_32bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_508: + case CLEARWATER_OTP_HPDET_CALIB_1 ... CLEARWATER_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... CLEARWATER_DSP1_SCRATCH_2_3: + case CLEARWATER_DSP2_CONFIG ... CLEARWATER_DSP2_SCRATCH_2_3: + case CLEARWATER_DSP3_CONFIG ... CLEARWATER_DSP3_SCRATCH_2_3: + case CLEARWATER_DSP4_CONFIG ... CLEARWATER_DSP4_SCRATCH_2_3: + case CLEARWATER_DSP5_CONFIG ... CLEARWATER_DSP5_SCRATCH_2_3: + case CLEARWATER_DSP6_CONFIG ... CLEARWATER_DSP6_SCRATCH_2_3: + case CLEARWATER_DSP7_CONFIG ... CLEARWATER_DSP7_SCRATCH_2_3: + return true; + default: + return clearwater_is_adsp_memory(dev, reg); + } +} + +const struct regmap_config clearwater_16bit_spi_regmap = { + .name = "clearwater_16bit", + .reg_bits = 32, + .pad_bits = 16, + .val_bits = 16, + + .max_register = 0x2fff, + .readable_reg = clearwater_16bit_readable_register, + .volatile_reg = clearwater_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = clearwater_reg_default, + .num_reg_defaults = ARRAY_SIZE(clearwater_reg_default), +}; +EXPORT_SYMBOL_GPL(clearwater_16bit_spi_regmap); + +const struct regmap_config clearwater_16bit_i2c_regmap = { + .name = "clearwater_16bit", + .reg_bits = 32, + .val_bits = 16, + + .max_register = 0x2fff, + .readable_reg = clearwater_16bit_readable_register, + .volatile_reg = clearwater_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = clearwater_reg_default, + .num_reg_defaults = ARRAY_SIZE(clearwater_reg_default), +}; +EXPORT_SYMBOL_GPL(clearwater_16bit_i2c_regmap); + +const struct regmap_config clearwater_32bit_spi_regmap = { + .name = "clearwater_32bit", + .reg_bits = 32, + .reg_stride = 2, + .pad_bits = 16, + .val_bits = 32, + + .max_register = CLEARWATER_DSP7_SCRATCH_2_3, + .readable_reg = clearwater_32bit_readable_register, + .volatile_reg = clearwater_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(clearwater_32bit_spi_regmap); + +const struct regmap_config clearwater_32bit_i2c_regmap = { + .name = "clearwater_32bit", + .reg_bits = 32, + .reg_stride = 2, + .val_bits = 32, + + .max_register = CLEARWATER_DSP7_SCRATCH_2_3, + .readable_reg = clearwater_32bit_readable_register, + .volatile_reg = clearwater_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(clearwater_32bit_i2c_regmap); diff --git a/drivers/mfd/cs47l15-tables.c b/drivers/mfd/cs47l15-tables.c new file mode 100644 index 00000000000..ecb272aabb4 --- /dev/null +++ b/drivers/mfd/cs47l15-tables.c @@ -0,0 +1,1759 @@ +/* + * cs47l15-tables.c -- data tables for CS47L15 + * + * Copyright 2015 Cirrus Logic + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include + +#include "arizona.h" + +static const struct reg_sequence cs47l15_reva_16_patch[] = { + { 0x8C, 0x5555 }, + { 0x8C, 0xAAAA }, + { 0x314, 0x0080 }, + { 0x4D4, 0x0008 }, + { 0x4CF, 0x0F00 }, + { 0x4A8, 0x6020 }, + { 0x4A9, 0x6020 }, + { 0x4D7, 0x1B2B }, + { 0x8C, 0xCCCC }, + { 0x8C, 0x3333 }, +}; + +int cs47l15_patch(struct arizona *arizona) +{ + int ret; + + ret = regmap_register_patch(arizona->regmap, + cs47l15_reva_16_patch, + ARRAY_SIZE(cs47l15_reva_16_patch)); + if (ret < 0) { + dev_err(arizona->dev, + "Error in applying 16-bit patch: %d\n", ret); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cs47l15_patch); + +static const struct regmap_irq cs47l15_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_BOOT_DONE] = { .reg_offset = 0, + .mask = CLEARWATER_BOOT_DONE_EINT1 }, + [ARIZONA_IRQ_CTRLIF_ERR] = { .reg_offset = 0, + .mask = CLEARWATER_CTRLIF_ERR_EINT1 }, + + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL1_LOCK_EINT1 }, + [MOON_IRQ_FLLAO_CLOCK_OK] = { .reg_offset = 1, + .mask = MOON_FLLAO_LOCK_EINT1}, + + [ARIZONA_IRQ_MICDET] = { .reg_offset = 5, + .mask = CLEARWATER_MICDET_EINT1 }, + [ARIZONA_IRQ_HPDET] = { .reg_offset = 5, + .mask = CLEARWATER_HPDET_EINT1}, + + [ARIZONA_IRQ_MICD_CLAMP_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_RISE_EINT1 }, + [ARIZONA_IRQ_MICD_CLAMP_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_FALL_EINT1 }, + [ARIZONA_IRQ_JD_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_FALL_EINT1 }, + [ARIZONA_IRQ_JD_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_RISE_EINT1 }, + + [ARIZONA_IRQ_DRC2_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC2_SIG_DET_EINT1 }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC1_SIG_DET_EINT1 }, + + [ARIZONA_IRQ_DSP_IRQ1] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ1_EINT1}, + [ARIZONA_IRQ_DSP_IRQ2] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ2_EINT1}, + [ARIZONA_IRQ_DSP_IRQ3] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ3_EINT1}, + [ARIZONA_IRQ_DSP_IRQ4] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ4_EINT1}, + [ARIZONA_IRQ_DSP_IRQ5] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ5_EINT1}, + [ARIZONA_IRQ_DSP_IRQ6] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ6_EINT1}, + [ARIZONA_IRQ_DSP_IRQ7] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ7_EINT1}, + [ARIZONA_IRQ_DSP_IRQ8] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ8_EINT1}, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { .reg_offset = 14, + .mask = CLEARWATER_SPK_OVERHEAT_WARN_EINT1}, + [ARIZONA_IRQ_SPK_OVERHEAT] = { .reg_offset = 14, + .mask = CLEARWATER_SPK_SHUTDOWN_EINT1}, + + [ARIZONA_IRQ_GP1] = { .reg_offset = 16, + .mask = CLEARWATER_GP1_EINT1}, + [ARIZONA_IRQ_GP2] = { .reg_offset = 16, + .mask = CLEARWATER_GP2_EINT1}, + [ARIZONA_IRQ_GP3] = { .reg_offset = 16, + .mask = CLEARWATER_GP3_EINT1}, + [ARIZONA_IRQ_GP4] = { .reg_offset = 16, + .mask = CLEARWATER_GP4_EINT1}, + [ARIZONA_IRQ_GP5] = { .reg_offset = 16, + .mask = CLEARWATER_GP5_EINT1}, + [ARIZONA_IRQ_GP6] = { .reg_offset = 16, + .mask = CLEARWATER_GP6_EINT1}, + [ARIZONA_IRQ_GP7] = { .reg_offset = 16, + .mask = CLEARWATER_GP7_EINT1}, + [ARIZONA_IRQ_GP8] = { .reg_offset = 16, + .mask = CLEARWATER_GP8_EINT1}, + + [MOON_IRQ_DSP1_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP1}, +}; + +const struct regmap_irq_chip cs47l15_irq = { + .name = "cs47l15 IRQ", + .status_base = CLEARWATER_IRQ1_STATUS_1, + .mask_base = CLEARWATER_IRQ1_MASK_1, + .ack_base = CLEARWATER_IRQ1_STATUS_1, + .num_regs = 33, + .irqs = cs47l15_irqs, + .num_irqs = ARRAY_SIZE(cs47l15_irqs), +}; +EXPORT_SYMBOL_GPL(cs47l15_irq); + +static const struct reg_default cs47l15_reg_default[] = { + { 0x00000008, 0x373B }, /* R8 (0x000008) - CTRL_IF_CFG_1 */ + { 0x00000020, 0x0000 }, /* R32 (0x000020) - TONE_GENERATOR_1 */ + { 0x00000021, 0x1000 }, /* R33 (0x000021) - TONE_GENERATOR_2 */ + { 0x00000022, 0x0000 }, /* R34 (0x000022) - TONE_GENERATOR_3 */ + { 0x00000023, 0x1000 }, /* R35 (0x000023) - TONE_GENERATOR_4 */ + { 0x00000024, 0x0000 }, /* R36 (0x000024) - TONE_GENERATOR_5 */ + { 0x00000030, 0x0000 }, /* R48 (0x000030) - PWM_DRIVE_1 */ + { 0x00000031, 0x0100 }, /* R49 (0x000031) - PWM_DRIVE_2 */ + { 0x00000032, 0x0100 }, /* R50 (0x000032) - PWM_DRIVE_3 */ + { 0x00000041, 0x0000 }, /* R65 (0x000041) - SEQUENCE_CONTROL */ + { 0x00000061, 0x01FF }, /* R97 (0x000061) - SAMPLE_RATE_SEQUENCE_SELECT_1 */ + { 0x00000062, 0x01FF }, /* R98 (0x000062) - SAMPLE_RATE_SEQUENCE_SELECT_2 */ + { 0x00000063, 0x01FF }, /* R99 (0x000063) - SAMPLE_RATE_SEQUENCE_SELECT_3 */ + { 0x00000064, 0x01FF }, /* R100 (0x000064) - SSAMPLE_RATE_SEQUENCE_SELECT_4 */ + { 0x00000066, 0x01FF }, /* R102 (0x000066) - ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 */ + { 0x00000067, 0x01FF }, /* R103 (0x000067) - ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 */ + { 0x00000068, 0x01FF }, /* R104 (0x000068) - SPARE_SEQUENCE_SELECT_13 */ + { 0x00000069, 0x01FF }, /* R105 (0x000069) - SPARE_SEQUENCE_SELECT_14 */ + { 0x0000006A, 0x01FF }, /* R106 (0x00006A) - SPARE_SEQUENCE_SELECT_15 */ + { 0x0000006B, 0x01FF }, /* R107 (0x00006B) - SPARE_SEQUENCE_SELECT_16 */ + { 0x00000090, 0x0000 }, /* R144 (0x000090) - Haptics Control 1 */ + { 0x00000091, 0x7FFF }, /* R145 (0x000091) - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 (0x000092) - HAPTICS_PHASE_1_INTENSITY */ + { 0x00000093, 0x0000 }, /* R147 (0x000093) - HAPTICS_PHASE_1_DURATION */ + { 0x00000094, 0x0000 }, /* R148 (0x000094) - HAPTICS_PHASE_2_INTENSITY */ + { 0x00000095, 0x0000 }, /* R149 (0x000095) - HAPTICS_PHASE_2_DURATION */ + { 0x00000096, 0x0000 }, /* R150 (0x000096) - HAPTICS_PHASE_3_INTENSITY */ + { 0x00000097, 0x0000 }, /* R151 (0x000097) - HAPTICS_PHASE_3_DURATION */ + { 0x000000A0, 0x0000 }, /* R160 (0x0000A0) - Comfort Noise Generator */ + { 0x00000100, 0x0002 }, /* R256 (0x000100) - CLOCK_32K_1 */ + { 0x00000101, 0x0404 }, /* R257 (0x000101) - SYSTEM_CLOCK_1 */ + { 0x00000102, 0x0011 }, /* R258 (0x000102) - SAMPLE_RATE_1 */ + { 0x00000103, 0x0011 }, /* R259 (0x000103) - SAMPLE_RATE_2 */ + { 0x00000104, 0x0011 }, /* R260 (0x000104) - SAMPLE_RATE_3 */ + { 0x00000120, 0x0304 }, /* R288 (0x000120) - DSP_CLOCK_1 */ + { 0x00000122, 0x0000 }, /* R290 (0x000122) - DSP_CLOCK_2 */ + { 0x00000149, 0x0000 }, /* R329 (0x000149) - OUTPUT_SYSTEM_CLOCK */ + { 0x00000152, 0x0000 }, /* R338 (0x000152) - RATE_ESTIMATOR_1 */ + { 0x00000153, 0x0000 }, /* R339 (0x000153) - RATE_ESTIMATOR_2 */ + { 0x00000154, 0x0000 }, /* R340 (0x000154) - RATE_ESTIMATOR_3 */ + { 0x00000155, 0x0000 }, /* R341 (0x000155) - RATE_ESTIMATOR_4 */ + { 0x00000156, 0x0000 }, /* R342 (0x000156) - RATE_ESTIMATOR_5 */ + { 0x00000171, 0x0002 }, /* R369 (0x000171) - FLL1_CONTROL_1 */ + { 0x00000172, 0x0008 }, /* R370 (0x000172) - FLL1_CONTROL_2 */ + { 0x00000173, 0x0018 }, /* R371 (0x000173) - FLL1_CONTROL_3 */ + { 0x00000174, 0x007D }, /* R372 (0x000174) - FLL1_CONTROL_4 */ + { 0x00000175, 0x0000 }, /* R373 (0x000175) - FLL1_CONTROL_5 */ + { 0x00000176, 0x0000 }, /* R374 (0x000176) - FLL1_CONTROL_6 */ + { 0x00000177, 0x0281 }, /* R375 (0x000177) - FLL1_LOOP_FILTER_TEST_1 */ + { 0x00000178, 0x0000 }, /* R376 (0x000178) - FLL1_NCO_TEST_0 */ + { 0x00000179, 0x0000 }, /* R377 (0x000179) - FLL1_CONTROL_7 */ + { 0x0000017A, 0x2906 }, /* R378 (0x00017A) - FLL1_EFS_2 */ + { 0x00000181, 0x0000 }, /* R385 (0x000181) - FLL1_SYNCHRONISER_1 */ + { 0x00000182, 0x0000 }, /* R386 (0x000182) - FLL1_SYNCHRONISER_2 */ + { 0x00000183, 0x0000 }, /* R387 (0x000183) - FLL1_SYNCHRONISER_3 */ + { 0x00000184, 0x0000 }, /* R388 (0x000184) - FLL1_SYNCHRONISER_4 */ + { 0x00000185, 0x0000 }, /* R389 (0x000185) - FLL1_SYNCHRONISER_5 */ + { 0x00000186, 0x0000 }, /* R390 (0x000186) - FLL1_SYNCHRONISER_6 */ + { 0x00000187, 0x0001 }, /* R391 (0x000187) - FLL1_SYNCHRONISER_7 */ + { 0x00000189, 0x0000 }, /* R393 (0x000189) - FLL1_SPREAD_SPECTRUM */ + { 0x0000018A, 0x0004 }, /* R394 (0x00018A) - FLL1_GPIO_CLOCK */ + { 0x000001D1, 0x0004 }, /* R465 (0x0001D1) - FLL_AO_CONTROL_1 */ + { 0x000001D2, 0x0004 }, /* R466 (0x0001D2) - FLL_AO_CONTROL_2 */ + { 0x000001D3, 0x0000 }, /* R467 (0x0001D3) - FLL_AO_CONTROL_3 */ + { 0x000001D4, 0x0000 }, /* R468 (0x0001D4) - FLL_AO_CONTROL_4 */ + { 0x000001D5, 0x0001 }, /* R469 (0x0001D5) - FLL_AO_CONTROL_5 */ + { 0x000001D6, 0x8004 }, /* R470 (0x0001D6) - FLL_AO_CONTROL_6 */ + { 0x000001D8, 0x0000 }, /* R472 (0x0001D8) - FLL_AO_CONTROL_7 */ + { 0x000001DA, 0x0077 }, /* R474 (0x0001DA) - FLL_AO_CONTROL_8 */ + { 0x000001DB, 0x0000 }, /* R475 (0x0001DB) - FLL_AO_CONTROL_9 */ + { 0x000001DC, 0x06DA }, /* R476 (0x0001DC) - FLL_AO_CONTROL_10 */ + { 0x000001DD, 0x0011 }, /* R477 (0x0001DD) - FLL_AO_CONTROL_11 */ + { 0x00000218, 0x00E6 }, /* R536 (0x000218) - MIC_BIAS_CTRL_1 */ + { 0x0000021C, 0x0222 }, /* R540 (0x00021C) - MIC_BIAS_CTRL_5 */ + { 0x00000299, 0x0000 }, /* R665 (0x000299) - HEADPHONE_DETECT_0 */ + { 0x0000029B, 0x0000 }, /* R667 (0x00029B) - HEADPHONE_DETECT_1 */ + { 0x000002A2, 0x0010 }, /* R674 (0x0002A2) - MIC_DETECT_1_CONTROL_0 */ + { 0x000002A3, 0x1102 }, /* R675 (0x0002A3) - MIC_DETECT_1_CONTROL_1 */ + { 0x000002A4, 0x009F }, /* R676 (0x0002A4) - MIC_DETECT_1_CONTROL_2 */ + { 0x000002A6, 0x3D3D }, /* R678 (0x0002A6) - MIC_DETECT_1_LEVEL_1 */ + { 0x000002A7, 0x3D3D }, /* R679 (0x0002A7) - MIC_DETECT_1_LEVEL_2 */ + { 0x000002A8, 0x333D }, /* R680 (0x0002A8) - MIC_DETECT_1_LEVEL_3 */ + { 0x000002A9, 0x202D }, /* R681 (0x0002A9) - MIC_DETECT_1_LEVEL_4 */ + { 0x000002C6, 0x0010 }, /* R710 (0x0002C6) - MICD_CLAMP_CONTROL */ + { 0x000002C8, 0x0000 }, /* R712 (0x0002C8) - GP_SWITCH_1 */ + { 0x000002D3, 0x0000 }, /* R723 (0x0002D3) - JACK_DETECT_ANALOGUE */ + { 0x00000300, 0x0000 }, /* R768 (0x000300) - INPUT_ENABLES */ + { 0x00000308, 0x0000 }, /* R776 (0x000308) - INPUT_RATE */ + { 0x00000309, 0x0022 }, /* R777 (0x000309) - INPUT_VOLUME_RAMP */ + { 0x0000030C, 0x0002 }, /* R780 (0x00030C) - HPF_CONTROL */ + { 0x00000310, 0x0080 }, /* R784 (0x000310) - IN1L_CONTROL */ + { 0x00000311, 0x0180 }, /* R785 (0x000311) - ADC_DIGITAL_VOLUME_1L */ + { 0x00000312, 0x0500 }, /* R786 (0x000312) - DMIC1L_CONTROL */ + { 0x00000313, 0x0000 }, /* R787 (0x000313) - IN1L_RATE_CONTROL */ + { 0x00000314, 0x0080 }, /* R788 (0x000314) - IN1R_CONTROL */ + { 0x00000315, 0x0180 }, /* R789 (0x000315) - ADC_DIGITAL_VOLUME_1R */ + { 0x00000316, 0x0000 }, /* R790 (0x000316) - DMIC1R_CONTROL */ + { 0x00000317, 0x0000 }, /* R791 (0x000317) - IN1R_RATE_CONTROL */ + { 0x00000318, 0x0000 }, /* R792 (0x000318) - IN2L_CONTROL */ + { 0x00000319, 0x0180 }, /* R793 (0x000319) - ADC_DIGITAL_VOLUME_2L */ + { 0x0000031A, 0x0500 }, /* R794 (0x00031A) - DMIC2L_CONTROL */ + { 0x0000031B, 0x0000 }, /* R795 (0x00031B) - IN2L_RATE_CONTROL */ + { 0x0000031C, 0x0800 }, /* R796 (0x00031C) - IN2R_CONTROL */ + { 0x0000031D, 0x0180 }, /* R797 (0x00031D) - ADC_DIGITAL_VOLUME_2R */ + { 0x0000031E, 0x0000 }, /* R798 (0x00031E) - DMIC2R_CONTROL */ + { 0x0000031F, 0x0000 }, /* R799 (0x00031F) - IN2R_RATE_CONTROL */ + { 0x000003A8, 0x2000 }, /* R936 (0x0003A8) - CS47L15_ADC_INT_BIAS */ + { 0x000003C4, 0x0000 }, /* R964 (0x0003C4) - CS47L15_PGA_BIAS_SEL */ + { 0x00000400, 0x0000 }, /* R1024 (0x000400) - OUTPUT_ENABLES_1 */ + { 0x00000408, 0x0000 }, /* R1032 (0x000408) - OUTPUT_RATE_1 */ + { 0x00000409, 0x0022 }, /* R1033 (0x000409) - OUTPUT_VOLUME_RAMP */ + { 0x00000410, 0x0080 }, /* R1040 (0x000410) - OUTPUT_PATH_CONFIG_1L */ + { 0x00000411, 0x0180 }, /* R1041 (0x000411) - DAC_DIGITAL_VOLUME_1L */ + { 0x00000412, 0x0000 }, /* R1042 (0x000412) - OUTPUT_PATH_CONFIG_1 */ + { 0x00000413, 0x0001 }, /* R1043 (0x000413) - NOISE_GATE_SELECT_1L */ + { 0x00000414, 0x0080 }, /* R1044 (0x000414) - OUTPUT_PATH_CONFIG_1R */ + { 0x00000415, 0x0180 }, /* R1045 (0x000415) - DAC_DIGITAL_VOLUME_1R */ + { 0x00000417, 0x0002 }, /* R1047 (0x000417) - NOISE_GATE_SELECT_1R */ + { 0x0000041A, 0x0600 }, /* R1050 (0x00041A) - OUTPUT_PATH_CONFIG_2 */ + { 0x00000428, 0x0000 }, /* R1064 (0x000428) - OUTPUT_PATH_CONFIG_4L */ + { 0x00000429, 0x0180 }, /* R1065 (0x000429) - DAC_DIGITAL_VOLUME_4L */ + { 0x0000042B, 0x0040 }, /* R1067 (0x00042B) - NOISE_GATE_SELECT_4L */ + { 0x00000430, 0x0000 }, /* R1072 (0x000430) - OUTPUT_PATH_CONFIG_5L */ + { 0x00000431, 0x0180 }, /* R1073 (0x000431) - DAC_DIGITAL_VOLUME_5L */ + { 0x00000433, 0x0100 }, /* R1075 (0x000433) - NOISE_GATE_SELECT_5L */ + { 0x00000434, 0x0000 }, /* R1076 (0x000434) - OUTPUT_PATH_CONFIG_5R */ + { 0x00000435, 0x0180 }, /* R1077 (0x000435) - DAC_DIGITAL_VOLUME_5R */ + { 0x00000437, 0x0200 }, /* R1079 (0x000437) - NOISE_GATE_SELECT_5R */ + { 0x00000440, 0x0003 }, /* R1088 (0x000440) - DRE Enable */ + { 0x00000448, 0x0883 }, /* R1096 (0x000448) - eDRE Enable */ + { 0x00000450, 0x0000 }, /* R1104 (0x000450) - DAC_AEC_CONTROL_1 */ + { 0x00000458, 0x0000 }, /* R1112 (0x000458) - NOISE_GATE_CONTROL */ + { 0x00000490, 0x0069 }, /* R1168 (0x000490) - PDM_SPK1_CTRL_1 */ + { 0x00000491, 0x0000 }, /* R1169 (0x000491) - PDM_SPK1_CTRL_2 */ + { 0x000004A0, 0x3080 }, /* R1184 (0x0004A0) - HP1 Short Circuit Ctrl */ + { 0x000004A8, 0x6020 }, /* R1192 (0x0004A8) - HP Test Ctrl 5 */ + { 0x000004A9, 0x6020 }, /* R1193 (0x0004A9) - HP Test Ctrl 6 */ + { 0x00000500, 0x000C }, /* R1280 (0x000500) - AIF1_BCLK_CTRL */ + { 0x00000501, 0x0000 }, /* R1281 (0x000501) - AIF1_TX_PIN_CTRL */ + { 0x00000502, 0x0000 }, /* R1282 (0x000502) - AIF1_RX_PIN_CTRL */ + { 0x00000503, 0x0000 }, /* R1283 (0x000503) - AIF1_RATE_CTRL */ + { 0x00000504, 0x0000 }, /* R1284 (0x000504) - AIF1_FORMAT */ + { 0x00000506, 0x0040 }, /* R1286 (0x000506) - AIF1_RX_BCLK_RATE */ + { 0x00000507, 0x1818 }, /* R1287 (0x000507) - AIF1_FRAME_CTRL_1 */ + { 0x00000508, 0x1818 }, /* R1288 (0x000508) - AIF1_FRAME_CTRL_2 */ + { 0x00000509, 0x0000 }, /* R1289 (0x000509) - AIF1_FRAME_CTRL_3 */ + { 0x0000050A, 0x0001 }, /* R1290 (0x00050A) - AIF1_FRAME_CTRL_4 */ + { 0x0000050B, 0x0002 }, /* R1291 (0x00050B) - AIF1_FRAME_CTRL_5 */ + { 0x0000050C, 0x0003 }, /* R1292 (0x00050C) - AIF1_FRAME_CTRL_6 */ + { 0x0000050D, 0x0004 }, /* R1293 (0x00050D) - AIF1_FRAME_CTRL_7 */ + { 0x0000050E, 0x0005 }, /* R1294 (0x00050E) - AIF1_FRAME_CTRL_8 */ + { 0x00000511, 0x0000 }, /* R1297 (0x000511) - AIF1_FRAME_CTRL_11 */ + { 0x00000512, 0x0001 }, /* R1298 (0x000512) - AIF1_FRAME_CTRL_12 */ + { 0x00000513, 0x0002 }, /* R1299 (0x000513) - AIF1_FRAME_CTRL_13 */ + { 0x00000514, 0x0003 }, /* R1300 (0x000514) - AIF1_FRAME_CTRL_14 */ + { 0x00000515, 0x0004 }, /* R1301 (0x000515) - AIF1_FRAME_CTRL_15 */ + { 0x00000516, 0x0005 }, /* R1302 (0x000516) - AIF1_FRAME_CTRL_16 */ + { 0x00000519, 0x0000 }, /* R1305 (0x000519) - AIF1_TX_ENABLES */ + { 0x0000051A, 0x0000 }, /* R1306 (0x00051A) - AIF1_RX_ENABLES */ + { 0x00000540, 0x000C }, /* R1344 (0x000540) - AIF2_BCLK_CTRL */ + { 0x00000541, 0x0000 }, /* R1345 (0x000541) - AIF2_TX_PIN_CTRL */ + { 0x00000542, 0x0000 }, /* R1346 (0x000542) - AIF2_RX_PIN_CTRL */ + { 0x00000543, 0x0000 }, /* R1347 (0x000543) - AIF2_RATE_CTRL */ + { 0x00000544, 0x0000 }, /* R1348 (0x000544) - AIF2_FORMAT */ + { 0x00000546, 0x0040 }, /* R1350 (0x000546) - AIF2_RX_BCLK_RATE */ + { 0x00000547, 0x1818 }, /* R1351 (0x000547) - AIF2_FRAME_CTRL_1 */ + { 0x00000548, 0x1818 }, /* R1352 (0x000548) - AIF2_FRAME_CTRL_2 */ + { 0x00000549, 0x0000 }, /* R1353 (0x000549) - AIF2_FRAME_CTRL_3 */ + { 0x0000054A, 0x0001 }, /* R1354 (0x00054A) - AIF2_FRAME_CTRL_4 */ + { 0x0000054B, 0x0002 }, /* R1355 (0x00054B) - AIF2_FRAME_CTRL_5 */ + { 0x0000054C, 0x0003 }, /* R1356 (0x00054C) - AIF2_FRAME_CTRL_6 */ + { 0x00000551, 0x0000 }, /* R1361 (0x000551) - AIF2_FRAME_CTRL_11 */ + { 0x00000552, 0x0001 }, /* R1362 (0x000552) - AIF2_FRAME_CTRL_12 */ + { 0x00000553, 0x0002 }, /* R1363 (0x000553) - AIF2_FRAME_CTRL_13 */ + { 0x00000554, 0x0003 }, /* R1364 (0x000554) - AIF2_FRAME_CTRL_14 */ + { 0x00000559, 0x0000 }, /* R1369 (0x000559) - AIF2_TX_ENABLES */ + { 0x0000055A, 0x0000 }, /* R1370 (0x00055A) - AIF2_RX_ENABLES */ + { 0x00000580, 0x000C }, /* R1408 (0x000580) - AIF3_BCLK_CTRL */ + { 0x00000581, 0x0000 }, /* R1409 (0x000581) - AIF3_TX_PIN_CTRL */ + { 0x00000582, 0x0000 }, /* R1410 (0x000582) - AIF3_RX_PIN_CTRL */ + { 0x00000583, 0x0000 }, /* R1411 (0x000583) - AIF3_RATE_CTRL */ + { 0x00000584, 0x0000 }, /* R1412 (0x000584) - AIF3_FORMAT */ + { 0x00000586, 0x0040 }, /* R1414 (0x000586) - AIF3_RX_BCLK_RATE */ + { 0x00000587, 0x1818 }, /* R1415 (0x000587) - AIF3_FRAME_CTRL_1 */ + { 0x00000588, 0x1818 }, /* R1416 (0x000588) - AIF3_FRAME_CTRL_2 */ + { 0x00000589, 0x0000 }, /* R1417 (0x000589) - AIF3_FRAME_CTRL_3 */ + { 0x0000058A, 0x0001 }, /* R1418 (0x00058A) - AIF3_FRAME_CTRL_4 */ + { 0x00000591, 0x0000 }, /* R1425 (0x000591) - AIF3_FRAME_CTRL_11 */ + { 0x00000592, 0x0001 }, /* R1426 (0x000592) - AIF3_FRAME_CTRL_12 */ + { 0x00000599, 0x0000 }, /* R1433 (0x000599) - AIF3_TX_ENABLES */ + { 0x0000059A, 0x0000 }, /* R1434 (0x00059A) - AIF3_RX_ENABLES */ + { 0x000005C2, 0x0000 }, /* R1474 (0x0005C2) - SPD1_TX_CONTROL */ + { 0x00000640, 0x0000 }, /* R1600 (0x000640) - PWM1MIX_INPUT_1_SOURCE */ + { 0x00000641, 0x0080 }, /* R1601 (0x000641) - PWM1MIX_INPUT_1_VOLUME */ + { 0x00000642, 0x0000 }, /* R1602 (0x000642) - PWM1MIX_INPUT_2_SOURCE */ + { 0x00000643, 0x0080 }, /* R1603 (0x000643) - PWM1MIX_INPUT_2_VOLUME */ + { 0x00000644, 0x0000 }, /* R1604 (0x000644) - PWM1MIX_INPUT_3_SOURCE */ + { 0x00000645, 0x0080 }, /* R1605 (0x000645) - PWM1MIX_INPUT_3_VOLUME */ + { 0x00000646, 0x0000 }, /* R1606 (0x000646) - PWM1MIX_INPUT_4_SOURCE */ + { 0x00000647, 0x0080 }, /* R1607 (0x000647) - PWM1MIX_INPUT_4_VOLUME */ + { 0x00000648, 0x0000 }, /* R1608 (0x000648) - PWM2MIX_INPUT_1_SOURCE */ + { 0x00000649, 0x0080 }, /* R1609 (0x000649) - PWM2MIX_INPUT_1_VOLUME */ + { 0x0000064A, 0x0000 }, /* R1610 (0x00064A) - PWM2MIX_INPUT_2_SOURCE */ + { 0x0000064B, 0x0080 }, /* R1611 (0x00064B) - PWM2MIX_INPUT_2_VOLUME */ + { 0x0000064C, 0x0000 }, /* R1612 (0x00064C) - PWM2MIX_INPUT_3_SOURCE */ + { 0x0000064D, 0x0080 }, /* R1613 (0x00064D) - PWM2MIX_INPUT_3_VOLUME */ + { 0x0000064E, 0x0000 }, /* R1614 (0x00064E) - PWM2MIX_INPUT_4_SOURCE */ + { 0x0000064F, 0x0080 }, /* R1615 (0x00064F) - PWM2MIX_INPUT_4_VOLUME */ + { 0x00000680, 0x0000 }, /* R1664 (0x000680) - OUT1LMIX_INPUT_1_SOURCE */ + { 0x00000681, 0x0080 }, /* R1665 (0x000681) - OUT1LMIX_INPUT_1_VOLUME */ + { 0x00000682, 0x0000 }, /* R1666 (0x000682) - OUT1LMIX_INPUT_2_SOURCE */ + { 0x00000683, 0x0080 }, /* R1667 (0x000683) - OUT1LMIX_INPUT_2_VOLUME */ + { 0x00000684, 0x0000 }, /* R1668 (0x000684) - OUT1LMIX_INPUT_3_SOURCE */ + { 0x00000685, 0x0080 }, /* R1669 (0x000685) - OUT1LMIX_INPUT_3_VOLUME */ + { 0x00000686, 0x0000 }, /* R1670 (0x000686) - OUT1LMIX_INPUT_4_SOURCE */ + { 0x00000687, 0x0080 }, /* R1671 (0x000687) - OUT1LMIX_INPUT_4_VOLUME */ + { 0x00000688, 0x0000 }, /* R1672 (0x000688) - OUT1RMIX_INPUT_1_SOURCE */ + { 0x00000689, 0x0080 }, /* R1673 (0x000689) - OUT1RMIX_INPUT_1_VOLUME */ + { 0x0000068A, 0x0000 }, /* R1674 (0x00068A) - OUT1RMIX_INPUT_2_SOURCE */ + { 0x0000068B, 0x0080 }, /* R1675 (0x00068B) - OUT1RMIX_INPUT_2_VOLUME */ + { 0x0000068C, 0x0000 }, /* R1676 (0x00068C) - OUT1RMIX_INPUT_3_SOURCE */ + { 0x0000068D, 0x0080 }, /* R1677 (0x00068D) - OUT1RMIX_INPUT_3_VOLUME */ + { 0x0000068E, 0x0000 }, /* R1678 (0x00068E) - OUT1RMIX_INPUT_4_SOURCE */ + { 0x0000068F, 0x0080 }, /* R1679 (0x00068F) - OUT1RMIX_INPUT_4_VOLUME */ + { 0x000006B0, 0x0000 }, /* R1712 (0x0006B0) - OUT4LMIX_INPUT_1_SOURCE */ + { 0x000006B1, 0x0080 }, /* R1713 (0x0006B1) - OUT4LMIX_INPUT_1_VOLUME */ + { 0x000006B2, 0x0000 }, /* R1714 (0x0006B2) - OUT4LMIX_INPUT_2_SOURCE */ + { 0x000006B3, 0x0080 }, /* R1715 (0x0006B3) - OUT4LMIX_INPUT_2_VOLUME */ + { 0x000006B4, 0x0000 }, /* R1716 (0x0006B4) - OUT4LMIX_INPUT_3_SOURCE */ + { 0x000006B5, 0x0080 }, /* R1717 (0x0006B5) - OUT4LMIX_INPUT_3_VOLUME */ + { 0x000006B6, 0x0000 }, /* R1718 (0x0006B6) - OUT4LMIX_INPUT_4_SOURCE */ + { 0x000006B7, 0x0080 }, /* R1719 (0x0006B7) - OUT4LMIX_INPUT_4_VOLUME */ + { 0x000006C0, 0x0000 }, /* R1728 (0x0006C0) - OUT5LMIX_INPUT_1_SOURCE */ + { 0x000006C1, 0x0080 }, /* R1729 (0x0006C1) - OUT5LMIX_INPUT_1_VOLUME */ + { 0x000006C2, 0x0000 }, /* R1730 (0x0006C2) - OUT5LMIX_INPUT_2_SOURCE */ + { 0x000006C3, 0x0080 }, /* R1731 (0x0006C3) - OUT5LMIX_INPUT_2_VOLUME */ + { 0x000006C4, 0x0000 }, /* R1732 (0x0006C4) - OUT5LMIX_INPUT_3_SOURCE */ + { 0x000006C5, 0x0080 }, /* R1733 (0x0006C5) - OUT5LMIX_INPUT_3_VOLUME */ + { 0x000006C6, 0x0000 }, /* R1734 (0x0006C6) - OUT5LMIX_INPUT_4_SOURCE */ + { 0x000006C7, 0x0080 }, /* R1735 (0x0006C7) - OUT5LMIX_INPUT_4_VOLUME */ + { 0x000006C8, 0x0000 }, /* R1736 (0x0006C8) - OUT5RMIX_INPUT_1_SOURCE */ + { 0x000006C9, 0x0080 }, /* R1737 (0x0006C9) - OUT5RMIX_INPUT_1_VOLUME */ + { 0x000006CA, 0x0000 }, /* R1738 (0x0006CA) - OUT5RMIX_INPUT_2_SOURCE */ + { 0x000006CB, 0x0080 }, /* R1739 (0x0006CB) - OUT5RMIX_INPUT_2_VOLUME */ + { 0x000006CC, 0x0000 }, /* R1740 (0x0006CC) - OUT5RMIX_INPUT_3_SOURCE */ + { 0x000006CD, 0x0080 }, /* R1741 (0x0006CD) - OUT5RMIX_INPUT_3_VOLUME */ + { 0x000006CE, 0x0000 }, /* R1742 (0x0006CE) - OUT5RMIX_INPUT_4_SOURCE */ + { 0x000006CF, 0x0080 }, /* R1743 (0x0006CF) - OUT5RMIX_INPUT_4_VOLUME */ + { 0x00000700, 0x0000 }, /* R1792 (0x000700) - AIF1TX1MIX_INPUT_1_SOURCE */ + { 0x00000701, 0x0080 }, /* R1793 (0x000701) - AIF1TX1MIX_INPUT_1_VOLUME */ + { 0x00000702, 0x0000 }, /* R1794 (0x000702) - AIF1TX1MIX_INPUT_2_SOURCE */ + { 0x00000703, 0x0080 }, /* R1795 (0x000703) - AIF1TX1MIX_INPUT_2_VOLUME */ + { 0x00000704, 0x0000 }, /* R1796 (0x000704) - AIF1TX1MIX_INPUT_3_SOURCE */ + { 0x00000705, 0x0080 }, /* R1797 (0x000705) - AIF1TX1MIX_INPUT_3_VOLUME */ + { 0x00000706, 0x0000 }, /* R1798 (0x000706) - AIF1TX1MIX_INPUT_4_SOURCE */ + { 0x00000707, 0x0080 }, /* R1799 (0x000707) - AIF1TX1MIX_INPUT_4_VOLUME */ + { 0x00000708, 0x0000 }, /* R1800 (0x000708) - AIF1TX2MIX_INPUT_1_SOURCE */ + { 0x00000709, 0x0080 }, /* R1801 (0x000709) - AIF1TX2MIX_INPUT_1_VOLUME */ + { 0x0000070A, 0x0000 }, /* R1802 (0x00070A) - AIF1TX2MIX_INPUT_2_SOURCE */ + { 0x0000070B, 0x0080 }, /* R1803 (0x00070B) - AIF1TX2MIX_INPUT_2_VOLUME */ + { 0x0000070C, 0x0000 }, /* R1804 (0x00070C) - AIF1TX2MIX_INPUT_3_SOURCE */ + { 0x0000070D, 0x0080 }, /* R1805 (0x00070D) - AIF1TX2MIX_INPUT_3_VOLUME */ + { 0x0000070E, 0x0000 }, /* R1806 (0x00070E) - AIF1TX2MIX_INPUT_4_SOURCE */ + { 0x0000070F, 0x0080 }, /* R1807 (0x00070F) - AIF1TX2MIX_INPUT_4_VOLUME */ + { 0x00000710, 0x0000 }, /* R1808 (0x000710) - AIF1TX3MIX_INPUT_1_SOURCE */ + { 0x00000711, 0x0080 }, /* R1809 (0x000711) - AIF1TX3MIX_INPUT_1_VOLUME */ + { 0x00000712, 0x0000 }, /* R1810 (0x000712) - AIF1TX3MIX_INPUT_2_SOURCE */ + { 0x00000713, 0x0080 }, /* R1811 (0x000713) - AIF1TX3MIX_INPUT_2_VOLUME */ + { 0x00000714, 0x0000 }, /* R1812 (0x000714) - AIF1TX3MIX_INPUT_3_SOURCE */ + { 0x00000715, 0x0080 }, /* R1813 (0x000715) - AIF1TX3MIX_INPUT_3_VOLUME */ + { 0x00000716, 0x0000 }, /* R1814 (0x000716) - AIF1TX3MIX_INPUT_4_SOURCE */ + { 0x00000717, 0x0080 }, /* R1815 (0x000717) - AIF1TX3MIX_INPUT_4_VOLUME */ + { 0x00000718, 0x0000 }, /* R1816 (0x000718) - AIF1TX4MIX_INPUT_1_SOURCE */ + { 0x00000719, 0x0080 }, /* R1817 (0x000719) - AIF1TX4MIX_INPUT_1_VOLUME */ + { 0x0000071A, 0x0000 }, /* R1818 (0x00071A) - AIF1TX4MIX_INPUT_2_SOURCE */ + { 0x0000071B, 0x0080 }, /* R1819 (0x00071B) - AIF1TX4MIX_INPUT_2_VOLUME */ + { 0x0000071C, 0x0000 }, /* R1820 (0x00071C) - AIF1TX4MIX_INPUT_3_SOURCE */ + { 0x0000071D, 0x0080 }, /* R1821 (0x00071D) - AIF1TX4MIX_INPUT_3_VOLUME */ + { 0x0000071E, 0x0000 }, /* R1822 (0x00071E) - AIF1TX4MIX_INPUT_4_SOURCE */ + { 0x0000071F, 0x0080 }, /* R1823 (0x00071F) - AIF1TX4MIX_INPUT_4_VOLUME */ + { 0x00000720, 0x0000 }, /* R1824 (0x000720) - AIF1TX5MIX_INPUT_1_SOURCE */ + { 0x00000721, 0x0080 }, /* R1825 (0x000721) - AIF1TX5MIX_INPUT_1_VOLUME */ + { 0x00000722, 0x0000 }, /* R1826 (0x000722) - AIF1TX5MIX_INPUT_2_SOURCE */ + { 0x00000723, 0x0080 }, /* R1827 (0x000723) - AIF1TX5MIX_INPUT_2_VOLUME */ + { 0x00000724, 0x0000 }, /* R1828 (0x000724) - AIF1TX5MIX_INPUT_3_SOURCE */ + { 0x00000725, 0x0080 }, /* R1829 (0x000725) - AIF1TX5MIX_INPUT_3_VOLUME */ + { 0x00000726, 0x0000 }, /* R1830 (0x000726) - AIF1TX5MIX_INPUT_4_SOURCE */ + { 0x00000727, 0x0080 }, /* R1831 (0x000727) - AIF1TX5MIX_INPUT_4_VOLUME */ + { 0x00000728, 0x0000 }, /* R1832 (0x000728) - AIF1TX6MIX_INPUT_1_SOURCE */ + { 0x00000729, 0x0080 }, /* R1833 (0x000729) - AIF1TX6MIX_INPUT_1_VOLUME */ + { 0x0000072A, 0x0000 }, /* R1834 (0x00072A) - AIF1TX6MIX_INPUT_2_SOURCE */ + { 0x0000072B, 0x0080 }, /* R1835 (0x00072B) - AIF1TX6MIX_INPUT_2_VOLUME */ + { 0x0000072C, 0x0000 }, /* R1836 (0x00072C) - AIF1TX6MIX_INPUT_3_SOURCE */ + { 0x0000072D, 0x0080 }, /* R1837 (0x00072D) - AIF1TX6MIX_INPUT_3_VOLUME */ + { 0x0000072E, 0x0000 }, /* R1838 (0x00072E) - AIF1TX6MIX_INPUT_4_SOURCE */ + { 0x0000072F, 0x0080 }, /* R1839 (0x00072F) - AIF1TX6MIX_INPUT_4_VOLUME */ + { 0x00000740, 0x0000 }, /* R1856 (0x000740) - AIF2TX1MIX_INPUT_1_SOURCE */ + { 0x00000741, 0x0080 }, /* R1857 (0x000741) - AIF2TX1MIX_INPUT_1_VOLUME */ + { 0x00000742, 0x0000 }, /* R1858 (0x000742) - AIF2TX1MIX_INPUT_2_SOURCE */ + { 0x00000743, 0x0080 }, /* R1859 (0x000743) - AIF2TX1MIX_INPUT_2_VOLUME */ + { 0x00000744, 0x0000 }, /* R1860 (0x000744) - AIF2TX1MIX_INPUT_3_SOURCE */ + { 0x00000745, 0x0080 }, /* R1861 (0x000745) - AIF2TX1MIX_INPUT_3_VOLUME */ + { 0x00000746, 0x0000 }, /* R1862 (0x000746) - AIF2TX1MIX_INPUT_4_SOURCE */ + { 0x00000747, 0x0080 }, /* R1863 (0x000747) - AIF2TX1MIX_INPUT_4_VOLUME */ + { 0x00000748, 0x0000 }, /* R1864 (0x000748) - AIF2TX2MIX_INPUT_1_SOURCE */ + { 0x00000749, 0x0080 }, /* R1865 (0x000749) - AIF2TX2MIX_INPUT_1_VOLUME */ + { 0x0000074A, 0x0000 }, /* R1866 (0x00074A) - AIF2TX2MIX_INPUT_2_SOURCE */ + { 0x0000074B, 0x0080 }, /* R1867 (0x00074B) - AIF2TX2MIX_INPUT_2_VOLUME */ + { 0x0000074C, 0x0000 }, /* R1868 (0x00074C) - AIF2TX2MIX_INPUT_3_SOURCE */ + { 0x0000074D, 0x0080 }, /* R1869 (0x00074D) - AIF2TX2MIX_INPUT_3_VOLUME */ + { 0x0000074E, 0x0000 }, /* R1870 (0x00074E) - AIF2TX2MIX_INPUT_4_SOURCE */ + { 0x0000074F, 0x0080 }, /* R1871 (0x00074F) - AIF2TX2MIX_INPUT_4_VOLUME */ + { 0x00000750, 0x0000 }, /* R1872 (0x000750) - AIF2TX3MIX_INPUT_1_SOURCE */ + { 0x00000751, 0x0080 }, /* R1873 (0x000751) - AIF2TX3MIX_INPUT_1_VOLUME */ + { 0x00000752, 0x0000 }, /* R1874 (0x000752) - AIF2TX3MIX_INPUT_2_SOURCE */ + { 0x00000753, 0x0080 }, /* R1875 (0x000753) - AIF2TX3MIX_INPUT_2_VOLUME */ + { 0x00000754, 0x0000 }, /* R1876 (0x000754) - AIF2TX3MIX_INPUT_3_SOURCE */ + { 0x00000755, 0x0080 }, /* R1877 (0x000755) - AIF2TX3MIX_INPUT_3_VOLUME */ + { 0x00000756, 0x0000 }, /* R1878 (0x000756) - AIF2TX3MIX_INPUT_4_SOURCE */ + { 0x00000757, 0x0080 }, /* R1879 (0x000757) - AIF2TX3MIX_INPUT_4_VOLUME */ + { 0x00000758, 0x0000 }, /* R1880 (0x000758) - AIF2TX4MIX_INPUT_1_SOURCE */ + { 0x00000759, 0x0080 }, /* R1881 (0x000759) - AIF2TX4MIX_INPUT_1_VOLUME */ + { 0x0000075A, 0x0000 }, /* R1882 (0x00075A) - AIF2TX4MIX_INPUT_2_SOURCE */ + { 0x0000075B, 0x0080 }, /* R1883 (0x00075B) - AIF2TX4MIX_INPUT_2_VOLUME */ + { 0x0000075C, 0x0000 }, /* R1884 (0x00075C) - AIF2TX4MIX_INPUT_3_SOURCE */ + { 0x0000075D, 0x0080 }, /* R1885 (0x00075D) - AIF2TX4MIX_INPUT_3_VOLUME */ + { 0x0000075E, 0x0000 }, /* R1886 (0x00075E) - AIF2TX4MIX_INPUT_4_SOURCE */ + { 0x0000075F, 0x0080 }, /* R1887 (0x00075F) - AIF2TX4MIX_INPUT_4_VOLUME */ + { 0x00000780, 0x0000 }, /* R1920 (0x000780) - AIF3TX1MIX_INPUT_1_SOURCE */ + { 0x00000781, 0x0080 }, /* R1921 (0x000781) - AIF3TX1MIX_INPUT_1_VOLUME */ + { 0x00000782, 0x0000 }, /* R1922 (0x000782) - AIF3TX1MIX_INPUT_2_SOURCE */ + { 0x00000783, 0x0080 }, /* R1923 (0x000783) - AIF3TX1MIX_INPUT_2_VOLUME */ + { 0x00000784, 0x0000 }, /* R1924 (0x000784) - AIF3TX1MIX_INPUT_3_SOURCE */ + { 0x00000785, 0x0080 }, /* R1925 (0x000785) - AIF3TX1MIX_INPUT_3_VOLUME */ + { 0x00000786, 0x0000 }, /* R1926 (0x000786) - AIF3TX1MIX_INPUT_4_SOURCE */ + { 0x00000787, 0x0080 }, /* R1927 (0x000787) - AIF3TX1MIX_INPUT_4_VOLUME */ + { 0x00000788, 0x0000 }, /* R1928 (0x000788) - AIF3TX2MIX_INPUT_1_SOURCE */ + { 0x00000789, 0x0080 }, /* R1929 (0x000789) - AIF3TX2MIX_INPUT_1_VOLUME */ + { 0x0000078A, 0x0000 }, /* R1930 (0x00078A) - AIF3TX2MIX_INPUT_2_SOURCE */ + { 0x0000078B, 0x0080 }, /* R1931 (0x00078B) - AIF3TX2MIX_INPUT_2_VOLUME */ + { 0x0000078C, 0x0000 }, /* R1932 (0x00078C) - AIF3TX2MIX_INPUT_3_SOURCE */ + { 0x0000078D, 0x0080 }, /* R1933 (0x00078D) - AIF3TX2MIX_INPUT_3_VOLUME */ + { 0x0000078E, 0x0000 }, /* R1934 (0x00078E) - AIF3TX2MIX_INPUT_4_SOURCE */ + { 0x0000078F, 0x0080 }, /* R1935 (0x00078F) - AIF3TX2MIX_INPUT_4_VOLUME */ + { 0x00000800, 0x0000 }, /* R2048 (0x000800) - SPDIF1TX1MIX_INPUT_1_SOURCE */ + { 0x00000801, 0x0080 }, /* R2049 (0x000801) - SPDIF1TX1MIX_INPUT_1_VOLUME */ + { 0x00000808, 0x0000 }, /* R2056 (0x000808) - SPDIF1TX2MIX_INPUT_1_SOURCE */ + { 0x00000809, 0x0080 }, /* R2057 (0x000809) - SPDIF1TX2MIX_INPUT_1_VOLUME */ + { 0x00000880, 0x0000 }, /* R2176 (0x000880) - EQ1MIX_INPUT_1_SOURCE */ + { 0x00000881, 0x0080 }, /* R2177 (0x000881) - EQ1MIX_INPUT_1_VOLUME */ + { 0x00000882, 0x0000 }, /* R2178 (0x000882) - EQ1MIX_INPUT_2_SOURCE */ + { 0x00000883, 0x0080 }, /* R2179 (0x000883) - EQ1MIX_INPUT_2_VOLUME */ + { 0x00000884, 0x0000 }, /* R2180 (0x000884) - EQ1MIX_INPUT_3_SOURCE */ + { 0x00000885, 0x0080 }, /* R2181 (0x000885) - EQ1MIX_INPUT_3_VOLUME */ + { 0x00000886, 0x0000 }, /* R2182 (0x000886) - EQ1MIX_INPUT_4_SOURCE */ + { 0x00000887, 0x0080 }, /* R2183 (0x000887) - EQ1MIX_INPUT_4_VOLUME */ + { 0x00000888, 0x0000 }, /* R2184 (0x000888) - EQ2MIX_INPUT_1_SOURCE */ + { 0x00000889, 0x0080 }, /* R2185 (0x000889) - EQ2MIX_INPUT_1_VOLUME */ + { 0x0000088A, 0x0000 }, /* R2186 (0x00088A) - EQ2MIX_INPUT_2_SOURCE */ + { 0x0000088B, 0x0080 }, /* R2187 (0x00088B) - EQ2MIX_INPUT_2_VOLUME */ + { 0x0000088C, 0x0000 }, /* R2188 (0x00088C) - EQ2MIX_INPUT_3_SOURCE */ + { 0x0000088D, 0x0080 }, /* R2189 (0x00088D) - EQ2MIX_INPUT_3_VOLUME */ + { 0x0000088E, 0x0000 }, /* R2190 (0x00088E) - EQ2MIX_INPUT_4_SOURCE */ + { 0x0000088F, 0x0080 }, /* R2191 (0x00088F) - EQ2MIX_INPUT_4_VOLUME */ + { 0x00000890, 0x0000 }, /* R2192 (0x000890) - EQ3MIX_INPUT_1_SOURCE */ + { 0x00000891, 0x0080 }, /* R2193 (0x000891) - EQ3MIX_INPUT_1_VOLUME */ + { 0x00000892, 0x0000 }, /* R2194 (0x000892) - EQ3MIX_INPUT_2_SOURCE */ + { 0x00000893, 0x0080 }, /* R2195 (0x000893) - EQ3MIX_INPUT_2_VOLUME */ + { 0x00000894, 0x0000 }, /* R2196 (0x000894) - EQ3MIX_INPUT_3_SOURCE */ + { 0x00000895, 0x0080 }, /* R2197 (0x000895) - EQ3MIX_INPUT_3_VOLUME */ + { 0x00000896, 0x0000 }, /* R2198 (0x000896) - EQ3MIX_INPUT_4_SOURCE */ + { 0x00000897, 0x0080 }, /* R2199 (0x000897) - EQ3MIX_INPUT_4_VOLUME */ + { 0x00000898, 0x0000 }, /* R2200 (0x000898) - EQ4MIX_INPUT_1_SOURCE */ + { 0x00000899, 0x0080 }, /* R2201 (0x000899) - EQ4MIX_INPUT_1_VOLUME */ + { 0x0000089A, 0x0000 }, /* R2202 (0x00089A) - EQ4MIX_INPUT_2_SOURCE */ + { 0x0000089B, 0x0080 }, /* R2203 (0x00089B) - EQ4MIX_INPUT_2_VOLUME */ + { 0x0000089C, 0x0000 }, /* R2204 (0x00089C) - EQ4MIX_INPUT_3_SOURCE */ + { 0x0000089D, 0x0080 }, /* R2205 (0x00089D) - EQ4MIX_INPUT_3_VOLUME */ + { 0x0000089E, 0x0000 }, /* R2206 (0x00089E) - EQ4MIX_INPUT_4_SOURCE */ + { 0x0000089F, 0x0080 }, /* R2207 (0x00089F) - EQ4MIX_INPUT_4_VOLUME */ + { 0x000008C0, 0x0000 }, /* R2240 (0x0008C0) - DRC1LMIX_INPUT_1_SOURCE */ + { 0x000008C1, 0x0080 }, /* R2241 (0x0008C1) - DRC1LMIX_INPUT_1_VOLUME */ + { 0x000008C2, 0x0000 }, /* R2242 (0x0008C2) - DRC1LMIX_INPUT_2_SOURCE */ + { 0x000008C3, 0x0080 }, /* R2243 (0x0008C3) - DRC1LMIX_INPUT_2_VOLUME */ + { 0x000008C4, 0x0000 }, /* R2244 (0x0008C4) - DRC1LMIX_INPUT_3_SOURCE */ + { 0x000008C5, 0x0080 }, /* R2245 (0x0008C5) - DRC1LMIX_INPUT_3_VOLUME */ + { 0x000008C6, 0x0000 }, /* R2246 (0x0008C6) - DRC1LMIX_INPUT_4_SOURCE */ + { 0x000008C7, 0x0080 }, /* R2247 (0x0008C7) - DRC1LMIX_INPUT_4_VOLUME */ + { 0x000008C8, 0x0000 }, /* R2248 (0x0008C8) - DRC1RMIX_INPUT_1_SOURCE */ + { 0x000008C9, 0x0080 }, /* R2249 (0x0008C9) - DRC1RMIX_INPUT_1_VOLUME */ + { 0x000008CA, 0x0000 }, /* R2250 (0x0008CA) - DRC1RMIX_INPUT_2_SOURCE */ + { 0x000008CB, 0x0080 }, /* R2251 (0x0008CB) - DRC1RMIX_INPUT_2_VOLUME */ + { 0x000008CC, 0x0000 }, /* R2252 (0x0008CC) - DRC1RMIX_INPUT_3_SOURCE */ + { 0x000008CD, 0x0080 }, /* R2253 (0x0008CD) - DRC1RMIX_INPUT_3_VOLUME */ + { 0x000008CE, 0x0000 }, /* R2254 (0x0008CE) - DRC1RMIX_INPUT_4_SOURCE */ + { 0x000008CF, 0x0080 }, /* R2255 (0x0008CF) - DRC1RMIX_INPUT_4_VOLUME */ + { 0x000008D0, 0x0000 }, /* R2256 (0x0008D0) - DRC2LMIX_INPUT_1_SOURCE */ + { 0x000008D1, 0x0080 }, /* R2257 (0x0008D1) - DRC2LMIX_INPUT_1_VOLUME */ + { 0x000008D2, 0x0000 }, /* R2258 (0x0008D2) - DRC2LMIX_INPUT_2_SOURCE */ + { 0x000008D3, 0x0080 }, /* R2259 (0x0008D3) - DRC2LMIX_INPUT_2_VOLUME */ + { 0x000008D4, 0x0000 }, /* R2260 (0x0008D4) - DRC2LMIX_INPUT_3_SOURCE */ + { 0x000008D5, 0x0080 }, /* R2261 (0x0008D5) - DRC2LMIX_INPUT_3_VOLUME */ + { 0x000008D6, 0x0000 }, /* R2262 (0x0008D6) - DRC2LMIX_INPUT_4_SOURCE */ + { 0x000008D7, 0x0080 }, /* R2263 (0x0008D7) - DRC2LMIX_INPUT_4_VOLUME */ + { 0x000008D8, 0x0000 }, /* R2264 (0x0008D8) - DRC2RMIX_INPUT_1_SOURCE */ + { 0x000008D9, 0x0080 }, /* R2265 (0x0008D9) - DRC2RMIX_INPUT_1_VOLUME */ + { 0x000008DA, 0x0000 }, /* R2266 (0x0008DA) - DRC2RMIX_INPUT_2_SOURCE */ + { 0x000008DB, 0x0080 }, /* R2267 (0x0008DB) - DRC2RMIX_INPUT_2_VOLUME */ + { 0x000008DC, 0x0000 }, /* R2268 (0x0008DC) - DRC2RMIX_INPUT_3_SOURCE */ + { 0x000008DD, 0x0080 }, /* R2269 (0x0008DD) - DRC2RMIX_INPUT_3_VOLUME */ + { 0x000008DE, 0x0000 }, /* R2270 (0x0008DE) - DRC2RMIX_INPUT_4_SOURCE */ + { 0x000008DF, 0x0080 }, /* R2271 (0x0008DF) - DRC2RMIX_INPUT_4_VOLUME */ + { 0x00000900, 0x0000 }, /* R2304 (0x000900) - HPLP1MIX_INPUT_1_SOURCE */ + { 0x00000901, 0x0080 }, /* R2305 (0x000901) - HPLP1MIX_INPUT_1_VOLUME */ + { 0x00000902, 0x0000 }, /* R2306 (0x000902) - HPLP1MIX_INPUT_2_SOURCE */ + { 0x00000903, 0x0080 }, /* R2307 (0x000903) - HPLP1MIX_INPUT_2_VOLUME */ + { 0x00000904, 0x0000 }, /* R2308 (0x000904) - HPLP1MIX_INPUT_3_SOURCE */ + { 0x00000905, 0x0080 }, /* R2309 (0x000905) - HPLP1MIX_INPUT_3_VOLUME */ + { 0x00000906, 0x0000 }, /* R2310 (0x000906) - HPLP1MIX_INPUT_4_SOURCE */ + { 0x00000907, 0x0080 }, /* R2311 (0x000907) - HPLP1MIX_INPUT_4_VOLUME */ + { 0x00000908, 0x0000 }, /* R2312 (0x000908) - HPLP2MIX_INPUT_1_SOURCE */ + { 0x00000909, 0x0080 }, /* R2313 (0x000909) - HPLP2MIX_INPUT_1_VOLUME */ + { 0x0000090A, 0x0000 }, /* R2314 (0x00090A) - HPLP2MIX_INPUT_2_SOURCE */ + { 0x0000090B, 0x0080 }, /* R2315 (0x00090B) - HPLP2MIX_INPUT_2_VOLUME */ + { 0x0000090C, 0x0000 }, /* R2316 (0x00090C) - HPLP2MIX_INPUT_3_SOURCE */ + { 0x0000090D, 0x0080 }, /* R2317 (0x00090D) - HPLP2MIX_INPUT_3_VOLUME */ + { 0x0000090E, 0x0000 }, /* R2318 (0x00090E) - HPLP2MIX_INPUT_4_SOURCE */ + { 0x0000090F, 0x0080 }, /* R2319 (0x00090F) - HPLP2MIX_INPUT_4_VOLUME */ + { 0x00000910, 0x0000 }, /* R2320 (0x000910) - HPLP3MIX_INPUT_1_SOURCE */ + { 0x00000911, 0x0080 }, /* R2321 (0x000911) - HPLP3MIX_INPUT_1_VOLUME */ + { 0x00000912, 0x0000 }, /* R2322 (0x000912) - HPLP3MIX_INPUT_2_SOURCE */ + { 0x00000913, 0x0080 }, /* R2323 (0x000913) - HPLP3MIX_INPUT_2_VOLUME */ + { 0x00000914, 0x0000 }, /* R2324 (0x000914) - HPLP3MIX_INPUT_3_SOURCE */ + { 0x00000915, 0x0080 }, /* R2325 (0x000915) - HPLP3MIX_INPUT_3_VOLUME */ + { 0x00000916, 0x0000 }, /* R2326 (0x000916) - HPLP3MIX_INPUT_4_SOURCE */ + { 0x00000917, 0x0080 }, /* R2327 (0x000917) - HPLP3MIX_INPUT_4_VOLUME */ + { 0x00000918, 0x0000 }, /* R2328 (0x000918) - HPLP4MIX_INPUT_1_SOURCE */ + { 0x00000919, 0x0080 }, /* R2329 (0x000919) - HPLP4MIX_INPUT_1_VOLUME */ + { 0x0000091A, 0x0000 }, /* R2330 (0x00091A) - HPLP4MIX_INPUT_2_SOURCE */ + { 0x0000091B, 0x0080 }, /* R2331 (0x00091B) - HPLP4MIX_INPUT_2_VOLUME */ + { 0x0000091C, 0x0000 }, /* R2332 (0x00091C) - HPLP4MIX_INPUT_3_SOURCE */ + { 0x0000091D, 0x0080 }, /* R2333 (0x00091D) - HPLP4MIX_INPUT_3_VOLUME */ + { 0x0000091E, 0x0000 }, /* R2334 (0x00091E) - HPLP4MIX_INPUT_4_SOURCE */ + { 0x0000091F, 0x0080 }, /* R2335 (0x00091F) - HPLP4MIX_INPUT_4_VOLUME */ + { 0x00000940, 0x0000 }, /* R2368 (0x000940) - DSP1LMIX_INPUT_1_SOURCE */ + { 0x00000941, 0x0080 }, /* R2369 (0x000941) - DSP1LMIX_INPUT_1_VOLUME */ + { 0x00000942, 0x0000 }, /* R2370 (0x000942) - DSP1LMIX_INPUT_2_SOURCE */ + { 0x00000943, 0x0080 }, /* R2371 (0x000943) - DSP1LMIX_INPUT_2_VOLUME */ + { 0x00000944, 0x0000 }, /* R2372 (0x000944) - DSP1LMIX_INPUT_3_SOURCE */ + { 0x00000945, 0x0080 }, /* R2373 (0x000945) - DSP1LMIX_INPUT_3_VOLUME */ + { 0x00000946, 0x0000 }, /* R2374 (0x000946) - DSP1LMIX_INPUT_4_SOURCE */ + { 0x00000947, 0x0080 }, /* R2375 (0x000947) - DSP1LMIX_INPUT_4_VOLUME */ + { 0x00000948, 0x0000 }, /* R2376 (0x000948) - DSP1RMIX_INPUT_1_SOURCE */ + { 0x00000949, 0x0080 }, /* R2377 (0x000949) - DSP1RMIX_INPUT_1_VOLUME */ + { 0x0000094A, 0x0000 }, /* R2378 (0x00094A) - DSP1RMIX_INPUT_2_SOURCE */ + { 0x0000094B, 0x0080 }, /* R2379 (0x00094B) - DSP1RMIX_INPUT_2_VOLUME */ + { 0x0000094C, 0x0000 }, /* R2380 (0x00094C) - DSP1RMIX_INPUT_3_SOURCE */ + { 0x0000094D, 0x0080 }, /* R2381 (0x00094D) - DSP1RMIX_INPUT_3_VOLUME */ + { 0x0000094E, 0x0000 }, /* R2382 (0x00094E) - DSP1RMIX_INPUT_4_SOURCE */ + { 0x0000094F, 0x0080 }, /* R2383 (0x00094F) - DSP1RMIX_INPUT_4_VOLUME */ + { 0x00000950, 0x0000 }, /* R2384 (0x000950) - DSP1AUX1MIX_INPUT_1_SOURCE */ + { 0x00000958, 0x0000 }, /* R2392 (0x000958) - DSP1AUX2MIX_INPUT_1_SOURCE */ + { 0x00000960, 0x0000 }, /* R2400 (0x000960) - DSP1AUX3MIX_INPUT_1_SOURCE */ + { 0x00000968, 0x0000 }, /* R2408 (0x000968) - DSP1AUX4MIX_INPUT_1_SOURCE */ + { 0x00000970, 0x0000 }, /* R2416 (0x000970) - DSP1AUX5MIX_INPUT_1_SOURCE */ + { 0x00000978, 0x0000 }, /* R2424 (0x000978) - DSP1AUX6MIX_INPUT_1_SOURCE */ + { 0x00000B00, 0x0000 }, /* R2816 (0x000B00) - ISRC1DEC1MIX_INPUT_1_SOURCE */ + { 0x00000B08, 0x0000 }, /* R2824 (0x000B08) - ISRC1DEC2MIX_INPUT_1_SOURCE */ + { 0x00000B10, 0x0000 }, /* R2832 (0x000B10) - ISRC1DEC3MIX_INPUT_1_SOURCE */ + { 0x00000B18, 0x0000 }, /* R2840 (0x000B18) - ISRC1DEC4MIX_INPUT_1_SOURCE */ + { 0x00000B20, 0x0000 }, /* R2848 (0x000B20) - ISRC1INT1MIX_INPUT_1_SOURCE */ + { 0x00000B28, 0x0000 }, /* R2856 (0x000B28) - ISRC1INT2MIX_INPUT_1_SOURCE */ + { 0x00000B30, 0x0000 }, /* R2864 (0x000B30) - ISRC1INT3MIX_INPUT_1_SOURCE */ + { 0x00000B38, 0x0000 }, /* R2872 (0x000B38) - ISRC1INT4MIX_INPUT_1_SOURCE */ + { 0x00000B40, 0x0000 }, /* R2880 (0x000B40) - ISRC2DEC1MIX_INPUT_1_SOURCE */ + { 0x00000B48, 0x0000 }, /* R2888 (0x000B48) - ISRC2DEC2MIX_INPUT_1_SOURCE */ + { 0x00000B50, 0x0000 }, /* R2896 (0x000B50) - ISRC2DEC3MIX_INPUT_1_SOURCE */ + { 0x00000B58, 0x0000 }, /* R2904 (0x000B58) - ISRC2DEC4MIX_INPUT_1_SOURCE */ + { 0x00000B60, 0x0000 }, /* R2912 (0x000B60) - ISRC2INT1MIX_INPUT_1_SOURCE */ + { 0x00000B68, 0x0000 }, /* R2920 (0x000B68) - ISRC2INT2MIX_INPUT_1_SOURCE */ + { 0x00000B70, 0x0000 }, /* R2928 (0x000B70) - ISRC2INT3MIX_INPUT_1_SOURCE */ + { 0x00000B78, 0x0000 }, /* R2936 (0x000B78) - ISRC2INT4MIX_INPUT_1_SOURCE */ + { 0x00000E00, 0x0000 }, /* R3584 (0x000E00) - FX_CTRL1 */ + { 0x00000E10, 0x6318 }, /* R3600 (0x000E10) - EQ1_1 */ + { 0x00000E11, 0x6300 }, /* R3601 (0x000E11) - EQ1_2 */ + { 0x00000E12, 0x0FC8 }, /* R3602 (0x000E12) - EQ1_3 */ + { 0x00000E13, 0x03FE }, /* R3603 (0x000E13) - EQ1_4 */ + { 0x00000E14, 0x00E0 }, /* R3604 (0x000E14) - EQ1_5 */ + { 0x00000E15, 0x1EC4 }, /* R3605 (0x000E15) - EQ1_6 */ + { 0x00000E16, 0xF136 }, /* R3606 (0x000E16) - EQ1_7 */ + { 0x00000E17, 0x0409 }, /* R3607 (0x000E17) - EQ1_8 */ + { 0x00000E18, 0x04CC }, /* R3608 (0x000E18) - EQ1_9 */ + { 0x00000E19, 0x1C9B }, /* R3609 (0x000E19) - EQ1_10 */ + { 0x00000E1A, 0xF337 }, /* R3610 (0x000E1A) - EQ1_11 */ + { 0x00000E1B, 0x040B }, /* R3611 (0x000E1B) - EQ1_12 */ + { 0x00000E1C, 0x0CBB }, /* R3612 (0x000E1C) - EQ1_13 */ + { 0x00000E1D, 0x16F8 }, /* R3613 (0x000E1D) - EQ1_14 */ + { 0x00000E1E, 0xF7D9 }, /* R3614 (0x000E1E) - EQ1_15 */ + { 0x00000E1F, 0x040A }, /* R3615 (0x000E1F) - EQ1_16 */ + { 0x00000E20, 0x1F14 }, /* R3616 (0x000E20) - EQ1_17 */ + { 0x00000E21, 0x058C }, /* R3617 (0x000E21) - EQ1_18 */ + { 0x00000E22, 0x0563 }, /* R3618 (0x000E22) - EQ1_19 */ + { 0x00000E23, 0x4000 }, /* R3619 (0x000E23) - EQ1_20 */ + { 0x00000E24, 0x0B75 }, /* R3620 (0x000E24) - EQ1_21 */ + { 0x00000E26, 0x6318 }, /* R3622 (0x000E26) - EQ2_1 */ + { 0x00000E27, 0x6300 }, /* R3623 (0x000E27) - EQ2_2 */ + { 0x00000E28, 0x0FC8 }, /* R3624 (0x000E28) - EQ2_3 */ + { 0x00000E29, 0x03FE }, /* R3625 (0x000E29) - EQ2_4 */ + { 0x00000E2A, 0x00E0 }, /* R3626 (0x000E2A) - EQ2_5 */ + { 0x00000E2B, 0x1EC4 }, /* R3627 (0x000E2B) - EQ2_6 */ + { 0x00000E2C, 0xF136 }, /* R3628 (0x000E2C) - EQ2_7 */ + { 0x00000E2D, 0x0409 }, /* R3629 (0x000E2D) - EQ2_8 */ + { 0x00000E2E, 0x04CC }, /* R3630 (0x000E2E) - EQ2_9 */ + { 0x00000E2F, 0x1C9B }, /* R3631 (0x000E2F) - EQ2_10 */ + { 0x00000E30, 0xF337 }, /* R3632 (0x000E30) - EQ2_11 */ + { 0x00000E31, 0x040B }, /* R3633 (0x000E31) - EQ2_12 */ + { 0x00000E32, 0x0CBB }, /* R3634 (0x000E32) - EQ2_13 */ + { 0x00000E33, 0x16F8 }, /* R3635 (0x000E33) - EQ2_14 */ + { 0x00000E34, 0xF7D9 }, /* R3636 (0x000E34) - EQ2_15 */ + { 0x00000E35, 0x040A }, /* R3637 (0x000E35) - EQ2_16 */ + { 0x00000E36, 0x1F14 }, /* R3638 (0x000E36) - EQ2_17 */ + { 0x00000E37, 0x058C }, /* R3639 (0x000E37) - EQ2_18 */ + { 0x00000E38, 0x0563 }, /* R3640 (0x000E38) - EQ2_19 */ + { 0x00000E39, 0x4000 }, /* R3641 (0x000E39) - EQ2_20 */ + { 0x00000E3A, 0x0B75 }, /* R3642 (0x000E3A) - EQ2_21 */ + { 0x00000E3C, 0x6318 }, /* R3644 (0x000E3C) - EQ3_1 */ + { 0x00000E3D, 0x6300 }, /* R3645 (0x000E3D) - EQ3_2 */ + { 0x00000E3E, 0x0FC8 }, /* R3646 (0x000E3E) - EQ3_3 */ + { 0x00000E3F, 0x03FE }, /* R3647 (0x000E3F) - EQ3_4 */ + { 0x00000E40, 0x00E0 }, /* R3648 (0x000E40) - EQ3_5 */ + { 0x00000E41, 0x1EC4 }, /* R3649 (0x000E41) - EQ3_6 */ + { 0x00000E42, 0xF136 }, /* R3650 (0x000E42) - EQ3_7 */ + { 0x00000E43, 0x0409 }, /* R3651 (0x000E43) - EQ3_8 */ + { 0x00000E44, 0x04CC }, /* R3652 (0x000E44) - EQ3_9 */ + { 0x00000E45, 0x1C9B }, /* R3653 (0x000E45) - EQ3_10 */ + { 0x00000E46, 0xF337 }, /* R3654 (0x000E46) - EQ3_11 */ + { 0x00000E47, 0x040B }, /* R3655 (0x000E47) - EQ3_12 */ + { 0x00000E48, 0x0CBB }, /* R3656 (0x000E48) - EQ3_13 */ + { 0x00000E49, 0x16F8 }, /* R3657 (0x000E49) - EQ3_14 */ + { 0x00000E4A, 0xF7D9 }, /* R3658 (0x000E4A) - EQ3_15 */ + { 0x00000E4B, 0x040A }, /* R3659 (0x000E4B) - EQ3_16 */ + { 0x00000E4C, 0x1F14 }, /* R3660 (0x000E4C) - EQ3_17 */ + { 0x00000E4D, 0x058C }, /* R3661 (0x000E4D) - EQ3_18 */ + { 0x00000E4E, 0x0563 }, /* R3662 (0x000E4E) - EQ3_19 */ + { 0x00000E4F, 0x4000 }, /* R3663 (0x000E4F) - EQ3_20 */ + { 0x00000E50, 0x0B75 }, /* R3664 (0x000E50) - EQ3_21 */ + { 0x00000E52, 0x6318 }, /* R3666 (0x000E52) - EQ4_1 */ + { 0x00000E53, 0x6300 }, /* R3667 (0x000E53) - EQ4_2 */ + { 0x00000E54, 0x0FC8 }, /* R3668 (0x000E54) - EQ4_3 */ + { 0x00000E55, 0x03FE }, /* R3669 (0x000E55) - EQ4_4 */ + { 0x00000E56, 0x00E0 }, /* R3670 (0x000E56) - EQ4_5 */ + { 0x00000E57, 0x1EC4 }, /* R3671 (0x000E57) - EQ4_6 */ + { 0x00000E58, 0xF136 }, /* R3672 (0x000E58) - EQ4_7 */ + { 0x00000E59, 0x0409 }, /* R3673 (0x000E59) - EQ4_8 */ + { 0x00000E5A, 0x04CC }, /* R3674 (0x000E5A) - EQ4_9 */ + { 0x00000E5B, 0x1C9B }, /* R3675 (0x000E5B) - EQ4_10 */ + { 0x00000E5C, 0xF337 }, /* R3676 (0x000E5C) - EQ4_11 */ + { 0x00000E5D, 0x040B }, /* R3677 (0x000E5D) - EQ4_12 */ + { 0x00000E5E, 0x0CBB }, /* R3678 (0x000E5E) - EQ4_13 */ + { 0x00000E5F, 0x16F8 }, /* R3679 (0x000E5F) - EQ4_14 */ + { 0x00000E60, 0xF7D9 }, /* R3680 (0x000E60) - EQ4_15 */ + { 0x00000E61, 0x040A }, /* R3681 (0x000E61) - EQ4_16 */ + { 0x00000E62, 0x1F14 }, /* R3682 (0x000E62) - EQ4_17 */ + { 0x00000E63, 0x058C }, /* R3683 (0x000E63) - EQ4_18 */ + { 0x00000E64, 0x0563 }, /* R3684 (0x000E64) - EQ4_19 */ + { 0x00000E65, 0x4000 }, /* R3685 (0x000E65) - EQ4_20 */ + { 0x00000E66, 0x0B75 }, /* R3686 (0x000E66) - EQ4_21 */ + { 0x00000E80, 0x0018 }, /* R3712 (0x000E80) - DRC1_CTRL1 */ + { 0x00000E81, 0x0933 }, /* R3713 (0x000E81) - DRC1_CTRL2 */ + { 0x00000E82, 0x0018 }, /* R3714 (0x000E82) - DRC1_CTRL3 */ + { 0x00000E83, 0x0000 }, /* R3715 (0x000E83) - DRC1_CTRL4 */ + { 0x00000E84, 0x0000 }, /* R3716 (0x000E84) - DRC1_CTRL5 */ + { 0x00000E88, 0x0018 }, /* R3720 (0x000E88) - DRC2_CTRL1 */ + { 0x00000E89, 0x0933 }, /* R3721 (0x000E89) - DRC2_CTRL2 */ + { 0x00000E8A, 0x0018 }, /* R3722 (0x000E8A) - DRC2_CTRL3 */ + { 0x00000E8B, 0x0000 }, /* R3723 (0x000E8B) - DRC2_CTRL4 */ + { 0x00000E8C, 0x0000 }, /* R3724 (0x000E8C) - DRC2_CTRL5 */ + { 0x00000EC0, 0x0000 }, /* R3776 (0x000EC0) - HPLPF1_1 */ + { 0x00000EC1, 0x0000 }, /* R3777 (0x000EC1) - HPLPF1_2 */ + { 0x00000EC4, 0x0000 }, /* R3780 (0x000EC4) - HPLPF2_1 */ + { 0x00000EC5, 0x0000 }, /* R3781 (0x000EC5) - HPLPF2_2 */ + { 0x00000EC8, 0x0000 }, /* R3784 (0x000EC8) - HPLPF3_1 */ + { 0x00000EC9, 0x0000 }, /* R3785 (0x000EC9) - HPLPF3_2 */ + { 0x00000ECC, 0x0000 }, /* R3788 (0x000ECC) - HPLPF4_1 */ + { 0x00000ECD, 0x0000 }, /* R3789 (0x000ECD) - HPLPF4_2 */ + { 0x00000EF0, 0x0000 }, /* R3824 (0x000EF0) - ISRC1_CTRL_1 */ + { 0x00000EF1, 0x0001 }, /* R3825 (0x000EF1) - ISRC1_CTRL_2 */ + { 0x00000EF2, 0x0000 }, /* R3826 (0x000EF2) - ISRC1_CTRL_3 */ + { 0x00000EF3, 0x0000 }, /* R3827 (0x000EF3) - ISRC2_CTRL_1 */ + { 0x00000EF4, 0x0001 }, /* R3828 (0x000EF4) - ISRC2_CTRL_2 */ + { 0x00000EF5, 0x0000 }, /* R3829 (0x000EF5) - ISRC2_CTRL_3 */ + { 0x00001300, 0x0000 }, /* R4864 (0x001300) - DAC Comp 1 */ + { 0x00001302, 0x0000 }, /* R4866 (0x001302) - DAC Comp 2 */ + { 0x00001380, 0x0000 }, /* R4992 (0x001380) - FRF_COEFFICIENT_1L_1 */ + { 0x00001381, 0x0000 }, /* R4993 (0x001381) - FRF_COEFFICIENT_1L_2 */ + { 0x00001382, 0x0000 }, /* R4994 (0x001382) - FRF_COEFFICIENT_1L_3 */ + { 0x00001383, 0x0000 }, /* R4995 (0x001383) - FRF_COEFFICIENT_1L_4 */ + { 0x00001390, 0x0000 }, /* R5008 (0x001390) - FRF_COEFFICIENT_1R_1 */ + { 0x00001391, 0x0000 }, /* R5009 (0x001391) - FRF_COEFFICIENT_1R_2 */ + { 0x00001392, 0x0000 }, /* R5010 (0x001392) - FRF_COEFFICIENT_1R_3 */ + { 0x00001393, 0x0000 }, /* R5011 (0x001393) - FRF_COEFFICIENT_1R_4 */ + { 0x000013E0, 0x0000 }, /* R5088 (0x0013E0) - FRF_COEFFICIENT_4L_1 */ + { 0x000013E1, 0x0000 }, /* R5089 (0x0013E1) - FRF_COEFFICIENT_4L_2 */ + { 0x000013E2, 0x0000 }, /* R5090 (0x0013E2) - FRF_COEFFICIENT_4L_3 */ + { 0x000013E3, 0x0000 }, /* R5091 (0x0013E3) - FRF_COEFFICIENT_4L_4 */ + { 0x00001400, 0x0000 }, /* R5120 (0x001400) - FRF_COEFFICIENT_5L_1 */ + { 0x00001401, 0x0000 }, /* R5121 (0x001401) - FRF_COEFFICIENT_5L_2 */ + { 0x00001402, 0x0000 }, /* R5122 (0x001402) - FRF_COEFFICIENT_5L_3 */ + { 0x00001403, 0x0000 }, /* R5123 (0x001403) - FRF_COEFFICIENT_5L_4 */ + { 0x00001410, 0x0000 }, /* R5136 (0x001410) - FRF_COEFFICIENT_5R_1 */ + { 0x00001411, 0x0000 }, /* R5137 (0x001411) - FRF_COEFFICIENT_5R_2 */ + { 0x00001412, 0x0000 }, /* R5138 (0x001412) - FRF_COEFFICIENT_5R_3 */ + { 0x00001413, 0x0000 }, /* R5139 (0x001413) - FRF_COEFFICIENT_5R_4 */ + { 0x00001701, 0xE800 }, /* R5889 (0x001701) - GPIO1_CTRL_2 */ + { 0x00001703, 0xE800 }, /* R5891 (0x001703) - GPIO2_CTRL_2 */ + { 0x00001705, 0xE800 }, /* R5893 (0x001705) - GPIO3_CTRL_2 */ + { 0x00001707, 0xE800 }, /* R5895 (0x001707) - GPIO4_CTRL_2 */ + { 0x00001709, 0xE800 }, /* R5897 (0x001709) - GPIO5_CTRL_2 */ + { 0x0000170B, 0xE800 }, /* R5899 (0x00170B) - GPIO6_CTRL_2 */ + { 0x0000170D, 0xE800 }, /* R5901 (0x00170D) - GPIO7_CTRL_2 */ + { 0x0000170F, 0xE800 }, /* R5903 (0x00170F) - GPIO8_CTRL_2 */ + { 0x00001711, 0xE800 }, /* R5905 (0x001711) - GPIO9_CTRL_2 */ + { 0x00001713, 0xE800 }, /* R5907 (0x001713) - GPIO10_CTRL_2 */ + { 0x00001715, 0xE800 }, /* R5909 (0x001715) - GPIO11_CTRL_2 */ + { 0x00001717, 0xE800 }, /* R5911 (0x001717) - GPIO12_CTRL_2 */ + { 0x00001719, 0xE800 }, /* R5913 (0x001719) - GPIO13_CTRL_2 */ + { 0x0000171B, 0xE800 }, /* R5915 (0x00171B) - GPIO14_CTRL_2 */ + { 0x0000171D, 0xE800 }, /* R5917 (0x00171D) - GPIO15_CTRL_2 */ + { 0x00001840, 0xFFFF }, /* R6208 (0x001840) - IRQ1_MASK_1 */ + { 0x00001841, 0xFFFF }, /* R6209 (0x001841) - IRQ1_MASK_2 */ + { 0x00001842, 0xFFFF }, /* R6210 (0x001842) - IRQ1 MASK 3 */ + { 0x00001843, 0xFFFF }, /* R6211 (0x001843) - IRQ1 MASK 4 */ + { 0x00001844, 0xFFFF }, /* R6212 (0x001844) - IRQ1 MASK 5 */ + { 0x00001845, 0xFFFF }, /* R6213 (0x001845) - IRQ1_MASK_6 */ + { 0x00001846, 0xFFFF }, /* R6214 (0x001846) - IRQ1_MASK_7 */ + { 0x00001847, 0xFFFF }, /* R6215 (0x001847) - IRQ1 MASK 8 */ + { 0x00001848, 0xFFFF }, /* R6216 (0x001848) - IRQ1_MASK_9 */ + { 0x00001849, 0xFFFF }, /* R6217 (0x001849) - IRQ1 MASK 10 */ + { 0x0000184A, 0xFFFF }, /* R6218 (0x00184A) - IRQ1_MASK_11 */ + { 0x0000184B, 0xFFFF }, /* R6219 (0x00184B) - IRQ1_MASK_12 */ + { 0x0000184C, 0xFFFF }, /* R6220 (0x00184C) - IRQ1_MASK_13 */ + { 0x0000184D, 0xFFFF }, /* R6221 (0x00184D) - IRQ1_MASK_14 */ + { 0x0000184E, 0xFFFF }, /* R6222 (0x00184E) - IRQ1_MASK_15 */ + { 0x0000184F, 0xFFFF }, /* R6223 (0x00184F) - IRQ1_MASK_16 */ + { 0x00001850, 0xFFFF }, /* R6224 (0x001850) - IRQ1_MASK_17 */ + { 0x00001851, 0xFFFF }, /* R6225 (0x001851) - IRQ1 MASK 18 */ + { 0x00001852, 0xFFFF }, /* R6226 (0x001852) - IRQ1 MASK 19 */ + { 0x00001853, 0xFFFF }, /* R6227 (0x001853) - IRQ1 MASK 20 */ + { 0x00001854, 0xFFFF }, /* R6228 (0x001854) - IRQ1_MASK_21 */ + { 0x00001855, 0xFFFF }, /* R6229 (0x001855) - IRQ1_MASK_22 */ + { 0x00001856, 0xFFFF }, /* R6230 (0x001856) - IRQ1_MASK_23 */ + { 0x00001857, 0xFFFF }, /* R6231 (0x001857) - IRQ1_MASK_24 */ + { 0x00001858, 0xFFFF }, /* R6232 (0x001858) - IRQ1_MASK_25 */ + { 0x00001859, 0xFFFF }, /* R6233 (0x001859) - IRQ1 MASK 26 */ + { 0x0000185A, 0xFFFF }, /* R6234 (0x00185A) - IRQ1_MASK_27 */ + { 0x0000185B, 0xFFFF }, /* R6235 (0x00185B) - IRQ1_MASK_28 */ + { 0x0000185C, 0xFFFF }, /* R6236 (0x00185C) - IRQ1 MASK 29 */ + { 0x0000185D, 0xFFFF }, /* R6237 (0x00185D) - IRQ1_MASK_30 */ + { 0x0000185E, 0xFFFF }, /* R6238 (0x00185E) - IRQ1_MASK_31 */ + { 0x0000185F, 0xFFFF }, /* R6239 (0x00185F) - IRQ1_MASK_32 */ + { 0x00001860, 0xFFFF }, /* R6240 (0x001860) - IRQ1_MASK_33 */ + { 0x00001948, 0xFFFF }, /* R6472 (0x001948) - IRQ2_MASK_9 */ + { 0x00001A06, 0x0000 }, /* R6662 (0x001A06) - INTERRUPT_DEBOUNCE_7 */ + { 0x00001A80, 0x4400 }, /* R6784 (0x001A80) - IRQ1_CTRL */ +}; + +static bool cs47l15_is_adsp_memory(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0x080000 ... 0x088ffe: + case 0x0a0000 ... 0x0a9ffe: + case 0x0c0000 ... 0x0c1ffe: + case 0x0e0000 ... 0x0e1ffe: + return true; + default: + return false; + } +} + +static bool cs47l15_16bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_SPI_CFG_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case CLEARWATER_COMFORT_NOISE_GENERATOR: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case CLEARWATER_DSP_CLOCK_1: + case CLEARWATER_DSP_CLOCK_2: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_CONTROL_7: + case ARIZONA_FLL1_EFS_2: + case ARIZONA_FLL1_LOOP_FILTER_TEST_1: + case ARIZONA_FLL1_NCO_TEST_0: + case ARIZONA_FLL1_SYNCHRONISER_1: + case ARIZONA_FLL1_SYNCHRONISER_2: + case ARIZONA_FLL1_SYNCHRONISER_3: + case ARIZONA_FLL1_SYNCHRONISER_4: + case ARIZONA_FLL1_SYNCHRONISER_5: + case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SYNCHRONISER_7: + case ARIZONA_FLL1_SPREAD_SPECTRUM: + case ARIZONA_FLL1_GPIO_CLOCK: + case MOON_FLLAO_CONTROL_1: + case MOON_FLLAO_CONTROL_2: + case MOON_FLLAO_CONTROL_3: + case MOON_FLLAO_CONTROL_4: + case MOON_FLLAO_CONTROL_5: + case MOON_FLLAO_CONTROL_6: + case MOON_FLLAO_CONTROL_7: + case MOON_FLLAO_CONTROL_8: + case MOON_FLLAO_CONTROL_9: + case MOON_FLLAO_CONTROL_10: + case MOON_FLLAO_CONTROL_11: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_5: + case MOON_HEADPHONE_DETECT_0: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HEADPHONE_DETECT_1: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case CLEARWATER_MICD_CLAMP_CONTROL: + case MOON_MIC_DETECT_0: + case ARIZONA_MIC_DETECT_1: + case ARIZONA_MIC_DETECT_2: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_MIC_DETECT_LEVEL_1: + case ARIZONA_MIC_DETECT_LEVEL_2: + case ARIZONA_MIC_DETECT_LEVEL_3: + case ARIZONA_MIC_DETECT_LEVEL_4: + case CLEARWATER_GP_SWITCH_1: + case ARIZONA_JACK_DETECT_ANALOGUE: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case MOON_IN1L_RATE_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case MOON_IN1R_RATE_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case MOON_IN2L_RATE_CONTROL: + case ARIZONA_IN2R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2R: + case ARIZONA_DMIC2R_CONTROL: + case MOON_IN2R_RATE_CONTROL: + case CS47L15_ADC_INT_BIAS: + case CS47L15_PGA_BIAS_SEL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case MOON_OUT1_CONFIG: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_OUTPUT_PATH_CONFIG_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case MOON_OUT2_CONFIG: + case ARIZONA_OUTPUT_PATH_CONFIG_4L: + case ARIZONA_DAC_DIGITAL_VOLUME_4L: + case ARIZONA_NOISE_GATE_SELECT_4L: + case ARIZONA_OUTPUT_PATH_CONFIG_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5L: + case ARIZONA_NOISE_GATE_SELECT_5L: + case ARIZONA_OUTPUT_PATH_CONFIG_5R: + case ARIZONA_DAC_DIGITAL_VOLUME_5R: + case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_DRE_ENABLE: + case CLEARWATER_EDRE_ENABLE: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_PDM_SPK1_CTRL_1: + case ARIZONA_PDM_SPK1_CTRL_2: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP_TEST_CTRL_5: + case ARIZONA_HP_TEST_CTRL_6: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_5: + case ARIZONA_AIF2_FRAME_CTRL_6: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_FRAME_CTRL_13: + case ARIZONA_AIF2_FRAME_CTRL_14: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_AIF3_BCLK_CTRL: + case ARIZONA_AIF3_TX_PIN_CTRL: + case ARIZONA_AIF3_RX_PIN_CTRL: + case ARIZONA_AIF3_RATE_CTRL: + case ARIZONA_AIF3_FORMAT: + case ARIZONA_AIF3_RX_BCLK_RATE: + case ARIZONA_AIF3_FRAME_CTRL_1: + case ARIZONA_AIF3_FRAME_CTRL_2: + case ARIZONA_AIF3_FRAME_CTRL_3: + case ARIZONA_AIF3_FRAME_CTRL_4: + case ARIZONA_AIF3_FRAME_CTRL_11: + case ARIZONA_AIF3_FRAME_CTRL_12: + case ARIZONA_AIF3_TX_ENABLES: + case ARIZONA_AIF3_RX_ENABLES: + case ARIZONA_SPD1_TX_CONTROL: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME: + case ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_2_SOURCE: + case ARIZONA_EQ1MIX_INPUT_2_VOLUME: + case ARIZONA_EQ1MIX_INPUT_3_SOURCE: + case ARIZONA_EQ1MIX_INPUT_3_VOLUME: + case ARIZONA_EQ1MIX_INPUT_4_SOURCE: + case ARIZONA_EQ1MIX_INPUT_4_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_2_SOURCE: + case ARIZONA_EQ2MIX_INPUT_2_VOLUME: + case ARIZONA_EQ2MIX_INPUT_3_SOURCE: + case ARIZONA_EQ2MIX_INPUT_3_VOLUME: + case ARIZONA_EQ2MIX_INPUT_4_SOURCE: + case ARIZONA_EQ2MIX_INPUT_4_VOLUME: + case ARIZONA_EQ3MIX_INPUT_1_SOURCE: + case ARIZONA_EQ3MIX_INPUT_1_VOLUME: + case ARIZONA_EQ3MIX_INPUT_2_SOURCE: + case ARIZONA_EQ3MIX_INPUT_2_VOLUME: + case ARIZONA_EQ3MIX_INPUT_3_SOURCE: + case ARIZONA_EQ3MIX_INPUT_3_VOLUME: + case ARIZONA_EQ3MIX_INPUT_4_SOURCE: + case ARIZONA_EQ3MIX_INPUT_4_VOLUME: + case ARIZONA_EQ4MIX_INPUT_1_SOURCE: + case ARIZONA_EQ4MIX_INPUT_1_VOLUME: + case ARIZONA_EQ4MIX_INPUT_2_SOURCE: + case ARIZONA_EQ4MIX_INPUT_2_VOLUME: + case ARIZONA_EQ4MIX_INPUT_3_SOURCE: + case ARIZONA_EQ4MIX_INPUT_3_VOLUME: + case ARIZONA_EQ4MIX_INPUT_4_SOURCE: + case ARIZONA_EQ4MIX_INPUT_4_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_4_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_EQ3_1: + case ARIZONA_EQ3_2: + case ARIZONA_EQ3_3: + case ARIZONA_EQ3_4: + case ARIZONA_EQ3_5: + case ARIZONA_EQ3_6: + case ARIZONA_EQ3_7: + case ARIZONA_EQ3_8: + case ARIZONA_EQ3_9: + case ARIZONA_EQ3_10: + case ARIZONA_EQ3_11: + case ARIZONA_EQ3_12: + case ARIZONA_EQ3_13: + case ARIZONA_EQ3_14: + case ARIZONA_EQ3_15: + case ARIZONA_EQ3_16: + case ARIZONA_EQ3_17: + case ARIZONA_EQ3_18: + case ARIZONA_EQ3_19: + case ARIZONA_EQ3_20: + case ARIZONA_EQ3_21: + case ARIZONA_EQ4_1: + case ARIZONA_EQ4_2: + case ARIZONA_EQ4_3: + case ARIZONA_EQ4_4: + case ARIZONA_EQ4_5: + case ARIZONA_EQ4_6: + case ARIZONA_EQ4_7: + case ARIZONA_EQ4_8: + case ARIZONA_EQ4_9: + case ARIZONA_EQ4_10: + case ARIZONA_EQ4_11: + case ARIZONA_EQ4_12: + case ARIZONA_EQ4_13: + case ARIZONA_EQ4_14: + case ARIZONA_EQ4_15: + case ARIZONA_EQ4_16: + case ARIZONA_EQ4_17: + case ARIZONA_EQ4_18: + case ARIZONA_EQ4_19: + case ARIZONA_EQ4_20: + case ARIZONA_EQ4_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case CLEARWATER_DRC2_CTRL1: + case CLEARWATER_DRC2_CTRL2: + case CLEARWATER_DRC2_CTRL3: + case CLEARWATER_DRC2_CTRL4: + case CLEARWATER_DRC2_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + case CLEARWATER_DAC_COMP_1: + case CLEARWATER_DAC_COMP_2: + case CLEARWATER_FRF_COEFFICIENT_1L_1: + case CLEARWATER_FRF_COEFFICIENT_1L_2: + case CLEARWATER_FRF_COEFFICIENT_1L_3: + case CLEARWATER_FRF_COEFFICIENT_1L_4: + case CLEARWATER_FRF_COEFFICIENT_1R_1: + case CLEARWATER_FRF_COEFFICIENT_1R_2: + case CLEARWATER_FRF_COEFFICIENT_1R_3: + case CLEARWATER_FRF_COEFFICIENT_1R_4: + case CLEARWATER_FRF_COEFFICIENT_4L_1: + case CLEARWATER_FRF_COEFFICIENT_4L_2: + case CLEARWATER_FRF_COEFFICIENT_4L_3: + case CLEARWATER_FRF_COEFFICIENT_4L_4: + case CLEARWATER_FRF_COEFFICIENT_5L_1: + case CLEARWATER_FRF_COEFFICIENT_5L_2: + case CLEARWATER_FRF_COEFFICIENT_5L_3: + case CLEARWATER_FRF_COEFFICIENT_5L_4: + case CLEARWATER_FRF_COEFFICIENT_5R_1: + case CLEARWATER_FRF_COEFFICIENT_5R_2: + case CLEARWATER_FRF_COEFFICIENT_5R_3: + case CLEARWATER_FRF_COEFFICIENT_5R_4: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO1_CTRL_2: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO2_CTRL_2: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO3_CTRL_2: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO4_CTRL_2: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO5_CTRL_2: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO6_CTRL_2: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO7_CTRL_2: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO8_CTRL_2: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO9_CTRL_2: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO10_CTRL_2: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO11_CTRL_2: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO12_CTRL_2: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO13_CTRL_2: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO14_CTRL_2: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO15_CTRL_2: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_3: + case CLEARWATER_IRQ1_STATUS_4: + case CLEARWATER_IRQ1_STATUS_5: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_8: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_10: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_16: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_20: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_26: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_29: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case MOON_IRQ1_STATUS_33: + case CLEARWATER_IRQ1_MASK_1: + case CLEARWATER_IRQ1_MASK_2: + case CLEARWATER_IRQ1_MASK_3: + case CLEARWATER_IRQ1_MASK_4: + case CLEARWATER_IRQ1_MASK_5: + case CLEARWATER_IRQ1_MASK_6: + case CLEARWATER_IRQ1_MASK_7: + case CLEARWATER_IRQ1_MASK_8: + case CLEARWATER_IRQ1_MASK_9: + case CLEARWATER_IRQ1_MASK_10: + case CLEARWATER_IRQ1_MASK_11: + case CLEARWATER_IRQ1_MASK_12: + case CLEARWATER_IRQ1_MASK_13: + case CLEARWATER_IRQ1_MASK_14: + case CLEARWATER_IRQ1_MASK_15: + case MOON_IRQ1_MASK_16: + case CLEARWATER_IRQ1_MASK_17: + case CLEARWATER_IRQ1_MASK_18: + case CLEARWATER_IRQ1_MASK_19: + case MOON_IRQ1_MASK_20: + case CLEARWATER_IRQ1_MASK_21: + case CLEARWATER_IRQ1_MASK_22: + case CLEARWATER_IRQ1_MASK_23: + case CLEARWATER_IRQ1_MASK_24: + case CLEARWATER_IRQ1_MASK_25: + case MOON_IRQ1_MASK_26: + case CLEARWATER_IRQ1_MASK_27: + case CLEARWATER_IRQ1_MASK_28: + case MOON_IRQ1_MASK_29: + case CLEARWATER_IRQ1_MASK_30: + case CLEARWATER_IRQ1_MASK_31: + case CLEARWATER_IRQ1_MASK_32: + case MOON_IRQ1_MASK_33: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_MASK_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + case CLEARWATER_INTERRUPT_DEBOUNCE_7: + case CLEARWATER_IRQ1_CTRL: + return true; + default: + return false; + } +} + +static bool cs47l15_16bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_FX_CTRL2: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_3: + case CLEARWATER_IRQ1_STATUS_4: + case CLEARWATER_IRQ1_STATUS_5: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_8: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_10: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_16: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_20: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_26: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_29: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case MOON_IRQ1_STATUS_33: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + return true; + default: + return false; + } +} + +static bool cs47l15_32bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_225: + case MOON_OTP_HPDET_CALIB_1 ... MOON_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + return true; + default: + return cs47l15_is_adsp_memory(dev, reg); + } +} + +static bool cs47l15_32bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_225: + case MOON_OTP_HPDET_CALIB_1 ... MOON_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + return true; + default: + return cs47l15_is_adsp_memory(dev, reg); + } +} + +const struct regmap_config cs47l15_16bit_spi_regmap = { + .name = "cs47l15_16bit", + .reg_bits = 32, + .pad_bits = 16, + .val_bits = 16, + + .max_register = CLEARWATER_INTERRUPT_RAW_STATUS_1, + .readable_reg = cs47l15_16bit_readable_register, + .volatile_reg = cs47l15_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = cs47l15_reg_default, + .num_reg_defaults = ARRAY_SIZE(cs47l15_reg_default), +}; +EXPORT_SYMBOL_GPL(cs47l15_16bit_spi_regmap); + +const struct regmap_config cs47l15_16bit_i2c_regmap = { + .name = "cs47l15_16bit", + .reg_bits = 32, + .val_bits = 16, + + .max_register = CLEARWATER_INTERRUPT_RAW_STATUS_1, + .readable_reg = cs47l15_16bit_readable_register, + .volatile_reg = cs47l15_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = cs47l15_reg_default, + .num_reg_defaults = ARRAY_SIZE(cs47l15_reg_default), +}; +EXPORT_SYMBOL_GPL(cs47l15_16bit_i2c_regmap); + +const struct regmap_config cs47l15_32bit_spi_regmap = { + .name = "cs47l15_32bit", + .reg_bits = 32, + .reg_stride = 2, + .pad_bits = 16, + .val_bits = 32, + + .max_register = MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + .readable_reg = cs47l15_32bit_readable_register, + .volatile_reg = cs47l15_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(cs47l15_32bit_spi_regmap); + +const struct regmap_config cs47l15_32bit_i2c_regmap = { + .name = "cs47l15_32bit", + .reg_bits = 32, + .reg_stride = 2, + .val_bits = 32, + + .max_register = MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + .readable_reg = cs47l15_32bit_readable_register, + .volatile_reg = cs47l15_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(cs47l15_32bit_i2c_regmap); diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/florida-tables.c similarity index 70% rename from drivers/mfd/wm5110-tables.c rename to drivers/mfd/florida-tables.c index c4159981529..d9c21a2b045 100644 --- a/drivers/mfd/wm5110-tables.c +++ b/drivers/mfd/florida-tables.c @@ -1,5 +1,5 @@ /* - * wm5110-tables.c -- WM5110 data tables + * florida-tables.c -- data tables for Florida-class codecs * * Copyright 2012 Wolfson Microelectronics plc * @@ -14,13 +14,14 @@ #include #include +#include #include "arizona.h" -#define WM5110_NUM_AOD_ISR 2 -#define WM5110_NUM_ISR 5 +#define FLORIDA_NUM_AOD_ISR 2 +#define FLORIDA_NUM_ISR 5 -static const struct reg_default wm5110_reva_patch[] = { +static const struct reg_sequence florida_reva_patch[] = { { 0x80, 0x3 }, { 0x44, 0x20 }, { 0x45, 0x40 }, @@ -133,7 +134,7 @@ static const struct reg_default wm5110_reva_patch[] = { { 0x209, 0x002A }, }; -static const struct reg_default wm5110_revb_patch[] = { +static const struct reg_sequence florida_revb_patch[] = { { 0x80, 0x3 }, { 0x36e, 0x0210 }, { 0x370, 0x0210 }, @@ -223,46 +224,92 @@ static const struct reg_default wm5110_revb_patch[] = { { 0x80, 0x0 }, }; +static const struct reg_sequence florida_revd_patch[] = { + { 0x80, 0x3 }, + { 0x80, 0x3 }, + { 0x393, 0x27 }, + { 0x394, 0x27 }, + { 0x395, 0x27 }, + { 0x396, 0x27 }, + { 0x397, 0x27 }, + { 0x398, 0x26 }, + { 0x221, 0x90 }, + { 0x211, 0x8 }, + { 0x36c, 0x1fb }, + { 0x26e, 0x64 }, + { 0x26f, 0xea }, + { 0x270, 0x1f16 }, + { 0x51b, 0x1 }, + { 0x55b, 0x1 }, + { 0x59b, 0x1 }, + { 0x4f0, 0x633 }, + { 0x441, 0xc059 }, + { 0x209, 0x27 }, + { 0x80, 0x0 }, + { 0x80, 0x0 }, +}; + +/* Add extra headphone write sequence locations */ +static const struct reg_sequence florida_reve_patch[] = { + { 0x80, 0x3 }, + { 0x80, 0x3 }, + { 0x4b, 0x138 }, + { 0x4c, 0x13d }, + { 0x80, 0x0 }, + { 0x80, 0x0 }, +}; + /* We use a function so we can use ARRAY_SIZE() */ -int wm5110_patch(struct arizona *arizona) +int florida_patch(struct arizona *arizona) { switch (arizona->rev) { case 0: return regmap_register_patch(arizona->regmap, - wm5110_reva_patch, - ARRAY_SIZE(wm5110_reva_patch)); + florida_reva_patch, + ARRAY_SIZE(florida_reva_patch)); case 1: return regmap_register_patch(arizona->regmap, - wm5110_revb_patch, - ARRAY_SIZE(wm5110_revb_patch)); - + florida_revb_patch, + ARRAY_SIZE(florida_revb_patch)); + case 3: + return regmap_register_patch(arizona->regmap, + florida_revd_patch, + ARRAY_SIZE(florida_revd_patch)); default: - return 0; + return regmap_register_patch(arizona->regmap, + florida_reve_patch, + ARRAY_SIZE(florida_reve_patch)); } } -EXPORT_SYMBOL_GPL(wm5110_patch); +EXPORT_SYMBOL_GPL(florida_patch); -static const struct regmap_irq wm5110_aod_irqs[ARIZONA_NUM_IRQ] = { +static const struct regmap_irq florida_aod_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_MICD_CLAMP_FALL] = { + .mask = ARIZONA_MICD_CLAMP_FALL_EINT1 + }, + [ARIZONA_IRQ_MICD_CLAMP_RISE] = { + .mask = ARIZONA_MICD_CLAMP_RISE_EINT1 + }, [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, }; -const struct regmap_irq_chip wm5110_aod = { - .name = "wm5110 AOD", +const struct regmap_irq_chip florida_aod = { + .name = "florida AOD", .status_base = ARIZONA_AOD_IRQ1, .mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1, .ack_base = ARIZONA_AOD_IRQ1, .wake_base = ARIZONA_WAKE_CONTROL, .wake_invert = 1, .num_regs = 1, - .irqs = wm5110_aod_irqs, - .num_irqs = ARRAY_SIZE(wm5110_aod_irqs), + .irqs = florida_aod_irqs, + .num_irqs = ARRAY_SIZE(florida_aod_irqs), }; -EXPORT_SYMBOL_GPL(wm5110_aod); +EXPORT_SYMBOL_GPL(florida_aod); -static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = { +static const struct regmap_irq florida_irqs[ARIZONA_NUM_IRQ] = { [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, @@ -305,11 +352,11 @@ static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = { .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 }, - [ARIZONA_IRQ_SPK_SHUTDOWN_WARN] = { - .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_WARN_EINT1 + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 }, - [ARIZONA_IRQ_SPK_SHUTDOWN] = { - .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 + [ARIZONA_IRQ_SPK_OVERHEAT] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 }, [ARIZONA_IRQ_HPDET] = { .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 @@ -381,15 +428,181 @@ static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = { [ARIZONA_IRQ_ISRC2_CFG_ERR] = { .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 }, + [ARIZONA_IRQ_HP3R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP3L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1 + }, + [ARIZONA_IRQ_HP2R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP2L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1 + }, + [ARIZONA_IRQ_HP1R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP1L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 + }, [ARIZONA_IRQ_BOOT_DONE] = { .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 }, - [ARIZONA_IRQ_DCS_DAC_DONE] = { - .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1 + [ARIZONA_IRQ_FLL2_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 + }, + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 }, - [ARIZONA_IRQ_DCS_HP_DONE] = { - .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1 +}; + +const struct regmap_irq_chip florida_irq = { + .name = "florida IRQ", + .status_base = ARIZONA_INTERRUPT_STATUS_1, + .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK, + .ack_base = ARIZONA_INTERRUPT_STATUS_1, + .num_regs = 5, + .irqs = florida_irqs, + .num_irqs = ARRAY_SIZE(florida_irqs), +}; +EXPORT_SYMBOL_GPL(florida_irq); + +static const struct regmap_irq florida_revd_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, + [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, + [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, + [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, + + [ARIZONA_IRQ_DSP4_RAM_RDY] = { + .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1 + }, + [ARIZONA_IRQ_DSP3_RAM_RDY] = { + .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 + }, + [ARIZONA_IRQ_DSP2_RAM_RDY] = { + .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 + }, + [ARIZONA_IRQ_DSP1_RAM_RDY] = { + .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ8] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ7] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ6] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ5] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ4] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ3] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ2] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ1] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 + }, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 + }, + [ARIZONA_IRQ_SPK_OVERHEAT] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 + }, + [ARIZONA_IRQ_HPDET] = { + .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 + }, + [ARIZONA_IRQ_MICDET] = { + .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 + }, + [ARIZONA_IRQ_WSEQ_DONE] = { + .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 + }, + [ARIZONA_IRQ_DRC2_SIG_DET] = { + .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 + }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { + .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 + }, + [ARIZONA_IRQ_ASRC2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 + }, + [ARIZONA_IRQ_ASRC1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 + }, + [ARIZONA_IRQ_UNDERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_OVERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_FLL2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 + }, + [ARIZONA_IRQ_FLL1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 + }, + + [ARIZONA_IRQ_CTRLIF_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1 + }, + [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = { + .reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 + }, + [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_SYSCLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_ISRC1_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_ISRC2_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_ISRC3_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_HP3R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP3L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1 + }, + [ARIZONA_IRQ_HP2R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP2L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1 + }, + [ARIZONA_IRQ_HP1R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP1L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 + }, + + [ARIZONA_IRQ_BOOT_DONE] = { + .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 + }, + [ARIZONA_IRQ_ASRC_CFG_ERR] = { + .reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1 }, [ARIZONA_IRQ_FLL2_CLOCK_OK] = { .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 @@ -397,28 +610,74 @@ static const struct regmap_irq wm5110_irqs[ARIZONA_NUM_IRQ] = { [ARIZONA_IRQ_FLL1_CLOCK_OK] = { .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 }, + + [ARIZONA_IRQ_DSP_SHARED_WR_COLL] = { + .reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1 + }, + [ARIZONA_IRQ_SPK_SHUTDOWN] = { + .reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 + }, + [ARIZONA_IRQ_SPK1R_SHORT] = { + .reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1 + }, + [ARIZONA_IRQ_SPK1L_SHORT] = { + .reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1 + }, + [ARIZONA_IRQ_HP3R_SC_NEG] = { + .reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1 + }, + [ARIZONA_IRQ_HP3R_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1 + }, + [ARIZONA_IRQ_HP3L_SC_NEG] = { + .reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1 + }, + [ARIZONA_IRQ_HP3L_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1 + }, + [ARIZONA_IRQ_HP2R_SC_NEG] = { + .reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1 + }, + [ARIZONA_IRQ_HP2R_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1 + }, + [ARIZONA_IRQ_HP2L_SC_NEG] = { + .reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1 + }, + [ARIZONA_IRQ_HP2L_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1 + }, + [ARIZONA_IRQ_HP1R_SC_NEG] = { + .reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1 + }, + [ARIZONA_IRQ_HP1R_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1 + }, + [ARIZONA_IRQ_HP1L_SC_NEG] = { + .reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1 + }, + [ARIZONA_IRQ_HP1L_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1 + }, }; -const struct regmap_irq_chip wm5110_irq = { - .name = "wm5110 IRQ", +const struct regmap_irq_chip florida_revd_irq = { + .name = "florida IRQ", .status_base = ARIZONA_INTERRUPT_STATUS_1, .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK, .ack_base = ARIZONA_INTERRUPT_STATUS_1, - .num_regs = 5, - .irqs = wm5110_irqs, - .num_irqs = ARRAY_SIZE(wm5110_irqs), + .num_regs = 6, + .irqs = florida_revd_irqs, + .num_irqs = ARRAY_SIZE(florida_revd_irqs), }; -EXPORT_SYMBOL_GPL(wm5110_irq); +EXPORT_SYMBOL_GPL(florida_revd_irq); -static const struct reg_default wm5110_reg_default[] = { +static const struct reg_default florida_reg_default[] = { { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */ { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */ { 0x0000000A, 0x0001 }, /* R10 - Ctrl IF I2C2 CFG 1 */ - { 0x0000000B, 0x0036 }, /* R11 - Ctrl IF I2C1 CFG 2 */ - { 0x0000000C, 0x0036 }, /* R12 - Ctrl IF I2C2 CFG 2 */ - { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */ - { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */ - { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */ + { 0x0000000B, 0x001A }, /* R11 - Ctrl IF I2C1 CFG 2 */ + { 0x0000000C, 0x001A }, /* R12 - Ctrl IF I2C2 CFG 2 */ { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */ { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */ { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */ @@ -429,14 +688,17 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */ { 0x00000040, 0x0000 }, /* R64 - Wake control */ { 0x00000041, 0x0000 }, /* R65 - Sequence control */ + { 0x00000042, 0x0000 }, /* R66 - Spare Triggers */ { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */ { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ - { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */ - { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */ - { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */ - { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */ + { 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */ + { 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */ + { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */ + { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */ + { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */ + { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */ { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ @@ -453,6 +715,7 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */ { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */ { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */ + { 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */ { 0x00000149, 0x0000 }, /* R329 - Output system clock */ { 0x0000014A, 0x0000 }, /* R330 - Output async clock */ { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */ @@ -460,54 +723,60 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */ { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */ { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */ - { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */ + { 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */ { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */ { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */ { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */ { 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */ { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */ - { 0x00000177, 0x0281 }, /* R375 - FLL1 Loop Filter Test 1 */ - { 0x00000178, 0x0000 }, /* R376 - FLL1 NCO Test 0 */ + { 0x00000179, 0x0000 }, /* R376 - FLL1 Control 7 */ { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */ { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */ { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */ { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */ { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */ { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */ + { 0x00000187, 0x0001 }, /* R390 - FLL1 Synchroniser 7 */ { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */ - { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */ - { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */ + { 0x0000018A, 0x000C }, /* R394 - FLL1 GPIO Clock */ + { 0x00000191, 0x0002 }, /* R401 - FLL2 Control 1 */ { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */ { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */ { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */ { 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */ { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */ - { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */ - { 0x00000198, 0x0000 }, /* R408 - FLL2 NCO Test 0 */ + { 0x00000199, 0x0000 }, /* R408 - FLL2 Control 7 */ { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */ { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */ { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */ { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */ { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */ { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */ + { 0x000001A7, 0x0001 }, /* R422 - FLL2 Synchroniser 7 */ { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */ - { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */ + { 0x000001AA, 0x000C }, /* R426 - FLL2 GPIO Clock */ { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */ { 0x00000210, 0x0184 }, /* R528 - LDO1 Control 1 */ - { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */ - { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */ - { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */ - { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */ + { 0x00000213, 0x03E4 }, /* R531 - LDO2 Control 1 */ + { 0x00000218, 0x00E6 }, /* R536 - Mic Bias Ctrl 1 */ + { 0x00000219, 0x00E6 }, /* R537 - Mic Bias Ctrl 2 */ + { 0x0000021A, 0x00E6 }, /* R538 - Mic Bias Ctrl 3 */ { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */ - { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */ - { 0x0000029C, 0x0000 }, /* R668 - Headphone Detect 2 */ + { 0x0000029B, 0x0028 }, /* R667 - Headphone Detect 1 */ + { 0x000002A2, 0x0000 }, /* R674 - Micd clamp control */ { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */ { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */ + { 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */ + { 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */ + { 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */ + { 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */ { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */ + { 0x000002CB, 0x0000 }, /* R715 - Isolation control */ { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */ { 0x00000300, 0x0000 }, /* R768 - Input Enables */ { 0x00000308, 0x0000 }, /* R776 - Input Rate */ { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ + { 0x0000030C, 0x0002 }, /* R780 - HPF Control */ { 0x00000310, 0x2080 }, /* R784 - IN1L Control */ { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ @@ -529,6 +798,7 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000328, 0x2000 }, /* R808 - IN4L Control */ { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */ { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */ + { 0x0000032C, 0x0000 }, /* R812 - IN4R Control */ { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */ { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */ { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ @@ -536,60 +806,94 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */ { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */ { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */ - { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */ + { 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */ { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */ { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */ { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */ - { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */ + { 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */ { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */ { 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */ { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */ - { 0x0000041A, 0x0080 }, /* R1050 - DAC Volume Limit 2L */ + { 0x0000041A, 0x0081 }, /* R1050 - DAC Volume Limit 2L */ { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */ { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */ { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */ - { 0x0000041E, 0x0080 }, /* R1054 - DAC Volume Limit 2R */ + { 0x0000041E, 0x0081 }, /* R1054 - DAC Volume Limit 2R */ { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */ { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */ { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */ - { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */ + { 0x00000422, 0x0081 }, /* R1058 - DAC Volume Limit 3L */ { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */ { 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */ { 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */ - { 0x00000426, 0x0080 }, /* R1062 - DAC Volume Limit 3R */ + { 0x00000426, 0x0081 }, /* R1062 - DAC Volume Limit 3R */ { 0x00000427, 0x0020 }, /* R1063 - Noise Gate Select 3R */ { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */ { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */ - { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */ + { 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */ { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */ { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */ { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */ - { 0x0000042E, 0x0080 }, /* R1070 - Out Volume 4R */ + { 0x0000042E, 0x0081 }, /* R1070 - Out Volume 4R */ { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */ { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */ { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */ - { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */ + { 0x00000432, 0x0081 }, /* R1074 - DAC Volume Limit 5L */ { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */ { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */ { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */ - { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */ + { 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */ { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */ { 0x00000438, 0x0000 }, /* R1080 - Output Path Config 6L */ { 0x00000439, 0x0180 }, /* R1081 - DAC Digital Volume 6L */ - { 0x0000043A, 0x0080 }, /* R1082 - DAC Volume Limit 6L */ + { 0x0000043A, 0x0081 }, /* R1082 - DAC Volume Limit 6L */ { 0x0000043B, 0x0400 }, /* R1083 - Noise Gate Select 6L */ { 0x0000043C, 0x0000 }, /* R1084 - Output Path Config 6R */ { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */ - { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */ + { 0x0000043E, 0x0081 }, /* R1086 - DAC Volume Limit 6R */ { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */ + { 0x00000440, 0x003F }, /* R1088 - DRE Enable */ { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ - { 0x00000458, 0x0001 }, /* R1112 - Noise Gate Control */ - { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */ - { 0x00000481, 0x0040 }, /* R1153 - Class W ANC Threshold 2 */ + { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ + { 0x00000460, 0x0C40 }, + { 0x00000461, 0x8000 }, + { 0x00000462, 0x0C41 }, + { 0x00000463, 0x4820 }, + { 0x00000464, 0x0C41 }, + { 0x00000465, 0x4040 }, + { 0x00000466, 0x0C41 }, + { 0x00000467, 0x3940 }, + { 0x00000468, 0x0C42 }, + { 0x00000469, 0x2030 }, + { 0x0000046A, 0x0842 }, + { 0x0000046B, 0x1990 }, + { 0x0000046C, 0x08C2 }, + { 0x0000046D, 0x1450 }, + { 0x0000046E, 0x08C6 }, + { 0x0000046F, 0x1020 }, + { 0x00000470, 0x08C6 }, + { 0x00000471, 0x0CD0 }, + { 0x00000472, 0x08C6 }, + { 0x00000473, 0x0A30 }, + { 0x00000474, 0x0442 }, + { 0x00000475, 0x0660 }, + { 0x00000476, 0x0446 }, + { 0x00000477, 0x0510 }, + { 0x00000478, 0x04C6 }, + { 0x00000479, 0x0400 }, + { 0x0000047A, 0x04CE }, + { 0x0000047B, 0x0330 }, + { 0x0000047C, 0x05DF }, + { 0x0000047D, 0x0001 }, + { 0x0000047E, 0x07FF }, + { 0x00000483, 0x0826 }, { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */ { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */ { 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */ { 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */ + { 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */ + { 0x000004A1, 0x3400 }, /* R1185 - HP2 Short Circuit Ctrl */ + { 0x000004A2, 0x3400 }, /* R1186 - HP3 Short Circuit Ctrl */ { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ @@ -628,8 +932,16 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */ { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */ { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */ + { 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */ + { 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */ + { 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */ + { 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */ { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */ { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */ + { 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */ + { 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */ + { 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */ + { 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */ { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */ { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */ { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ @@ -866,6 +1178,38 @@ static const struct reg_default wm5110_reg_default[] = { { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ + { 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */ + { 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */ + { 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */ + { 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */ + { 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */ + { 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */ + { 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */ + { 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */ + { 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */ + { 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */ + { 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */ + { 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */ + { 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */ + { 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */ + { 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */ + { 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */ + { 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */ + { 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */ + { 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */ + { 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */ + { 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */ + { 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */ + { 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */ + { 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */ + { 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */ + { 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */ + { 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */ + { 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */ + { 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */ + { 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */ + { 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */ + { 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */ { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */ { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */ { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */ @@ -1165,42 +1509,43 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */ { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */ { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */ + { 0x00000C18, 0x0000 }, /* R3096 - GP Switch 1 */ { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */ - { 0x00000C21, 0x8001 }, /* R3105 - Misc Pad Ctrl 2 */ + { 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */ { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */ { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */ { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */ { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */ - { 0x00000C30, 0x8282 }, /* R3120 - Misc Pad Ctrl 7 */ - { 0x00000C31, 0x0082 }, /* R3121 - Misc Pad Ctrl 8 */ - { 0x00000C32, 0x8282 }, /* R3122 - Misc Pad Ctrl 9 */ - { 0x00000C33, 0x8282 }, /* R3123 - Misc Pad Ctrl 10 */ - { 0x00000C34, 0x8282 }, /* R3124 - Misc Pad Ctrl 11 */ - { 0x00000C35, 0x8282 }, /* R3125 - Misc Pad Ctrl 12 */ - { 0x00000C36, 0x8282 }, /* R3126 - Misc Pad Ctrl 13 */ - { 0x00000C37, 0x8282 }, /* R3127 - Misc Pad Ctrl 14 */ - { 0x00000C38, 0x8282 }, /* R3128 - Misc Pad Ctrl 15 */ - { 0x00000C39, 0x8282 }, /* R3129 - Misc Pad Ctrl 16 */ - { 0x00000C3A, 0x8282 }, /* R3130 - Misc Pad Ctrl 17 */ - { 0x00000C3B, 0x8282 }, /* R3131 - Misc Pad Ctrl 18 */ - { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */ - { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */ - { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */ + { 0x00000C30, 0x0404 }, /* R3120 - Misc Pad Ctrl 7 */ + { 0x00000C31, 0x0004 }, /* R3121 - Misc Pad Ctrl 8 */ + { 0x00000C32, 0x0404 }, /* R3122 - Misc Pad Ctrl 9 */ + { 0x00000C33, 0x0404 }, /* R3123 - Misc Pad Ctrl 10 */ + { 0x00000C34, 0x0404 }, /* R3124 - Misc Pad Ctrl 11 */ + { 0x00000C35, 0x0404 }, /* R3125 - Misc Pad Ctrl 12 */ + { 0x00000C36, 0x0404 }, /* R3126 - Misc Pad Ctrl 13 */ + { 0x00000C37, 0x0404 }, /* R3127 - Misc Pad Ctrl 14 */ + { 0x00000C38, 0x0004 }, /* R3128 - Misc Pad Ctrl 15 */ + { 0x00000C39, 0x0404 }, /* R3129 - Misc Pad Ctrl 16 */ + { 0x00000C3A, 0x0404 }, /* R3130 - Misc Pad Ctrl 17 */ + { 0x00000C3B, 0x0404 }, /* R3131 - Misc Pad Ctrl 18 */ + { 0x00000D08, 0x000F }, /* R3336 - Interrupt Status 1 Mask */ + { 0x00000D09, 0x0FFF }, /* R3337 - Interrupt Status 2 Mask */ + { 0x00000D0A, 0xFFEF }, /* R3338 - Interrupt Status 3 Mask */ { 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */ - { 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */ + { 0x00000D0C, 0xFE3B }, /* R3340 - Interrupt Status 5 Mask */ + { 0x00000D0D, 0xFFFF }, /* R3341 - Interrupt Status 6 Mask */ { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */ - { 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */ - { 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */ - { 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */ + { 0x00000D18, 0x000F }, /* R3352 - IRQ2 Status 1 Mask */ + { 0x00000D19, 0x0FFF }, /* R3353 - IRQ2 Status 2 Mask */ + { 0x00000D1A, 0xFFEF }, /* R3354 - IRQ2 Status 3 Mask */ { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */ - { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */ + { 0x00000D1C, 0xFE3B }, /* R3356 - IRQ2 Status 5 Mask */ + { 0x00000D1D, 0xFFFF }, /* R3357 - IRQ2 Status 6 Mask */ { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */ - { 0x00000D50, 0x0000 }, /* R3408 - AOD wkup and trig */ - { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */ - { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */ + { 0x00000D53, 0x00FC }, /* R3411 - AOD IRQ Mask IRQ1 */ + { 0x00000D54, 0x00FC }, /* R3412 - AOD IRQ Mask IRQ2 */ { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */ { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */ - { 0x00000E01, 0x0000 }, /* R3585 - FX_Ctrl2 */ { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */ { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */ { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */ @@ -1305,6 +1650,7 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */ { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */ + { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */ { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */ { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */ { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */ @@ -1314,20 +1660,251 @@ static const struct reg_default wm5110_reg_default[] = { { 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */ { 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */ { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */ - { 0x00000F00, 0x0000 }, /* R3840 - Clock Control */ { 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */ + { 0x00000F08, 0x001c }, /* R3848 - ANC Coefficient */ + { 0x00000F09, 0x0000 }, /* R3849 - ANC Coefficient */ + { 0x00000F0A, 0x0000 }, /* R3850 - ANC Coefficient */ + { 0x00000F0B, 0x0000 }, /* R3851 - ANC Coefficient */ + { 0x00000F0C, 0x0000 }, /* R3852 - ANC Coefficient */ + { 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */ + { 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */ + { 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */ + { 0x00000F10, 0x0001 }, /* R3856 - ANC Coefficient */ + { 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */ + { 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */ + { 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */ + { 0x00000F17, 0x0004 }, /* R3863 - FCL ADC Reformatter Control */ + { 0x00000F18, 0x0004 }, /* R3864 - ANC Coefficient */ + { 0x00000F19, 0x0002 }, /* R3865 - ANC Coefficient */ + { 0x00000F1A, 0x0000 }, /* R3866 - ANC Coefficient */ + { 0x00000F1B, 0x0010 }, /* R3867 - ANC Coefficient */ + { 0x00000F1C, 0x0000 }, /* R3868 - ANC Coefficient */ + { 0x00000F1D, 0x0000 }, /* R3869 - ANC Coefficient */ + { 0x00000F1E, 0x0000 }, /* R3870 - ANC Coefficient */ + { 0x00000F1F, 0x0000 }, /* R3871 - ANC Coefficient */ + { 0x00000F20, 0x0000 }, /* R3872 - ANC Coefficient */ + { 0x00000F21, 0x0000 }, /* R3873 - ANC Coefficient */ + { 0x00000F22, 0x0000 }, /* R3874 - ANC Coefficient */ + { 0x00000F23, 0x0000 }, /* R3875 - ANC Coefficient */ + { 0x00000F24, 0x0000 }, /* R3876 - ANC Coefficient */ + { 0x00000F25, 0x0000 }, /* R3877 - ANC Coefficient */ + { 0x00000F26, 0x0000 }, /* R3878 - ANC Coefficient */ + { 0x00000F27, 0x0000 }, /* R3879 - ANC Coefficient */ + { 0x00000F28, 0x0000 }, /* R3880 - ANC Coefficient */ + { 0x00000F29, 0x0000 }, /* R3881 - ANC Coefficient */ + { 0x00000F2A, 0x0000 }, /* R3882 - ANC Coefficient */ + { 0x00000F2B, 0x0000 }, /* R3883 - ANC Coefficient */ + { 0x00000F2C, 0x0000 }, /* R3884 - ANC Coefficient */ + { 0x00000F2D, 0x0000 }, /* R3885 - ANC Coefficient */ + { 0x00000F2E, 0x0000 }, /* R3886 - ANC Coefficient */ + { 0x00000F2F, 0x0000 }, /* R3887 - ANC Coefficient */ + { 0x00000F30, 0x0000 }, /* R3888 - ANC Coefficient */ + { 0x00000F31, 0x0000 }, /* R3889 - ANC Coefficient */ + { 0x00000F32, 0x0000 }, /* R3890 - ANC Coefficient */ + { 0x00000F33, 0x0000 }, /* R3891 - ANC Coefficient */ + { 0x00000F34, 0x0000 }, /* R3892 - ANC Coefficient */ + { 0x00000F35, 0x0000 }, /* R3893 - ANC Coefficient */ + { 0x00000F36, 0x0000 }, /* R3894 - ANC Coefficient */ + { 0x00000F37, 0x0000 }, /* R3895 - ANC Coefficient */ + { 0x00000F38, 0x0000 }, /* R3896 - ANC Coefficient */ + { 0x00000F39, 0x0000 }, /* R3897 - ANC Coefficient */ + { 0x00000F3A, 0x0000 }, /* R3898 - ANC Coefficient */ + { 0x00000F3B, 0x0000 }, /* R3899 - ANC Coefficient */ + { 0x00000F3C, 0x0000 }, /* R3900 - ANC Coefficient */ + { 0x00000F3D, 0x0000 }, /* R3901 - ANC Coefficient */ + { 0x00000F3E, 0x0000 }, /* R3902 - ANC Coefficient */ + { 0x00000F3F, 0x0000 }, /* R3903 - ANC Coefficient */ + { 0x00000F40, 0x0000 }, /* R3904 - ANC Coefficient */ + { 0x00000F41, 0x0000 }, /* R3905 - ANC Coefficient */ + { 0x00000F42, 0x0000 }, /* R3906 - ANC Coefficient */ + { 0x00000F43, 0x0000 }, /* R3907 - ANC Coefficient */ + { 0x00000F44, 0x0000 }, /* R3908 - ANC Coefficient */ + { 0x00000F45, 0x0000 }, /* R3909 - ANC Coefficient */ + { 0x00000F46, 0x0000 }, /* R3910 - ANC Coefficient */ + { 0x00000F47, 0x0000 }, /* R3911 - ANC Coefficient */ + { 0x00000F48, 0x0000 }, /* R3912 - ANC Coefficient */ + { 0x00000F49, 0x0000 }, /* R3913 - ANC Coefficient */ + { 0x00000F4A, 0x0000 }, /* R3914 - ANC Coefficient */ + { 0x00000F4B, 0x0000 }, /* R3915 - ANC Coefficient */ + { 0x00000F4C, 0x0000 }, /* R3916 - ANC Coefficient */ + { 0x00000F4D, 0x0000 }, /* R3917 - ANC Coefficient */ + { 0x00000F4E, 0x0000 }, /* R3918 - ANC Coefficient */ + { 0x00000F4F, 0x0000 }, /* R3919 - ANC Coefficient */ + { 0x00000F50, 0x0000 }, /* R3920 - ANC Coefficient */ + { 0x00000F51, 0x0000 }, /* R3921 - ANC Coefficient */ + { 0x00000F52, 0x0000 }, /* R3922 - ANC Coefficient */ + { 0x00000F53, 0x0000 }, /* R3923 - ANC Coefficient */ + { 0x00000F54, 0x0000 }, /* R3924 - ANC Coefficient */ + { 0x00000F55, 0x0000 }, /* R3925 - ANC Coefficient */ + { 0x00000F56, 0x0000 }, /* R3926 - ANC Coefficient */ + { 0x00000F57, 0x0000 }, /* R3927 - ANC Coefficient */ + { 0x00000F58, 0x0000 }, /* R3928 - ANC Coefficient */ + { 0x00000F59, 0x0000 }, /* R3929 - ANC Coefficient */ + { 0x00000F5A, 0x0000 }, /* R3930 - ANC Coefficient */ + { 0x00000F5B, 0x0000 }, /* R3931 - ANC Coefficient */ + { 0x00000F5C, 0x0000 }, /* R3932 - ANC Coefficient */ + { 0x00000F5D, 0x0000 }, /* R3933 - ANC Coefficient */ + { 0x00000F5E, 0x0000 }, /* R3934 - ANC Coefficient */ + { 0x00000F5F, 0x0000 }, /* R3935 - ANC Coefficient */ + { 0x00000F60, 0x0000 }, /* R3936 - ANC Coefficient */ + { 0x00000F61, 0x0000 }, /* R3937 - ANC Coefficient */ + { 0x00000F62, 0x0000 }, /* R3938 - ANC Coefficient */ + { 0x00000F63, 0x0000 }, /* R3939 - ANC Coefficient */ + { 0x00000F64, 0x0000 }, /* R3940 - ANC Coefficient */ + { 0x00000F65, 0x0000 }, /* R3941 - ANC Coefficient */ + { 0x00000F66, 0x0000 }, /* R3942 - ANC Coefficient */ + { 0x00000F67, 0x0000 }, /* R3943 - ANC Coefficient */ + { 0x00000F68, 0x0000 }, /* R3944 - ANC Coefficient */ + { 0x00000F69, 0x0000 }, /* R3945 - ANC Coefficient */ + { 0x00000F70, 0x0000 }, /* R3952 - FCR Filter Control */ + { 0x00000F72, 0x0004 }, /* R3954 - FCR ADC Reformatter Control */ + { 0x00000F73, 0x0004 }, /* R3955 - ANC Coefficient */ + { 0x00000F74, 0x0002 }, /* R3956 - ANC Coefficient */ + { 0x00000F75, 0x0000 }, /* R3957 - ANC Coefficient */ + { 0x00000F76, 0x0010 }, /* R3958 - ANC Coefficient */ + { 0x00000F77, 0x0000 }, /* R3959 - ANC Coefficient */ + { 0x00000F78, 0x0000 }, /* R3960 - ANC Coefficient */ + { 0x00000F79, 0x0000 }, /* R3961 - ANC Coefficient */ + { 0x00000F7A, 0x0000 }, /* R3962 - ANC Coefficient */ + { 0x00000F7B, 0x0000 }, /* R3963 - ANC Coefficient */ + { 0x00000F7C, 0x0000 }, /* R3964 - ANC Coefficient */ + { 0x00000F7D, 0x0000 }, /* R3965 - ANC Coefficient */ + { 0x00000F7E, 0x0000 }, /* R3966 - ANC Coefficient */ + { 0x00000F7F, 0x0000 }, /* R3967 - ANC Coefficient */ + { 0x00000F80, 0x0000 }, /* R3968 - ANC Coefficient */ + { 0x00000F81, 0x0000 }, /* R3969 - ANC Coefficient */ + { 0x00000F82, 0x0000 }, /* R3970 - ANC Coefficient */ + { 0x00000F83, 0x0000 }, /* R3971 - ANC Coefficient */ + { 0x00000F84, 0x0000 }, /* R3972 - ANC Coefficient */ + { 0x00000F85, 0x0000 }, /* R3973 - ANC Coefficient */ + { 0x00000F86, 0x0000 }, /* R3974 - ANC Coefficient */ + { 0x00000F87, 0x0000 }, /* R3975 - ANC Coefficient */ + { 0x00000F88, 0x0000 }, /* R3976 - ANC Coefficient */ + { 0x00000F89, 0x0000 }, /* R3977 - ANC Coefficient */ + { 0x00000F8A, 0x0000 }, /* R3978 - ANC Coefficient */ + { 0x00000F8B, 0x0000 }, /* R3979 - ANC Coefficient */ + { 0x00000F8C, 0x0000 }, /* R3980 - ANC Coefficient */ + { 0x00000F8D, 0x0000 }, /* R3981 - ANC Coefficient */ + { 0x00000F8E, 0x0000 }, /* R3982 - ANC Coefficient */ + { 0x00000F8F, 0x0000 }, /* R3983 - ANC Coefficient */ + { 0x00000F90, 0x0000 }, /* R3984 - ANC Coefficient */ + { 0x00000F91, 0x0000 }, /* R3985 - ANC Coefficient */ + { 0x00000F92, 0x0000 }, /* R3986 - ANC Coefficient */ + { 0x00000F93, 0x0000 }, /* R3987 - ANC Coefficient */ + { 0x00000F94, 0x0000 }, /* R3988 - ANC Coefficient */ + { 0x00000F95, 0x0000 }, /* R3989 - ANC Coefficient */ + { 0x00000F96, 0x0000 }, /* R3990 - ANC Coefficient */ + { 0x00000F97, 0x0000 }, /* R3991 - ANC Coefficient */ + { 0x00000F98, 0x0000 }, /* R3992 - ANC Coefficient */ + { 0x00000F99, 0x0000 }, /* R3993 - ANC Coefficient */ + { 0x00000F9A, 0x0000 }, /* R3994 - ANC Coefficient */ + { 0x00000F9B, 0x0000 }, /* R3995 - ANC Coefficient */ + { 0x00000F9C, 0x0000 }, /* R3996 - ANC Coefficient */ + { 0x00000F9D, 0x0000 }, /* R3997 - ANC Coefficient */ + { 0x00000F9E, 0x0000 }, /* R3998 - ANC Coefficient */ + { 0x00000F9F, 0x0000 }, /* R3999 - ANC Coefficient */ + { 0x00000FA0, 0x0000 }, /* R4000 - ANC Coefficient */ + { 0x00000FA1, 0x0000 }, /* R4001 - ANC Coefficient */ + { 0x00000FA2, 0x0000 }, /* R4002 - ANC Coefficient */ + { 0x00000FA3, 0x0000 }, /* R4003 - ANC Coefficient */ + { 0x00000FA4, 0x0000 }, /* R4004 - ANC Coefficient */ + { 0x00000FA5, 0x0000 }, /* R4005 - ANC Coefficient */ + { 0x00000FA6, 0x0000 }, /* R4006 - ANC Coefficient */ + { 0x00000FA7, 0x0000 }, /* R4007 - ANC Coefficient */ + { 0x00000FA8, 0x0000 }, /* R4008 - ANC Coefficient */ + { 0x00000FA9, 0x0000 }, /* R4009 - ANC Coefficient */ + { 0x00000FAA, 0x0000 }, /* R4010 - ANC Coefficient */ + { 0x00000FAB, 0x0000 }, /* R4011 - ANC Coefficient */ + { 0x00000FAC, 0x0000 }, /* R4012 - ANC Coefficient */ + { 0x00000FAD, 0x0000 }, /* R4013 - ANC Coefficient */ + { 0x00000FAE, 0x0000 }, /* R4014 - ANC Coefficient */ + { 0x00000FAF, 0x0000 }, /* R4015 - ANC Coefficient */ + { 0x00000FB0, 0x0000 }, /* R4016 - ANC Coefficient */ + { 0x00000FB1, 0x0000 }, /* R4017 - ANC Coefficient */ + { 0x00000FB2, 0x0000 }, /* R4018 - ANC Coefficient */ + { 0x00000FB3, 0x0000 }, /* R4019 - ANC Coefficient */ + { 0x00000FB4, 0x0000 }, /* R4020 - ANC Coefficient */ + { 0x00000FB5, 0x0000 }, /* R4021 - ANC Coefficient */ + { 0x00000FB6, 0x0000 }, /* R4022 - ANC Coefficient */ + { 0x00000FB7, 0x0000 }, /* R4023 - ANC Coefficient */ + { 0x00000FB8, 0x0000 }, /* R4024 - ANC Coefficient */ + { 0x00000FB9, 0x0000 }, /* R4025 - ANC Coefficient */ + { 0x00000FBA, 0x0000 }, /* R4026 - ANC Coefficient */ + { 0x00000FBB, 0x0000 }, /* R4027 - ANC Coefficient */ + { 0x00000FBC, 0x0000 }, /* R4028 - ANC Coefficient */ + { 0x00000FBD, 0x0000 }, /* R4029 - ANC Coefficient */ + { 0x00000FBE, 0x0000 }, /* R4030 - ANC Coefficient */ + { 0x00000FBF, 0x0000 }, /* R4031 - ANC Coefficient */ + { 0x00000FC0, 0x0000 }, /* R4032 - ANC Coefficient */ + { 0x00000FC1, 0x0000 }, /* R4033 - ANC Coefficient */ + { 0x00000FC2, 0x0000 }, /* R4034 - ANC Coefficient */ + { 0x00000FC3, 0x0000 }, /* R4035 - ANC Coefficient */ + { 0x00000FC4, 0x0000 }, /* R4036 - ANC Coefficient */ { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */ - { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */ { 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */ - { 0x00001201, 0x0000 }, /* R4609 - DSP2 Clocking 1 */ { 0x00001300, 0x0010 }, /* R4864 - DSP3 Control 1 */ - { 0x00001301, 0x0000 }, /* R4865 - DSP3 Clocking 1 */ { 0x00001400, 0x0010 }, /* R5120 - DSP4 Control 1 */ - { 0x00001401, 0x0000 }, /* R5121 - DSP4 Clocking 1 */ - { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */ }; -static bool wm5110_readable_register(struct device *dev, unsigned int reg) +static bool florida_is_rev_b_adsp_memory(unsigned int reg) +{ + if ((reg >= 0x100000 && reg < 0x103000) || + (reg >= 0x180000 && reg < 0x181000) || + (reg >= 0x190000 && reg < 0x192000) || + (reg >= 0x1a8000 && reg < 0x1a9000) || + (reg >= 0x200000 && reg < 0x209000) || + (reg >= 0x280000 && reg < 0x281000) || + (reg >= 0x290000 && reg < 0x29a000) || + (reg >= 0x2a8000 && reg < 0x2aa000) || + (reg >= 0x300000 && reg < 0x30f000) || + (reg >= 0x380000 && reg < 0x382000) || + (reg >= 0x390000 && reg < 0x39e000) || + (reg >= 0x3a8000 && reg < 0x3b6000) || + (reg >= 0x400000 && reg < 0x403000) || + (reg >= 0x480000 && reg < 0x481000) || + (reg >= 0x490000 && reg < 0x492000) || + (reg >= 0x4a8000 && reg < 0x4a9000)) + return true; + else + return false; +} + +static bool florida_is_rev_d_adsp_memory(unsigned int reg) +{ + if ((reg >= 0x100000 && reg < 0x106000) || + (reg >= 0x180000 && reg < 0x182000) || + (reg >= 0x190000 && reg < 0x198000) || + (reg >= 0x1a8000 && reg < 0x1aa000) || + (reg >= 0x200000 && reg < 0x20f000) || + (reg >= 0x280000 && reg < 0x282000) || + (reg >= 0x290000 && reg < 0x29c000) || + (reg >= 0x2a6000 && reg < 0x2b4000) || + (reg >= 0x300000 && reg < 0x30f000) || + (reg >= 0x380000 && reg < 0x382000) || + (reg >= 0x390000 && reg < 0x3a2000) || + (reg >= 0x3a6000 && reg < 0x3b4000) || + (reg >= 0x400000 && reg < 0x406000) || + (reg >= 0x480000 && reg < 0x482000) || + (reg >= 0x490000 && reg < 0x498000) || + (reg >= 0x4a8000 && reg < 0x4aa000)) + return true; + else + return false; +} + +static bool florida_is_adsp_memory(struct device *dev, unsigned int reg) +{ + struct arizona *arizona = dev_get_drvdata(dev); + + switch (arizona->rev) { + case 0 ... 2: + return florida_is_rev_b_adsp_memory(reg); + default: + return florida_is_rev_d_adsp_memory(reg); + } +} + +static bool florida_readable_register(struct device *dev, unsigned int reg) { switch (reg) { case ARIZONA_SOFTWARE_RESET: @@ -1350,6 +1927,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_PWM_DRIVE_3: case ARIZONA_WAKE_CONTROL: case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SPARE_TRIGGERS: case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: @@ -1358,7 +1936,11 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: case ARIZONA_COMFORT_NOISE_GENERATOR: + case ARIZONA_HP_DETECT_CALIBRATION_1: + case ARIZONA_HP_DETECT_CALIBRATION_2: case ARIZONA_HAPTICS_CONTROL_1: case ARIZONA_HAPTICS_CONTROL_2: case ARIZONA_HAPTICS_PHASE_1_INTENSITY: @@ -1379,6 +1961,8 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_ASYNC_CLOCK_1: case ARIZONA_ASYNC_SAMPLE_RATE_1: case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: case ARIZONA_OUTPUT_SYSTEM_CLOCK: case ARIZONA_OUTPUT_ASYNC_CLOCK: case ARIZONA_RATE_ESTIMATOR_1: @@ -1392,14 +1976,14 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_FLL1_CONTROL_4: case ARIZONA_FLL1_CONTROL_5: case ARIZONA_FLL1_CONTROL_6: - case ARIZONA_FLL1_LOOP_FILTER_TEST_1: - case ARIZONA_FLL1_NCO_TEST_0: + case ARIZONA_FLL1_CONTROL_7: case ARIZONA_FLL1_SYNCHRONISER_1: case ARIZONA_FLL1_SYNCHRONISER_2: case ARIZONA_FLL1_SYNCHRONISER_3: case ARIZONA_FLL1_SYNCHRONISER_4: case ARIZONA_FLL1_SYNCHRONISER_5: case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SYNCHRONISER_7: case ARIZONA_FLL1_SPREAD_SPECTRUM: case ARIZONA_FLL1_GPIO_CLOCK: case ARIZONA_FLL2_CONTROL_1: @@ -1408,14 +1992,14 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_FLL2_CONTROL_4: case ARIZONA_FLL2_CONTROL_5: case ARIZONA_FLL2_CONTROL_6: - case ARIZONA_FLL2_LOOP_FILTER_TEST_1: - case ARIZONA_FLL2_NCO_TEST_0: + case ARIZONA_FLL2_CONTROL_7: case ARIZONA_FLL2_SYNCHRONISER_1: case ARIZONA_FLL2_SYNCHRONISER_2: case ARIZONA_FLL2_SYNCHRONISER_3: case ARIZONA_FLL2_SYNCHRONISER_4: case ARIZONA_FLL2_SYNCHRONISER_5: case ARIZONA_FLL2_SYNCHRONISER_6: + case ARIZONA_FLL2_SYNCHRONISER_7: case ARIZONA_FLL2_SPREAD_SPECTRUM: case ARIZONA_FLL2_GPIO_CLOCK: case ARIZONA_MIC_CHARGE_PUMP_1: @@ -1424,18 +2008,33 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_MIC_BIAS_CTRL_1: case ARIZONA_MIC_BIAS_CTRL_2: case ARIZONA_MIC_BIAS_CTRL_3: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HP_CTRL_2L: + case ARIZONA_HP_CTRL_2R: + case ARIZONA_HP_CTRL_3L: + case ARIZONA_HP_CTRL_3R: case ARIZONA_ACCESSORY_DETECT_MODE_1: case ARIZONA_HEADPHONE_DETECT_1: case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_MICD_CLAMP_CONTROL: case ARIZONA_MIC_DETECT_1: case ARIZONA_MIC_DETECT_2: case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_MIC_DETECT_LEVEL_1: + case ARIZONA_MIC_DETECT_LEVEL_2: + case ARIZONA_MIC_DETECT_LEVEL_3: + case ARIZONA_MIC_DETECT_LEVEL_4: case ARIZONA_MIC_NOISE_MIX_CONTROL_1: + case ARIZONA_ISOLATION_CONTROL: case ARIZONA_JACK_DETECT_ANALOGUE: case ARIZONA_INPUT_ENABLES: case ARIZONA_INPUT_ENABLES_STATUS: case ARIZONA_INPUT_RATE: case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: case ARIZONA_IN1L_CONTROL: case ARIZONA_ADC_DIGITAL_VOLUME_1L: case ARIZONA_DMIC1L_CONTROL: @@ -1457,8 +2056,15 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_IN4L_CONTROL: case ARIZONA_ADC_DIGITAL_VOLUME_4L: case ARIZONA_DMIC4L_CONTROL: + case ARIZONA_IN4R_CONTROL: case ARIZONA_ADC_DIGITAL_VOLUME_4R: case ARIZONA_DMIC4R_CONTROL: + case ARIZONA_ADC_VCO_CAL_4: + case ARIZONA_ADC_VCO_CAL_5: + case ARIZONA_ADC_VCO_CAL_6: + case ARIZONA_ADC_VCO_CAL_7: + case ARIZONA_ADC_VCO_CAL_8: + case ARIZONA_ADC_VCO_CAL_9: case ARIZONA_OUTPUT_ENABLES_1: case ARIZONA_OUTPUT_STATUS_1: case ARIZONA_RAW_OUTPUT_STATUS_1: @@ -1512,12 +2118,18 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DAC_DIGITAL_VOLUME_6R: case ARIZONA_DAC_VOLUME_LIMIT_6R: case ARIZONA_NOISE_GATE_SELECT_6R: + case ARIZONA_DRE_ENABLE: case ARIZONA_DAC_AEC_CONTROL_1: case ARIZONA_NOISE_GATE_CONTROL: case ARIZONA_PDM_SPK1_CTRL_1: case ARIZONA_PDM_SPK1_CTRL_2: case ARIZONA_PDM_SPK2_CTRL_1: case ARIZONA_PDM_SPK2_CTRL_2: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP2_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP3_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP_TEST_CTRL_1: + case ARIZONA_SPK_CTRL_5: case ARIZONA_AIF1_BCLK_CTRL: case ARIZONA_AIF1_TX_PIN_CTRL: case ARIZONA_AIF1_RX_PIN_CTRL: @@ -1556,8 +2168,16 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_AIF2_FRAME_CTRL_2: case ARIZONA_AIF2_FRAME_CTRL_3: case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_5: + case ARIZONA_AIF2_FRAME_CTRL_6: + case ARIZONA_AIF2_FRAME_CTRL_7: + case ARIZONA_AIF2_FRAME_CTRL_8: case ARIZONA_AIF2_FRAME_CTRL_11: case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_FRAME_CTRL_13: + case ARIZONA_AIF2_FRAME_CTRL_14: + case ARIZONA_AIF2_FRAME_CTRL_15: + case ARIZONA_AIF2_FRAME_CTRL_16: case ARIZONA_AIF2_TX_ENABLES: case ARIZONA_AIF2_RX_ENABLES: case ARIZONA_AIF3_BCLK_CTRL: @@ -1796,6 +2416,38 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME: case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: @@ -2095,6 +2747,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_GPIO5_CTRL: case ARIZONA_IRQ_CTRL_1: case ARIZONA_GPIO_DEBOUNCE_CONFIG: + case ARIZONA_GP_SWITCH_1: case ARIZONA_MISC_PAD_CTRL_1: case ARIZONA_MISC_PAD_CTRL_2: case ARIZONA_MISC_PAD_CTRL_3: @@ -2118,22 +2771,26 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_INTERRUPT_STATUS_3: case ARIZONA_INTERRUPT_STATUS_4: case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_INTERRUPT_STATUS_6: case ARIZONA_INTERRUPT_STATUS_1_MASK: case ARIZONA_INTERRUPT_STATUS_2_MASK: case ARIZONA_INTERRUPT_STATUS_3_MASK: case ARIZONA_INTERRUPT_STATUS_4_MASK: case ARIZONA_INTERRUPT_STATUS_5_MASK: + case ARIZONA_INTERRUPT_STATUS_6_MASK: case ARIZONA_INTERRUPT_CONTROL: case ARIZONA_IRQ2_STATUS_1: case ARIZONA_IRQ2_STATUS_2: case ARIZONA_IRQ2_STATUS_3: case ARIZONA_IRQ2_STATUS_4: case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_IRQ2_STATUS_6: case ARIZONA_IRQ2_STATUS_1_MASK: case ARIZONA_IRQ2_STATUS_2_MASK: case ARIZONA_IRQ2_STATUS_3_MASK: case ARIZONA_IRQ2_STATUS_4_MASK: case ARIZONA_IRQ2_STATUS_5_MASK: + case ARIZONA_IRQ2_STATUS_6_MASK: case ARIZONA_IRQ2_CONTROL: case ARIZONA_INTERRUPT_RAW_STATUS_2: case ARIZONA_INTERRUPT_RAW_STATUS_3: @@ -2142,6 +2799,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_INTERRUPT_RAW_STATUS_6: case ARIZONA_INTERRUPT_RAW_STATUS_7: case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_INTERRUPT_RAW_STATUS_9: case ARIZONA_IRQ_PIN_STATUS: case ARIZONA_AOD_WKUP_AND_TRIG: case ARIZONA_AOD_IRQ1: @@ -2257,6 +2915,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_ASRC_ENABLE: case ARIZONA_ASRC_STATUS: case ARIZONA_ASRC_RATE1: + case ARIZONA_ASRC_RATE2: case ARIZONA_ISRC_1_CTRL_1: case ARIZONA_ISRC_1_CTRL_2: case ARIZONA_ISRC_1_CTRL_3: @@ -2269,43 +2928,177 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg) case ARIZONA_CLOCK_CONTROL: case ARIZONA_ANC_SRC: case ARIZONA_DSP_STATUS: + case ARIZONA_ANC_COEFF_START ... ARIZONA_ANC_COEFF_END: + case ARIZONA_FCL_FILTER_CONTROL: + case ARIZONA_FCL_ADC_REFORMATTER_CONTROL: + case ARIZONA_FCL_COEFF_START ... ARIZONA_FCL_COEFF_END: + case ARIZONA_FCR_FILTER_CONTROL: + case ARIZONA_FCR_ADC_REFORMATTER_CONTROL: + case ARIZONA_FCR_COEFF_START ... ARIZONA_FCR_COEFF_END: case ARIZONA_DSP1_CONTROL_1: case ARIZONA_DSP1_CLOCKING_1: case ARIZONA_DSP1_STATUS_1: case ARIZONA_DSP1_STATUS_2: + case ARIZONA_DSP1_STATUS_3: + case ARIZONA_DSP1_STATUS_4: + case ARIZONA_DSP1_WDMA_BUFFER_1: + case ARIZONA_DSP1_WDMA_BUFFER_2: + case ARIZONA_DSP1_WDMA_BUFFER_3: + case ARIZONA_DSP1_WDMA_BUFFER_4: + case ARIZONA_DSP1_WDMA_BUFFER_5: + case ARIZONA_DSP1_WDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_BUFFER_7: + case ARIZONA_DSP1_WDMA_BUFFER_8: + case ARIZONA_DSP1_RDMA_BUFFER_1: + case ARIZONA_DSP1_RDMA_BUFFER_2: + case ARIZONA_DSP1_RDMA_BUFFER_3: + case ARIZONA_DSP1_RDMA_BUFFER_4: + case ARIZONA_DSP1_RDMA_BUFFER_5: + case ARIZONA_DSP1_RDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_CONFIG_1: + case ARIZONA_DSP1_WDMA_CONFIG_2: + case ARIZONA_DSP1_WDMA_OFFSET_1: + case ARIZONA_DSP1_RDMA_CONFIG_1: + case ARIZONA_DSP1_RDMA_OFFSET_1: + case ARIZONA_DSP1_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP1_SCRATCH_0: + case ARIZONA_DSP1_SCRATCH_1: + case ARIZONA_DSP1_SCRATCH_2: + case ARIZONA_DSP1_SCRATCH_3: case ARIZONA_DSP2_CONTROL_1: case ARIZONA_DSP2_CLOCKING_1: case ARIZONA_DSP2_STATUS_1: case ARIZONA_DSP2_STATUS_2: + case ARIZONA_DSP2_STATUS_3: + case ARIZONA_DSP2_STATUS_4: + case ARIZONA_DSP2_WDMA_BUFFER_1: + case ARIZONA_DSP2_WDMA_BUFFER_2: + case ARIZONA_DSP2_WDMA_BUFFER_3: + case ARIZONA_DSP2_WDMA_BUFFER_4: + case ARIZONA_DSP2_WDMA_BUFFER_5: + case ARIZONA_DSP2_WDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_BUFFER_7: + case ARIZONA_DSP2_WDMA_BUFFER_8: + case ARIZONA_DSP2_RDMA_BUFFER_1: + case ARIZONA_DSP2_RDMA_BUFFER_2: + case ARIZONA_DSP2_RDMA_BUFFER_3: + case ARIZONA_DSP2_RDMA_BUFFER_4: + case ARIZONA_DSP2_RDMA_BUFFER_5: + case ARIZONA_DSP2_RDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_CONFIG_1: + case ARIZONA_DSP2_WDMA_CONFIG_2: + case ARIZONA_DSP2_WDMA_OFFSET_1: + case ARIZONA_DSP2_RDMA_CONFIG_1: + case ARIZONA_DSP2_RDMA_OFFSET_1: + case ARIZONA_DSP2_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP2_SCRATCH_0: + case ARIZONA_DSP2_SCRATCH_1: + case ARIZONA_DSP2_SCRATCH_2: + case ARIZONA_DSP2_SCRATCH_3: case ARIZONA_DSP3_CONTROL_1: case ARIZONA_DSP3_CLOCKING_1: case ARIZONA_DSP3_STATUS_1: case ARIZONA_DSP3_STATUS_2: + case ARIZONA_DSP3_STATUS_3: + case ARIZONA_DSP3_STATUS_4: + case ARIZONA_DSP3_WDMA_BUFFER_1: + case ARIZONA_DSP3_WDMA_BUFFER_2: + case ARIZONA_DSP3_WDMA_BUFFER_3: + case ARIZONA_DSP3_WDMA_BUFFER_4: + case ARIZONA_DSP3_WDMA_BUFFER_5: + case ARIZONA_DSP3_WDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_BUFFER_7: + case ARIZONA_DSP3_WDMA_BUFFER_8: + case ARIZONA_DSP3_RDMA_BUFFER_1: + case ARIZONA_DSP3_RDMA_BUFFER_2: + case ARIZONA_DSP3_RDMA_BUFFER_3: + case ARIZONA_DSP3_RDMA_BUFFER_4: + case ARIZONA_DSP3_RDMA_BUFFER_5: + case ARIZONA_DSP3_RDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_CONFIG_1: + case ARIZONA_DSP3_WDMA_CONFIG_2: + case ARIZONA_DSP3_WDMA_OFFSET_1: + case ARIZONA_DSP3_RDMA_CONFIG_1: + case ARIZONA_DSP3_RDMA_OFFSET_1: + case ARIZONA_DSP3_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP3_SCRATCH_0: + case ARIZONA_DSP3_SCRATCH_1: + case ARIZONA_DSP3_SCRATCH_2: + case ARIZONA_DSP3_SCRATCH_3: case ARIZONA_DSP4_CONTROL_1: case ARIZONA_DSP4_CLOCKING_1: case ARIZONA_DSP4_STATUS_1: case ARIZONA_DSP4_STATUS_2: + case ARIZONA_DSP4_STATUS_3: + case ARIZONA_DSP4_STATUS_4: + case ARIZONA_DSP4_WDMA_BUFFER_1: + case ARIZONA_DSP4_WDMA_BUFFER_2: + case ARIZONA_DSP4_WDMA_BUFFER_3: + case ARIZONA_DSP4_WDMA_BUFFER_4: + case ARIZONA_DSP4_WDMA_BUFFER_5: + case ARIZONA_DSP4_WDMA_BUFFER_6: + case ARIZONA_DSP4_WDMA_BUFFER_7: + case ARIZONA_DSP4_WDMA_BUFFER_8: + case ARIZONA_DSP4_RDMA_BUFFER_1: + case ARIZONA_DSP4_RDMA_BUFFER_2: + case ARIZONA_DSP4_RDMA_BUFFER_3: + case ARIZONA_DSP4_RDMA_BUFFER_4: + case ARIZONA_DSP4_RDMA_BUFFER_5: + case ARIZONA_DSP4_RDMA_BUFFER_6: + case ARIZONA_DSP4_WDMA_CONFIG_1: + case ARIZONA_DSP4_WDMA_CONFIG_2: + case ARIZONA_DSP4_WDMA_OFFSET_1: + case ARIZONA_DSP4_RDMA_CONFIG_1: + case ARIZONA_DSP4_RDMA_OFFSET_1: + case ARIZONA_DSP4_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP4_SCRATCH_0: + case ARIZONA_DSP4_SCRATCH_1: + case ARIZONA_DSP4_SCRATCH_2: + case ARIZONA_DSP4_SCRATCH_3: + case 0x460 ... 0x47E: + case 0x483: return true; default: - return false; + return florida_is_adsp_memory(dev, reg); } } -static bool wm5110_volatile_register(struct device *dev, unsigned int reg) +static bool florida_volatile_register(struct device *dev, unsigned int reg) { switch (reg) { case ARIZONA_SOFTWARE_RESET: case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HP_DETECT_CALIBRATION_1: + case ARIZONA_HP_DETECT_CALIBRATION_2: case ARIZONA_HAPTICS_STATUS: case ARIZONA_SAMPLE_RATE_1_STATUS: case ARIZONA_SAMPLE_RATE_2_STATUS: case ARIZONA_SAMPLE_RATE_3_STATUS: case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HP_CTRL_2L: + case ARIZONA_HP_CTRL_2R: + case ARIZONA_HP_CTRL_3L: + case ARIZONA_HP_CTRL_3R: case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: case ARIZONA_INPUT_ENABLES_STATUS: case ARIZONA_OUTPUT_STATUS_1: case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_ADC_VCO_CAL_4: + case ARIZONA_ADC_VCO_CAL_5: + case ARIZONA_ADC_VCO_CAL_6: + case ARIZONA_ADC_VCO_CAL_7: + case ARIZONA_ADC_VCO_CAL_8: + case ARIZONA_ADC_VCO_CAL_9: + case ARIZONA_HP_TEST_CTRL_1: case ARIZONA_SLIMBUS_RX_PORT_STATUS: case ARIZONA_SLIMBUS_TX_PORT_STATUS: case ARIZONA_INTERRUPT_STATUS_1: @@ -2313,11 +3106,13 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg) case ARIZONA_INTERRUPT_STATUS_3: case ARIZONA_INTERRUPT_STATUS_4: case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_INTERRUPT_STATUS_6: case ARIZONA_IRQ2_STATUS_1: case ARIZONA_IRQ2_STATUS_2: case ARIZONA_IRQ2_STATUS_3: case ARIZONA_IRQ2_STATUS_4: case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_IRQ2_STATUS_6: case ARIZONA_INTERRUPT_RAW_STATUS_2: case ARIZONA_INTERRUPT_RAW_STATUS_3: case ARIZONA_INTERRUPT_RAW_STATUS_4: @@ -2325,52 +3120,165 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg) case ARIZONA_INTERRUPT_RAW_STATUS_6: case ARIZONA_INTERRUPT_RAW_STATUS_7: case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_INTERRUPT_RAW_STATUS_9: case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_AOD_WKUP_AND_TRIG: case ARIZONA_AOD_IRQ1: case ARIZONA_AOD_IRQ2: + case ARIZONA_AOD_IRQ_RAW_STATUS: + case ARIZONA_FX_CTRL2: case ARIZONA_ASRC_STATUS: + case ARIZONA_CLOCK_CONTROL: case ARIZONA_DSP_STATUS: - case ARIZONA_DSP1_CONTROL_1: - case ARIZONA_DSP1_CLOCKING_1: case ARIZONA_DSP1_STATUS_1: case ARIZONA_DSP1_STATUS_2: + case ARIZONA_DSP1_STATUS_3: + case ARIZONA_DSP1_STATUS_4: + case ARIZONA_DSP1_WDMA_BUFFER_1: + case ARIZONA_DSP1_WDMA_BUFFER_2: + case ARIZONA_DSP1_WDMA_BUFFER_3: + case ARIZONA_DSP1_WDMA_BUFFER_4: + case ARIZONA_DSP1_WDMA_BUFFER_5: + case ARIZONA_DSP1_WDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_BUFFER_7: + case ARIZONA_DSP1_WDMA_BUFFER_8: + case ARIZONA_DSP1_RDMA_BUFFER_1: + case ARIZONA_DSP1_RDMA_BUFFER_2: + case ARIZONA_DSP1_RDMA_BUFFER_3: + case ARIZONA_DSP1_RDMA_BUFFER_4: + case ARIZONA_DSP1_RDMA_BUFFER_5: + case ARIZONA_DSP1_RDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_CONFIG_1: + case ARIZONA_DSP1_WDMA_CONFIG_2: + case ARIZONA_DSP1_WDMA_OFFSET_1: + case ARIZONA_DSP1_RDMA_CONFIG_1: + case ARIZONA_DSP1_RDMA_OFFSET_1: + case ARIZONA_DSP1_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP1_SCRATCH_0: + case ARIZONA_DSP1_SCRATCH_1: + case ARIZONA_DSP1_SCRATCH_2: + case ARIZONA_DSP1_SCRATCH_3: + case ARIZONA_DSP1_CLOCKING_1: case ARIZONA_DSP2_STATUS_1: case ARIZONA_DSP2_STATUS_2: + case ARIZONA_DSP2_STATUS_3: + case ARIZONA_DSP2_STATUS_4: + case ARIZONA_DSP2_WDMA_BUFFER_1: + case ARIZONA_DSP2_WDMA_BUFFER_2: + case ARIZONA_DSP2_WDMA_BUFFER_3: + case ARIZONA_DSP2_WDMA_BUFFER_4: + case ARIZONA_DSP2_WDMA_BUFFER_5: + case ARIZONA_DSP2_WDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_BUFFER_7: + case ARIZONA_DSP2_WDMA_BUFFER_8: + case ARIZONA_DSP2_RDMA_BUFFER_1: + case ARIZONA_DSP2_RDMA_BUFFER_2: + case ARIZONA_DSP2_RDMA_BUFFER_3: + case ARIZONA_DSP2_RDMA_BUFFER_4: + case ARIZONA_DSP2_RDMA_BUFFER_5: + case ARIZONA_DSP2_RDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_CONFIG_1: + case ARIZONA_DSP2_WDMA_CONFIG_2: + case ARIZONA_DSP2_WDMA_OFFSET_1: + case ARIZONA_DSP2_RDMA_CONFIG_1: + case ARIZONA_DSP2_RDMA_OFFSET_1: + case ARIZONA_DSP2_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP2_SCRATCH_0: + case ARIZONA_DSP2_SCRATCH_1: + case ARIZONA_DSP2_SCRATCH_2: + case ARIZONA_DSP2_SCRATCH_3: + case ARIZONA_DSP2_CLOCKING_1: case ARIZONA_DSP3_STATUS_1: case ARIZONA_DSP3_STATUS_2: + case ARIZONA_DSP3_STATUS_3: + case ARIZONA_DSP3_STATUS_4: + case ARIZONA_DSP3_WDMA_BUFFER_1: + case ARIZONA_DSP3_WDMA_BUFFER_2: + case ARIZONA_DSP3_WDMA_BUFFER_3: + case ARIZONA_DSP3_WDMA_BUFFER_4: + case ARIZONA_DSP3_WDMA_BUFFER_5: + case ARIZONA_DSP3_WDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_BUFFER_7: + case ARIZONA_DSP3_WDMA_BUFFER_8: + case ARIZONA_DSP3_RDMA_BUFFER_1: + case ARIZONA_DSP3_RDMA_BUFFER_2: + case ARIZONA_DSP3_RDMA_BUFFER_3: + case ARIZONA_DSP3_RDMA_BUFFER_4: + case ARIZONA_DSP3_RDMA_BUFFER_5: + case ARIZONA_DSP3_RDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_CONFIG_1: + case ARIZONA_DSP3_WDMA_CONFIG_2: + case ARIZONA_DSP3_WDMA_OFFSET_1: + case ARIZONA_DSP3_RDMA_CONFIG_1: + case ARIZONA_DSP3_RDMA_OFFSET_1: + case ARIZONA_DSP3_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP3_SCRATCH_0: + case ARIZONA_DSP3_SCRATCH_1: + case ARIZONA_DSP3_SCRATCH_2: + case ARIZONA_DSP3_SCRATCH_3: + case ARIZONA_DSP3_CLOCKING_1: case ARIZONA_DSP4_STATUS_1: case ARIZONA_DSP4_STATUS_2: + case ARIZONA_DSP4_STATUS_3: + case ARIZONA_DSP4_STATUS_4: + case ARIZONA_DSP4_WDMA_BUFFER_1: + case ARIZONA_DSP4_WDMA_BUFFER_2: + case ARIZONA_DSP4_WDMA_BUFFER_3: + case ARIZONA_DSP4_WDMA_BUFFER_4: + case ARIZONA_DSP4_WDMA_BUFFER_5: + case ARIZONA_DSP4_WDMA_BUFFER_6: + case ARIZONA_DSP4_WDMA_BUFFER_7: + case ARIZONA_DSP4_WDMA_BUFFER_8: + case ARIZONA_DSP4_RDMA_BUFFER_1: + case ARIZONA_DSP4_RDMA_BUFFER_2: + case ARIZONA_DSP4_RDMA_BUFFER_3: + case ARIZONA_DSP4_RDMA_BUFFER_4: + case ARIZONA_DSP4_RDMA_BUFFER_5: + case ARIZONA_DSP4_RDMA_BUFFER_6: + case ARIZONA_DSP4_WDMA_CONFIG_1: + case ARIZONA_DSP4_WDMA_CONFIG_2: + case ARIZONA_DSP4_WDMA_OFFSET_1: + case ARIZONA_DSP4_RDMA_CONFIG_1: + case ARIZONA_DSP4_RDMA_OFFSET_1: + case ARIZONA_DSP4_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP4_SCRATCH_0: + case ARIZONA_DSP4_SCRATCH_1: + case ARIZONA_DSP4_SCRATCH_2: + case ARIZONA_DSP4_SCRATCH_3: + case ARIZONA_DSP4_CLOCKING_1: return true; default: - return false; + return florida_is_adsp_memory(dev, reg); } } -const struct regmap_config wm5110_spi_regmap = { +#define FLORIDA_MAX_REGISTER 0x4a9fff + +const struct regmap_config florida_spi_regmap = { .reg_bits = 32, .pad_bits = 16, .val_bits = 16, - .max_register = ARIZONA_DSP1_STATUS_2, - .readable_reg = wm5110_readable_register, - .volatile_reg = wm5110_volatile_register, + .max_register = FLORIDA_MAX_REGISTER, + .readable_reg = florida_readable_register, + .volatile_reg = florida_volatile_register, .cache_type = REGCACHE_RBTREE, - .reg_defaults = wm5110_reg_default, - .num_reg_defaults = ARRAY_SIZE(wm5110_reg_default), + .reg_defaults = florida_reg_default, + .num_reg_defaults = ARRAY_SIZE(florida_reg_default), }; -EXPORT_SYMBOL_GPL(wm5110_spi_regmap); +EXPORT_SYMBOL_GPL(florida_spi_regmap); -const struct regmap_config wm5110_i2c_regmap = { +const struct regmap_config florida_i2c_regmap = { .reg_bits = 32, .val_bits = 16, - .max_register = ARIZONA_DSP1_STATUS_2, - .readable_reg = wm5110_readable_register, - .volatile_reg = wm5110_volatile_register, + .max_register = FLORIDA_MAX_REGISTER, + .readable_reg = florida_readable_register, + .volatile_reg = florida_volatile_register, .cache_type = REGCACHE_RBTREE, - .reg_defaults = wm5110_reg_default, - .num_reg_defaults = ARRAY_SIZE(wm5110_reg_default), + .reg_defaults = florida_reg_default, + .num_reg_defaults = ARRAY_SIZE(florida_reg_default), }; -EXPORT_SYMBOL_GPL(wm5110_i2c_regmap); +EXPORT_SYMBOL_GPL(florida_i2c_regmap); diff --git a/drivers/mfd/largo-tables.c b/drivers/mfd/largo-tables.c new file mode 100644 index 00000000000..02a8a7500ca --- /dev/null +++ b/drivers/mfd/largo-tables.c @@ -0,0 +1,1621 @@ +/* + * largo-tables.c -- data tables for Largo codec + * + * Copyright 2014 CirrusLogic, Inc. + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include + +#include "arizona.h" + +#define LARGO_NUM_ISR 5 + +static const struct reg_sequence largo_reva_patch[] = { + { 0x80, 0x3 }, + { 0x27C, 0x0010 }, + { 0x221, 0x0070 }, + { 0x80, 0x0 }, +}; + +/* We use a function so we can use ARRAY_SIZE() */ +int largo_patch(struct arizona *arizona) +{ + return regmap_register_patch(arizona->regmap, + largo_reva_patch, + ARRAY_SIZE(largo_reva_patch)); +} +EXPORT_SYMBOL_GPL(largo_patch); + +static const struct regmap_irq largo_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, + [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, + + [ARIZONA_IRQ_DSP3_RAM_RDY] = { + .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 + }, + [ARIZONA_IRQ_DSP2_RAM_RDY] = { + .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ8] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ7] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ6] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ5] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ4] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ3] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ2] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 + }, + [ARIZONA_IRQ_DSP_IRQ1] = { + .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 + }, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 + }, + [ARIZONA_IRQ_SPK_OVERHEAT] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 + }, + [ARIZONA_IRQ_WSEQ_DONE] = { + .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 + }, + [ARIZONA_IRQ_DRC2_SIG_DET] = { + .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 + }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { + .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 + }, + [ARIZONA_IRQ_ASRC2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 + }, + [ARIZONA_IRQ_ASRC1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 + }, + [ARIZONA_IRQ_UNDERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_OVERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_FLL2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 + }, + [ARIZONA_IRQ_FLL1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 + }, + + [ARIZONA_IRQ_CTRLIF_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1 + }, + [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = { + .reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 + }, + [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_SYSCLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_ISRC1_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_ISRC2_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_ISRC3_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_HP1R_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 + }, + [ARIZONA_IRQ_HP1L_DONE] = { + .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 + }, + + [ARIZONA_IRQ_BOOT_DONE] = { + .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 + }, + [ARIZONA_IRQ_ASRC_CFG_ERR] = { + .reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_FLL2_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 + }, + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 + }, + + [ARIZONA_IRQ_DSP_SHARED_WR_COLL] = { + .reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1 + }, + [ARIZONA_IRQ_SPK_SHUTDOWN] = { + .reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 + }, + [ARIZONA_IRQ_SPK1R_SHORT] = { + .reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1 + }, + [ARIZONA_IRQ_SPK1L_SHORT] = { + .reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1 + }, + [ARIZONA_IRQ_HP1R_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1 + }, + [ARIZONA_IRQ_HP1L_SC_POS] = { + .reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1 + }, +}; + +const struct regmap_irq_chip largo_irq = { + .name = "largo IRQ", + .status_base = ARIZONA_INTERRUPT_STATUS_1, + .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK, + .ack_base = ARIZONA_INTERRUPT_STATUS_1, + .num_regs = 6, + .irqs = largo_irqs, + .num_irqs = ARRAY_SIZE(largo_irqs), +}; +EXPORT_SYMBOL_GPL(largo_irq); + +static const struct reg_default largo_reg_default[] = { + { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */ + { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */ + { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */ + { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */ + { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */ + { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */ + { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */ + { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */ + { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */ + { 0x00000041, 0x0000 }, /* R65 - Sequence control */ + { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */ + { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ + { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ + { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ + { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ + { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ + { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */ + { 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */ + { 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */ + { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */ + { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */ + { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */ + { 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */ + { 0x00000101, 0x0504 }, /* R257 - System Clock 1 */ + { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */ + { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */ + { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */ + { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */ + { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */ + { 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */ + { 0x00000149, 0x0000 }, /* R329 - Output system clock */ + { 0x0000014A, 0x0000 }, /* R330 - Output async clock */ + { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */ + { 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */ + { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */ + { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */ + { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */ + { 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */ + { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */ + { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */ + { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */ + { 0x00000175, 0x0006 }, /* R373 - FLL1 Control 5 */ + { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */ + { 0x00000179, 0x0000 }, /* R376 - FLL1 Control 7 */ + { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */ + { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */ + { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */ + { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */ + { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */ + { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */ + { 0x00000187, 0x0001 }, /* R390 - FLL1 Synchroniser 7 */ + { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */ + { 0x0000018A, 0x000C }, /* R394 - FLL1 GPIO Clock */ + { 0x00000191, 0x0002 }, /* R401 - FLL2 Control 1 */ + { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */ + { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */ + { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */ + { 0x00000195, 0x000C }, /* R405 - FLL2 Control 5 */ + { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */ + { 0x00000199, 0x0000 }, /* R408 - FLL2 Control 7 */ + { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */ + { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */ + { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */ + { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */ + { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */ + { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */ + { 0x000001A7, 0x0001 }, /* R422 - FLL2 Synchroniser 7 */ + { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */ + { 0x000001AA, 0x000C }, /* R426 - FLL2 GPIO Clock */ + { 0x00000218, 0x00E6 }, /* R536 - Mic Bias Ctrl 1 */ + { 0x00000219, 0x00E6 }, /* R537 - Mic Bias Ctrl 2 */ + { 0x00000300, 0x0000 }, /* R768 - Input Enables */ + { 0x00000308, 0x0000 }, /* R776 - Input Rate */ + { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ + { 0x0000030C, 0x0002 }, /* R780 - HPF Control */ + { 0x00000310, 0x2000 }, /* R784 - IN1L Control */ + { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ + { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ + { 0x00000314, 0x0000 }, /* R788 - IN1R Control */ + { 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */ + { 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */ + { 0x00000318, 0x2000 }, /* R792 - IN2L Control */ + { 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */ + { 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */ + { 0x0000031C, 0x0000 }, /* R796 - IN2R Control */ + { 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */ + { 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */ + { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ + { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */ + { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */ + { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */ + { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */ + { 0x00000412, 0x0081 }, /* R1042 - DAC Volume Limit 1L */ + { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */ + { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */ + { 0x00000416, 0x0081 }, /* R1046 - DAC Volume Limit 1R */ + { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */ + { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */ + { 0x0000042A, 0x0081 }, /* R1066 - Out Volume 4L */ + { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */ + { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ + { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ + { 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */ + { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ + { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ + { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ + { 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */ + { 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */ + { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */ + { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ + { 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */ + { 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */ + { 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */ + { 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */ + { 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */ + { 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */ + { 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */ + { 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */ + { 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */ + { 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */ + { 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */ + { 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */ + { 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */ + { 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */ + { 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */ + { 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */ + { 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */ + { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */ + { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */ + { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */ + { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ + { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */ + { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */ + { 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */ + { 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */ + { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */ + { 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */ + { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */ + { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */ + { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */ + { 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */ + { 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */ + { 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */ + { 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */ + { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */ + { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */ + { 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */ + { 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */ + { 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */ + { 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */ + { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */ + { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */ + { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ + { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */ + { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */ + { 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */ + { 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */ + { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */ + { 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */ + { 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */ + { 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */ + { 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */ + { 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */ + { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */ + { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */ + { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */ + { 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */ + { 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */ + { 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */ + { 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */ + { 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */ + { 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */ + { 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */ + { 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */ + { 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */ + { 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */ + { 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */ + { 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */ + { 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */ + { 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */ + { 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */ + { 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */ + { 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */ + { 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */ + { 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */ + { 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */ + { 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */ + { 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */ + { 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */ + { 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */ + { 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */ + { 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */ + { 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */ + { 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */ + { 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */ + { 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */ + { 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */ + { 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */ + { 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */ + { 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */ + { 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */ + { 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */ + { 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */ + { 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */ + { 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */ + { 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */ + { 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */ + { 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */ + { 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */ + { 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */ + { 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */ + { 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */ + { 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */ + { 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */ + { 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */ + { 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */ + { 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */ + { 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */ + { 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */ + { 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */ + { 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */ + { 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */ + { 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */ + { 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */ + { 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */ + { 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */ + { 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */ + { 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */ + { 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */ + { 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */ + { 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */ + { 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */ + { 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */ + { 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */ + { 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */ + { 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */ + { 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */ + { 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */ + { 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */ + { 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */ + { 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */ + { 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */ + { 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */ + { 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */ + { 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */ + { 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */ + { 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */ + { 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */ + { 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */ + { 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */ + { 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */ + { 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */ + { 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */ + { 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */ + { 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */ + { 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */ + { 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */ + { 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */ + { 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */ + { 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */ + { 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */ + { 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */ + { 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */ + { 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */ + { 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */ + { 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */ + { 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */ + { 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */ + { 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */ + { 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */ + { 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */ + { 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */ + { 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */ + { 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */ + { 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */ + { 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */ + { 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */ + { 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */ + { 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */ + { 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */ + { 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */ + { 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */ + { 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */ + { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ + { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ + { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ + { 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */ + { 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */ + { 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */ + { 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */ + { 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */ + { 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */ + { 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */ + { 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */ + { 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */ + { 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */ + { 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */ + { 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */ + { 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */ + { 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */ + { 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */ + { 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */ + { 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */ + { 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */ + { 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */ + { 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */ + { 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */ + { 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */ + { 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */ + { 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */ + { 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */ + { 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */ + { 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */ + { 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */ + { 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */ + { 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */ + { 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */ + { 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */ + { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */ + { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */ + { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */ + { 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */ + { 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */ + { 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */ + { 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */ + { 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */ + { 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */ + { 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */ + { 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */ + { 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */ + { 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */ + { 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */ + { 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */ + { 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */ + { 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */ + { 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */ + { 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */ + { 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */ + { 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */ + { 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */ + { 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */ + { 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */ + { 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */ + { 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */ + { 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */ + { 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */ + { 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */ + { 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */ + { 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */ + { 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */ + { 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */ + { 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */ + { 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */ + { 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */ + { 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */ + { 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */ + { 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */ + { 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */ + { 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */ + { 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */ + { 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */ + { 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */ + { 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */ + { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */ + { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */ + { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */ + { 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */ + { 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */ + { 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */ + { 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */ + { 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */ + { 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */ + { 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */ + { 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */ + { 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */ + { 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */ + { 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */ + { 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */ + { 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */ + { 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */ + { 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */ + { 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */ + { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */ + { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */ + { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */ + { 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */ + { 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */ + { 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */ + { 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */ + { 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */ + { 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */ + { 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */ + { 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */ + { 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */ + { 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */ + { 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */ + { 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */ + { 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */ + { 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */ + { 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */ + { 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */ + { 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */ + { 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */ + { 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */ + { 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */ + { 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */ + { 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */ + { 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */ + { 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */ + { 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */ + { 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */ + { 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */ + { 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */ + { 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */ + { 0x00000980, 0x0000 }, /* R2432 - DSP2LMIX Input 1 Source */ + { 0x00000981, 0x0080 }, /* R2433 - DSP2LMIX Input 1 Volume */ + { 0x00000982, 0x0000 }, /* R2434 - DSP2LMIX Input 2 Source */ + { 0x00000983, 0x0080 }, /* R2435 - DSP2LMIX Input 2 Volume */ + { 0x00000984, 0x0000 }, /* R2436 - DSP2LMIX Input 3 Source */ + { 0x00000985, 0x0080 }, /* R2437 - DSP2LMIX Input 3 Volume */ + { 0x00000986, 0x0000 }, /* R2438 - DSP2LMIX Input 4 Source */ + { 0x00000987, 0x0080 }, /* R2439 - DSP2LMIX Input 4 Volume */ + { 0x00000988, 0x0000 }, /* R2440 - DSP2RMIX Input 1 Source */ + { 0x00000989, 0x0080 }, /* R2441 - DSP2RMIX Input 1 Volume */ + { 0x0000098A, 0x0000 }, /* R2442 - DSP2RMIX Input 2 Source */ + { 0x0000098B, 0x0080 }, /* R2443 - DSP2RMIX Input 2 Volume */ + { 0x0000098C, 0x0000 }, /* R2444 - DSP2RMIX Input 3 Source */ + { 0x0000098D, 0x0080 }, /* R2445 - DSP2RMIX Input 3 Volume */ + { 0x0000098E, 0x0000 }, /* R2446 - DSP2RMIX Input 4 Source */ + { 0x0000098F, 0x0080 }, /* R2447 - DSP2RMIX Input 4 Volume */ + { 0x00000990, 0x0000 }, /* R2448 - DSP2AUX1MIX Input 1 Source */ + { 0x00000998, 0x0000 }, /* R2456 - DSP2AUX2MIX Input 1 Source */ + { 0x000009A0, 0x0000 }, /* R2464 - DSP2AUX3MIX Input 1 Source */ + { 0x000009A8, 0x0000 }, /* R2472 - DSP2AUX4MIX Input 1 Source */ + { 0x000009B0, 0x0000 }, /* R2480 - DSP2AUX5MIX Input 1 Source */ + { 0x000009B8, 0x0000 }, /* R2488 - DSP2AUX6MIX Input 1 Source */ + { 0x000009C0, 0x0000 }, /* R2496 - DSP3LMIX Input 1 Source */ + { 0x000009C1, 0x0080 }, /* R2497 - DSP3LMIX Input 1 Volume */ + { 0x000009C2, 0x0000 }, /* R2498 - DSP3LMIX Input 2 Source */ + { 0x000009C3, 0x0080 }, /* R2499 - DSP3LMIX Input 2 Volume */ + { 0x000009C4, 0x0000 }, /* R2500 - DSP3LMIX Input 3 Source */ + { 0x000009C5, 0x0080 }, /* R2501 - DSP3LMIX Input 3 Volume */ + { 0x000009C6, 0x0000 }, /* R2502 - DSP3LMIX Input 4 Source */ + { 0x000009C7, 0x0080 }, /* R2503 - DSP3LMIX Input 4 Volume */ + { 0x000009C8, 0x0000 }, /* R2504 - DSP3RMIX Input 1 Source */ + { 0x000009C9, 0x0080 }, /* R2505 - DSP3RMIX Input 1 Volume */ + { 0x000009CA, 0x0000 }, /* R2506 - DSP3RMIX Input 2 Source */ + { 0x000009CB, 0x0080 }, /* R2507 - DSP3RMIX Input 2 Volume */ + { 0x000009CC, 0x0000 }, /* R2508 - DSP3RMIX Input 3 Source */ + { 0x000009CD, 0x0080 }, /* R2509 - DSP3RMIX Input 3 Volume */ + { 0x000009CE, 0x0000 }, /* R2510 - DSP3RMIX Input 4 Source */ + { 0x000009CF, 0x0080 }, /* R2511 - DSP3RMIX Input 4 Volume */ + { 0x000009D0, 0x0000 }, /* R2512 - DSP3AUX1MIX Input 1 Source */ + { 0x000009D8, 0x0000 }, /* R2520 - DSP3AUX2MIX Input 1 Source */ + { 0x000009E0, 0x0000 }, /* R2528 - DSP3AUX3MIX Input 1 Source */ + { 0x000009E8, 0x0000 }, /* R2536 - DSP3AUX4MIX Input 1 Source */ + { 0x000009F0, 0x0000 }, /* R2544 - DSP3AUX5MIX Input 1 Source */ + { 0x000009F8, 0x0000 }, /* R2552 - DSP3AUX6MIX Input 1 Source */ + { 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */ + { 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */ + { 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */ + { 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */ + { 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */ + { 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */ + { 0x00000B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */ + { 0x00000B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */ + { 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */ + { 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */ + { 0x00000B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */ + { 0x00000B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */ + { 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */ + { 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */ + { 0x00000B50, 0x0000 }, /* R2896 - ISRC2DEC3MIX Input 1 Source */ + { 0x00000B58, 0x0000 }, /* R2904 - ISRC2DEC4MIX Input 1 Source */ + { 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */ + { 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */ + { 0x00000B70, 0x0000 }, /* R2928 - ISRC2INT3MIX Input 1 Source */ + { 0x00000B78, 0x0000 }, /* R2936 - ISRC2INT4MIX Input 1 Source */ + { 0x00000B80, 0x0000 }, /* R2944 - ISRC3DEC1MIX Input 1 Source */ + { 0x00000B88, 0x0000 }, /* R2952 - ISRC3DEC2MIX Input 1 Source */ + { 0x00000B90, 0x0000 }, /* R2960 - ISRC3DEC3MIX Input 1 Source */ + { 0x00000B98, 0x0000 }, /* R2968 - ISRC3DEC4MIX Input 1 Source */ + { 0x00000BA0, 0x0000 }, /* R2976 - ISRC3INT1MIX Input 1 Source */ + { 0x00000BA8, 0x0000 }, /* R2984 - ISRC3INT2MIX Input 1 Source */ + { 0x00000BB0, 0x0000 }, /* R2992 - ISRC3INT3MIX Input 1 Source */ + { 0x00000BB8, 0x0000 }, /* R3000 - ISRC3INT4MIX Input 1 Source */ + { 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */ + { 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */ + { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */ + { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */ + { 0x00000C20, 0x0002 }, /* R3104 - Misc Pad Ctrl 1 */ + { 0x00000C21, 0x0000 }, /* R3105 - Misc Pad Ctrl 2 */ + { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */ + { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */ + { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */ + { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */ + { 0x00000C30, 0x0404 }, /* R3120 - Misc Pad Ctrl 7 */ + { 0x00000C32, 0x0404 }, /* R3122 - Misc Pad Ctrl 9 */ + { 0x00000C33, 0x0404 }, /* R3123 - Misc Pad Ctrl 10 */ + { 0x00000C34, 0x0404 }, /* R3124 - Misc Pad Ctrl 11 */ + { 0x00000C35, 0x0404 }, /* R3125 - Misc Pad Ctrl 12 */ + { 0x00000C36, 0x0400 }, /* R3126 - Misc Pad Ctrl 13 */ + { 0x00000C37, 0x0404 }, /* R3127 - Misc Pad Ctrl 14 */ + { 0x00000C39, 0x0400 }, /* R3129 - Misc Pad Ctrl 16 */ + { 0x00000D08, 0x0007 }, /* R3336 - Interrupt Status 1 Mask */ + { 0x00000D09, 0x06FF }, /* R3337 - Interrupt Status 2 Mask */ + { 0x00000D0A, 0xCFEF }, /* R3338 - Interrupt Status 3 Mask */ + { 0x00000D0B, 0xFFC3 }, /* R3339 - Interrupt Status 4 Mask */ + { 0x00000D0C, 0x000B }, /* R3340 - Interrupt Status 5 Mask */ + { 0x00000D0D, 0xD005 }, /* R3341 - Interrupt Status 6 Mask */ + { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */ + { 0x00000D18, 0x0007 }, /* R3352 - IRQ2 Status 1 Mask */ + { 0x00000D19, 0x06FF }, /* R3353 - IRQ2 Status 2 Mask */ + { 0x00000D1A, 0xCFEF }, /* R3354 - IRQ2 Status 3 Mask */ + { 0x00000D1B, 0xFFC3 }, /* R3355 - IRQ2 Status 4 Mask */ + { 0x00000D1C, 0x000B }, /* R3356 - IRQ2 Status 5 Mask */ + { 0x00000D1D, 0xD005 }, /* R3357 - IRQ2 Status 6 Mask */ + { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */ + { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */ + { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */ + { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */ + { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */ + { 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */ + { 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */ + { 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */ + { 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */ + { 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */ + { 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */ + { 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */ + { 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */ + { 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */ + { 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */ + { 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */ + { 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */ + { 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */ + { 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */ + { 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */ + { 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */ + { 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */ + { 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */ + { 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */ + { 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */ + { 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */ + { 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */ + { 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */ + { 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */ + { 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */ + { 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */ + { 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */ + { 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */ + { 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */ + { 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */ + { 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */ + { 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */ + { 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */ + { 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */ + { 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */ + { 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */ + { 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */ + { 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */ + { 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */ + { 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */ + { 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */ + { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */ + { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */ + { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */ + { 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */ + { 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */ + { 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */ + { 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */ + { 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */ + { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */ + { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */ + { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */ + { 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */ + { 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */ + { 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */ + { 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */ + { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ + { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */ + { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */ + { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */ + { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */ + { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */ + { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */ + { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */ + { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */ + { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */ + { 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */ + { 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */ + { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */ + { 0x00001200, 0x0010 }, /* R4608 - DSP2 Control 1 */ + { 0x00001300, 0x0010 }, /* R4864 - DSP3 Control 1 */ +}; + +static bool largo_is_adsp_memory(struct device *dev, unsigned int reg) +{ + if ((reg >= 0x200000 && reg < 0x206000) || + (reg >= 0x280000 && reg < 0x282000) || + (reg >= 0x290000 && reg < 0x2a8000) || + (reg >= 0x2a8000 && reg < 0x2b4000) || + (reg >= 0x300000 && reg < 0x309000) || + (reg >= 0x380000 && reg < 0x382000) || + (reg >= 0x390000 && reg < 0x3a8000) || + (reg >= 0x3a8000 && reg < 0x3b4000)) + return true; + else + return false; +} + +static bool largo_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_SPI_CFG_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_COMFORT_NOISE_GENERATOR: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_CLOCK_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_OUTPUT_ASYNC_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_CONTROL_7: + case ARIZONA_FLL1_SYNCHRONISER_1: + case ARIZONA_FLL1_SYNCHRONISER_2: + case ARIZONA_FLL1_SYNCHRONISER_3: + case ARIZONA_FLL1_SYNCHRONISER_4: + case ARIZONA_FLL1_SYNCHRONISER_5: + case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SYNCHRONISER_7: + case ARIZONA_FLL1_SPREAD_SPECTRUM: + case ARIZONA_FLL1_GPIO_CLOCK: + case ARIZONA_FLL2_CONTROL_1: + case ARIZONA_FLL2_CONTROL_2: + case ARIZONA_FLL2_CONTROL_3: + case ARIZONA_FLL2_CONTROL_4: + case ARIZONA_FLL2_CONTROL_5: + case ARIZONA_FLL2_CONTROL_6: + case ARIZONA_FLL2_CONTROL_7: + case ARIZONA_FLL2_SYNCHRONISER_1: + case ARIZONA_FLL2_SYNCHRONISER_2: + case ARIZONA_FLL2_SYNCHRONISER_3: + case ARIZONA_FLL2_SYNCHRONISER_4: + case ARIZONA_FLL2_SYNCHRONISER_5: + case ARIZONA_FLL2_SYNCHRONISER_6: + case ARIZONA_FLL2_SYNCHRONISER_7: + case ARIZONA_FLL2_SPREAD_SPECTRUM: + case ARIZONA_FLL2_GPIO_CLOCK: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_2: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case ARIZONA_IN2R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2R: + case ARIZONA_DMIC2R_CONTROL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case ARIZONA_DAC_VOLUME_LIMIT_1L: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_DAC_VOLUME_LIMIT_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_4L: + case ARIZONA_OUT_VOLUME_4L: + case ARIZONA_NOISE_GATE_SELECT_4L: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_SPK_CTRL_5: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_TX_BCLK_RATE: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_9: + case ARIZONA_AIF1_FRAME_CTRL_10: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_FRAME_CTRL_17: + case ARIZONA_AIF1_FRAME_CTRL_18: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_5: + case ARIZONA_AIF2_FRAME_CTRL_6: + case ARIZONA_AIF2_FRAME_CTRL_7: + case ARIZONA_AIF2_FRAME_CTRL_8: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_FRAME_CTRL_13: + case ARIZONA_AIF2_FRAME_CTRL_14: + case ARIZONA_AIF2_FRAME_CTRL_15: + case ARIZONA_AIF2_FRAME_CTRL_16: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_AIF3_BCLK_CTRL: + case ARIZONA_AIF3_TX_PIN_CTRL: + case ARIZONA_AIF3_RX_PIN_CTRL: + case ARIZONA_AIF3_RATE_CTRL: + case ARIZONA_AIF3_FORMAT: + case ARIZONA_AIF3_RX_BCLK_RATE: + case ARIZONA_AIF3_FRAME_CTRL_1: + case ARIZONA_AIF3_FRAME_CTRL_2: + case ARIZONA_AIF3_FRAME_CTRL_3: + case ARIZONA_AIF3_FRAME_CTRL_4: + case ARIZONA_AIF3_FRAME_CTRL_11: + case ARIZONA_AIF3_FRAME_CTRL_12: + case ARIZONA_AIF3_TX_ENABLES: + case ARIZONA_AIF3_RX_ENABLES: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_2_SOURCE: + case ARIZONA_EQ1MIX_INPUT_2_VOLUME: + case ARIZONA_EQ1MIX_INPUT_3_SOURCE: + case ARIZONA_EQ1MIX_INPUT_3_VOLUME: + case ARIZONA_EQ1MIX_INPUT_4_SOURCE: + case ARIZONA_EQ1MIX_INPUT_4_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_2_SOURCE: + case ARIZONA_EQ2MIX_INPUT_2_VOLUME: + case ARIZONA_EQ2MIX_INPUT_3_SOURCE: + case ARIZONA_EQ2MIX_INPUT_3_VOLUME: + case ARIZONA_EQ2MIX_INPUT_4_SOURCE: + case ARIZONA_EQ2MIX_INPUT_4_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_4_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE: + case ARIZONA_GPIO1_CTRL: + case ARIZONA_GPIO2_CTRL: + case ARIZONA_IRQ_CTRL_1: + case ARIZONA_GPIO_DEBOUNCE_CONFIG: + case ARIZONA_MISC_PAD_CTRL_1: + case ARIZONA_MISC_PAD_CTRL_2: + case ARIZONA_MISC_PAD_CTRL_3: + case ARIZONA_MISC_PAD_CTRL_4: + case ARIZONA_MISC_PAD_CTRL_5: + case ARIZONA_MISC_PAD_CTRL_6: + case ARIZONA_MISC_PAD_CTRL_7: + case ARIZONA_MISC_PAD_CTRL_9: + case ARIZONA_MISC_PAD_CTRL_10: + case ARIZONA_MISC_PAD_CTRL_11: + case ARIZONA_MISC_PAD_CTRL_12: + case ARIZONA_MISC_PAD_CTRL_13: + case ARIZONA_MISC_PAD_CTRL_14: + case ARIZONA_MISC_PAD_CTRL_16: + case ARIZONA_INTERRUPT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_2: + case ARIZONA_INTERRUPT_STATUS_3: + case ARIZONA_INTERRUPT_STATUS_4: + case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_INTERRUPT_STATUS_6: + case ARIZONA_INTERRUPT_STATUS_1_MASK: + case ARIZONA_INTERRUPT_STATUS_2_MASK: + case ARIZONA_INTERRUPT_STATUS_3_MASK: + case ARIZONA_INTERRUPT_STATUS_4_MASK: + case ARIZONA_INTERRUPT_STATUS_5_MASK: + case ARIZONA_INTERRUPT_STATUS_6_MASK: + case ARIZONA_INTERRUPT_CONTROL: + case ARIZONA_IRQ2_STATUS_1: + case ARIZONA_IRQ2_STATUS_2: + case ARIZONA_IRQ2_STATUS_3: + case ARIZONA_IRQ2_STATUS_4: + case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_IRQ2_STATUS_6: + case ARIZONA_IRQ2_STATUS_1_MASK: + case ARIZONA_IRQ2_STATUS_2_MASK: + case ARIZONA_IRQ2_STATUS_3_MASK: + case ARIZONA_IRQ2_STATUS_4_MASK: + case ARIZONA_IRQ2_STATUS_5_MASK: + case ARIZONA_IRQ2_STATUS_6_MASK: + case ARIZONA_IRQ2_CONTROL: + case ARIZONA_INTERRUPT_RAW_STATUS_2: + case ARIZONA_INTERRUPT_RAW_STATUS_3: + case ARIZONA_INTERRUPT_RAW_STATUS_4: + case ARIZONA_INTERRUPT_RAW_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_7: + case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_INTERRUPT_RAW_STATUS_9: + case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case ARIZONA_DRC2_CTRL1: + case ARIZONA_DRC2_CTRL2: + case ARIZONA_DRC2_CTRL3: + case ARIZONA_DRC2_CTRL4: + case ARIZONA_DRC2_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case ARIZONA_ASRC_ENABLE: + case ARIZONA_ASRC_STATUS: + case ARIZONA_ASRC_RATE1: + case ARIZONA_ASRC_RATE2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + case ARIZONA_ISRC_3_CTRL_1: + case ARIZONA_ISRC_3_CTRL_2: + case ARIZONA_ISRC_3_CTRL_3: + case ARIZONA_DSP2_CONTROL_1: + case ARIZONA_DSP2_CLOCKING_1: + case ARIZONA_DSP2_STATUS_1: + case ARIZONA_DSP2_STATUS_2: + case ARIZONA_DSP2_STATUS_3: + case ARIZONA_DSP2_STATUS_4: + case ARIZONA_DSP2_WDMA_BUFFER_1: + case ARIZONA_DSP2_WDMA_BUFFER_2: + case ARIZONA_DSP2_WDMA_BUFFER_3: + case ARIZONA_DSP2_WDMA_BUFFER_4: + case ARIZONA_DSP2_WDMA_BUFFER_5: + case ARIZONA_DSP2_WDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_BUFFER_7: + case ARIZONA_DSP2_WDMA_BUFFER_8: + case ARIZONA_DSP2_RDMA_BUFFER_1: + case ARIZONA_DSP2_RDMA_BUFFER_2: + case ARIZONA_DSP2_RDMA_BUFFER_3: + case ARIZONA_DSP2_RDMA_BUFFER_4: + case ARIZONA_DSP2_RDMA_BUFFER_5: + case ARIZONA_DSP2_RDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_CONFIG_1: + case ARIZONA_DSP2_WDMA_CONFIG_2: + case ARIZONA_DSP2_WDMA_OFFSET_1: + case ARIZONA_DSP2_RDMA_CONFIG_1: + case ARIZONA_DSP2_RDMA_OFFSET_1: + case ARIZONA_DSP2_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP2_SCRATCH_0: + case ARIZONA_DSP2_SCRATCH_1: + case ARIZONA_DSP2_SCRATCH_2: + case ARIZONA_DSP2_SCRATCH_3: + case ARIZONA_DSP3_CONTROL_1: + case ARIZONA_DSP3_CLOCKING_1: + case ARIZONA_DSP3_STATUS_1: + case ARIZONA_DSP3_STATUS_2: + case ARIZONA_DSP3_STATUS_3: + case ARIZONA_DSP3_STATUS_4: + case ARIZONA_DSP3_WDMA_BUFFER_1: + case ARIZONA_DSP3_WDMA_BUFFER_2: + case ARIZONA_DSP3_WDMA_BUFFER_3: + case ARIZONA_DSP3_WDMA_BUFFER_4: + case ARIZONA_DSP3_WDMA_BUFFER_5: + case ARIZONA_DSP3_WDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_BUFFER_7: + case ARIZONA_DSP3_WDMA_BUFFER_8: + case ARIZONA_DSP3_RDMA_BUFFER_1: + case ARIZONA_DSP3_RDMA_BUFFER_2: + case ARIZONA_DSP3_RDMA_BUFFER_3: + case ARIZONA_DSP3_RDMA_BUFFER_4: + case ARIZONA_DSP3_RDMA_BUFFER_5: + case ARIZONA_DSP3_RDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_CONFIG_1: + case ARIZONA_DSP3_WDMA_CONFIG_2: + case ARIZONA_DSP3_WDMA_OFFSET_1: + case ARIZONA_DSP3_RDMA_CONFIG_1: + case ARIZONA_DSP3_RDMA_OFFSET_1: + case ARIZONA_DSP3_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP3_SCRATCH_0: + case ARIZONA_DSP3_SCRATCH_1: + case ARIZONA_DSP3_SCRATCH_2: + case ARIZONA_DSP3_SCRATCH_3: + return true; + default: + return largo_is_adsp_memory(dev, reg); + } +} + +static bool largo_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_2: + case ARIZONA_INTERRUPT_STATUS_3: + case ARIZONA_INTERRUPT_STATUS_4: + case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_INTERRUPT_STATUS_6: + case ARIZONA_IRQ2_STATUS_1: + case ARIZONA_IRQ2_STATUS_2: + case ARIZONA_IRQ2_STATUS_3: + case ARIZONA_IRQ2_STATUS_4: + case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_IRQ2_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_2: + case ARIZONA_INTERRUPT_RAW_STATUS_3: + case ARIZONA_INTERRUPT_RAW_STATUS_4: + case ARIZONA_INTERRUPT_RAW_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_7: + case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_INTERRUPT_RAW_STATUS_9: + case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_FX_CTRL2: + case ARIZONA_ASRC_STATUS: + case ARIZONA_DSP2_STATUS_1: + case ARIZONA_DSP2_STATUS_2: + case ARIZONA_DSP2_STATUS_3: + case ARIZONA_DSP2_STATUS_4: + case ARIZONA_DSP2_WDMA_BUFFER_1: + case ARIZONA_DSP2_WDMA_BUFFER_2: + case ARIZONA_DSP2_WDMA_BUFFER_3: + case ARIZONA_DSP2_WDMA_BUFFER_4: + case ARIZONA_DSP2_WDMA_BUFFER_5: + case ARIZONA_DSP2_WDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_BUFFER_7: + case ARIZONA_DSP2_WDMA_BUFFER_8: + case ARIZONA_DSP2_RDMA_BUFFER_1: + case ARIZONA_DSP2_RDMA_BUFFER_2: + case ARIZONA_DSP2_RDMA_BUFFER_3: + case ARIZONA_DSP2_RDMA_BUFFER_4: + case ARIZONA_DSP2_RDMA_BUFFER_5: + case ARIZONA_DSP2_RDMA_BUFFER_6: + case ARIZONA_DSP2_WDMA_CONFIG_1: + case ARIZONA_DSP2_WDMA_CONFIG_2: + case ARIZONA_DSP2_WDMA_OFFSET_1: + case ARIZONA_DSP2_RDMA_CONFIG_1: + case ARIZONA_DSP2_RDMA_OFFSET_1: + case ARIZONA_DSP2_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP2_SCRATCH_0: + case ARIZONA_DSP2_SCRATCH_1: + case ARIZONA_DSP2_SCRATCH_2: + case ARIZONA_DSP2_SCRATCH_3: + case ARIZONA_DSP2_CLOCKING_1: + case ARIZONA_DSP3_STATUS_1: + case ARIZONA_DSP3_STATUS_2: + case ARIZONA_DSP3_STATUS_3: + case ARIZONA_DSP3_STATUS_4: + case ARIZONA_DSP3_WDMA_BUFFER_1: + case ARIZONA_DSP3_WDMA_BUFFER_2: + case ARIZONA_DSP3_WDMA_BUFFER_3: + case ARIZONA_DSP3_WDMA_BUFFER_4: + case ARIZONA_DSP3_WDMA_BUFFER_5: + case ARIZONA_DSP3_WDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_BUFFER_7: + case ARIZONA_DSP3_WDMA_BUFFER_8: + case ARIZONA_DSP3_RDMA_BUFFER_1: + case ARIZONA_DSP3_RDMA_BUFFER_2: + case ARIZONA_DSP3_RDMA_BUFFER_3: + case ARIZONA_DSP3_RDMA_BUFFER_4: + case ARIZONA_DSP3_RDMA_BUFFER_5: + case ARIZONA_DSP3_RDMA_BUFFER_6: + case ARIZONA_DSP3_WDMA_CONFIG_1: + case ARIZONA_DSP3_WDMA_CONFIG_2: + case ARIZONA_DSP3_WDMA_OFFSET_1: + case ARIZONA_DSP3_RDMA_CONFIG_1: + case ARIZONA_DSP3_RDMA_OFFSET_1: + case ARIZONA_DSP3_EXTERNAL_START_SELECT_1: + case ARIZONA_DSP3_SCRATCH_0: + case ARIZONA_DSP3_SCRATCH_1: + case ARIZONA_DSP3_SCRATCH_2: + case ARIZONA_DSP3_SCRATCH_3: + case ARIZONA_DSP3_CLOCKING_1: + return true; + default: + return largo_is_adsp_memory(dev, reg); + } +} + +#define LARGO_MAX_REGISTER 0x3b3fff + +const struct regmap_config largo_spi_regmap = { + .reg_bits = 32, + .pad_bits = 16, + .val_bits = 16, + + .max_register = LARGO_MAX_REGISTER, + .readable_reg = largo_readable_register, + .volatile_reg = largo_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = largo_reg_default, + .num_reg_defaults = ARRAY_SIZE(largo_reg_default), +}; +EXPORT_SYMBOL_GPL(largo_spi_regmap); + diff --git a/drivers/mfd/marley-tables.c b/drivers/mfd/marley-tables.c new file mode 100644 index 00000000000..4d66d5708d7 --- /dev/null +++ b/drivers/mfd/marley-tables.c @@ -0,0 +1,1941 @@ +/* + * marley-tables.c -- data tables for Marley class codecs + * + * Copyright 2015 Cirrus Logic + * + * Author: Piotr Stankiewicz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include + +#include "arizona.h" + +static const struct reg_sequence marley_16_patch[] = { + { 0x460, 0x0c40 }, + { 0x461, 0xcd1a }, + { 0x462, 0x0c40 }, + { 0x463, 0xb53b }, + { 0x464, 0x0c40 }, + { 0x465, 0x7503 }, + { 0x466, 0x0c40 }, + { 0x467, 0x4a41 }, + { 0x468, 0x0041 }, + { 0x469, 0x3491 }, + { 0x46a, 0x0841 }, + { 0x46b, 0x1f50 }, + { 0x46c, 0x0446 }, + { 0x46d, 0x14ed }, + { 0x46e, 0x0446 }, + { 0x46f, 0x1455 }, + { 0x470, 0x04c6 }, + { 0x471, 0x1220 }, + { 0x472, 0x04c6 }, + { 0x473, 0x040f }, + { 0x474, 0x04ce }, + { 0x475, 0x0339 }, + { 0x476, 0x05df }, + { 0x477, 0x028f }, + { 0x478, 0x05df }, + { 0x479, 0x0209 }, + { 0x47a, 0x05df }, + { 0x47b, 0x00cf }, + { 0x47c, 0x05df }, + { 0x47d, 0x0001 }, + { 0x47e, 0x07ff }, +}; + +/* We use a function so we can use ARRAY_SIZE() */ +int marley_patch(struct arizona *arizona) +{ + int ret = 0; + const struct reg_default *patch16 = NULL; + unsigned int num16; + + patch16 = marley_16_patch; + num16 = ARRAY_SIZE(marley_16_patch); + + ret = regmap_register_patch(arizona->regmap, patch16, num16); + if (ret < 0) + dev_err(arizona->dev, "Error applying 16-bit patch: %d\n", ret); + + return ret; +} +EXPORT_SYMBOL_GPL(marley_patch); + +static const struct regmap_irq marley_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_BOOT_DONE] = { .reg_offset = 0, + .mask = CLEARWATER_BOOT_DONE_EINT1 }, + [ARIZONA_IRQ_CTRLIF_ERR] = { .reg_offset = 0, + .mask = CLEARWATER_CTRLIF_ERR_EINT1 }, + + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL1_LOCK_EINT1 }, + + [ARIZONA_IRQ_MICDET] = { .reg_offset = 5, + .mask = CLEARWATER_MICDET_EINT1 }, + [ARIZONA_IRQ_HPDET] = { .reg_offset = 5, + .mask = CLEARWATER_HPDET_EINT1}, + + [ARIZONA_IRQ_MICD_CLAMP_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_RISE_EINT1 }, + [ARIZONA_IRQ_MICD_CLAMP_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_FALL_EINT1 }, + [ARIZONA_IRQ_JD_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_FALL_EINT1 }, + [ARIZONA_IRQ_JD_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_RISE_EINT1 }, + + [ARIZONA_IRQ_DRC2_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC2_SIG_DET_EINT1 }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC1_SIG_DET_EINT1 }, + + [ARIZONA_IRQ_DSP_IRQ1] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ1_EINT1}, + [ARIZONA_IRQ_DSP_IRQ2] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ2_EINT1}, + [ARIZONA_IRQ_DSP_IRQ3] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ3_EINT1}, + [ARIZONA_IRQ_DSP_IRQ4] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ4_EINT1}, + [ARIZONA_IRQ_DSP_IRQ5] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ5_EINT1}, + [ARIZONA_IRQ_DSP_IRQ6] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ6_EINT1}, + [ARIZONA_IRQ_DSP_IRQ7] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ7_EINT1}, + [ARIZONA_IRQ_DSP_IRQ8] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ8_EINT1}, + + [ARIZONA_IRQ_HP2R_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP2R_SC_EINT1}, + [ARIZONA_IRQ_HP2L_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP2L_SC_EINT1}, + [ARIZONA_IRQ_HP1R_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP1R_SC_EINT1}, + [ARIZONA_IRQ_HP1L_SC_POS] = { .reg_offset = 11, + .mask = CLEARWATER_HP1L_SC_EINT1}, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { .reg_offset = 14, + .mask = CLEARWATER_SPK_OVERHEAT_WARN_EINT1}, + [ARIZONA_IRQ_SPK_OVERHEAT] = { .reg_offset = 14, + .mask = CLEARWATER_SPK_SHUTDOWN_EINT1}, + + [ARIZONA_IRQ_GP1] = { .reg_offset = 16, + .mask = CLEARWATER_GP1_EINT1}, + [ARIZONA_IRQ_GP2] = { .reg_offset = 16, + .mask = CLEARWATER_GP2_EINT1}, + [ARIZONA_IRQ_GP3] = { .reg_offset = 16, + .mask = CLEARWATER_GP3_EINT1}, + [ARIZONA_IRQ_GP4] = { .reg_offset = 16, + .mask = CLEARWATER_GP4_EINT1}, + [ARIZONA_IRQ_GP5] = { .reg_offset = 16, + .mask = CLEARWATER_GP5_EINT1}, + [ARIZONA_IRQ_GP6] = { .reg_offset = 16, + .mask = CLEARWATER_GP6_EINT1}, + [ARIZONA_IRQ_GP7] = { .reg_offset = 16, + .mask = CLEARWATER_GP7_EINT1}, + [ARIZONA_IRQ_GP8] = { .reg_offset = 16, + .mask = CLEARWATER_GP8_EINT1}, +}; + +const struct regmap_irq_chip marley_irq = { + .name = "marley IRQ", + .status_base = CLEARWATER_IRQ1_STATUS_1, + .mask_base = CLEARWATER_IRQ1_MASK_1, + .ack_base = CLEARWATER_IRQ1_STATUS_1, + .num_regs = 32, + .irqs = marley_irqs, + .num_irqs = ARRAY_SIZE(marley_irqs), +}; +EXPORT_SYMBOL_GPL(marley_irq); + +static const struct reg_default marley_reg_default[] = { + { 0x00000008, 0x0308 }, /* R8 (0x8) - Ctrl IF CFG 1 */ + { 0x00000009, 0x0200 }, /* R9 (0x9) - Ctrl IF CFG 2 */ + { 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */ + { 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */ + { 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */ + { 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */ + { 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */ + { 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */ + { 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */ + { 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */ + { 0x00000041, 0x0000 }, /* R65 (0x41) - Sequence control */ + { 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */ + { 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */ + { 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */ + { 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4*/ + { 0x00000066, 0x01ff }, /* R102 (0x66) - Always On Triggers Sequence Select 1*/ + { 0x00000067, 0x01ff }, /* R103 (0x67) - Always On Triggers Sequence Select 2*/ + { 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */ + { 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics phase 1 intensity */ + { 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics phase 1 duration */ + { 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics phase 2 intensity */ + { 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics phase 2 duration */ + { 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics phase 3 intensity */ + { 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics phase 3 duration */ + { 0x000000A0, 0x0000 }, /* R160 (0xA0) - Comfort Noise Generator */ + { 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */ + { 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */ + { 0x00000102, 0x0011 }, /* R258 (0x102) - Sample rate 1 */ + { 0x00000103, 0x0011 }, /* R259 (0x103) - Sample rate 2 */ + { 0x00000104, 0x0011 }, /* R260 (0x104) - Sample rate 3 */ + { 0x00000120, 0x0305 }, /* R288 (0x120) - DSP Clock 1 */ + { 0x00000122, 0x0000 }, /* R290 (0x122) - DSP Clock 2 */ + { 0x00000149, 0x0000 }, /* R329 (0x149) - Output system clock */ + { 0x0000014a, 0x0000 }, /* R330 (0x14A) - Output async clock */ + { 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */ + { 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */ + { 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */ + { 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */ + { 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */ + { 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */ + { 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */ + { 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */ + { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ + { 0x00000175, 0x0000 }, /* R373 (0x175) - FLL1 Control 5 */ + { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ + { 0x00000177, 0x0281 }, /* R375 (0x177) - FLL1 Loop Filter Test 1 */ + { 0x00000178, 0x0000 }, /* R376 (0x178) - FLL1 NCO Test 0 */ + { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ + { 0x0000017f, 0x0000 }, /* R383 (0x17f) - FLL1 Synchroniser 1 */ + { 0x00000180, 0x0000 }, /* R384 (0x180) - FLL1 Synchroniser 2 */ + { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 3 */ + { 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 4 */ + { 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 5 */ + { 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 6 */ + { 0x00000185, 0x0001 }, /* R389 (0x185) - FLL1 Synchroniser 7 */ + { 0x00000187, 0x0000 }, /* R391 (0x187) - FLL1 Spread Spectrum */ + { 0x00000188, 0x000c }, /* R392 (0x188) - FLL1 GPIO Clock */ + { 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */ + { 0x0000020B, 0x0400 }, /* R523 (0x20B) - HP Charge Pump 8 */ + { 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */ + { 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */ + { 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */ + { 0x0000021c, 0x0022 }, /* R540 (0x21c) - Mic Bias Ctrl 5 */ + { 0x0000021e, 0x0022 }, /* R542 (0x21e) - Mic Bias Ctrl 6 */ + { 0x0000027e, 0x0000 }, /* R638 (0x27E) - EDRE HP stereo control */ + { 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */ + { 0x0000029b, 0x0000 }, /* R667 (0x29B) - Headphone Detect 1 */ + { 0x000002a3, 0x1102 }, /* R675 (0x2A3) - Mic Detect 1 */ + { 0x000002a4, 0x009f }, /* R676 (0x2A4) - Mic Detect 2 */ + { 0x000002a6, 0x3d3d }, /* R678 (0x2a6) - Mic Detect Level 1 */ + { 0x000002a7, 0x3d3d }, /* R679 (0x2a7) - Mic Detect Level 2 */ + { 0x000002a8, 0x333d }, /* R680 (0x2a8) - Mic Detect Level 3 */ + { 0x000002a9, 0x202d }, /* R681 (0x2a9) - Mic Detect Level 4 */ + { 0x000002c3, 0x0000 }, /* R707 (0x2c3) - Mic noise mix control 1 */ + { 0x000002c6, 0x0010 }, /* R710 (0x2c5) - Mic Clamp control */ + { 0x000002c8, 0x0000 }, /* R712 (0x2C8) - GP switch 1 */ + { 0x000002d3, 0x0000 }, /* R723 (0x2D3) - Jack detect analogue */ + { 0x00000300, 0x0000 }, /* R768 (0x300) - Input Enables */ + { 0x00000308, 0x0000 }, /* R776 (0x308) - Input Rate */ + { 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */ + { 0x0000030c, 0x0002 }, /* R780 (0x30C) - HPF Control */ + { 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */ + { 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */ + { 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */ + { 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */ + { 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */ + { 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */ + { 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */ + { 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */ + { 0x0000031a, 0x0500 }, /* R794 (0x31A) - DMIC2L Control */ + { 0x0000031c, 0x0080 }, /* R796 (0x31C) - IN2R Control */ + { 0x0000031d, 0x0180 }, /* R797 (0x31D) - ADC Digital Volume 2R */ + { 0x0000031e, 0x0000 }, /* R798 (0x31E) - DMIC2R Control */ + { 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */ + { 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */ + { 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */ + { 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */ + { 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */ + { 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */ + { 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */ + { 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */ + { 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */ + { 0x00000428, 0x0000 }, /* R1064 (0x428) - Output Path Config 4L */ + { 0x00000429, 0x0180 }, /* R1065 (0x429) - DAC Digital Volume 4L */ + { 0x0000042b, 0x0040 }, /* R1067 (0x42B) - Noise Gate Select 4L */ + { 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */ + { 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */ + { 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */ + { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ + { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ + { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ + { 0x00000440, 0x0003 }, /* R1088 (0x440) - DRE Enable */ + { 0x00000448, 0x0a83 }, /* R1096 (0x448) - eDRE Enable */ + { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ + { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ + { 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 CTRL 1 */ + { 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */ + { 0x000004a0, 0x3080 }, /* R1184 (0x4a0) - HP1 Short Circuit Ctrl */ + { 0x000004a8, 0x7120 }, /* R1192 (0x4a8) - HP Test Ctrl 5 */ + { 0x000004a9, 0x7120 }, /* R1193 (0x4a9) - HP Test Ctrl 6 */ + { 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */ + { 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */ + { 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */ + { 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */ + { 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */ + { 0x00000505, 0x0040 }, /* R1285 (0x505) - AIF1 Tx BCLK Rate */ + { 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */ + { 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */ + { 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */ + { 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */ + { 0x0000050a, 0x0001 }, /* R1290 (0x50A) - AIF1 Frame Ctrl 4 */ + { 0x0000050b, 0x0002 }, /* R1291 (0x50B) - AIF1 Frame Ctrl 5 */ + { 0x0000050c, 0x0003 }, /* R1292 (0x50C) - AIF1 Frame Ctrl 6 */ + { 0x0000050d, 0x0004 }, /* R1293 (0x50D) - AIF1 Frame Ctrl 7 */ + { 0x0000050e, 0x0005 }, /* R1294 (0x50E) - AIF1 Frame Ctrl 8 */ + { 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */ + { 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */ + { 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */ + { 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */ + { 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */ + { 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */ + { 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */ + { 0x0000051a, 0x0000 }, /* R1306 (0x51A) - AIF1 Rx Enables */ + { 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */ + { 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */ + { 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */ + { 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */ + { 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */ + { 0x00000545, 0x0040 }, /* R1349 (0x545) - AIF2 Tx BCLK Rate */ + { 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */ + { 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */ + { 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */ + { 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */ + { 0x0000054a, 0x0001 }, /* R1354 (0x54A) - AIF2 Frame Ctrl 4 */ + { 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */ + { 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */ + { 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */ + { 0x0000055a, 0x0000 }, /* R1370 (0x55A) - AIF2 Rx Enables */ + { 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */ + { 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */ + { 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */ + { 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */ + { 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */ + { 0x00000585, 0x0040 }, /* R1413 (0x585) - AIF3 Tx BCLK Rate */ + { 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */ + { 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */ + { 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */ + { 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */ + { 0x0000058a, 0x0001 }, /* R1418 (0x58A) - AIF3 Frame Ctrl 4 */ + { 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */ + { 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */ + { 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */ + { 0x0000059a, 0x0000 }, /* R1434 (0x59A) - AIF3 Rx Enables */ + { 0x000005c2, 0x0000 }, /* R1474 (0x5c2) - SPD1 TX Control */ + { 0x000005e3, 0x0000 }, /* R1507 (0x5E3) - SLIMbus Framer Ref Gear */ + { 0x000005e5, 0x0000 }, /* R1509 (0x5E5) - SLIMbus Rates 1 */ + { 0x000005e6, 0x0000 }, /* R1510 (0x5E6) - SLIMbus Rates 2 */ + { 0x000005e7, 0x0000 }, /* R1511 (0x5E7) - SLIMbus Rates 3 */ + { 0x000005e9, 0x0000 }, /* R1513 (0x5E9) - SLIMbus Rates 5 */ + { 0x000005ea, 0x0000 }, /* R1514 (0x5EA) - SLIMbus Rates 6 */ + { 0x000005eb, 0x0000 }, /* R1515 (0x5EB) - SLIMbus Rates 7 */ + { 0x000005f5, 0x0000 }, /* R1525 (0x5F5) - SLIMbus RX Channel Enable */ + { 0x000005f6, 0x0000 }, /* R1526 (0x5F6) - SLIMbus TX Channel Enable */ + { 0x00000640, 0x0000 }, /* R1600 (0x640) - PWM1MIX Input 1 Source */ + { 0x00000641, 0x0080 }, /* R1601 (0x641) - PWM1MIX Input 1 Volume */ + { 0x00000642, 0x0000 }, /* R1602 (0x642) - PWM1MIX Input 2 Source */ + { 0x00000643, 0x0080 }, /* R1603 (0x643) - PWM1MIX Input 2 Volume */ + { 0x00000644, 0x0000 }, /* R1604 (0x644) - PWM1MIX Input 3 Source */ + { 0x00000645, 0x0080 }, /* R1605 (0x645) - PWM1MIX Input 3 Volume */ + { 0x00000646, 0x0000 }, /* R1606 (0x646) - PWM1MIX Input 4 Source */ + { 0x00000647, 0x0080 }, /* R1607 (0x647) - PWM1MIX Input 4 Volume */ + { 0x00000648, 0x0000 }, /* R1608 (0x648) - PWM2MIX Input 1 Source */ + { 0x00000649, 0x0080 }, /* R1609 (0x649) - PWM2MIX Input 1 Volume */ + { 0x0000064a, 0x0000 }, /* R1610 (0x64a) - PWM2MIX Input 2 Source */ + { 0x0000064b, 0x0080 }, /* R1611 (0x64b) - PWM2MIX Input 2 Volume */ + { 0x0000064c, 0x0000 }, /* R1612 (0x64c) - PWM2MIX Input 3 Source */ + { 0x0000064d, 0x0080 }, /* R1613 (0x64d) - PWM2MIX Input 3 Volume */ + { 0x0000064e, 0x0000 }, /* R1614 (0x64e) - PWM2MIX Input 4 Source */ + { 0x0000064f, 0x0080 }, /* R1615 (0x64f) - PWM2MIX Input 4 Volume */ + { 0x00000680, 0x0000 }, /* R1664 (0x680) - OUT1LMIX Input 1 Source */ + { 0x00000681, 0x0080 }, /* R1665 (0x681) - OUT1LMIX Input 1 Volume */ + { 0x00000682, 0x0000 }, /* R1666 (0x682) - OUT1LMIX Input 2 Source */ + { 0x00000683, 0x0080 }, /* R1667 (0x683) - OUT1LMIX Input 2 Volume */ + { 0x00000684, 0x0000 }, /* R1668 (0x684) - OUT1LMIX Input 3 Source */ + { 0x00000685, 0x0080 }, /* R1669 (0x685) - OUT1LMIX Input 3 Volume */ + { 0x00000686, 0x0000 }, /* R1670 (0x686) - OUT1LMIX Input 4 Source */ + { 0x00000687, 0x0080 }, /* R1671 (0x687) - OUT1LMIX Input 4 Volume */ + { 0x00000688, 0x0000 }, /* R1672 (0x688) - OUT1RMIX Input 1 Source */ + { 0x00000689, 0x0080 }, /* R1673 (0x689) - OUT1RMIX Input 1 Volume */ + { 0x0000068a, 0x0000 }, /* R1674 (0x68a) - OUT1RMIX Input 2 Source */ + { 0x0000068b, 0x0080 }, /* R1675 (0x68b) - OUT1RMIX Input 2 Volume */ + { 0x0000068c, 0x0000 }, /* R1672 (0x68c) - OUT1RMIX Input 3 Source */ + { 0x0000068d, 0x0080 }, /* R1673 (0x68d) - OUT1RMIX Input 3 Volume */ + { 0x0000068e, 0x0000 }, /* R1674 (0x68e) - OUT1RMIX Input 4 Source */ + { 0x0000068f, 0x0080 }, /* R1675 (0x68f) - OUT1RMIX Input 4 Volume */ + { 0x000006b0, 0x0000 }, /* R1712 (0x6b0) - OUT4LMIX Input 1 Source */ + { 0x000006b1, 0x0080 }, /* R1713 (0x6b1) - OUT4LMIX Input 1 Volume */ + { 0x000006b2, 0x0000 }, /* R1714 (0x6b2) - OUT4LMIX Input 2 Source */ + { 0x000006b3, 0x0080 }, /* R1715 (0x6b3) - OUT4LMIX Input 2 Volume */ + { 0x000006b4, 0x0000 }, /* R1716 (0x6b4) - OUT4LMIX Input 3 Source */ + { 0x000006b5, 0x0080 }, /* R1717 (0x6b5) - OUT4LMIX Input 3 Volume */ + { 0x000006b6, 0x0000 }, /* R1718 (0x6b6) - OUT4LMIX Input 4 Source */ + { 0x000006b7, 0x0080 }, /* R1719 (0x6b7) - OUT4LMIX Input 4 Volume */ + { 0x000006c0, 0x0000 }, /* R1728 (0x6c0) - OUT5LMIX Input 1 Source */ + { 0x000006c1, 0x0080 }, /* R1729 (0x6c1) - OUT5LMIX Input 1 Volume */ + { 0x000006c2, 0x0000 }, /* R1730 (0x6c2) - OUT5LMIX Input 2 Source */ + { 0x000006c3, 0x0080 }, /* R1731 (0x6c3) - OUT5LMIX Input 2 Volume */ + { 0x000006c4, 0x0000 }, /* R1732 (0x6c4) - OUT5LMIX Input 3 Source */ + { 0x000006c5, 0x0080 }, /* R1733 (0x6c5) - OUT5LMIX Input 3 Volume */ + { 0x000006c6, 0x0000 }, /* R1734 (0x6c6) - OUT5LMIX Input 4 Source */ + { 0x000006c7, 0x0080 }, /* R1735 (0x6c7) - OUT5LMIX Input 4 Volume */ + { 0x000006c8, 0x0000 }, /* R1736 (0x6c8) - OUT5RMIX Input 1 Source */ + { 0x000006c9, 0x0080 }, /* R1737 (0x6c9) - OUT5RMIX Input 1 Volume */ + { 0x000006ca, 0x0000 }, /* R1738 (0x6ca) - OUT5RMIX Input 2 Source */ + { 0x000006cb, 0x0080 }, /* R1739 (0x6cb) - OUT5RMIX Input 2 Volume */ + { 0x000006cc, 0x0000 }, /* R1740 (0x6cc) - OUT5RMIX Input 3 Source */ + { 0x000006cd, 0x0080 }, /* R1741 (0x6cd) - OUT5RMIX Input 3 Volume */ + { 0x000006ce, 0x0000 }, /* R1742 (0x6ce) - OUT5RMIX Input 4 Source */ + { 0x000006cf, 0x0080 }, /* R1743 (0x6cf) - OUT5RMIX Input 4 Volume */ + { 0x00000700, 0x0000 }, /* R1792 (0x700) - AIF1TX1MIX Input 1 Source */ + { 0x00000701, 0x0080 }, /* R1793 (0x701) - AIF1TX1MIX Input 1 Volume */ + { 0x00000702, 0x0000 }, /* R1794 (0x702) - AIF1TX1MIX Input 2 Source */ + { 0x00000703, 0x0080 }, /* R1795 (0x703) - AIF1TX1MIX Input 2 Volume */ + { 0x00000704, 0x0000 }, /* R1796 (0x704) - AIF1TX1MIX Input 3 Source */ + { 0x00000705, 0x0080 }, /* R1797 (0x705) - AIF1TX1MIX Input 3 Volume */ + { 0x00000706, 0x0000 }, /* R1798 (0x706) - AIF1TX1MIX Input 4 Source */ + { 0x00000707, 0x0080 }, /* R1799 (0x707) - AIF1TX1MIX Input 4 Volume */ + { 0x00000708, 0x0000 }, /* R1800 (0x708) - AIF1TX2MIX Input 1 Source */ + { 0x00000709, 0x0080 }, /* R1801 (0x709) - AIF1TX2MIX Input 1 Volume */ + { 0x0000070a, 0x0000 }, /* R1802 (0x70a) - AIF1TX2MIX Input 2 Source */ + { 0x0000070b, 0x0080 }, /* R1803 (0x70b) - AIF1TX2MIX Input 2 Volume */ + { 0x0000070c, 0x0000 }, /* R1804 (0x70c) - AIF1TX2MIX Input 3 Source */ + { 0x0000070d, 0x0080 }, /* R1805 (0x70d) - AIF1TX2MIX Input 3 Volume */ + { 0x0000070e, 0x0000 }, /* R1806 (0x70e) - AIF1TX2MIX Input 4 Source */ + { 0x0000070f, 0x0080 }, /* R1807 (0x70f) - AIF1TX2MIX Input 4 Volume */ + { 0x00000710, 0x0000 }, /* R1808 (0x710) - AIF1TX3MIX Input 1 Source */ + { 0x00000711, 0x0080 }, /* R1809 (0x711) - AIF1TX3MIX Input 1 Volume */ + { 0x00000712, 0x0000 }, /* R1810 (0x712) - AIF1TX3MIX Input 2 Source */ + { 0x00000713, 0x0080 }, /* R1811 (0x713) - AIF1TX3MIX Input 2 Volume */ + { 0x00000714, 0x0000 }, /* R1812 (0x714) - AIF1TX3MIX Input 3 Source */ + { 0x00000715, 0x0080 }, /* R1813 (0x715) - AIF1TX3MIX Input 3 Volume */ + { 0x00000716, 0x0000 }, /* R1814 (0x716) - AIF1TX3MIX Input 4 Source */ + { 0x00000717, 0x0080 }, /* R1815 (0x717) - AIF1TX3MIX Input 4 Volume */ + { 0x00000718, 0x0000 }, /* R1816 (0x718) - AIF1TX4MIX Input 1 Source */ + { 0x00000719, 0x0080 }, /* R1817 (0x719) - AIF1TX4MIX Input 1 Volume */ + { 0x0000071a, 0x0000 }, /* R1818 (0x71a) - AIF1TX4MIX Input 2 Source */ + { 0x0000071b, 0x0080 }, /* R1819 (0x71b) - AIF1TX4MIX Input 2 Volume */ + { 0x0000071c, 0x0000 }, /* R1820 (0x71c) - AIF1TX4MIX Input 3 Source */ + { 0x0000071d, 0x0080 }, /* R1821 (0x71d) - AIF1TX4MIX Input 3 Volume */ + { 0x0000071e, 0x0000 }, /* R1822 (0x71e) - AIF1TX4MIX Input 4 Source */ + { 0x0000071f, 0x0080 }, /* R1823 (0x71f) - AIF1TX4MIX Input 4 Volume */ + { 0x00000720, 0x0000 }, /* R1824 (0x720) - AIF1TX5MIX Input 1 Source */ + { 0x00000721, 0x0080 }, /* R1825 (0x721) - AIF1TX5MIX Input 1 Volume */ + { 0x00000722, 0x0000 }, /* R1826 (0x722) - AIF1TX5MIX Input 2 Source */ + { 0x00000723, 0x0080 }, /* R1827 (0x723) - AIF1TX5MIX Input 2 Volume */ + { 0x00000724, 0x0000 }, /* R1828 (0x724) - AIF1TX5MIX Input 3 Source */ + { 0x00000725, 0x0080 }, /* R1829 (0x725) - AIF1TX5MIX Input 3 Volume */ + { 0x00000726, 0x0000 }, /* R1830 (0x726) - AIF1TX5MIX Input 4 Source */ + { 0x00000727, 0x0080 }, /* R1831 (0x727) - AIF1TX5MIX Input 4 Volume */ + { 0x00000728, 0x0000 }, /* R1832 (0x728) - AIF1TX6MIX Input 1 Source */ + { 0x00000729, 0x0080 }, /* R1833 (0x729) - AIF1TX6MIX Input 1 Volume */ + { 0x0000072a, 0x0000 }, /* R1834 (0x72a) - AIF1TX6MIX Input 2 Source */ + { 0x0000072b, 0x0080 }, /* R1835 (0x72b) - AIF1TX6MIX Input 2 Volume */ + { 0x0000072c, 0x0000 }, /* R1836 (0x72c) - AIF1TX6MIX Input 3 Source */ + { 0x0000072d, 0x0080 }, /* R1837 (0x72d) - AIF1TX6MIX Input 3 Volume */ + { 0x0000072e, 0x0000 }, /* R1838 (0x72e) - AIF1TX6MIX Input 4 Source */ + { 0x0000072f, 0x0080 }, /* R1839 (0x72f) - AIF1TX6MIX Input 4 Volume */ + { 0x00000740, 0x0000 }, /* R1856 (0x740) - AIF2TX1MIX Input 1 Source */ + { 0x00000741, 0x0080 }, /* R1857 (0x741) - AIF2TX1MIX Input 1 Volume */ + { 0x00000742, 0x0000 }, /* R1858 (0x742) - AIF2TX1MIX Input 2 Source */ + { 0x00000743, 0x0080 }, /* R1859 (0x743) - AIF2TX1MIX Input 2 Volume */ + { 0x00000744, 0x0000 }, /* R1860 (0x744) - AIF2TX1MIX Input 3 Source */ + { 0x00000745, 0x0080 }, /* R1861 (0x745) - AIF2TX1MIX Input 3 Volume */ + { 0x00000746, 0x0000 }, /* R1862 (0x746) - AIF2TX1MIX Input 4 Source */ + { 0x00000747, 0x0080 }, /* R1863 (0x747) - AIF2TX1MIX Input 4 Volume */ + { 0x00000748, 0x0000 }, /* R1864 (0x748) - AIF2TX2MIX Input 1 Source */ + { 0x00000749, 0x0080 }, /* R1865 (0x749) - AIF2TX2MIX Input 1 Volume */ + { 0x0000074a, 0x0000 }, /* R1866 (0x74a) - AIF2TX2MIX Input 2 Source */ + { 0x0000074b, 0x0080 }, /* R1867 (0x74b) - AIF2TX2MIX Input 2 Volume */ + { 0x0000074c, 0x0000 }, /* R1868 (0x74c) - AIF2TX2MIX Input 3 Source */ + { 0x0000074d, 0x0080 }, /* R1869 (0x74d) - AIF2TX2MIX Input 3 Volume */ + { 0x0000074e, 0x0000 }, /* R1870 (0x74e) - AIF2TX2MIX Input 4 Source */ + { 0x0000074f, 0x0080 }, /* R1871 (0x74f) - AIF2TX2MIX Input 4 Volume */ + { 0x00000780, 0x0000 }, /* R1920 (0x780) - AIF3TX1MIX Input 1 Source */ + { 0x00000781, 0x0080 }, /* R1921 (0x781) - AIF3TX1MIX Input 1 Volume */ + { 0x00000782, 0x0000 }, /* R1922 (0x782) - AIF3TX1MIX Input 2 Source */ + { 0x00000783, 0x0080 }, /* R1923 (0x783) - AIF3TX1MIX Input 2 Volume */ + { 0x00000784, 0x0000 }, /* R1924 (0x784) - AIF3TX1MIX Input 3 Source */ + { 0x00000785, 0x0080 }, /* R1925 (0x785) - AIF3TX1MIX Input 3 Volume */ + { 0x00000786, 0x0000 }, /* R1926 (0x786) - AIF3TX1MIX Input 4 Source */ + { 0x00000787, 0x0080 }, /* R1927 (0x787) - AIF3TX1MIX Input 4 Volume */ + { 0x00000788, 0x0000 }, /* R1928 (0x788) - AIF3TX2MIX Input 1 Source */ + { 0x00000789, 0x0080 }, /* R1929 (0x789) - AIF3TX2MIX Input 1 Volume */ + { 0x0000078a, 0x0000 }, /* R1930 (0x78a) - AIF3TX2MIX Input 2 Source */ + { 0x0000078b, 0x0080 }, /* R1931 (0x78b) - AIF3TX2MIX Input 2 Volume */ + { 0x0000078c, 0x0000 }, /* R1932 (0x78c) - AIF3TX2MIX Input 3 Source */ + { 0x0000078d, 0x0080 }, /* R1933 (0x78d) - AIF3TX2MIX Input 3 Volume */ + { 0x0000078e, 0x0000 }, /* R1934 (0x78e) - AIF3TX2MIX Input 4 Source */ + { 0x0000078f, 0x0080 }, /* R1935 (0x78f) - AIF3TX2MIX Input 4 Volume */ + { 0x000007c0, 0x0000 }, /* R1984 (0x7c0) - SLIMTX1MIX Input 1 Source */ + { 0x000007c1, 0x0080 }, /* R1985 (0x7c1) - SLIMTX1MIX Input 1 Volume */ + { 0x000007c2, 0x0000 }, /* R1986 (0x7c2) - SLIMTX1MIX Input 2 Source */ + { 0x000007c3, 0x0080 }, /* R1987 (0x7c3) - SLIMTX1MIX Input 2 Volume */ + { 0x000007c4, 0x0000 }, /* R1988 (0x7c4) - SLIMTX1MIX Input 3 Source */ + { 0x000007c5, 0x0080 }, /* R1989 (0x7c5) - SLIMTX1MIX Input 3 Volume */ + { 0x000007c6, 0x0000 }, /* R1990 (0x7c6) - SLIMTX1MIX Input 4 Source */ + { 0x000007c7, 0x0080 }, /* R1991 (0x7c7) - SLIMTX1MIX Input 4 Volume */ + { 0x000007c8, 0x0000 }, /* R1992 (0x7c8) - SLIMTX2MIX Input 1 Source */ + { 0x000007c9, 0x0080 }, /* R1993 (0x7c9) - SLIMTX2MIX Input 1 Volume */ + { 0x000007ca, 0x0000 }, /* R1994 (0x7ca) - SLIMTX2MIX Input 2 Source */ + { 0x000007cb, 0x0080 }, /* R1995 (0x7cb) - SLIMTX2MIX Input 2 Volume */ + { 0x000007cc, 0x0000 }, /* R1996 (0x7cc) - SLIMTX2MIX Input 3 Source */ + { 0x000007cd, 0x0080 }, /* R1997 (0x7cd) - SLIMTX2MIX Input 3 Volume */ + { 0x000007ce, 0x0000 }, /* R1998 (0x7ce) - SLIMTX2MIX Input 4 Source */ + { 0x000007cf, 0x0080 }, /* R1999 (0x7cf) - SLIMTX2MIX Input 4 Volume */ + { 0x000007d0, 0x0000 }, /* R2000 (0x7d0) - SLIMTX3MIX Input 1 Source */ + { 0x000007d1, 0x0080 }, /* R2001 (0x7d1) - SLIMTX3MIX Input 1 Volume */ + { 0x000007d2, 0x0000 }, /* R2002 (0x7d2) - SLIMTX3MIX Input 2 Source */ + { 0x000007d3, 0x0080 }, /* R2003 (0x7d3) - SLIMTX3MIX Input 2 Volume */ + { 0x000007d4, 0x0000 }, /* R2004 (0x7d4) - SLIMTX3MIX Input 3 Source */ + { 0x000007d5, 0x0080 }, /* R2005 (0x7d5) - SLIMTX3MIX Input 3 Volume */ + { 0x000007d6, 0x0000 }, /* R2006 (0x7d6) - SLIMTX3MIX Input 4 Source */ + { 0x000007d7, 0x0080 }, /* R2007 (0x7d7) - SLIMTX3MIX Input 4 Volume */ + { 0x000007d8, 0x0000 }, /* R2008 (0x7d8) - SLIMTX4MIX Input 1 Source */ + { 0x000007d9, 0x0080 }, /* R2009 (0x7d9) - SLIMTX4MIX Input 1 Volume */ + { 0x000007da, 0x0000 }, /* R2010 (0x7da) - SLIMTX4MIX Input 2 Source */ + { 0x000007db, 0x0080 }, /* R2011 (0x7db) - SLIMTX4MIX Input 2 Volume */ + { 0x000007dc, 0x0000 }, /* R2012 (0x7dc) - SLIMTX4MIX Input 3 Source */ + { 0x000007dd, 0x0080 }, /* R2013 (0x7dd) - SLIMTX4MIX Input 3 Volume */ + { 0x000007de, 0x0000 }, /* R2014 (0x7de) - SLIMTX4MIX Input 4 Source */ + { 0x000007df, 0x0080 }, /* R2015 (0x7df) - SLIMTX4MIX Input 4 Volume */ + { 0x000007e0, 0x0000 }, /* R2016 (0x7e0) - SLIMTX5MIX Input 1 Source */ + { 0x000007e1, 0x0080 }, /* R2017 (0x7e1) - SLIMTX5MIX Input 1 Volume */ + { 0x000007e2, 0x0000 }, /* R2018 (0x7e2) - SLIMTX5MIX Input 2 Source */ + { 0x000007e3, 0x0080 }, /* R2019 (0x7e3) - SLIMTX5MIX Input 2 Volume */ + { 0x000007e4, 0x0000 }, /* R2020 (0x7e4) - SLIMTX5MIX Input 3 Source */ + { 0x000007e5, 0x0080 }, /* R2021 (0x7e5) - SLIMTX5MIX Input 3 Volume */ + { 0x000007e6, 0x0000 }, /* R2022 (0x7e6) - SLIMTX5MIX Input 4 Source */ + { 0x000007e7, 0x0080 }, /* R2023 (0x7e7) - SLIMTX5MIX Input 4 Volume */ + { 0x000007e8, 0x0000 }, /* R2024 (0x7e8) - SLIMTX6MIX Input 1 Source */ + { 0x000007e9, 0x0080 }, /* R2025 (0x7e9) - SLIMTX6MIX Input 1 Volume */ + { 0x000007ea, 0x0000 }, /* R2026 (0x7ea) - SLIMTX6MIX Input 2 Source */ + { 0x000007eb, 0x0080 }, /* R2027 (0x7eb) - SLIMTX6MIX Input 2 Volume */ + { 0x000007ec, 0x0000 }, /* R2028 (0x7ec) - SLIMTX6MIX Input 3 Source */ + { 0x000007ed, 0x0080 }, /* R2029 (0x7ed) - SLIMTX6MIX Input 3 Volume */ + { 0x000007ee, 0x0000 }, /* R2030 (0x7ee) - SLIMTX6MIX Input 4 Source */ + { 0x000007ef, 0x0080 }, /* R2031 (0x7ef) - SLIMTX6MIX Input 4 Volume */ + { 0x00000800, 0x0000 }, /* R2048 (0x800) - SPDIF1TX1MIX Input 1 Source*/ + { 0x00000801, 0x0080 }, /* R2049 (0x801) - SPDIF1TX1MIX Input 1 Volume*/ + { 0x00000808, 0x0000 }, /* R2056 (0x808) - SPDIF1TX2MIX Input 1 Source*/ + { 0x00000809, 0x0080 }, /* R2057 (0x809) - SPDIF1TX2MIX Input 1 Volume*/ + { 0x00000880, 0x0000 }, /* R2176 (0x880) - EQ1MIX Input 1 Source */ + { 0x00000881, 0x0080 }, /* R2177 (0x881) - EQ1MIX Input 1 Volume */ + { 0x00000882, 0x0000 }, /* R2178 (0x882) - EQ1MIX Input 2 Source */ + { 0x00000883, 0x0080 }, /* R2179 (0x883) - EQ1MIX Input 2 Volume */ + { 0x00000884, 0x0000 }, /* R2180 (0x884) - EQ1MIX Input 3 Source */ + { 0x00000885, 0x0080 }, /* R2181 (0x885) - EQ1MIX Input 3 Volume */ + { 0x00000886, 0x0000 }, /* R2182 (0x886) - EQ1MIX Input 4 Source */ + { 0x00000887, 0x0080 }, /* R2183 (0x887) - EQ1MIX Input 4 Volume */ + { 0x00000888, 0x0000 }, /* R2184 (0x888) - EQ2MIX Input 1 Source */ + { 0x00000889, 0x0080 }, /* R2185 (0x889) - EQ2MIX Input 1 Volume */ + { 0x0000088a, 0x0000 }, /* R2186 (0x88a) - EQ2MIX Input 2 Source */ + { 0x0000088b, 0x0080 }, /* R2187 (0x88b) - EQ2MIX Input 2 Volume */ + { 0x0000088c, 0x0000 }, /* R2188 (0x88c) - EQ2MIX Input 3 Source */ + { 0x0000088d, 0x0080 }, /* R2189 (0x88d) - EQ2MIX Input 3 Volume */ + { 0x0000088e, 0x0000 }, /* R2190 (0x88e) - EQ2MIX Input 4 Source */ + { 0x0000088f, 0x0080 }, /* R2191 (0x88f) - EQ2MIX Input 4 Volume */ + { 0x00000890, 0x0000 }, /* R2192 (0x890) - EQ3MIX Input 1 Source */ + { 0x00000891, 0x0080 }, /* R2193 (0x891) - EQ3MIX Input 1 Volume */ + { 0x00000892, 0x0000 }, /* R2194 (0x892) - EQ3MIX Input 2 Source */ + { 0x00000893, 0x0080 }, /* R2195 (0x893) - EQ3MIX Input 2 Volume */ + { 0x00000894, 0x0000 }, /* R2196 (0x894) - EQ3MIX Input 3 Source */ + { 0x00000895, 0x0080 }, /* R2197 (0x895) - EQ3MIX Input 3 Volume */ + { 0x00000896, 0x0000 }, /* R2198 (0x896) - EQ3MIX Input 4 Source */ + { 0x00000897, 0x0080 }, /* R2199 (0x897) - EQ3MIX Input 4 Volume */ + { 0x00000898, 0x0000 }, /* R2200 (0x898) - EQ4MIX Input 1 Source */ + { 0x00000899, 0x0080 }, /* R2201 (0x899) - EQ4MIX Input 1 Volume */ + { 0x0000089a, 0x0000 }, /* R2202 (0x89a) - EQ4MIX Input 2 Source */ + { 0x0000089b, 0x0080 }, /* R2203 (0x89b) - EQ4MIX Input 2 Volume */ + { 0x0000089c, 0x0000 }, /* R2204 (0x89c) - EQ4MIX Input 3 Source */ + { 0x0000089d, 0x0080 }, /* R2205 (0x89d) - EQ4MIX Input 3 Volume */ + { 0x0000089e, 0x0000 }, /* R2206 (0x89e) - EQ4MIX Input 4 Source */ + { 0x0000089f, 0x0080 }, /* R2207 (0x89f) - EQ4MIX Input 4 Volume */ + { 0x000008c0, 0x0000 }, /* R2240 (0x8c0) - DRC1LMIX Input 1 Source */ + { 0x000008c1, 0x0080 }, /* R2241 (0x8c1) - DRC1LMIX Input 1 Volume */ + { 0x000008c2, 0x0000 }, /* R2242 (0x8c2) - DRC1LMIX Input 2 Source */ + { 0x000008c3, 0x0080 }, /* R2243 (0x8c3) - DRC1LMIX Input 2 Volume */ + { 0x000008c4, 0x0000 }, /* R2244 (0x8c4) - DRC1LMIX Input 3 Source */ + { 0x000008c5, 0x0080 }, /* R2245 (0x8c5) - DRC1LMIX Input 3 Volume */ + { 0x000008c6, 0x0000 }, /* R2246 (0x8c6) - DRC1LMIX Input 4 Source */ + { 0x000008c7, 0x0080 }, /* R2247 (0x8c7) - DRC1LMIX Input 4 Volume */ + { 0x000008c8, 0x0000 }, /* R2248 (0x8c8) - DRC1RMIX Input 1 Source */ + { 0x000008c9, 0x0080 }, /* R2249 (0x8c9) - DRC1RMIX Input 1 Volume */ + { 0x000008ca, 0x0000 }, /* R2250 (0x8ca) - DRC1RMIX Input 2 Source */ + { 0x000008cb, 0x0080 }, /* R2251 (0x8cb) - DRC1RMIX Input 2 Volume */ + { 0x000008cc, 0x0000 }, /* R2252 (0x8cc) - DRC1RMIX Input 3 Source */ + { 0x000008cd, 0x0080 }, /* R2253 (0x8cd) - DRC1RMIX Input 3 Volume */ + { 0x000008ce, 0x0000 }, /* R2254 (0x8ce) - DRC1RMIX Input 4 Source */ + { 0x000008cf, 0x0080 }, /* R2255 (0x8cf) - DRC1RMIX Input 4 Volume */ + { 0x000008d0, 0x0000 }, /* R2256 (0x8d0) - DRC2LMIX Input 1 Source */ + { 0x000008d1, 0x0080 }, /* R2257 (0x8d1) - DRC2LMIX Input 1 Volume */ + { 0x000008d2, 0x0000 }, /* R2258 (0x8d2) - DRC2LMIX Input 2 Source */ + { 0x000008d3, 0x0080 }, /* R2259 (0x8d3) - DRC2LMIX Input 2 Volume */ + { 0x000008d4, 0x0000 }, /* R2260 (0x8d4) - DRC2LMIX Input 3 Source */ + { 0x000008d5, 0x0080 }, /* R2261 (0x8d5) - DRC2LMIX Input 3 Volume */ + { 0x000008d6, 0x0000 }, /* R2262 (0x8d6) - DRC2LMIX Input 4 Source */ + { 0x000008d7, 0x0080 }, /* R2263 (0x8d7) - DRC2LMIX Input 4 Volume */ + { 0x000008d8, 0x0000 }, /* R2264 (0x8d8) - DRC2RMIX Input 1 Source */ + { 0x000008d9, 0x0080 }, /* R2265 (0x8d9) - DRC2RMIX Input 1 Volume */ + { 0x000008da, 0x0000 }, /* R2266 (0x8da) - DRC2RMIX Input 2 Source */ + { 0x000008db, 0x0080 }, /* R2267 (0x8db) - DRC2RMIX Input 2 Volume */ + { 0x000008dc, 0x0000 }, /* R2268 (0x8dc) - DRC2RMIX Input 3 Source */ + { 0x000008dd, 0x0080 }, /* R2269 (0x8dd) - DRC2RMIX Input 3 Volume */ + { 0x000008de, 0x0000 }, /* R2270 (0x8de) - DRC2RMIX Input 4 Source */ + { 0x000008df, 0x0080 }, /* R2271 (0x8df) - DRC2RMIX Input 4 Volume */ + { 0x00000900, 0x0000 }, /* R2304 (0x900) - HPLP1MIX Input 1 Source */ + { 0x00000901, 0x0080 }, /* R2305 (0x901) - HPLP1MIX Input 1 Volume */ + { 0x00000902, 0x0000 }, /* R2306 (0x902) - HPLP1MIX Input 2 Source */ + { 0x00000903, 0x0080 }, /* R2307 (0x903) - HPLP1MIX Input 2 Volume */ + { 0x00000904, 0x0000 }, /* R2308 (0x904) - HPLP1MIX Input 3 Source */ + { 0x00000905, 0x0080 }, /* R2309 (0x905) - HPLP1MIX Input 3 Volume */ + { 0x00000906, 0x0000 }, /* R2310 (0x906) - HPLP1MIX Input 4 Source */ + { 0x00000907, 0x0080 }, /* R2311 (0x907) - HPLP1MIX Input 4 Volume */ + { 0x00000908, 0x0000 }, /* R2312 (0x908) - HPLP2MIX Input 1 Source */ + { 0x00000909, 0x0080 }, /* R2313 (0x909) - HPLP2MIX Input 1 Volume */ + { 0x0000090a, 0x0000 }, /* R2314 (0x90a) - HPLP2MIX Input 2 Source */ + { 0x0000090b, 0x0080 }, /* R2315 (0x90b) - HPLP2MIX Input 2 Volume */ + { 0x0000090c, 0x0000 }, /* R2316 (0x90c) - HPLP2MIX Input 3 Source */ + { 0x0000090d, 0x0080 }, /* R2317 (0x90d) - HPLP2MIX Input 3 Volume */ + { 0x0000090e, 0x0000 }, /* R2318 (0x90e) - HPLP2MIX Input 4 Source */ + { 0x0000090f, 0x0080 }, /* R2319 (0x90f) - HPLP2MIX Input 4 Volume */ + { 0x00000910, 0x0000 }, /* R2320 (0x910) - HPLP3MIX Input 1 Source */ + { 0x00000911, 0x0080 }, /* R2321 (0x911) - HPLP3MIX Input 1 Volume */ + { 0x00000912, 0x0000 }, /* R2322 (0x912) - HPLP3MIX Input 2 Source */ + { 0x00000913, 0x0080 }, /* R2323 (0x913) - HPLP3MIX Input 2 Volume */ + { 0x00000914, 0x0000 }, /* R2324 (0x914) - HPLP3MIX Input 3 Source */ + { 0x00000915, 0x0080 }, /* R2325 (0x915) - HPLP3MIX Input 3 Volume */ + { 0x00000916, 0x0000 }, /* R2326 (0x916) - HPLP3MIX Input 4 Source */ + { 0x00000917, 0x0080 }, /* R2327 (0x917) - HPLP3MIX Input 4 Volume */ + { 0x00000918, 0x0000 }, /* R2328 (0x918) - HPLP4MIX Input 1 Source */ + { 0x00000919, 0x0080 }, /* R2329 (0x919) - HPLP4MIX Input 1 Volume */ + { 0x0000091a, 0x0000 }, /* R2330 (0x91a) - HPLP4MIX Input 2 Source */ + { 0x0000091b, 0x0080 }, /* R2331 (0x91b) - HPLP4MIX Input 2 Volume */ + { 0x0000091c, 0x0000 }, /* R2332 (0x91c) - HPLP4MIX Input 3 Source */ + { 0x0000091d, 0x0080 }, /* R2333 (0x91d) - HPLP4MIX Input 3 Volume */ + { 0x0000091e, 0x0000 }, /* R2334 (0x91e) - HPLP4MIX Input 4 Source */ + { 0x0000091f, 0x0080 }, /* R2335 (0x91f) - HPLP4MIX Input 4 Volume */ + { 0x00000940, 0x0000 }, /* R2368 (0x940) - DSP1LMIX Input 1 Source */ + { 0x00000941, 0x0080 }, /* R2369 (0x941) - DSP1LMIX Input 1 Volume */ + { 0x00000942, 0x0000 }, /* R2370 (0x942) - DSP1LMIX Input 2 Source */ + { 0x00000943, 0x0080 }, /* R2371 (0x943) - DSP1LMIX Input 2 Volume */ + { 0x00000944, 0x0000 }, /* R2372 (0x944) - DSP1LMIX Input 3 Source */ + { 0x00000945, 0x0080 }, /* R2373 (0x945) - DSP1LMIX Input 3 Volume */ + { 0x00000946, 0x0000 }, /* R2374 (0x946) - DSP1LMIX Input 4 Source */ + { 0x00000947, 0x0080 }, /* R2375 (0x947) - DSP1LMIX Input 4 Volume */ + { 0x00000948, 0x0000 }, /* R2376 (0x948) - DSP1RMIX Input 1 Source */ + { 0x00000949, 0x0080 }, /* R2377 (0x949) - DSP1RMIX Input 1 Volume */ + { 0x0000094a, 0x0000 }, /* R2378 (0x94a) - DSP1RMIX Input 2 Source */ + { 0x0000094b, 0x0080 }, /* R2379 (0x94b) - DSP1RMIX Input 2 Volume */ + { 0x0000094c, 0x0000 }, /* R2380 (0x94c) - DSP1RMIX Input 3 Source */ + { 0x0000094d, 0x0080 }, /* R2381 (0x94d) - DSP1RMIX Input 3 Volume */ + { 0x0000094e, 0x0000 }, /* R2382 (0x94e) - DSP1RMIX Input 4 Source */ + { 0x0000094f, 0x0080 }, /* R2383 (0x94f) - DSP1RMIX Input 4 Volume */ + { 0x00000950, 0x0000 }, /* R2384 (0x950) - DSP1AUX1MIX Input 1 Source */ + { 0x00000958, 0x0000 }, /* R2392 (0x958) - DSP1AUX2MIX Input 1 Source */ + { 0x00000960, 0x0000 }, /* R2400 (0x960) - DSP1AUX3MIX Input 1 Source */ + { 0x00000968, 0x0000 }, /* R2408 (0x968) - DSP1AUX4MIX Input 1 Source */ + { 0x00000970, 0x0000 }, /* R2416 (0x970) - DSP1AUX5MIX Input 1 Source */ + { 0x00000978, 0x0000 }, /* R2424 (0x978) - DSP1AUX6MIX Input 1 Source */ + { 0x00000980, 0x0000 }, /* R2432 (0x980) - DSP2LMIX Input 1 Source */ + { 0x00000981, 0x0080 }, /* R2433 (0x981) - DSP2LMIX Input 1 Volume */ + { 0x00000982, 0x0000 }, /* R2434 (0x982) - DSP2LMIX Input 2 Source */ + { 0x00000983, 0x0080 }, /* R2435 (0x983) - DSP2LMIX Input 2 Volume */ + { 0x00000984, 0x0000 }, /* R2436 (0x984) - DSP2LMIX Input 3 Source */ + { 0x00000985, 0x0080 }, /* R2437 (0x985) - DSP2LMIX Input 3 Volume */ + { 0x00000986, 0x0000 }, /* R2438 (0x986) - DSP2LMIX Input 4 Source */ + { 0x00000987, 0x0080 }, /* R2439 (0x987) - DSP2LMIX Input 4 Volume */ + { 0x00000988, 0x0000 }, /* R2440 (0x988) - DSP2RMIX Input 1 Source */ + { 0x00000989, 0x0080 }, /* R2441 (0x989) - DSP2RMIX Input 1 Volume */ + { 0x0000098a, 0x0000 }, /* R2442 (0x98a) - DSP2RMIX Input 2 Source */ + { 0x0000098b, 0x0080 }, /* R2443 (0x98b) - DSP2RMIX Input 2 Volume */ + { 0x0000098c, 0x0000 }, /* R2444 (0x98c) - DSP2RMIX Input 3 Source */ + { 0x0000098d, 0x0080 }, /* R2445 (0x98d) - DSP2RMIX Input 3 Volume */ + { 0x0000098e, 0x0000 }, /* R2446 (0x98e) - DSP2RMIX Input 4 Source */ + { 0x0000098f, 0x0080 }, /* R2447 (0x98f) - DSP2RMIX Input 4 Volume */ + { 0x00000990, 0x0000 }, /* R2448 (0x990) - DSP2AUX1MIX Input 1 Source */ + { 0x00000998, 0x0000 }, /* R2456 (0x998) - DSP2AUX2MIX Input 1 Source */ + { 0x000009a0, 0x0000 }, /* R2464 (0x9a0) - DSP2AUX3MIX Input 1 Source */ + { 0x000009a8, 0x0000 }, /* R2472 (0x9a8) - DSP2AUX4MIX Input 1 Source */ + { 0x000009b0, 0x0000 }, /* R2480 (0x9b0) - DSP2AUX5MIX Input 1 Source */ + { 0x000009b8, 0x0000 }, /* R2488 (0x9b8) - DSP2AUX6MIX Input 1 Source */ + { 0x000009c0, 0x0000 }, /* R2496 (0x9c0) - DSP3LMIX Input 1 Source */ + { 0x000009c1, 0x0080 }, /* R2497 (0x9c1) - DSP3LMIX Input 1 Volume */ + { 0x000009c2, 0x0000 }, /* R2498 (0x9c2) - DSP3LMIX Input 2 Source */ + { 0x000009c3, 0x0080 }, /* R2499 (0x9c3) - DSP3LMIX Input 2 Volume */ + { 0x000009c4, 0x0000 }, /* R2500 (0x9c4) - DSP3LMIX Input 3 Source */ + { 0x000009c5, 0x0080 }, /* R2501 (0x9c5) - DSP3LMIX Input 3 Volume */ + { 0x000009c6, 0x0000 }, /* R2502 (0x9c6) - DSP3LMIX Input 4 Source */ + { 0x000009c7, 0x0080 }, /* R2503 (0x9c7) - DSP3LMIX Input 4 Volume */ + { 0x000009c8, 0x0000 }, /* R2504 (0x9c8) - DSP3RMIX Input 1 Source */ + { 0x000009c9, 0x0080 }, /* R2505 (0x9c9) - DSP3RMIX Input 1 Volume */ + { 0x000009ca, 0x0000 }, /* R2506 (0x9ca) - DSP3RMIX Input 2 Source */ + { 0x000009cb, 0x0080 }, /* R2507 (0x9cb) - DSP3RMIX Input 2 Volume */ + { 0x000009cc, 0x0000 }, /* R2508 (0x9cc) - DSP3RMIX Input 3 Source */ + { 0x000009cd, 0x0080 }, /* R2509 (0x9cd) - DSP3RMIX Input 3 Volume */ + { 0x000009ce, 0x0000 }, /* R2510 (0x9ce) - DSP3RMIX Input 4 Source */ + { 0x000009cf, 0x0080 }, /* R2511 (0x9cf) - DSP3RMIX Input 4 Volume */ + { 0x000009d0, 0x0000 }, /* R2512 (0x9d0) - DSP3AUX1MIX Input 1 Source */ + { 0x000009d8, 0x0000 }, /* R2520 (0x9d8) - DSP3AUX2MIX Input 1 Source */ + { 0x000009e0, 0x0000 }, /* R2528 (0x9e0) - DSP3AUX3MIX Input 1 Source */ + { 0x000009e8, 0x0000 }, /* R2536 (0x9e8) - DSP3AUX4MIX Input 1 Source */ + { 0x000009f0, 0x0000 }, /* R2544 (0x9f0) - DSP3AUX5MIX Input 1 Source */ + { 0x000009f8, 0x0000 }, /* R2552 (0x9f8) - DSP3AUX6MIX Input 1 Source */ + { 0x00000b00, 0x0000 }, /* R2816 (0xb00) - ISRC1DEC1MIX Input 1 Source*/ + { 0x00000b08, 0x0000 }, /* R2824 (0xb08) - ISRC1DEC2MIX Input 1 Source*/ + { 0x00000b10, 0x0000 }, /* R2832 (0xb10) - ISRC1DEC3MIX Input 1 Source*/ + { 0x00000b18, 0x0000 }, /* R2840 (0xb18) - ISRC1DEC4MIX Input 1 Source*/ + { 0x00000b20, 0x0000 }, /* R2848 (0xb20) - ISRC1INT1MIX Input 1 Source*/ + { 0x00000b28, 0x0000 }, /* R2856 (0xb28) - ISRC1INT2MIX Input 1 Source*/ + { 0x00000b30, 0x0000 }, /* R2864 (0xb30) - ISRC1INT3MIX Input 1 Source*/ + { 0x00000b38, 0x0000 }, /* R2872 (0xb38) - ISRC1INT4MIX Input 1 Source*/ + { 0x00000b40, 0x0000 }, /* R2880 (0xb40) - ISRC2DEC1MIX Input 1 Source*/ + { 0x00000b48, 0x0000 }, /* R2888 (0xb48) - ISRC2DEC2MIX Input 1 Source*/ + { 0x00000b50, 0x0000 }, /* R2896 (0xb50) - ISRC2DEC3MIX Input 1 Source*/ + { 0x00000b58, 0x0000 }, /* R2904 (0xb58) - ISRC2DEC4MIX Input 1 Source*/ + { 0x00000b60, 0x0000 }, /* R2912 (0xb60) - ISRC2INT1MIX Input 1 Source*/ + { 0x00000b68, 0x0000 }, /* R2920 (0xb68) - ISRC2INT2MIX Input 1 Source*/ + { 0x00000b70, 0x0000 }, /* R2928 (0xb70) - ISRC2INT3MIX Input 1 Source*/ + { 0x00000b78, 0x0000 }, /* R2936 (0xb78) - ISRC2INT4MIX Input 1 Source*/ + { 0x00000e00, 0x0000 }, /* R3584 (0xe00) - FX Ctrl1 */ + { 0x00000e10, 0x6318 }, /* R3600 (0xe10) - EQ1_1 */ + { 0x00000e11, 0x6300 }, /* R3601 (0xe11) - EQ1_2 */ + { 0x00000e12, 0x0fc8 }, /* R3602 (0xe12) - EQ1_3 */ + { 0x00000e13, 0x03fe }, /* R3603 (0xe13) - EQ1_4 */ + { 0x00000e14, 0x00e0 }, /* R3604 (0xe14) - EQ1_5 */ + { 0x00000e15, 0x1ec4 }, /* R3605 (0xe15) - EQ1_6 */ + { 0x00000e16, 0xf136 }, /* R3606 (0xe16) - EQ1_7 */ + { 0x00000e17, 0x0409 }, /* R3607 (0xe17) - EQ1_8 */ + { 0x00000e18, 0x04cc }, /* R3608 (0xe18) - EQ1_9 */ + { 0x00000e19, 0x1c9b }, /* R3609 (0xe19) - EQ1_10 */ + { 0x00000e1a, 0xf337 }, /* R3610 (0xe1a) - EQ1_11 */ + { 0x00000e1b, 0x040b }, /* R3611 (0xe1b) - EQ1_12 */ + { 0x00000e1c, 0x0cbb }, /* R3612 (0xe1c) - EQ1_13 */ + { 0x00000e1d, 0x16f8 }, /* R3613 (0xe1d) - EQ1_14 */ + { 0x00000e1e, 0xf7d9 }, /* R3614 (0xe1e) - EQ1_15 */ + { 0x00000e1f, 0x040a }, /* R3615 (0xe1f) - EQ1_16 */ + { 0x00000e20, 0x1f14 }, /* R3616 (0xe20) - EQ1_17 */ + { 0x00000e21, 0x058c }, /* R3617 (0xe21) - EQ1_18 */ + { 0x00000e22, 0x0563 }, /* R3618 (0xe22) - EQ1_19 */ + { 0x00000e23, 0x4000 }, /* R3619 (0xe23) - EQ1_20 */ + { 0x00000e24, 0x0b75 }, /* R3620 (0xe24) - EQ1_21 */ + { 0x00000e26, 0x6318 }, /* R3622 (0xe26) - EQ2_1 */ + { 0x00000e27, 0x6300 }, /* R3623 (0xe27) - EQ2_2 */ + { 0x00000e28, 0x0fc8 }, /* R3624 (0xe28) - EQ2_3 */ + { 0x00000e29, 0x03fe }, /* R3625 (0xe29) - EQ2_4 */ + { 0x00000e2a, 0x00e0 }, /* R3626 (0xe2a) - EQ2_5 */ + { 0x00000e2b, 0x1ec4 }, /* R3627 (0xe2b) - EQ2_6 */ + { 0x00000e2c, 0xf136 }, /* R3628 (0xe2c) - EQ2_7 */ + { 0x00000e2d, 0x0409 }, /* R3629 (0xe2d) - EQ2_8 */ + { 0x00000e2e, 0x04cc }, /* R3630 (0xe2e) - EQ2_9 */ + { 0x00000e2f, 0x1c9b }, /* R3631 (0xe2f) - EQ2_10 */ + { 0x00000e30, 0xf337 }, /* R3632 (0xe30) - EQ2_11 */ + { 0x00000e31, 0x040b }, /* R3633 (0xe31) - EQ2_12 */ + { 0x00000e32, 0x0cbb }, /* R3634 (0xe32) - EQ2_13 */ + { 0x00000e33, 0x16f8 }, /* R3635 (0xe33) - EQ2_14 */ + { 0x00000e34, 0xf7d9 }, /* R3636 (0xe34) - EQ2_15 */ + { 0x00000e35, 0x040a }, /* R3637 (0xe35) - EQ2_16 */ + { 0x00000e36, 0x1f14 }, /* R3638 (0xe36) - EQ2_17 */ + { 0x00000e37, 0x058c }, /* R3639 (0xe37) - EQ2_18 */ + { 0x00000e38, 0x0563 }, /* R3640 (0xe38) - EQ2_19 */ + { 0x00000e39, 0x4000 }, /* R3641 (0xe39) - EQ2_20 */ + { 0x00000e3a, 0x0b75 }, /* R3642 (0xe3a) - EQ2_21 */ + { 0x00000e3c, 0x6318 }, /* R3644 (0xe3c) - EQ3_1 */ + { 0x00000e3d, 0x6300 }, /* R3645 (0xe3d) - EQ3_2 */ + { 0x00000e3e, 0x0fc8 }, /* R3646 (0xe3e) - EQ3_3 */ + { 0x00000e3f, 0x03fe }, /* R3647 (0xe3f) - EQ3_4 */ + { 0x00000e40, 0x00e0 }, /* R3648 (0xe40) - EQ3_5 */ + { 0x00000e41, 0x1ec4 }, /* R3649 (0xe41) - EQ3_6 */ + { 0x00000e42, 0xf136 }, /* R3650 (0xe42) - EQ3_7 */ + { 0x00000e43, 0x0409 }, /* R3651 (0xe43) - EQ3_8 */ + { 0x00000e44, 0x04cc }, /* R3652 (0xe44) - EQ3_9 */ + { 0x00000e45, 0x1c9b }, /* R3653 (0xe45) - EQ3_10 */ + { 0x00000e46, 0xf337 }, /* R3654 (0xe46) - EQ3_11 */ + { 0x00000e47, 0x040b }, /* R3655 (0xe47) - EQ3_12 */ + { 0x00000e48, 0x0cbb }, /* R3656 (0xe48) - EQ3_13 */ + { 0x00000e49, 0x16f8 }, /* R3657 (0xe49) - EQ3_14 */ + { 0x00000e4a, 0xf7d9 }, /* R3658 (0xe4a) - EQ3_15 */ + { 0x00000e4b, 0x040a }, /* R3659 (0xe4b) - EQ3_16 */ + { 0x00000e4c, 0x1f14 }, /* R3660 (0xe4c) - EQ3_17 */ + { 0x00000e4d, 0x058c }, /* R3661 (0xe4d) - EQ3_18 */ + { 0x00000e4e, 0x0563 }, /* R3662 (0xe4e) - EQ3_19 */ + { 0x00000e4f, 0x4000 }, /* R3663 (0xe4f) - EQ3_20 */ + { 0x00000e50, 0x0b75 }, /* R3664 (0xe50) - EQ3_21 */ + { 0x00000e52, 0x6318 }, /* R3666 (0xe52) - EQ4_1 */ + { 0x00000e53, 0x6300 }, /* R3667 (0xe53) - EQ4_2 */ + { 0x00000e54, 0x0fc8 }, /* R3668 (0xe54) - EQ4_3 */ + { 0x00000e55, 0x03fe }, /* R3669 (0xe55) - EQ4_4 */ + { 0x00000e56, 0x00e0 }, /* R3670 (0xe56) - EQ4_5 */ + { 0x00000e57, 0x1ec4 }, /* R3671 (0xe57) - EQ4_6 */ + { 0x00000e58, 0xf136 }, /* R3672 (0xe58) - EQ4_7 */ + { 0x00000e59, 0x0409 }, /* R3673 (0xe59) - EQ4_8 */ + { 0x00000e5a, 0x04cc }, /* R3674 (0xe5a) - EQ4_9 */ + { 0x00000e5b, 0x1c9b }, /* R3675 (0xe5b) - EQ4_10 */ + { 0x00000e5c, 0xf337 }, /* R3676 (0xe5c) - EQ4_11 */ + { 0x00000e5d, 0x040b }, /* R3677 (0xe5d) - EQ4_12 */ + { 0x00000e5e, 0x0cbb }, /* R3678 (0xe5e) - EQ4_13 */ + { 0x00000e5f, 0x16f8 }, /* R3679 (0xe5f) - EQ4_14 */ + { 0x00000e60, 0xf7d9 }, /* R3680 (0xe60) - EQ4_15 */ + { 0x00000e61, 0x040a }, /* R3681 (0xe61) - EQ4_16 */ + { 0x00000e62, 0x1f14 }, /* R3682 (0xe62) - EQ4_17 */ + { 0x00000e63, 0x058c }, /* R3683 (0xe63) - EQ4_18 */ + { 0x00000e64, 0x0563 }, /* R3684 (0xe64) - EQ4_19 */ + { 0x00000e65, 0x4000 }, /* R3685 (0xe65) - EQ4_20 */ + { 0x00000e66, 0x0b75 }, /* R3686 (0xe66) - EQ4_21 */ + { 0x00000e80, 0x0018 }, /* R3712 (0xe80) - DRC1 ctrl1 */ + { 0x00000e81, 0x0933 }, /* R3713 (0xe81) - DRC1 ctrl2 */ + { 0x00000e82, 0x0018 }, /* R3714 (0xe82) - DRC1 ctrl3 */ + { 0x00000e83, 0x0000 }, /* R3715 (0xe83) - DRC1 ctrl4 */ + { 0x00000e84, 0x0000 }, /* R3716 (0xe84) - DRC1 ctrl5 */ + { 0x00000e88, 0x0018 }, /* R3720 (0xe88) - DRC2 ctrl1 */ + { 0x00000e89, 0x0933 }, /* R3721 (0xe89) - DRC2 ctrl2 */ + { 0x00000e8a, 0x0018 }, /* R3722 (0xe8a) - DRC2 ctrl3 */ + { 0x00000e8b, 0x0000 }, /* R3723 (0xe8b) - DRC2 ctrl4 */ + { 0x00000e8c, 0x0000 }, /* R3724 (0xe8c) - DRC2 ctrl5 */ + { 0x00000ec0, 0x0000 }, /* R3776 (0xec0) - HPLPF1_1 */ + { 0x00000ec1, 0x0000 }, /* R3777 (0xec1) - HPLPF1_2 */ + { 0x00000ec4, 0x0000 }, /* R3780 (0xec4) - HPLPF2_1 */ + { 0x00000ec5, 0x0000 }, /* R3781 (0xec5) - HPLPF2_2 */ + { 0x00000ec8, 0x0000 }, /* R3784 (0xec8) - HPLPF3_1 */ + { 0x00000ec9, 0x0000 }, /* R3785 (0xec9) - HPLPF3_2 */ + { 0x00000ecc, 0x0000 }, /* R3788 (0xecc) - HPLPF4_1 */ + { 0x00000ecd, 0x0000 }, /* R3789 (0xecd) - HPLPF4_2 */ + { 0x00000ef0, 0x0000 }, /* R3824 (0xef0) - ISRC 1 CTRL 1 */ + { 0x00000ef1, 0x0001 }, /* R3825 (0xef1) - ISRC 1 CTRL 2 */ + { 0x00000ef2, 0x0000 }, /* R3826 (0xef2) - ISRC 1 CTRL 3 */ + { 0x00000ef3, 0x0000 }, /* R3827 (0xef3) - ISRC 2 CTRL 1 */ + { 0x00000ef4, 0x0001 }, /* R3828 (0xef4) - ISRC 2 CTRL 2 */ + { 0x00000ef5, 0x0000 }, /* R3829 (0xef5) - ISRC 2 CTRL 3 */ + { 0x00001300, 0x0000 }, /* R4864 (0x1300) - DAC Comp 1 */ + { 0x00001302, 0x0000 }, /* R4866 (0x1302) - DAC Comp 2 */ + { 0x00001380, 0x0000 }, /* R4992 (0x1380) - FRF Coefficient 1L 1 */ + { 0x00001381, 0x0000 }, /* R4993 (0x1381) - FRF Coefficient 1L 2 */ + { 0x00001382, 0x0000 }, /* R4994 (0x1382) - FRF Coefficient 1L 3 */ + { 0x00001383, 0x0000 }, /* R4995 (0x1383) - FRF Coefficient 1L 4 */ + { 0x00001390, 0x0000 }, /* R5008 (0x1390) - FRF Coefficient 1R 1 */ + { 0x00001391, 0x0000 }, /* R5009 (0x1391) - FRF Coefficient 1R 2 */ + { 0x00001392, 0x0000 }, /* R5010 (0x1392) - FRF Coefficient 1R 3 */ + { 0x00001393, 0x0000 }, /* R5011 (0x1393) - FRF Coefficient 1R 4 */ + { 0x000013a0, 0x0000 }, /* R5024 (0x13a0) - FRF Coefficient 4L 1 */ + { 0x000013a1, 0x0000 }, /* R5025 (0x13a1) - FRF Coefficient 4L 2 */ + { 0x000013a2, 0x0000 }, /* R5026 (0x13a2) - FRF Coefficient 4L 3 */ + { 0x000013a3, 0x0000 }, /* R5027 (0x13a3) - FRF Coefficient 4L 4 */ + { 0x000013b0, 0x0000 }, /* R5040 (0x13b0) - FRF Coefficient 5L 1 */ + { 0x000013b1, 0x0000 }, /* R5041 (0x13b1) - FRF Coefficient 5L 2 */ + { 0x000013b2, 0x0000 }, /* R5042 (0x13b2) - FRF Coefficient 5L 3 */ + { 0x000013b3, 0x0000 }, /* R5043 (0x13b3) - FRF Coefficient 5L 4 */ + { 0x000013c0, 0x0000 }, /* R5040 (0x13c0) - FRF Coefficient 5R 1 */ + { 0x000013c1, 0x0000 }, /* R5041 (0x13c1) - FRF Coefficient 5R 2 */ + { 0x000013c2, 0x0000 }, /* R5042 (0x13c2) - FRF Coefficient 5R 3 */ + { 0x000013c3, 0x0000 }, /* R5043 (0x13c3) - FRF Coefficient 5R 4 */ + { 0x00001701, 0xf000 }, /* R5889 (0x1701) - GPIO1 Control 2 */ + { 0x00001703, 0xf000 }, /* R5891 (0x1703) - GPIO2 Control 2 */ + { 0x00001705, 0xf000 }, /* R5893 (0x1705) - GPIO3 Control 2 */ + { 0x00001707, 0xf000 }, /* R5895 (0x1707) - GPIO4 Control 2 */ + { 0x00001709, 0xf000 }, /* R5897 (0x1709) - GPIO5 Control 2 */ + { 0x0000170b, 0xf000 }, /* R5899 (0x170b) - GPIO6 Control 2 */ + { 0x0000170d, 0xf000 }, /* R5901 (0x170d) - GPIO7 Control 2 */ + { 0x0000170f, 0xf000 }, /* R5903 (0x170f) - GPIO8 Control 2 */ + { 0x00001711, 0xf000 }, /* R5905 (0x1711) - GPIO9 Control 2 */ + { 0x00001713, 0xf000 }, /* R5907 (0x1713) - GPIO10 Control 2 */ + { 0x00001715, 0xf000 }, /* R5909 (0x1715) - GPIO11 Control 2 */ + { 0x00001717, 0xf000 }, /* R5911 (0x1717) - GPIO12 Control 2 */ + { 0x00001719, 0xf000 }, /* R5913 (0x1719) - GPIO13 Control 2 */ + { 0x0000171B, 0xf000 }, /* R5915 (0x171B) - GPIO14 Control 2 */ + { 0x0000171D, 0xf000 }, /* R5917 (0x171D) - GPIO15 Control 2 */ + { 0x0000171F, 0xf000 }, /* R5919 (0x171F) - GPIO16 Control 2 */ + { 0x00001802, 0x0000 }, /* R6146 (0x1802) - IRQ1 Status 3 */ + { 0x00001803, 0x0000 }, /* R6147 (0x1803) - IRQ1 Status 4 */ + { 0x00001804, 0x0000 }, /* R6148 (0x1804) - IRQ1 Status 5 */ + { 0x00001807, 0x0000 }, /* R6151 (0x1807) - IRQ1 Status 8 */ + { 0x00001809, 0x0000 }, /* R6153 (0x1809) - IRQ1 Status 10 */ + { 0x0000180f, 0x0000 }, /* R6159 (0x180f) - IRQ1 Status 16 */ + { 0x00001811, 0x0000 }, /* R6161 (0x1811) - IRQ1 Status 18 */ + { 0x00001812, 0x0000 }, /* R6162 (0x1812) - IRQ1 Status 19 */ + { 0x00001813, 0x0000 }, /* R6163 (0x1813) - IRQ1 Status 20 */ + { 0x00001819, 0x0000 }, /* R6169 (0x1819) - IRQ1 Status 26 */ + { 0x0000181c, 0x0000 }, /* R6172 (0x181c) - IRQ1 Status 29 */ + { 0x00001840, 0xffff }, /* R6208 (0x1840) - IRQ1 Mask 1 */ + { 0x00001841, 0xffff }, /* R6209 (0x1841) - IRQ1 Mask 2 */ + { 0x00001842, 0xffff }, /* R6210 (0x1842) - IRQ1 Mask 3 */ + { 0x00001843, 0xffff }, /* R6211 (0x1843) - IRQ1 Mask 4 */ + { 0x00001844, 0xffff }, /* R6212 (0x1844) - IRQ1 Mask 5 */ + { 0x00001845, 0xffff }, /* R6213 (0x1845) - IRQ1 Mask 6 */ + { 0x00001846, 0xffff }, /* R6214 (0x1846) - IRQ1 Mask 7 */ + { 0x00001847, 0xffff }, /* R6215 (0x1847) - IRQ1 Mask 8 */ + { 0x00001848, 0xffff }, /* R6216 (0x1848) - IRQ1 Mask 9 */ + { 0x00001849, 0xffff }, /* R6217 (0x1849) - IRQ1 Mask 10 */ + { 0x0000184a, 0xffff }, /* R6218 (0x184a) - IRQ1 Mask 11 */ + { 0x0000184b, 0xffff }, /* R6219 (0x184b) - IRQ1 Mask 12 */ + { 0x0000184c, 0xffff }, /* R6220 (0x184c) - IRQ1 Mask 13 */ + { 0x0000184d, 0xffff }, /* R6221 (0x184d) - IRQ1 Mask 14 */ + { 0x0000184e, 0xffff }, /* R6222 (0x184e) - IRQ1 Mask 15 */ + { 0x0000184f, 0xffff }, /* R6223 (0x184f) - IRQ1 Mask 16 */ + { 0x00001850, 0xffff }, /* R6224 (0x1850) - IRQ1 Mask 17 */ + { 0x00001851, 0xffff }, /* R6225 (0x1851) - IRQ1 Mask 18 */ + { 0x00001852, 0xffff }, /* R6226 (0x1852) - IRQ1 Mask 19 */ + { 0x00001853, 0xffff }, /* R6227 (0x1853) - IRQ1 Mask 20 */ + { 0x00001854, 0xffff }, /* R6228 (0x1854) - IRQ1 Mask 21 */ + { 0x00001855, 0xffff }, /* R6229 (0x1855) - IRQ1 Mask 22 */ + { 0x00001856, 0xffff }, /* R6230 (0x1856) - IRQ1 Mask 23 */ + { 0x00001857, 0xffff }, /* R6231 (0x1857) - IRQ1 Mask 24 */ + { 0x00001858, 0xffff }, /* R6232 (0x1858) - IRQ1 Mask 25 */ + { 0x00001859, 0xffff }, /* R6233 (0x1859) - IRQ1 Mask 26 */ + { 0x0000185a, 0xffff }, /* R6234 (0x185a) - IRQ1 Mask 27 */ + { 0x0000185b, 0xffff }, /* R6235 (0x185b) - IRQ1 Mask 28 */ + { 0x0000185c, 0xffff }, /* R6236 (0x185c) - IRQ1 Mask 29 */ + { 0x0000185d, 0xffff }, /* R6237 (0x185d) - IRQ1 Mask 30 */ + { 0x0000185e, 0xffff }, /* R6238 (0x185e) - IRQ1 Mask 31 */ + { 0x0000185f, 0xffff }, /* R6239 (0x185f) - IRQ1 Mask 32 */ + { 0x00001948, 0xffff }, /* R6472 (0x1948) - IRQ2 Mask 9 */ + { 0x00001A06, 0x0000 }, /* R6662 (0x1a06) - Interrupt Debounce 7 */ + { 0x00001a80, 0x4400 }, /* R6784 (0x1a80) - IRQ1 CTRL */ +}; + +static bool marley_is_adsp_memory(struct device *dev, unsigned int reg) +{ + if ((reg >= 0x080000 && reg <= 0x085ffe) || + (reg >= 0x0a0000 && reg <= 0x0a7ffe) || + (reg >= 0x0c0000 && reg <= 0x0c1ffe) || + (reg >= 0x0e0000 && reg <= 0x0e1ffe) || + (reg >= 0x100000 && reg <= 0x10effe) || + (reg >= 0x120000 && reg <= 0x12bffe) || + (reg >= 0x136000 && reg <= 0x137ffe) || + (reg >= 0x140000 && reg <= 0x14bffe) || + (reg >= 0x160000 && reg <= 0x161ffe) || + (reg >= 0x180000 && reg <= 0x18effe) || + (reg >= 0x1a0000 && reg <= 0x1b1ffe) || + (reg >= 0x1b6000 && reg <= 0x1b7ffe) || + (reg >= 0x1c0000 && reg <= 0x1cbffe) || + (reg >= 0x1e0000 && reg <= 0x1e1ffe)) + return true; + else + return false; +} + +static bool marley_16bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_SPI_CFG_1: + case ARIZONA_CTRL_IF_I2C1_CFG_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case CLEARWATER_COMFORT_NOISE_GENERATOR: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case CLEARWATER_DSP_CLOCK_1: + case CLEARWATER_DSP_CLOCK_2: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_OUTPUT_ASYNC_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_CONTROL_7: + case ARIZONA_FLL1_LOOP_FILTER_TEST_1: + case ARIZONA_FLL1_NCO_TEST_0: + case MARLEY_FLL1_SYNCHRONISER_1: + case MARLEY_FLL1_SYNCHRONISER_2: + case MARLEY_FLL1_SYNCHRONISER_3: + case MARLEY_FLL1_SYNCHRONISER_4: + case MARLEY_FLL1_SYNCHRONISER_5: + case MARLEY_FLL1_SYNCHRONISER_6: + case MARLEY_FLL1_SYNCHRONISER_7: + case MARLEY_FLL1_SPREAD_SPECTRUM: + case MARLEY_FLL1_GPIO_CLOCK: + case ARIZONA_MIC_CHARGE_PUMP_1: + case CLEARWATER_CP_MODE: + case ARIZONA_LDO2_CONTROL_1: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_2: + case ARIZONA_MIC_BIAS_CTRL_5: + case ARIZONA_MIC_BIAS_CTRL_6: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_DCS_HP1L_CONTROL: + case ARIZONA_DCS_HP1R_CONTROL: + case CLEARWATER_EDRE_HP_STEREO_CONTROL: + case ARIZONA_ACCESSORY_DETECT_MODE_1: + case ARIZONA_HEADPHONE_DETECT_1: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case CLEARWATER_MICD_CLAMP_CONTROL: + case ARIZONA_MIC_DETECT_1: + case ARIZONA_MIC_DETECT_2: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_MIC_DETECT_LEVEL_1: + case ARIZONA_MIC_DETECT_LEVEL_2: + case ARIZONA_MIC_DETECT_LEVEL_3: + case ARIZONA_MIC_DETECT_LEVEL_4: + case ARIZONA_MIC_NOISE_MIX_CONTROL_1: + case CLEARWATER_GP_SWITCH_1: + case ARIZONA_JACK_DETECT_ANALOGUE: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case ARIZONA_IN2R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2R: + case ARIZONA_DMIC2R_CONTROL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_OUTPUT_PATH_CONFIG_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case ARIZONA_OUTPUT_PATH_CONFIG_4L: + case ARIZONA_DAC_DIGITAL_VOLUME_4L: + case ARIZONA_NOISE_GATE_SELECT_4L: + case ARIZONA_OUTPUT_PATH_CONFIG_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5L: + case ARIZONA_NOISE_GATE_SELECT_5L: + case ARIZONA_OUTPUT_PATH_CONFIG_5R: + case ARIZONA_DAC_DIGITAL_VOLUME_5R: + case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_DRE_ENABLE: + case CLEARWATER_EDRE_ENABLE: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_PDM_SPK1_CTRL_1: + case ARIZONA_PDM_SPK1_CTRL_2: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP_TEST_CTRL_5: + case ARIZONA_HP_TEST_CTRL_6: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_TX_BCLK_RATE: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_TX_BCLK_RATE: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_AIF3_BCLK_CTRL: + case ARIZONA_AIF3_TX_PIN_CTRL: + case ARIZONA_AIF3_RX_PIN_CTRL: + case ARIZONA_AIF3_RATE_CTRL: + case ARIZONA_AIF3_FORMAT: + case ARIZONA_AIF3_TX_BCLK_RATE: + case ARIZONA_AIF3_RX_BCLK_RATE: + case ARIZONA_AIF3_FRAME_CTRL_1: + case ARIZONA_AIF3_FRAME_CTRL_2: + case ARIZONA_AIF3_FRAME_CTRL_3: + case ARIZONA_AIF3_FRAME_CTRL_4: + case ARIZONA_AIF3_FRAME_CTRL_11: + case ARIZONA_AIF3_FRAME_CTRL_12: + case ARIZONA_AIF3_TX_ENABLES: + case ARIZONA_AIF3_RX_ENABLES: + case ARIZONA_SPD1_TX_CONTROL: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_FRAMER_REF_GEAR: + case ARIZONA_SLIMBUS_RATES_1: + case ARIZONA_SLIMBUS_RATES_2: + case ARIZONA_SLIMBUS_RATES_3: + case ARIZONA_SLIMBUS_RATES_5: + case ARIZONA_SLIMBUS_RATES_6: + case ARIZONA_SLIMBUS_RATES_7: + case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME: + case ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_2_SOURCE: + case ARIZONA_EQ1MIX_INPUT_2_VOLUME: + case ARIZONA_EQ1MIX_INPUT_3_SOURCE: + case ARIZONA_EQ1MIX_INPUT_3_VOLUME: + case ARIZONA_EQ1MIX_INPUT_4_SOURCE: + case ARIZONA_EQ1MIX_INPUT_4_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_2_SOURCE: + case ARIZONA_EQ2MIX_INPUT_2_VOLUME: + case ARIZONA_EQ2MIX_INPUT_3_SOURCE: + case ARIZONA_EQ2MIX_INPUT_3_VOLUME: + case ARIZONA_EQ2MIX_INPUT_4_SOURCE: + case ARIZONA_EQ2MIX_INPUT_4_VOLUME: + case ARIZONA_EQ3MIX_INPUT_1_SOURCE: + case ARIZONA_EQ3MIX_INPUT_1_VOLUME: + case ARIZONA_EQ3MIX_INPUT_2_SOURCE: + case ARIZONA_EQ3MIX_INPUT_2_VOLUME: + case ARIZONA_EQ3MIX_INPUT_3_SOURCE: + case ARIZONA_EQ3MIX_INPUT_3_VOLUME: + case ARIZONA_EQ3MIX_INPUT_4_SOURCE: + case ARIZONA_EQ3MIX_INPUT_4_VOLUME: + case ARIZONA_EQ4MIX_INPUT_1_SOURCE: + case ARIZONA_EQ4MIX_INPUT_1_VOLUME: + case ARIZONA_EQ4MIX_INPUT_2_SOURCE: + case ARIZONA_EQ4MIX_INPUT_2_VOLUME: + case ARIZONA_EQ4MIX_INPUT_3_SOURCE: + case ARIZONA_EQ4MIX_INPUT_3_VOLUME: + case ARIZONA_EQ4MIX_INPUT_4_SOURCE: + case ARIZONA_EQ4MIX_INPUT_4_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_4_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_EQ3_1: + case ARIZONA_EQ3_2: + case ARIZONA_EQ3_3: + case ARIZONA_EQ3_4: + case ARIZONA_EQ3_5: + case ARIZONA_EQ3_6: + case ARIZONA_EQ3_7: + case ARIZONA_EQ3_8: + case ARIZONA_EQ3_9: + case ARIZONA_EQ3_10: + case ARIZONA_EQ3_11: + case ARIZONA_EQ3_12: + case ARIZONA_EQ3_13: + case ARIZONA_EQ3_14: + case ARIZONA_EQ3_15: + case ARIZONA_EQ3_16: + case ARIZONA_EQ3_17: + case ARIZONA_EQ3_18: + case ARIZONA_EQ3_19: + case ARIZONA_EQ3_20: + case ARIZONA_EQ3_21: + case ARIZONA_EQ4_1: + case ARIZONA_EQ4_2: + case ARIZONA_EQ4_3: + case ARIZONA_EQ4_4: + case ARIZONA_EQ4_5: + case ARIZONA_EQ4_6: + case ARIZONA_EQ4_7: + case ARIZONA_EQ4_8: + case ARIZONA_EQ4_9: + case ARIZONA_EQ4_10: + case ARIZONA_EQ4_11: + case ARIZONA_EQ4_12: + case ARIZONA_EQ4_13: + case ARIZONA_EQ4_14: + case ARIZONA_EQ4_15: + case ARIZONA_EQ4_16: + case ARIZONA_EQ4_17: + case ARIZONA_EQ4_18: + case ARIZONA_EQ4_19: + case ARIZONA_EQ4_20: + case ARIZONA_EQ4_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case CLEARWATER_DRC2_CTRL1: + case CLEARWATER_DRC2_CTRL2: + case CLEARWATER_DRC2_CTRL3: + case CLEARWATER_DRC2_CTRL4: + case CLEARWATER_DRC2_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + case CLEARWATER_DAC_COMP_1: + case CLEARWATER_DAC_COMP_2: + case CLEARWATER_FRF_COEFFICIENT_1L_1: + case CLEARWATER_FRF_COEFFICIENT_1L_2: + case CLEARWATER_FRF_COEFFICIENT_1L_3: + case CLEARWATER_FRF_COEFFICIENT_1L_4: + case CLEARWATER_FRF_COEFFICIENT_1R_1: + case CLEARWATER_FRF_COEFFICIENT_1R_2: + case CLEARWATER_FRF_COEFFICIENT_1R_3: + case CLEARWATER_FRF_COEFFICIENT_1R_4: + case MARLEY_FRF_COEFFICIENT_4L_1: + case MARLEY_FRF_COEFFICIENT_4L_2: + case MARLEY_FRF_COEFFICIENT_4L_3: + case MARLEY_FRF_COEFFICIENT_4L_4: + case MARLEY_FRF_COEFFICIENT_5L_1: + case MARLEY_FRF_COEFFICIENT_5L_2: + case MARLEY_FRF_COEFFICIENT_5L_3: + case MARLEY_FRF_COEFFICIENT_5L_4: + case MARLEY_FRF_COEFFICIENT_5R_1: + case MARLEY_FRF_COEFFICIENT_5R_2: + case MARLEY_FRF_COEFFICIENT_5R_3: + case MARLEY_FRF_COEFFICIENT_5R_4: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO1_CTRL_2: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO2_CTRL_2: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO3_CTRL_2: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO4_CTRL_2: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO5_CTRL_2: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO6_CTRL_2: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO7_CTRL_2: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO8_CTRL_2: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO9_CTRL_2: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO10_CTRL_2: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO11_CTRL_2: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO12_CTRL_2: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO13_CTRL_2: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO14_CTRL_2: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO15_CTRL_2: + case CLEARWATER_GPIO16_CTRL_1: + case CLEARWATER_GPIO16_CTRL_2: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_3: + case CLEARWATER_IRQ1_STATUS_4: + case CLEARWATER_IRQ1_STATUS_5: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_8: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_10: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_16: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_20: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_26: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_29: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case CLEARWATER_IRQ1_MASK_1: + case CLEARWATER_IRQ1_MASK_2: + case CLEARWATER_IRQ1_MASK_3: + case CLEARWATER_IRQ1_MASK_4: + case CLEARWATER_IRQ1_MASK_5: + case CLEARWATER_IRQ1_MASK_6: + case CLEARWATER_IRQ1_MASK_7: + case CLEARWATER_IRQ1_MASK_8: + case CLEARWATER_IRQ1_MASK_9: + case CLEARWATER_IRQ1_MASK_10: + case CLEARWATER_IRQ1_MASK_11: + case CLEARWATER_IRQ1_MASK_12: + case CLEARWATER_IRQ1_MASK_13: + case CLEARWATER_IRQ1_MASK_14: + case CLEARWATER_IRQ1_MASK_15: + case MOON_IRQ1_MASK_16: + case CLEARWATER_IRQ1_MASK_17: + case CLEARWATER_IRQ1_MASK_18: + case CLEARWATER_IRQ1_MASK_19: + case MOON_IRQ1_MASK_20: + case CLEARWATER_IRQ1_MASK_21: + case CLEARWATER_IRQ1_MASK_22: + case CLEARWATER_IRQ1_MASK_23: + case CLEARWATER_IRQ1_MASK_24: + case CLEARWATER_IRQ1_MASK_25: + case MOON_IRQ1_MASK_26: + case CLEARWATER_IRQ1_MASK_27: + case CLEARWATER_IRQ1_MASK_28: + case MOON_IRQ1_MASK_29: + case CLEARWATER_IRQ1_MASK_30: + case CLEARWATER_IRQ1_MASK_31: + case CLEARWATER_IRQ1_MASK_32: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_MASK_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + case CLEARWATER_INTERRUPT_DEBOUNCE_7: + case CLEARWATER_IRQ1_CTRL: + return true; + default: + return false; + } +} + +static bool marley_16bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_DCS_HP1L_CONTROL: + case ARIZONA_DCS_HP1R_CONTROL: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_FX_CTRL2: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO16_CTRL_1: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + return true; + default: + return false; + } +} + +static bool marley_32bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_252: + case MARLEY_OTP_HPDET_CALIB_1 ... MARLEY_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... CLEARWATER_DSP1_SCRATCH_2_3: + case CLEARWATER_DSP2_CONFIG ... CLEARWATER_DSP2_SCRATCH_2_3: + case CLEARWATER_DSP3_CONFIG ... CLEARWATER_DSP3_SCRATCH_2_3: + return true; + default: + return marley_is_adsp_memory(dev, reg); + } +} + +static bool marley_32bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_252: + case MARLEY_OTP_HPDET_CALIB_1 ... MARLEY_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... CLEARWATER_DSP1_SCRATCH_2_3: + case CLEARWATER_DSP2_CONFIG ... CLEARWATER_DSP2_SCRATCH_2_3: + case CLEARWATER_DSP3_CONFIG ... CLEARWATER_DSP3_SCRATCH_2_3: + return true; + default: + return marley_is_adsp_memory(dev, reg); + } +} + +const struct regmap_config marley_16bit_spi_regmap = { + .name = "marley_16bit", + .reg_bits = 32, + .pad_bits = 16, + .val_bits = 16, + + .max_register = 0x1b00, + .readable_reg = marley_16bit_readable_register, + .volatile_reg = marley_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = marley_reg_default, + .num_reg_defaults = ARRAY_SIZE(marley_reg_default), +}; +EXPORT_SYMBOL_GPL(marley_16bit_spi_regmap); + +const struct regmap_config marley_16bit_i2c_regmap = { + .name = "marley_16bit", + .reg_bits = 32, + .val_bits = 16, + + .max_register = 0x1b00, + .readable_reg = marley_16bit_readable_register, + .volatile_reg = marley_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = marley_reg_default, + .num_reg_defaults = ARRAY_SIZE(marley_reg_default), +}; +EXPORT_SYMBOL_GPL(marley_16bit_i2c_regmap); + +const struct regmap_config marley_32bit_spi_regmap = { + .name = "marley_32bit", + .reg_bits = 32, + .reg_stride = 2, + .pad_bits = 16, + .val_bits = 32, + + .max_register = CLEARWATER_DSP3_SCRATCH_2_3, + .readable_reg = marley_32bit_readable_register, + .volatile_reg = marley_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(marley_32bit_spi_regmap); + +const struct regmap_config marley_32bit_i2c_regmap = { + .name = "marley_32bit", + .reg_bits = 32, + .reg_stride = 2, + .val_bits = 32, + + .max_register = CLEARWATER_DSP3_SCRATCH_2_3, + .readable_reg = marley_32bit_readable_register, + .volatile_reg = marley_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(marley_32bit_i2c_regmap); diff --git a/drivers/mfd/moon-tables.c b/drivers/mfd/moon-tables.c new file mode 100644 index 00000000000..09ebd9f4803 --- /dev/null +++ b/drivers/mfd/moon-tables.c @@ -0,0 +1,3083 @@ +/* + * moon-tables.c -- data tables for MOON class codecs + * + * Copyright 2015 Cirrus Logic + * + * Author: Nikesh Oswal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include + +#include "arizona.h" + +static const struct reg_sequence moon_reva_16_patch[] = { + { 0x8A, 0x5555 }, + { 0x8A, 0xAAAA }, + { 0x4CF, 0x0700 }, + { 0x171, 0x0003 }, + { 0x101, 0x0444 }, + { 0x159, 0x0002 }, + { 0x120, 0x0444 }, + { 0x1D1, 0x0004 }, + { 0x1E0, 0xC084 }, + { 0x159, 0x0000 }, + { 0x120, 0x0404 }, + { 0x101, 0x0404 }, + { 0x171, 0x0002 }, + { 0x17A, 0x2906 }, + { 0x19A, 0x2906 }, + { 0x441, 0xC750 }, + { 0x340, 0x0001 }, + { 0x112, 0x0405 }, + { 0x124, 0x0C49 }, + { 0x1300, 0x050E }, + { 0x1302, 0x0101 }, + { 0x1380, 0x0425 }, + { 0x1381, 0xF6D8 }, + { 0x1382, 0x0632 }, + { 0x1383, 0xFEC8 }, + { 0x1390, 0x042F }, + { 0x1391, 0xF6CA }, + { 0x1392, 0x0637 }, + { 0x1393, 0xFEC8 }, + { 0x281, 0x0000 }, + { 0x282, 0x0000 }, + { 0x4EA, 0x0100 }, + { 0x8A, 0xCCCC }, + { 0x8A, 0x3333 }, +}; + +/* We use a function so we can use ARRAY_SIZE() */ +int moon_patch(struct arizona *arizona) +{ + int ret; + const struct reg_default *patch16 = NULL; + unsigned int num16; + + patch16 = moon_reva_16_patch; + num16 = ARRAY_SIZE(moon_reva_16_patch); + + if (patch16) { + ret = regmap_register_patch(arizona->regmap, patch16, num16); + if (ret < 0) { + dev_err(arizona->dev, + "Error in applying 16-bit patch: %d\n", ret); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(moon_patch); + +static const struct regmap_irq moon_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_BOOT_DONE] = { .reg_offset = 0, + .mask = CLEARWATER_BOOT_DONE_EINT1 }, + [ARIZONA_IRQ_CTRLIF_ERR] = { .reg_offset = 0, + .mask = CLEARWATER_CTRLIF_ERR_EINT1 }, + + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL1_LOCK_EINT1 }, + [ARIZONA_IRQ_FLL2_CLOCK_OK] = { .reg_offset = 1, + .mask = CLEARWATER_FLL2_LOCK_EINT1}, + [MOON_IRQ_FLLAO_CLOCK_OK] = { .reg_offset = 1, + .mask = MOON_FLLAO_LOCK_EINT1}, + + [ARIZONA_IRQ_MICDET] = { .reg_offset = 5, + .mask = CLEARWATER_MICDET_EINT1 }, + [MOON_IRQ_MICDET2] = { .reg_offset = 5, + .mask = MOON_MICDET2_EINT1 }, + [ARIZONA_IRQ_HPDET] = { .reg_offset = 5, + .mask = CLEARWATER_HPDET_EINT1}, + + [ARIZONA_IRQ_MICD_CLAMP_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_RISE_EINT1 }, + [ARIZONA_IRQ_MICD_CLAMP_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_MICD_CLAMP_FALL_EINT1 }, + [ARIZONA_IRQ_JD_FALL] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_FALL_EINT1 }, + [ARIZONA_IRQ_JD_RISE] = { .reg_offset = 6, + .mask = CLEARWATER_JD1_RISE_EINT1 }, + + [ARIZONA_IRQ_ASRC2_LOCK] = { .reg_offset = 8, + .mask = CLEARWATER_ASRC2_IN1_LOCK_EINT1 }, + [ARIZONA_IRQ_ASRC1_LOCK] = { .reg_offset = 8, + .mask = CLEARWATER_ASRC1_IN1_LOCK_EINT1 }, + [ARIZONA_IRQ_DRC2_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC2_SIG_DET_EINT1 }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { .reg_offset = 8, + .mask = CLEARWATER_DRC1_SIG_DET_EINT1 }, + + [ARIZONA_IRQ_DSP_IRQ1] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ1_EINT1}, + [ARIZONA_IRQ_DSP_IRQ2] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ2_EINT1}, + [ARIZONA_IRQ_DSP_IRQ3] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ3_EINT1}, + [ARIZONA_IRQ_DSP_IRQ4] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ4_EINT1}, + [ARIZONA_IRQ_DSP_IRQ5] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ5_EINT1}, + [ARIZONA_IRQ_DSP_IRQ6] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ6_EINT1}, + [ARIZONA_IRQ_DSP_IRQ7] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ7_EINT1}, + [ARIZONA_IRQ_DSP_IRQ8] = { .reg_offset = 10, + .mask = CLEARWATER_DSP_IRQ8_EINT1}, + + [ARIZONA_IRQ_GP1] = { .reg_offset = 16, + .mask = CLEARWATER_GP1_EINT1}, + [ARIZONA_IRQ_GP2] = { .reg_offset = 16, + .mask = CLEARWATER_GP2_EINT1}, + [ARIZONA_IRQ_GP3] = { .reg_offset = 16, + .mask = CLEARWATER_GP3_EINT1}, + [ARIZONA_IRQ_GP4] = { .reg_offset = 16, + .mask = CLEARWATER_GP4_EINT1}, + [ARIZONA_IRQ_GP5] = { .reg_offset = 16, + .mask = CLEARWATER_GP5_EINT1}, + [ARIZONA_IRQ_GP6] = { .reg_offset = 16, + .mask = CLEARWATER_GP6_EINT1}, + [ARIZONA_IRQ_GP7] = { .reg_offset = 16, + .mask = CLEARWATER_GP7_EINT1}, + [ARIZONA_IRQ_GP8] = { .reg_offset = 16, + .mask = CLEARWATER_GP8_EINT1}, + + [MOON_IRQ_DSP1_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP1}, + [MOON_IRQ_DSP2_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP2}, + [MOON_IRQ_DSP3_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP3}, + [MOON_IRQ_DSP4_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP4}, + [MOON_IRQ_DSP5_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP5}, + [MOON_IRQ_DSP6_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP6}, + [MOON_IRQ_DSP7_BUS_ERROR] = { .reg_offset = 32, + .mask = MOON_ADSP_ERROR_STATUS_DSP7}, +}; + +const struct regmap_irq_chip moon_irq = { + .name = "moon IRQ", + .status_base = CLEARWATER_IRQ1_STATUS_1, + .mask_base = CLEARWATER_IRQ1_MASK_1, + .ack_base = CLEARWATER_IRQ1_STATUS_1, + .num_regs = 33, + .irqs = moon_irqs, + .num_irqs = ARRAY_SIZE(moon_irqs), +}; +EXPORT_SYMBOL_GPL(moon_irq); + +static const struct reg_default moon_reg_default[] = { + { 0x00000008, 0x0308 }, /* R8 - Ctrl IF CFG 1 */ + { 0x00000009, 0x0200 }, /* R9 - Ctrl IF CFG 2 */ + { 0x0000000A, 0x0308 }, /* R10 - Ctrl IF CFG 3 */ + { 0x00000020, 0x0000 }, /* R32 (0x20) - Tone Generator 1 */ + { 0x00000021, 0x1000 }, /* R33 (0x21) - Tone Generator 2 */ + { 0x00000022, 0x0000 }, /* R34 (0x22) - Tone Generator 3 */ + { 0x00000023, 0x1000 }, /* R35 (0x23) - Tone Generator 4 */ + { 0x00000024, 0x0000 }, /* R36 (0x24) - Tone Generator 5 */ + { 0x00000030, 0x0000 }, /* R48 (0x30) - PWM Drive 1 */ + { 0x00000031, 0x0100 }, /* R49 (0x31) - PWM Drive 2 */ + { 0x00000032, 0x0100 }, /* R50 (0x32) - PWM Drive 3 */ + { 0x00000041, 0x0000 }, /* R65 (0x41) - Sequence control */ + { 0x00000061, 0x01ff }, /* R97 (0x61) - Sample Rate Sequence Select 1 */ + { 0x00000062, 0x01ff }, /* R98 (0x62) - Sample Rate Sequence Select 2 */ + { 0x00000063, 0x01ff }, /* R99 (0x63) - Sample Rate Sequence Select 3 */ + { 0x00000064, 0x01ff }, /* R100 (0x64) - Sample Rate Sequence Select 4 */ + { 0x00000066, 0x01ff }, + { 0x00000067, 0x01ff }, + { 0x00000068, 0x01ff }, /* R104 (0x68) - Always On Triggers Sequence Select 1 */ + { 0x00000069, 0x01ff }, /* R105 (0x69) - Always On Triggers Sequence Select 2 */ + { 0x0000006a, 0x01ff }, /* R106 (0x6A) - Always On Triggers Sequence Select 3 */ + { 0x0000006b, 0x01ff }, /* R107 (0x6B) - Always On Triggers Sequence Select 4 */ + { 0x00000090, 0x0000 }, /* R144 (0x90) - Haptics Control 1 */ + { 0x00000091, 0x7fff }, /* R145 (0x91) - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 (0x92) - Haptics phase 1 intensity */ + { 0x00000093, 0x0000 }, /* R147 (0x93) - Haptics phase 1 duration */ + { 0x00000094, 0x0000 }, /* R148 (0x94) - Haptics phase 2 intensity */ + { 0x00000095, 0x0000 }, /* R149 (0x95) - Haptics phase 2 duration */ + { 0x00000096, 0x0000 }, /* R150 (0x96) - Haptics phase 3 intensity */ + { 0x00000097, 0x0000 }, /* R151 (0x97) - Haptics phase 3 duration */ + { 0x000000A0, 0x0000 }, /* R160 (0xA0) - Clearwater Comfort Noise Generator */ + { 0x00000100, 0x0002 }, /* R256 (0x100) - Clock 32k 1 */ + { 0x00000101, 0x0404 }, /* R257 (0x101) - System Clock 1 */ + { 0x00000102, 0x0011 }, /* R258 (0x102) - Sample rate 1 */ + { 0x00000103, 0x0011 }, /* R259 (0x103) - Sample rate 2 */ + { 0x00000104, 0x0011 }, /* R260 (0x104) - Sample rate 3 */ + { 0x00000112, 0x0405 }, /* R274 (0x112) - Async clock 1 */ + { 0x00000113, 0x0011 }, /* R275 (0x113) - Async sample rate 1 */ + { 0x00000114, 0x0011 }, /* R276 (0x114) - Async sample rate 2 */ + { 0x00000120, 0x0404 }, + { 0x00000122, 0x0000 }, + { 0x00000149, 0x0000 }, /* R329 (0x149) - Output system clock */ + { 0x0000014a, 0x0000 }, /* R330 (0x14A) - Output async clock */ + { 0x00000152, 0x0000 }, /* R338 (0x152) - Rate Estimator 1 */ + { 0x00000153, 0x0000 }, /* R339 (0x153) - Rate Estimator 2 */ + { 0x00000154, 0x0000 }, /* R340 (0x154) - Rate Estimator 3 */ + { 0x00000155, 0x0000 }, /* R341 (0x155) - Rate Estimator 4 */ + { 0x00000156, 0x0000 }, /* R342 (0x156) - Rate Estimator 5 */ + { 0x00000171, 0x0002 }, /* R369 (0x171) - FLL1 Control 1 */ + { 0x00000172, 0x0008 }, /* R370 (0x172) - FLL1 Control 2 */ + { 0x00000173, 0x0018 }, /* R371 (0x173) - FLL1 Control 3 */ + { 0x00000174, 0x007d }, /* R372 (0x174) - FLL1 Control 4 */ + { 0x00000175, 0x0000 }, /* R373 - FLL1 Control 5 */ + { 0x00000176, 0x0000 }, /* R374 (0x176) - FLL1 Control 6 */ + { 0x00000177, 0x0281 }, /* R375 (0x177) - FLL1 Loop Filter Test 1 */ + { 0x00000178, 0x0000 }, + { 0x00000179, 0x0000 }, /* R377 (0x179) - FLL1 Control 7 */ + { 0x0000017a, 0x2906 }, /* R377 (0x17A) - FLL1 Efs 2 */ + { 0x00000181, 0x0000 }, /* R385 (0x181) - FLL1 Synchroniser 1 */ + { 0x00000182, 0x0000 }, /* R386 (0x182) - FLL1 Synchroniser 2 */ + { 0x00000183, 0x0000 }, /* R387 (0x183) - FLL1 Synchroniser 3 */ + { 0x00000184, 0x0000 }, /* R388 (0x184) - FLL1 Synchroniser 4 */ + { 0x00000185, 0x0000 }, /* R389 (0x185) - FLL1 Synchroniser 5 */ + { 0x00000186, 0x0000 }, /* R390 (0x186) - FLL1 Synchroniser 6 */ + { 0x00000187, 0x0001 }, /* R391 (0x187) - FLL1 Synchroniser 7 */ + { 0x00000189, 0x0000 }, /* R393 (0x189) - FLL1 Spread Spectrum */ + { 0x0000018a, 0x0004 }, /* R394 (0x18A) - FLL1 GPIO Clock */ + { 0x00000191, 0x0002 }, /* R401 (0x191) - FLL2 Control 1 */ + { 0x00000192, 0x0008 }, /* R402 (0x192) - FLL2 Control 2 */ + { 0x00000193, 0x0018 }, /* R403 (0x193) - FLL2 Control 3 */ + { 0x00000194, 0x007d }, /* R404 (0x194) - FLL2 Control 4 */ + { 0x00000195, 0x0000 }, /* R405 - FLL2 Control 5 */ + { 0x00000196, 0x0000 }, /* R406 (0x196) - FLL2 Control 6 */ + { 0x00000197, 0x0281 }, /* R407 (0x197) - FLL2 Loop Filter Test 1 */ + { 0x00000198, 0x0000 }, + { 0x00000199, 0x0000 }, /* R409 (0x199) - FLL2 Control 7 */ + { 0x0000019a, 0x2906 }, /* R410 (0x19A) - FLL2 Efs 2 */ + { 0x000001a1, 0x0000 }, /* R417 (0x1A1) - FLL2 Synchroniser 1 */ + { 0x000001a2, 0x0000 }, /* R418 (0x1A2) - FLL2 Synchroniser 2 */ + { 0x000001a3, 0x0000 }, /* R419 (0x1A3) - FLL2 Synchroniser 3 */ + { 0x000001a4, 0x0000 }, /* R420 (0x1A4) - FLL2 Synchroniser 4 */ + { 0x000001a5, 0x0000 }, /* R421 (0x1A5) - FLL2 Synchroniser 5 */ + { 0x000001a6, 0x0000 }, /* R422 (0x1A6) - FLL2 Synchroniser 6 */ + { 0x000001a7, 0x0001 }, /* R423 (0x1A7) - FLL2 Synchroniser 7 */ + { 0x000001a9, 0x0000 }, /* R425 (0x1A9) - FLL2 Spread Spectrum */ + { 0x000001aa, 0x0004 }, /* R426 (0x1AA) - FLL2 GPIO Clock */ + { 0x000001D1, 0x0004 }, /* R465 - FLLAO_CONTROL_1 */ + { 0x000001D2, 0x0004 }, /* R466 - FLLAO_CONTROL_2 */ + { 0x000001D3, 0x0000 }, /* R467 - FLLAO_CONTROL_3 */ + { 0x000001D4, 0x0000 }, /* R468 - FLLAO_CONTROL_4 */ + { 0x000001D5, 0x0001 }, /* R469 - FLLAO_CONTROL_5 */ + { 0x000001D6, 0x8004 }, /* R470 - FLLAO_CONTROL_6 */ + { 0x000001D8, 0x0000 }, /* R472 - FLLAO_CONTROL_7 */ + { 0x000001DA, 0x0070 }, /* R474 - FLLAO_CONTROL_8 */ + { 0x000001DB, 0x0000 }, /* R475 - FLLAO_CONTROL_9 */ + { 0x000001DC, 0x06DA }, /* R476 - FLLAO_CONTROL_10 */ + { 0x000001DD, 0x0011 }, /* R477 - FLLAO_CONTROL_11 */ + { 0x00000200, 0x0006 }, /* R512 (0x200) - Mic Charge Pump 1 */ + { 0x00000213, 0x03e4 }, /* R531 (0x213) - LDO2 Control 1 */ + { 0x00000218, 0x00e6 }, /* R536 (0x218) - Mic Bias Ctrl 1 */ + { 0x00000219, 0x00e6 }, /* R537 (0x219) - Mic Bias Ctrl 2 */ + { 0x0000021C, 0x2222 }, /* R540 - Mic Bias Ctrl 5 */ + { 0x0000021E, 0x2222 }, /* R542 - Mic Bias Ctrl 6 */ + { 0x0000027e, 0x0000 }, /* R638 (0x27E) - Clearwater EDRE HP stereo control */ + { 0x00000293, 0x0080 }, /* R659 (0x293) - Accessory Detect Mode 1 */ + { 0x00000299, 0x0000 }, /* R665 (0x299) - Headphone Detect 0 */ + { 0x0000029b, 0x0000 }, /* R667 (0x29B) - Headphone Detect 1 */ + { 0x000002a2, 0x0010 }, /* R674 (0x2A2) - Mic Detect 0 */ + { 0x000002a3, 0x1102 }, /* R675 (0x2A3) - Mic Detect 1 */ + { 0x000002a4, 0x009f }, /* R676 (0x2A4) - Mic Detect 2 */ + { 0x000002a6, 0x3d3d }, + { 0x000002a7, 0x3d3d }, + { 0x000002a8, 0x333d }, + { 0x000002a9, 0x202d }, + { 0x000002b2, 0x0010 }, /* R690 (0x2B2) - MicDetect2-0 */ + { 0x000002b3, 0x1102 }, /* R691 (0x2B3) - MicDetect2-1 */ + { 0x000002b4, 0x009f }, /* R692 (0x2B4) - MicDetect2-2 */ + { 0x000002b6, 0x3D3D }, + { 0x000002b7, 0x3D3D }, + { 0x000002b8, 0x333D }, + { 0x000002b9, 0x202D }, + { 0x000002c6, 0x0010 }, + { 0x000002c8, 0x0000 }, /* R712 (0x2C8) - GP switch 1 */ + { 0x000002d3, 0x0000 }, /* R723 (0x2D3) - Jack detect analogue */ + { 0x00000300, 0x0000 }, /* R666 (0x300) - input_enable */ + { 0x00000308, 0x0400 }, /* R776 (0x308) - Input Rate */ + { 0x00000309, 0x0022 }, /* R777 (0x309) - Input Volume Ramp */ + { 0x0000030c, 0x0002 }, /* R780 (0x30C) - HPF Control */ + { 0x00000310, 0x0080 }, /* R784 (0x310) - IN1L Control */ + { 0x00000311, 0x0180 }, /* R785 (0x311) - ADC Digital Volume 1L */ + { 0x00000312, 0x0500 }, /* R786 (0x312) - DMIC1L Control */ + { 0x00000313, 0x0000 }, /* R787 (0x313) - IN1L Rate Control */ + { 0x00000314, 0x0080 }, /* R788 (0x314) - IN1R Control */ + { 0x00000315, 0x0180 }, /* R789 (0x315) - ADC Digital Volume 1R */ + { 0x00000316, 0x0000 }, /* R790 (0x316) - DMIC1R Control */ + { 0x00000317, 0x0000 }, /* R791 (0x317) - IN1R Rate Control */ + { 0x00000318, 0x0080 }, /* R792 (0x318) - IN2L Control */ + { 0x00000319, 0x0180 }, /* R793 (0x319) - ADC Digital Volume 2L */ + { 0x0000031a, 0x0500 }, /* R794 (0x31A) - DMIC2L Control */ + { 0x0000031b, 0x0000 }, /* R795 (0x31B) - IN2L Rate Control */ + { 0x0000031c, 0x0080 }, /* R796 (0x31C) - IN2R Control */ + { 0x0000031d, 0x0180 }, /* R797 (0x31D) - ADC Digital Volume 2R */ + { 0x0000031e, 0x0000 }, /* R798 (0x31E) - DMIC2R Control */ + { 0x0000031f, 0x0000 }, /* R799 (0x31F) - IN2R Rate Control */ + { 0x00000320, 0x0000 }, /* R800 (0x320) - IN3L Control */ + { 0x00000321, 0x0180 }, /* R801 (0x321) - ADC Digital Volume 3L */ + { 0x00000322, 0x0500 }, /* R802 (0x322) - DMIC3L Control */ + { 0x00000323, 0x0000 }, /* R803 (0x323) - IN3L Rate Control */ + { 0x00000324, 0x0000 }, /* R804 (0x324) - IN3R Control */ + { 0x00000325, 0x0180 }, /* R805 (0x325) - ADC Digital Volume 3R */ + { 0x00000326, 0x0000 }, /* R806 (0x326) - DMIC3R Control */ + { 0x00000327, 0x0000 }, /* R807 (0x327) - IN3R Rate Control */ + { 0x00000328, 0x0000 }, /* R808 (0x328) - IN4 Control */ + { 0x00000329, 0x0180 }, /* R809 (0x329) - ADC Digital Volume 4L */ + { 0x0000032a, 0x0500 }, /* R810 (0x32A) - DMIC4L Control */ + { 0x0000032b, 0x0000 }, /* R811 (0x32B) - IN4L Rate Control */ + { 0x0000032c, 0x0000 }, /* R812 (0x32C) - IN4R Control */ + { 0x0000032d, 0x0180 }, /* R813 (0x32D) - ADC Digital Volume 4R */ + { 0x0000032e, 0x0000 }, /* R814 (0x32E) - DMIC4R Control */ + { 0x0000032f, 0x0000 }, /* R815 (0x32F) - IN4R Rate Control */ + { 0x00000330, 0x0000 }, /* R816 - IN5L Control */ + { 0x00000331, 0x0180 }, /* R817 - ADC Digital Volume 5L */ + { 0x00000332, 0x0500 }, /* R818 - DMIC5L Control */ + { 0x00000333, 0x0000 }, /* R819 (0x333) - IN5L Rate Control */ + { 0x00000334, 0x0000 }, /* R820 - IN5R Control */ + { 0x00000335, 0x0180 }, /* R821 - ADC Digital Volume 5R */ + { 0x00000336, 0x0000 }, /* R822 - DMIC5R Control */ + { 0x00000337, 0x0000 }, /* R823 (0x337) - IN5R Rate Control */ + { 0x00000400, 0x0000 }, /* R1024 (0x400) - Output Enables 1 */ + { 0x00000408, 0x0000 }, /* R1032 (0x408) - Output Rate 1 */ + { 0x00000409, 0x0022 }, /* R1033 (0x409) - Output Volume Ramp */ + { 0x00000410, 0x0080 }, /* R1040 (0x410) - Output Path Config 1L */ + { 0x00000411, 0x0180 }, /* R1041 (0x411) - DAC Digital Volume 1L */ + { 0x00000412, 0x0000 }, /* R1042 (0x412) - moon_out1_config */ + { 0x00000413, 0x0001 }, /* R1043 (0x413) - Noise Gate Select 1L */ + { 0x00000414, 0x0080 }, /* R1044 (0x414) - Output Path Config 1R */ + { 0x00000415, 0x0180 }, /* R1045 (0x415) - DAC Digital Volume 1R */ + { 0x00000417, 0x0002 }, /* R1047 (0x417) - Noise Gate Select 1R */ + { 0x00000418, 0x0080 }, /* R1048 (0x418) - Output Path Config 2L */ + { 0x00000419, 0x0180 }, /* R1049 (0x419) - DAC Digital Volume 2L */ + { 0x0000041A, 0x0002 }, /* R1050 (0x41A) - moon_out2_config */ + { 0x0000041b, 0x0004 }, /* R1051 (0x41B) - Noise Gate Select 2L */ + { 0x0000041c, 0x0080 }, /* R1052 (0x41C) - Output Path Config 2R */ + { 0x0000041d, 0x0180 }, /* R1053 (0x41D) - DAC Digital Volume 2R */ + { 0x0000041f, 0x0008 }, /* R1055 (0x41F) - Noise Gate Select 2R */ + { 0x00000420, 0x0080 }, /* R1056 (0x420) - Output Path Config 3L */ + { 0x00000421, 0x0180 }, /* R1057 (0x421) - DAC Digital Volume 3L */ + { 0x00000423, 0x0010 }, /* R1059 (0x423) - Noise Gate Select 3L */ + { 0x00000424, 0x0080 }, /* R1060 (0x424) - Output Path Config 3R */ + { 0x00000425, 0x0180 }, /* R1061 (0x425) - DAC Digital Volume 3R */ + { 0x00000427, 0x0020 }, + { 0x00000430, 0x0000 }, /* R1072 (0x430) - Output Path Config 5L */ + { 0x00000431, 0x0180 }, /* R1073 (0x431) - DAC Digital Volume 5L */ + { 0x00000433, 0x0100 }, /* R1075 (0x433) - Noise Gate Select 5L */ + { 0x00000434, 0x0000 }, /* R1076 (0x434) - Output Path Config 5R */ + { 0x00000435, 0x0180 }, /* R1077 (0x435) - DAC Digital Volume 5R */ + { 0x00000437, 0x0200 }, /* R1079 (0x437) - Noise Gate Select 5R */ + { 0x00000440, 0x003f }, /* R1088 (0x440) - DRE Enable */ + { 0x00000448, 0x003f }, /* R1096 (0x448) - eDRE Enable */ + { 0x00000450, 0x0000 }, /* R1104 (0x450) - DAC AEC Control 1 */ + { 0x00000458, 0x0000 }, /* R1112 (0x458) - Noise Gate Control */ + { 0x00000490, 0x0069 }, /* R1168 (0x490) - PDM SPK1 CTRL 1 */ + { 0x00000491, 0x0000 }, /* R1169 (0x491) - PDM SPK1 CTRL 2 */ + { 0x000004A0, 0x3080 }, /* R1184 - HP1 Short Circuit Ctrl */ + { 0x000004A1, 0x3000 }, /* R1185 - HP2 Short Circuit Ctrl */ + { 0x000004A2, 0x3000 }, /* R1186 - HP3 Short Circuit Ctrl */ + { 0x000004A8, 0x7120 }, /* R1192 - HP Test Ctrl 5 */ + { 0x000004A9, 0x7120 }, /* R1193 - HP Test Ctrl 6 */ + { 0x00000500, 0x000c }, /* R1280 (0x500) - AIF1 BCLK Ctrl */ + { 0x00000501, 0x0000 }, /* R1281 (0x501) - AIF1 Tx Pin Ctrl */ + { 0x00000502, 0x0000 }, /* R1282 (0x502) - AIF1 Rx Pin Ctrl */ + { 0x00000503, 0x0000 }, /* R1283 (0x503) - AIF1 Rate Ctrl */ + { 0x00000504, 0x0000 }, /* R1284 (0x504) - AIF1 Format */ + { 0x00000505, 0x0040 }, /* R1285 (0x505) - AIF1 Tx BCLK Rate */ + { 0x00000506, 0x0040 }, /* R1286 (0x506) - AIF1 Rx BCLK Rate */ + { 0x00000507, 0x1818 }, /* R1287 (0x507) - AIF1 Frame Ctrl 1 */ + { 0x00000508, 0x1818 }, /* R1288 (0x508) - AIF1 Frame Ctrl 2 */ + { 0x00000509, 0x0000 }, /* R1289 (0x509) - AIF1 Frame Ctrl 3 */ + { 0x0000050a, 0x0001 }, /* R1290 (0x50A) - AIF1 Frame Ctrl 4 */ + { 0x0000050b, 0x0002 }, /* R1291 (0x50B) - AIF1 Frame Ctrl 5 */ + { 0x0000050c, 0x0003 }, /* R1292 (0x50C) - AIF1 Frame Ctrl 6 */ + { 0x0000050d, 0x0004 }, /* R1293 (0x50D) - AIF1 Frame Ctrl 7 */ + { 0x0000050e, 0x0005 }, /* R1294 (0x50E) - AIF1 Frame Ctrl 8 */ + { 0x0000050f, 0x0006 }, /* R1295 (0x50F) - AIF1 Frame Ctrl 9 */ + { 0x00000510, 0x0007 }, /* R1296 (0x510) - AIF1 Frame Ctrl 10 */ + { 0x00000511, 0x0000 }, /* R1297 (0x511) - AIF1 Frame Ctrl 11 */ + { 0x00000512, 0x0001 }, /* R1298 (0x512) - AIF1 Frame Ctrl 12 */ + { 0x00000513, 0x0002 }, /* R1299 (0x513) - AIF1 Frame Ctrl 13 */ + { 0x00000514, 0x0003 }, /* R1300 (0x514) - AIF1 Frame Ctrl 14 */ + { 0x00000515, 0x0004 }, /* R1301 (0x515) - AIF1 Frame Ctrl 15 */ + { 0x00000516, 0x0005 }, /* R1302 (0x516) - AIF1 Frame Ctrl 16 */ + { 0x00000517, 0x0006 }, /* R1303 (0x517) - AIF1 Frame Ctrl 17 */ + { 0x00000518, 0x0007 }, /* R1304 (0x518) - AIF1 Frame Ctrl 18 */ + { 0x00000519, 0x0000 }, /* R1305 (0x519) - AIF1 Tx Enables */ + { 0x0000051a, 0x0000 }, /* R1306 (0x51A) - AIF1 Rx Enables */ + { 0x00000540, 0x000c }, /* R1344 (0x540) - AIF2 BCLK Ctrl */ + { 0x00000541, 0x0000 }, /* R1345 (0x541) - AIF2 Tx Pin Ctrl */ + { 0x00000542, 0x0000 }, /* R1346 (0x542) - AIF2 Rx Pin Ctrl */ + { 0x00000543, 0x0000 }, /* R1347 (0x543) - AIF2 Rate Ctrl */ + { 0x00000544, 0x0000 }, /* R1348 (0x544) - AIF2 Format */ + { 0x00000545, 0x0040 }, /* R1349 (0x545) - AIF2 Tx BCLK Rate */ + { 0x00000546, 0x0040 }, /* R1350 (0x546) - AIF2 Rx BCLK Rate */ + { 0x00000547, 0x1818 }, /* R1351 (0x547) - AIF2 Frame Ctrl 1 */ + { 0x00000548, 0x1818 }, /* R1352 (0x548) - AIF2 Frame Ctrl 2 */ + { 0x00000549, 0x0000 }, /* R1353 (0x549) - AIF2 Frame Ctrl 3 */ + { 0x0000054a, 0x0001 }, /* R1354 (0x54A) - AIF2 Frame Ctrl 4 */ + { 0x0000054b, 0x0002 }, /* R1355 (0x54B) - AIF2 Frame Ctrl 5 */ + { 0x0000054c, 0x0003 }, /* R1356 (0x54C) - AIF2 Frame Ctrl 6 */ + { 0x0000054d, 0x0004 }, /* R1357 (0x54D) - AIF2 Frame Ctrl 7 */ + { 0x0000054e, 0x0005 }, /* R1358 (0x54E) - AIF2 Frame Ctrl 8 */ + { 0x0000054F, 0x0006 }, /* R1359 - AIF2 Frame Ctrl 9 */ + { 0x00000550, 0x0007 }, /* R1360 - AIF2 Frame Ctrl 10 */ + { 0x00000551, 0x0000 }, /* R1361 (0x551) - AIF2 Frame Ctrl 11 */ + { 0x00000552, 0x0001 }, /* R1362 (0x552) - AIF2 Frame Ctrl 12 */ + { 0x00000553, 0x0002 }, /* R1363 (0x553) - AIF2 Frame Ctrl 13 */ + { 0x00000554, 0x0003 }, /* R1364 (0x554) - AIF2 Frame Ctrl 14 */ + { 0x00000555, 0x0004 }, /* R1365 (0x555) - AIF2 Frame Ctrl 15 */ + { 0x00000556, 0x0005 }, /* R1366 (0x556) - AIF2 Frame Ctrl 16 */ + { 0x00000557, 0x0006 }, /* R1367 - AIF2 Frame Ctrl 17 */ + { 0x00000558, 0x0007 }, /* R1368 - AIF2 Frame Ctrl 18 */ + { 0x00000559, 0x0000 }, /* R1369 (0x559) - AIF2 Tx Enables */ + { 0x0000055a, 0x0000 }, /* R1370 (0x55A) - AIF2 Rx Enables */ + { 0x00000580, 0x000c }, /* R1408 (0x580) - AIF3 BCLK Ctrl */ + { 0x00000581, 0x0000 }, /* R1409 (0x581) - AIF3 Tx Pin Ctrl */ + { 0x00000582, 0x0000 }, /* R1410 (0x582) - AIF3 Rx Pin Ctrl */ + { 0x00000583, 0x0000 }, /* R1411 (0x583) - AIF3 Rate Ctrl */ + { 0x00000584, 0x0000 }, /* R1412 (0x584) - AIF3 Format */ + { 0x00000585, 0x0040 }, /* R1413 (0x585) - AIF3 Tx BCLK Rate */ + { 0x00000586, 0x0040 }, /* R1414 (0x586) - AIF3 Rx BCLK Rate */ + { 0x00000587, 0x1818 }, /* R1415 (0x587) - AIF3 Frame Ctrl 1 */ + { 0x00000588, 0x1818 }, /* R1416 (0x588) - AIF3 Frame Ctrl 2 */ + { 0x00000589, 0x0000 }, /* R1417 (0x589) - AIF3 Frame Ctrl 3 */ + { 0x0000058a, 0x0001 }, /* R1418 (0x58A) - AIF3 Frame Ctrl 4 */ + { 0x00000591, 0x0000 }, /* R1425 (0x591) - AIF3 Frame Ctrl 11 */ + { 0x00000592, 0x0001 }, /* R1426 (0x592) - AIF3 Frame Ctrl 12 */ + { 0x00000599, 0x0000 }, /* R1433 (0x599) - AIF3 Tx Enables */ + { 0x0000059a, 0x0000 }, /* R1434 (0x59A) - AIF3 Rx Enables */ + { 0x000005a0, 0x000c }, /* R1440 - AIF4 BCLK Ctrl */ + { 0x000005a1, 0x0000 }, /* R1441 - AIF4 Tx Pin Ctrl */ + { 0x000005a2, 0x0000 }, /* R1442 - AIF4 Rx Pin Ctrl */ + { 0x000005a3, 0x0000 }, /* R1443 - AIF4 Rate Ctrl */ + { 0x000005a4, 0x0000 }, /* R1444 - AIF4 Format */ + { 0x000005a5, 0x0040 }, /* R1445 - AIF4 Tx BCLK Rate */ + { 0x000005a6, 0x0040 }, /* R1446 - AIF4 Rx BCLK Rate */ + { 0x000005a7, 0x1818 }, /* R1447 - AIF4 Frame Ctrl 1 */ + { 0x000005a8, 0x1818 }, /* R1448 - AIF4 Frame Ctrl 2 */ + { 0x000005a9, 0x0000 }, /* R1449 - AIF4 Frame Ctrl 3 */ + { 0x000005aa, 0x0001 }, /* R1450 - AIF4 Frame Ctrl 4 */ + { 0x000005b1, 0x0000 }, /* R1457 - AIF4 Frame Ctrl 11 */ + { 0x000005b2, 0x0001 }, /* R1458 - AIF4 Frame Ctrl 12 */ + { 0x000005b9, 0x0000 }, /* R1465 - AIF4 Tx Enables */ + { 0x000005ba, 0x0000 }, /* R1466 - AIF4 Rx Enables */ + { 0x000005C2, 0x0000 }, /* R1474 - SPD1 TX Control */ + { 0x000005e3, 0x0000 }, /* R1507 (0x5E3) - SLIMbus Framer Ref Gear */ + { 0x000005e5, 0x0000 }, /* R1509 (0x5E5) - SLIMbus Rates 1 */ + { 0x000005e6, 0x0000 }, /* R1510 (0x5E6) - SLIMbus Rates 2 */ + { 0x000005e7, 0x0000 }, /* R1511 (0x5E7) - SLIMbus Rates 3 */ + { 0x000005e8, 0x0000 }, /* R1512 (0x5E8) - SLIMbus Rates 4 */ + { 0x000005e9, 0x0000 }, /* R1513 (0x5E9) - SLIMbus Rates 5 */ + { 0x000005ea, 0x0000 }, /* R1514 (0x5EA) - SLIMbus Rates 6 */ + { 0x000005eb, 0x0000 }, /* R1515 (0x5EB) - SLIMbus Rates 7 */ + { 0x000005ec, 0x0000 }, /* R1516 (0x5EC) - SLIMbus Rates 8 */ + { 0x000005f5, 0x0000 }, /* R1525 (0x5F5) - SLIMbus RX Channel Enable */ + { 0x000005f6, 0x0000 }, /* R1526 (0x5F6) - SLIMbus TX Channel Enable */ + { 0x00000640, 0x0000 }, + { 0x00000641, 0x0080 }, + { 0x00000642, 0x0000 }, + { 0x00000643, 0x0080 }, + { 0x00000644, 0x0000 }, + { 0x00000645, 0x0080 }, + { 0x00000646, 0x0000 }, + { 0x00000647, 0x0080 }, + { 0x00000648, 0x0000 }, + { 0x00000649, 0x0080 }, + { 0x0000064a, 0x0000 }, + { 0x0000064b, 0x0080 }, + { 0x0000064c, 0x0000 }, + { 0x0000064d, 0x0080 }, + { 0x0000064e, 0x0000 }, + { 0x0000064f, 0x0080 }, + { 0x00000680, 0x0000 }, + { 0x00000681, 0x0080 }, + { 0x00000682, 0x0000 }, + { 0x00000683, 0x0080 }, + { 0x00000684, 0x0000 }, + { 0x00000685, 0x0080 }, + { 0x00000686, 0x0000 }, + { 0x00000687, 0x0080 }, + { 0x00000688, 0x0000 }, + { 0x00000689, 0x0080 }, + { 0x0000068a, 0x0000 }, + { 0x0000068b, 0x0080 }, + { 0x0000068c, 0x0000 }, + { 0x0000068d, 0x0080 }, + { 0x0000068e, 0x0000 }, + { 0x0000068f, 0x0080 }, + { 0x00000690, 0x0000 }, + { 0x00000691, 0x0080 }, + { 0x00000692, 0x0000 }, + { 0x00000693, 0x0080 }, + { 0x00000694, 0x0000 }, + { 0x00000695, 0x0080 }, + { 0x00000696, 0x0000 }, + { 0x00000697, 0x0080 }, + { 0x00000698, 0x0000 }, + { 0x00000699, 0x0080 }, + { 0x0000069a, 0x0000 }, + { 0x0000069b, 0x0080 }, + { 0x0000069c, 0x0000 }, + { 0x0000069d, 0x0080 }, + { 0x0000069e, 0x0000 }, + { 0x0000069f, 0x0080 }, + { 0x000006a0, 0x0000 }, + { 0x000006a1, 0x0080 }, + { 0x000006a2, 0x0000 }, + { 0x000006a3, 0x0080 }, + { 0x000006a4, 0x0000 }, + { 0x000006a5, 0x0080 }, + { 0x000006a6, 0x0000 }, + { 0x000006a7, 0x0080 }, + { 0x000006a8, 0x0000 }, + { 0x000006a9, 0x0080 }, + { 0x000006aa, 0x0000 }, + { 0x000006ab, 0x0080 }, + { 0x000006ac, 0x0000 }, + { 0x000006ad, 0x0080 }, + { 0x000006ae, 0x0000 }, + { 0x000006af, 0x0080 }, + { 0x000006c0, 0x0000 }, + { 0x000006c1, 0x0080 }, + { 0x000006c2, 0x0000 }, + { 0x000006c3, 0x0080 }, + { 0x000006c4, 0x0000 }, + { 0x000006c5, 0x0080 }, + { 0x000006c6, 0x0000 }, + { 0x000006c7, 0x0080 }, + { 0x000006c8, 0x0000 }, + { 0x000006c9, 0x0080 }, + { 0x000006ca, 0x0000 }, + { 0x000006cb, 0x0080 }, + { 0x000006cc, 0x0000 }, + { 0x000006cd, 0x0080 }, + { 0x000006ce, 0x0000 }, + { 0x000006cf, 0x0080 }, + { 0x00000700, 0x0000 }, + { 0x00000701, 0x0080 }, + { 0x00000702, 0x0000 }, + { 0x00000703, 0x0080 }, + { 0x00000704, 0x0000 }, + { 0x00000705, 0x0080 }, + { 0x00000706, 0x0000 }, + { 0x00000707, 0x0080 }, + { 0x00000708, 0x0000 }, + { 0x00000709, 0x0080 }, + { 0x0000070a, 0x0000 }, + { 0x0000070b, 0x0080 }, + { 0x0000070c, 0x0000 }, + { 0x0000070d, 0x0080 }, + { 0x0000070e, 0x0000 }, + { 0x0000070f, 0x0080 }, + { 0x00000710, 0x0000 }, + { 0x00000711, 0x0080 }, + { 0x00000712, 0x0000 }, + { 0x00000713, 0x0080 }, + { 0x00000714, 0x0000 }, + { 0x00000715, 0x0080 }, + { 0x00000716, 0x0000 }, + { 0x00000717, 0x0080 }, + { 0x00000718, 0x0000 }, + { 0x00000719, 0x0080 }, + { 0x0000071a, 0x0000 }, + { 0x0000071b, 0x0080 }, + { 0x0000071c, 0x0000 }, + { 0x0000071d, 0x0080 }, + { 0x0000071e, 0x0000 }, + { 0x0000071f, 0x0080 }, + { 0x00000720, 0x0000 }, + { 0x00000721, 0x0080 }, + { 0x00000722, 0x0000 }, + { 0x00000723, 0x0080 }, + { 0x00000724, 0x0000 }, + { 0x00000725, 0x0080 }, + { 0x00000726, 0x0000 }, + { 0x00000727, 0x0080 }, + { 0x00000728, 0x0000 }, + { 0x00000729, 0x0080 }, + { 0x0000072a, 0x0000 }, + { 0x0000072b, 0x0080 }, + { 0x0000072c, 0x0000 }, + { 0x0000072d, 0x0080 }, + { 0x0000072e, 0x0000 }, + { 0x0000072f, 0x0080 }, + { 0x00000730, 0x0000 }, + { 0x00000731, 0x0080 }, + { 0x00000732, 0x0000 }, + { 0x00000733, 0x0080 }, + { 0x00000734, 0x0000 }, + { 0x00000735, 0x0080 }, + { 0x00000736, 0x0000 }, + { 0x00000737, 0x0080 }, + { 0x00000738, 0x0000 }, + { 0x00000739, 0x0080 }, + { 0x0000073a, 0x0000 }, + { 0x0000073b, 0x0080 }, + { 0x0000073c, 0x0000 }, + { 0x0000073d, 0x0080 }, + { 0x0000073e, 0x0000 }, + { 0x0000073f, 0x0080 }, + { 0x00000740, 0x0000 }, + { 0x00000741, 0x0080 }, + { 0x00000742, 0x0000 }, + { 0x00000743, 0x0080 }, + { 0x00000744, 0x0000 }, + { 0x00000745, 0x0080 }, + { 0x00000746, 0x0000 }, + { 0x00000747, 0x0080 }, + { 0x00000748, 0x0000 }, + { 0x00000749, 0x0080 }, + { 0x0000074a, 0x0000 }, + { 0x0000074b, 0x0080 }, + { 0x0000074c, 0x0000 }, + { 0x0000074d, 0x0080 }, + { 0x0000074e, 0x0000 }, + { 0x0000074f, 0x0080 }, + { 0x00000750, 0x0000 }, + { 0x00000751, 0x0080 }, + { 0x00000752, 0x0000 }, + { 0x00000753, 0x0080 }, + { 0x00000754, 0x0000 }, + { 0x00000755, 0x0080 }, + { 0x00000756, 0x0000 }, + { 0x00000757, 0x0080 }, + { 0x00000758, 0x0000 }, + { 0x00000759, 0x0080 }, + { 0x0000075a, 0x0000 }, + { 0x0000075b, 0x0080 }, + { 0x0000075c, 0x0000 }, + { 0x0000075d, 0x0080 }, + { 0x0000075e, 0x0000 }, + { 0x0000075f, 0x0080 }, + { 0x00000760, 0x0000 }, + { 0x00000761, 0x0080 }, + { 0x00000762, 0x0000 }, + { 0x00000763, 0x0080 }, + { 0x00000764, 0x0000 }, + { 0x00000765, 0x0080 }, + { 0x00000766, 0x0000 }, + { 0x00000767, 0x0080 }, + { 0x00000768, 0x0000 }, + { 0x00000769, 0x0080 }, + { 0x0000076a, 0x0000 }, + { 0x0000076b, 0x0080 }, + { 0x0000076c, 0x0000 }, + { 0x0000076d, 0x0080 }, + { 0x0000076e, 0x0000 }, + { 0x0000076f, 0x0080 }, + { 0x00000770, 0x0000 }, + { 0x00000771, 0x0080 }, + { 0x00000772, 0x0000 }, + { 0x00000773, 0x0080 }, + { 0x00000774, 0x0000 }, + { 0x00000775, 0x0080 }, + { 0x00000776, 0x0000 }, + { 0x00000777, 0x0080 }, + { 0x00000778, 0x0000 }, + { 0x00000779, 0x0080 }, + { 0x0000077a, 0x0000 }, + { 0x0000077b, 0x0080 }, + { 0x0000077c, 0x0000 }, + { 0x0000077d, 0x0080 }, + { 0x0000077e, 0x0000 }, + { 0x0000077f, 0x0080 }, + { 0x00000780, 0x0000 }, + { 0x00000781, 0x0080 }, + { 0x00000782, 0x0000 }, + { 0x00000783, 0x0080 }, + { 0x00000784, 0x0000 }, + { 0x00000785, 0x0080 }, + { 0x00000786, 0x0000 }, + { 0x00000787, 0x0080 }, + { 0x00000788, 0x0000 }, + { 0x00000789, 0x0080 }, + { 0x0000078a, 0x0000 }, + { 0x0000078b, 0x0080 }, + { 0x0000078c, 0x0000 }, + { 0x0000078d, 0x0080 }, + { 0x0000078e, 0x0000 }, + { 0x0000078f, 0x0080 }, + { 0x000007a0, 0x0000 }, /* R1952 - AIF4TX1MIX Input 1 Source */ + { 0x000007a1, 0x0080 }, /* R1953 - AIF4TX1MIX Input 1 Volume */ + { 0x000007a2, 0x0000 }, /* R1954 - AIF4TX1MIX Input 2 Source */ + { 0x000007a3, 0x0080 }, /* R1955 - AIF4TX1MIX Input 2 Volume */ + { 0x000007a4, 0x0000 }, /* R1956 - AIF4TX1MIX Input 3 Source */ + { 0x000007a5, 0x0080 }, /* R1957 - AIF4TX1MIX Input 3 Volume */ + { 0x000007a6, 0x0000 }, /* R1958 - AIF4TX1MIX Input 4 Source */ + { 0x000007a7, 0x0080 }, /* R1959 - AIF4TX1MIX Input 4 Volume */ + { 0x000007a8, 0x0000 }, /* R1960 - AIF4TX2MIX Input 1 Source */ + { 0x000007a9, 0x0080 }, /* R1961 - AIF4TX2MIX Input 1 Volume */ + { 0x000007aa, 0x0000 }, /* R1962 - AIF4TX2MIX Input 2 Source */ + { 0x000007ab, 0x0080 }, /* R1963 - AIF4TX2MIX Input 2 Volume */ + { 0x000007ac, 0x0000 }, /* R1964 - AIF4TX2MIX Input 3 Source */ + { 0x000007ad, 0x0080 }, /* R1965 - AIF4TX2MIX Input 3 Volume */ + { 0x000007ae, 0x0000 }, /* R1966 - AIF4TX2MIX Input 4 Source */ + { 0x000007af, 0x0080 }, /* R1967 - AIF4TX2MIX Input 4 Volume */ + { 0x000007c0, 0x0000 }, + { 0x000007c1, 0x0080 }, + { 0x000007c2, 0x0000 }, + { 0x000007c3, 0x0080 }, + { 0x000007c4, 0x0000 }, + { 0x000007c5, 0x0080 }, + { 0x000007c6, 0x0000 }, + { 0x000007c7, 0x0080 }, + { 0x000007c8, 0x0000 }, + { 0x000007c9, 0x0080 }, + { 0x000007ca, 0x0000 }, + { 0x000007cb, 0x0080 }, + { 0x000007cc, 0x0000 }, + { 0x000007cd, 0x0080 }, + { 0x000007ce, 0x0000 }, + { 0x000007cf, 0x0080 }, + { 0x000007d0, 0x0000 }, + { 0x000007d1, 0x0080 }, + { 0x000007d2, 0x0000 }, + { 0x000007d3, 0x0080 }, + { 0x000007d4, 0x0000 }, + { 0x000007d5, 0x0080 }, + { 0x000007d6, 0x0000 }, + { 0x000007d7, 0x0080 }, + { 0x000007d8, 0x0000 }, + { 0x000007d9, 0x0080 }, + { 0x000007da, 0x0000 }, + { 0x000007db, 0x0080 }, + { 0x000007dc, 0x0000 }, + { 0x000007dd, 0x0080 }, + { 0x000007de, 0x0000 }, + { 0x000007df, 0x0080 }, + { 0x000007e0, 0x0000 }, + { 0x000007e1, 0x0080 }, + { 0x000007e2, 0x0000 }, + { 0x000007e3, 0x0080 }, + { 0x000007e4, 0x0000 }, + { 0x000007e5, 0x0080 }, + { 0x000007e6, 0x0000 }, + { 0x000007e7, 0x0080 }, + { 0x000007e8, 0x0000 }, + { 0x000007e9, 0x0080 }, + { 0x000007ea, 0x0000 }, + { 0x000007eb, 0x0080 }, + { 0x000007ec, 0x0000 }, + { 0x000007ed, 0x0080 }, + { 0x000007ee, 0x0000 }, + { 0x000007ef, 0x0080 }, + { 0x000007f0, 0x0000 }, + { 0x000007f1, 0x0080 }, + { 0x000007f2, 0x0000 }, + { 0x000007f3, 0x0080 }, + { 0x000007f4, 0x0000 }, + { 0x000007f5, 0x0080 }, + { 0x000007f6, 0x0000 }, + { 0x000007f7, 0x0080 }, + { 0x000007f8, 0x0000 }, + { 0x000007f9, 0x0080 }, + { 0x000007fa, 0x0000 }, + { 0x000007fb, 0x0080 }, + { 0x000007fc, 0x0000 }, + { 0x000007fd, 0x0080 }, + { 0x000007fe, 0x0000 }, + { 0x000007ff, 0x0080 }, + { 0x00000800, 0x0000 }, + { 0x00000801, 0x0080 }, + { 0x00000808, 0x0000 }, + { 0x00000809, 0x0080 }, + { 0x00000880, 0x0000 }, + { 0x00000881, 0x0080 }, + { 0x00000882, 0x0000 }, + { 0x00000883, 0x0080 }, + { 0x00000884, 0x0000 }, + { 0x00000885, 0x0080 }, + { 0x00000886, 0x0000 }, + { 0x00000887, 0x0080 }, + { 0x00000888, 0x0000 }, + { 0x00000889, 0x0080 }, + { 0x0000088a, 0x0000 }, + { 0x0000088b, 0x0080 }, + { 0x0000088c, 0x0000 }, + { 0x0000088d, 0x0080 }, + { 0x0000088e, 0x0000 }, + { 0x0000088f, 0x0080 }, + { 0x00000890, 0x0000 }, + { 0x00000891, 0x0080 }, + { 0x00000892, 0x0000 }, + { 0x00000893, 0x0080 }, + { 0x00000894, 0x0000 }, + { 0x00000895, 0x0080 }, + { 0x00000896, 0x0000 }, + { 0x00000897, 0x0080 }, + { 0x00000898, 0x0000 }, + { 0x00000899, 0x0080 }, + { 0x0000089a, 0x0000 }, + { 0x0000089b, 0x0080 }, + { 0x0000089c, 0x0000 }, + { 0x0000089d, 0x0080 }, + { 0x0000089e, 0x0000 }, + { 0x0000089f, 0x0080 }, + { 0x000008c0, 0x0000 }, + { 0x000008c1, 0x0080 }, + { 0x000008c2, 0x0000 }, + { 0x000008c3, 0x0080 }, + { 0x000008c4, 0x0000 }, + { 0x000008c5, 0x0080 }, + { 0x000008c6, 0x0000 }, + { 0x000008c7, 0x0080 }, + { 0x000008c8, 0x0000 }, + { 0x000008c9, 0x0080 }, + { 0x000008ca, 0x0000 }, + { 0x000008cb, 0x0080 }, + { 0x000008cc, 0x0000 }, + { 0x000008cd, 0x0080 }, + { 0x000008ce, 0x0000 }, + { 0x000008cf, 0x0080 }, + { 0x000008d0, 0x0000 }, + { 0x000008d1, 0x0080 }, + { 0x000008d2, 0x0000 }, + { 0x000008d3, 0x0080 }, + { 0x000008d4, 0x0000 }, + { 0x000008d5, 0x0080 }, + { 0x000008d6, 0x0000 }, + { 0x000008d7, 0x0080 }, + { 0x000008d8, 0x0000 }, + { 0x000008d9, 0x0080 }, + { 0x000008da, 0x0000 }, + { 0x000008db, 0x0080 }, + { 0x000008dc, 0x0000 }, + { 0x000008dd, 0x0080 }, + { 0x000008de, 0x0000 }, + { 0x000008df, 0x0080 }, + { 0x00000900, 0x0000 }, + { 0x00000901, 0x0080 }, + { 0x00000902, 0x0000 }, + { 0x00000903, 0x0080 }, + { 0x00000904, 0x0000 }, + { 0x00000905, 0x0080 }, + { 0x00000906, 0x0000 }, + { 0x00000907, 0x0080 }, + { 0x00000908, 0x0000 }, + { 0x00000909, 0x0080 }, + { 0x0000090a, 0x0000 }, + { 0x0000090b, 0x0080 }, + { 0x0000090c, 0x0000 }, + { 0x0000090d, 0x0080 }, + { 0x0000090e, 0x0000 }, + { 0x0000090f, 0x0080 }, + { 0x00000910, 0x0000 }, + { 0x00000911, 0x0080 }, + { 0x00000912, 0x0000 }, + { 0x00000913, 0x0080 }, + { 0x00000914, 0x0000 }, + { 0x00000915, 0x0080 }, + { 0x00000916, 0x0000 }, + { 0x00000917, 0x0080 }, + { 0x00000918, 0x0000 }, + { 0x00000919, 0x0080 }, + { 0x0000091a, 0x0000 }, + { 0x0000091b, 0x0080 }, + { 0x0000091c, 0x0000 }, + { 0x0000091d, 0x0080 }, + { 0x0000091e, 0x0000 }, + { 0x0000091f, 0x0080 }, + { 0x00000940, 0x0000 }, + { 0x00000941, 0x0080 }, + { 0x00000942, 0x0000 }, + { 0x00000943, 0x0080 }, + { 0x00000944, 0x0000 }, + { 0x00000945, 0x0080 }, + { 0x00000946, 0x0000 }, + { 0x00000947, 0x0080 }, + { 0x00000948, 0x0000 }, + { 0x00000949, 0x0080 }, + { 0x0000094a, 0x0000 }, + { 0x0000094b, 0x0080 }, + { 0x0000094c, 0x0000 }, + { 0x0000094d, 0x0080 }, + { 0x0000094e, 0x0000 }, + { 0x0000094f, 0x0080 }, + { 0x00000950, 0x0000 }, + { 0x00000958, 0x0000 }, + { 0x00000960, 0x0000 }, + { 0x00000968, 0x0000 }, + { 0x00000970, 0x0000 }, + { 0x00000978, 0x0000 }, + { 0x00000980, 0x0000 }, + { 0x00000981, 0x0080 }, + { 0x00000982, 0x0000 }, + { 0x00000983, 0x0080 }, + { 0x00000984, 0x0000 }, + { 0x00000985, 0x0080 }, + { 0x00000986, 0x0000 }, + { 0x00000987, 0x0080 }, + { 0x00000988, 0x0000 }, + { 0x00000989, 0x0080 }, + { 0x0000098a, 0x0000 }, + { 0x0000098b, 0x0080 }, + { 0x0000098c, 0x0000 }, + { 0x0000098d, 0x0080 }, + { 0x0000098e, 0x0000 }, + { 0x0000098f, 0x0080 }, + { 0x00000990, 0x0000 }, + { 0x00000998, 0x0000 }, + { 0x000009a0, 0x0000 }, + { 0x000009a8, 0x0000 }, + { 0x000009b0, 0x0000 }, + { 0x000009b8, 0x0000 }, + { 0x000009c0, 0x0000 }, + { 0x000009c1, 0x0080 }, + { 0x000009c2, 0x0000 }, + { 0x000009c3, 0x0080 }, + { 0x000009c4, 0x0000 }, + { 0x000009c5, 0x0080 }, + { 0x000009c6, 0x0000 }, + { 0x000009c7, 0x0080 }, + { 0x000009c8, 0x0000 }, + { 0x000009c9, 0x0080 }, + { 0x000009ca, 0x0000 }, + { 0x000009cb, 0x0080 }, + { 0x000009cc, 0x0000 }, + { 0x000009cd, 0x0080 }, + { 0x000009ce, 0x0000 }, + { 0x000009cf, 0x0080 }, + { 0x000009d0, 0x0000 }, + { 0x000009d8, 0x0000 }, + { 0x000009e0, 0x0000 }, + { 0x000009e8, 0x0000 }, + { 0x000009f0, 0x0000 }, + { 0x000009f8, 0x0000 }, + { 0x00000a00, 0x0000 }, + { 0x00000a01, 0x0080 }, + { 0x00000a02, 0x0000 }, + { 0x00000a03, 0x0080 }, + { 0x00000a04, 0x0000 }, + { 0x00000a05, 0x0080 }, + { 0x00000a06, 0x0000 }, + { 0x00000a07, 0x0080 }, + { 0x00000a08, 0x0000 }, + { 0x00000a09, 0x0080 }, + { 0x00000a0a, 0x0000 }, + { 0x00000a0b, 0x0080 }, + { 0x00000a0c, 0x0000 }, + { 0x00000a0d, 0x0080 }, + { 0x00000a0e, 0x0000 }, + { 0x00000a0f, 0x0080 }, + { 0x00000a10, 0x0000 }, + { 0x00000a18, 0x0000 }, + { 0x00000a20, 0x0000 }, + { 0x00000a28, 0x0000 }, + { 0x00000a30, 0x0000 }, + { 0x00000a38, 0x0000 }, + { 0x00000a40, 0x0000 }, + { 0x00000a41, 0x0080 }, + { 0x00000a42, 0x0000 }, + { 0x00000a43, 0x0080 }, + { 0x00000a44, 0x0000 }, + { 0x00000a45, 0x0080 }, + { 0x00000a46, 0x0000 }, + { 0x00000a47, 0x0080 }, + { 0x00000a48, 0x0000 }, + { 0x00000a49, 0x0080 }, + { 0x00000a4a, 0x0000 }, + { 0x00000a4b, 0x0080 }, + { 0x00000a4c, 0x0000 }, + { 0x00000a4d, 0x0080 }, + { 0x00000a4e, 0x0000 }, + { 0x00000a4f, 0x0080 }, + { 0x00000a50, 0x0000 }, + { 0x00000a58, 0x0000 }, + { 0x00000a60, 0x0000 }, + { 0x00000a68, 0x0000 }, + { 0x00000a70, 0x0000 }, + { 0x00000a78, 0x0000 }, + { 0x00000a80, 0x0000 }, + { 0x00000a88, 0x0000 }, + { 0x00000a90, 0x0000 }, + { 0x00000a98, 0x0000 }, + { 0x00000aa0, 0x0000 }, + { 0x00000aa8, 0x0000 }, + { 0x00000ab0, 0x0000 }, + { 0x00000ab8, 0x0000 }, + { 0x00000b00, 0x0000 }, + { 0x00000b08, 0x0000 }, + { 0x00000b10, 0x0000 }, + { 0x00000b18, 0x0000 }, + { 0x00000b20, 0x0000 }, + { 0x00000b28, 0x0000 }, + { 0x00000b30, 0x0000 }, + { 0x00000b38, 0x0000 }, + { 0x00000b40, 0x0000 }, + { 0x00000b48, 0x0000 }, + { 0x00000b50, 0x0000 }, + { 0x00000b58, 0x0000 }, + { 0x00000b60, 0x0000 }, + { 0x00000b68, 0x0000 }, + { 0x00000b70, 0x0000 }, + { 0x00000b78, 0x0000 }, + { 0x00000b80, 0x0000 }, + { 0x00000b88, 0x0000 }, + { 0x00000ba0, 0x0000 }, + { 0x00000ba8, 0x0000 }, + { 0x00000bc0, 0x0000 }, /* R3008 - ISRC4DEC1MIX Input 1 Source */ + { 0x00000bc8, 0x0000 }, /* R3016 - ISRC4DEC2MIX Input 1 Source */ + { 0x00000be0, 0x0000 }, /* R3040 - ISRC4INT1MIX Input 1 Source */ + { 0x00000be8, 0x0000 }, /* R3048 - ISRC4INT2MIX Input 1 Source */ + { 0x00000c00, 0x0000 }, + { 0x00000c01, 0x0080 }, + { 0x00000c02, 0x0000 }, + { 0x00000c03, 0x0080 }, + { 0x00000c04, 0x0000 }, + { 0x00000c05, 0x0080 }, + { 0x00000c06, 0x0000 }, + { 0x00000c07, 0x0080 }, + { 0x00000c08, 0x0000 }, + { 0x00000c09, 0x0080 }, + { 0x00000c0a, 0x0000 }, + { 0x00000c0b, 0x0080 }, + { 0x00000c0c, 0x0000 }, + { 0x00000c0d, 0x0080 }, + { 0x00000c0e, 0x0000 }, + { 0x00000c0f, 0x0080 }, + { 0x00000c10, 0x0000 }, /* R3088 (0xC10) - DSP6AUX1MIX Input 1 */ + { 0x00000c18, 0x0000 }, /* R3088 (0xC18) - DSP6AUX2MIX Input 1 */ + { 0x00000c20, 0x0000 }, /* R3088 (0xC20) - DSP6AUX3MIX Input 1 */ + { 0x00000c28, 0x0000 }, /* R3088 (0xC28) - DSP6AUX4MIX Input 1 */ + { 0x00000c30, 0x0000 }, /* R3088 (0xC30) - DSP6AUX5MIX Input 1 */ + { 0x00000c38, 0x0000 }, /* R3088 (0xC38) - DSP6AUX6MIX Input 1 */ + { 0x00000c40, 0x0000 }, + { 0x00000c41, 0x0080 }, + { 0x00000c42, 0x0000 }, + { 0x00000c43, 0x0080 }, + { 0x00000c44, 0x0000 }, + { 0x00000c45, 0x0080 }, + { 0x00000c46, 0x0000 }, + { 0x00000c47, 0x0080 }, + { 0x00000c48, 0x0000 }, + { 0x00000c49, 0x0080 }, + { 0x00000c4a, 0x0000 }, + { 0x00000c4b, 0x0080 }, + { 0x00000c4c, 0x0000 }, + { 0x00000c4d, 0x0080 }, + { 0x00000c4e, 0x0000 }, + { 0x00000c4f, 0x0080 }, + { 0x00000c50, 0x0000 }, + { 0x00000c58, 0x0000 }, + { 0x00000c60, 0x0000 }, + { 0x00000c68, 0x0000 }, + { 0x00000c70, 0x0000 }, + { 0x00000c78, 0x0000 }, + { 0x00000dc0, 0x0000 }, + { 0x00000dc8, 0x0000 }, + { 0x00000dd0, 0x0000 }, + { 0x00000dd8, 0x0000 }, + { 0x00000de0, 0x0000 }, + { 0x00000de8, 0x0000 }, + { 0x00000df0, 0x0000 }, + { 0x00000df8, 0x0000 }, + { 0x00000e00, 0x0000 }, /* R3584 (0xE00) - FX_Ctrl1 */ + { 0x00000e10, 0x6318 }, /* R3600 (0xE10) - EQ1_1 */ + { 0x00000e11, 0x6300 }, /* R3601 (0xE11) - EQ1_2 */ + { 0x00000e12, 0x0fc8 }, /* R3602 (0xE12) - EQ1_3 */ + { 0x00000e13, 0x03fe }, /* R3603 (0xE13) - EQ1_4 */ + { 0x00000e14, 0x00e0 }, /* R3604 (0xE14) - EQ1_5 */ + { 0x00000e15, 0x1ec4 }, /* R3605 (0xE15) - EQ1_6 */ + { 0x00000e16, 0xf136 }, /* R3606 (0xE16) - EQ1_7 */ + { 0x00000e17, 0x0409 }, /* R3607 (0xE17) - EQ1_8 */ + { 0x00000e18, 0x04cc }, /* R3608 (0xE18) - EQ1_9 */ + { 0x00000e19, 0x1c9b }, /* R3609 (0xE19) - EQ1_10 */ + { 0x00000e1a, 0xf337 }, /* R3610 (0xE1A) - EQ1_11 */ + { 0x00000e1b, 0x040b }, /* R3611 (0xE1B) - EQ1_12 */ + { 0x00000e1c, 0x0cbb }, /* R3612 (0xE1C) - EQ1_13 */ + { 0x00000e1d, 0x16f8 }, /* R3613 (0xE1D) - EQ1_14 */ + { 0x00000e1e, 0xf7d9 }, /* R3614 (0xE1E) - EQ1_15 */ + { 0x00000e1f, 0x040a }, /* R3615 (0xE1F) - EQ1_16 */ + { 0x00000e20, 0x1f14 }, /* R3616 (0xE20) - EQ1_17 */ + { 0x00000e21, 0x058c }, /* R3617 (0xE21) - EQ1_18 */ + { 0x00000e22, 0x0563 }, /* R3618 (0xE22) - EQ1_19 */ + { 0x00000e23, 0x4000 }, /* R3619 (0xE23) - EQ1_20 */ + { 0x00000e24, 0x0b75 }, /* R3620 (0xE24) - EQ1_21 */ + { 0x00000e26, 0x6318 }, /* R3622 (0xE26) - EQ2_1 */ + { 0x00000e27, 0x6300 }, /* R3623 (0xE27) - EQ2_2 */ + { 0x00000e28, 0x0fc8 }, /* R3624 (0xE28) - EQ2_3 */ + { 0x00000e29, 0x03fe }, /* R3625 (0xE29) - EQ2_4 */ + { 0x00000e2a, 0x00e0 }, /* R3626 (0xE2A) - EQ2_5 */ + { 0x00000e2b, 0x1ec4 }, /* R3627 (0xE2B) - EQ2_6 */ + { 0x00000e2c, 0xf136 }, /* R3628 (0xE2C) - EQ2_7 */ + { 0x00000e2d, 0x0409 }, /* R3629 (0xE2D) - EQ2_8 */ + { 0x00000e2e, 0x04cc }, /* R3630 (0xE2E) - EQ2_9 */ + { 0x00000e2f, 0x1c9b }, /* R3631 (0xE2F) - EQ2_10 */ + { 0x00000e30, 0xf337 }, /* R3632 (0xE30) - EQ2_11 */ + { 0x00000e31, 0x040b }, /* R3633 (0xE31) - EQ2_12 */ + { 0x00000e32, 0x0cbb }, /* R3634 (0xE32) - EQ2_13 */ + { 0x00000e33, 0x16f8 }, /* R3635 (0xE33) - EQ2_14 */ + { 0x00000e34, 0xf7d9 }, /* R3636 (0xE34) - EQ2_15 */ + { 0x00000e35, 0x040a }, /* R3637 (0xE35) - EQ2_16 */ + { 0x00000e36, 0x1f14 }, /* R3638 (0xE36) - EQ2_17 */ + { 0x00000e37, 0x058c }, /* R3639 (0xE37) - EQ2_18 */ + { 0x00000e38, 0x0563 }, /* R3640 (0xE38) - EQ2_19 */ + { 0x00000e39, 0x4000 }, /* R3641 (0xE39) - EQ2_20 */ + { 0x00000e3a, 0x0b75 }, /* R3642 (0xE3A) - EQ2_21 */ + { 0x00000e3c, 0x6318 }, /* R3644 (0xE3C) - EQ3_1 */ + { 0x00000e3d, 0x6300 }, /* R3645 (0xE3D) - EQ3_2 */ + { 0x00000e3e, 0x0fc8 }, /* R3646 (0xE3E) - EQ3_3 */ + { 0x00000e3f, 0x03fe }, /* R3647 (0xE3F) - EQ3_4 */ + { 0x00000e40, 0x00e0 }, /* R3648 (0xE40) - EQ3_5 */ + { 0x00000e41, 0x1ec4 }, /* R3649 (0xE41) - EQ3_6 */ + { 0x00000e42, 0xf136 }, /* R3650 (0xE42) - EQ3_7 */ + { 0x00000e43, 0x0409 }, /* R3651 (0xE43) - EQ3_8 */ + { 0x00000e44, 0x04cc }, /* R3652 (0xE44) - EQ3_9 */ + { 0x00000e45, 0x1c9b }, /* R3653 (0xE45) - EQ3_10 */ + { 0x00000e46, 0xf337 }, /* R3654 (0xE46) - EQ3_11 */ + { 0x00000e47, 0x040b }, /* R3655 (0xE47) - EQ3_12 */ + { 0x00000e48, 0x0cbb }, /* R3656 (0xE48) - EQ3_13 */ + { 0x00000e49, 0x16f8 }, /* R3657 (0xE49) - EQ3_14 */ + { 0x00000e4a, 0xf7d9 }, /* R3658 (0xE4A) - EQ3_15 */ + { 0x00000e4b, 0x040a }, /* R3659 (0xE4B) - EQ3_16 */ + { 0x00000e4c, 0x1f14 }, /* R3660 (0xE4C) - EQ3_17 */ + { 0x00000e4d, 0x058c }, /* R3661 (0xE4D) - EQ3_18 */ + { 0x00000e4e, 0x0563 }, /* R3662 (0xE4E) - EQ3_19 */ + { 0x00000e4f, 0x4000 }, /* R3663 (0xE4F) - EQ3_20 */ + { 0x00000e50, 0x0b75 }, /* R3664 (0xE50) - EQ3_21 */ + { 0x00000e52, 0x6318 }, /* R3666 (0xE52) - EQ4_1 */ + { 0x00000e53, 0x6300 }, /* R3667 (0xE53) - EQ4_2 */ + { 0x00000e54, 0x0fc8 }, /* R3668 (0xE54) - EQ4_3 */ + { 0x00000e55, 0x03fe }, /* R3669 (0xE55) - EQ4_4 */ + { 0x00000e56, 0x00e0 }, /* R3670 (0xE56) - EQ4_5 */ + { 0x00000e57, 0x1ec4 }, /* R3671 (0xE57) - EQ4_6 */ + { 0x00000e58, 0xf136 }, /* R3672 (0xE58) - EQ4_7 */ + { 0x00000e59, 0x0409 }, /* R3673 (0xE59) - EQ4_8 */ + { 0x00000e5a, 0x04cc }, /* R3674 (0xE5A) - EQ4_9 */ + { 0x00000e5b, 0x1c9b }, /* R3675 (0xE5B) - EQ4_10 */ + { 0x00000e5c, 0xf337 }, /* R3676 (0xE5C) - EQ4_11 */ + { 0x00000e5d, 0x040b }, /* R3677 (0xE5D) - EQ4_12 */ + { 0x00000e5e, 0x0cbb }, /* R3678 (0xE5E) - EQ4_13 */ + { 0x00000e5f, 0x16f8 }, /* R3679 (0xE5F) - EQ4_14 */ + { 0x00000e60, 0xf7d9 }, /* R3680 (0xE60) - EQ4_15 */ + { 0x00000e61, 0x040a }, /* R3681 (0xE61) - EQ4_16 */ + { 0x00000e62, 0x1f14 }, /* R3682 (0xE62) - EQ4_17 */ + { 0x00000e63, 0x058c }, /* R3683 (0xE63) - EQ4_18 */ + { 0x00000e64, 0x0563 }, /* R3684 (0xE64) - EQ4_19 */ + { 0x00000e65, 0x4000 }, /* R3685 (0xE65) - EQ4_20 */ + { 0x00000e66, 0x0b75 }, /* R3686 (0xE66) - EQ4_21 */ + { 0x00000e80, 0x0018 }, /* R3712 (0xE80) - DRC1 ctrl1 */ + { 0x00000e81, 0x0933 }, /* R3713 (0xE81) - DRC1 ctrl2 */ + { 0x00000e82, 0x0018 }, /* R3714 (0xE82) - DRC1 ctrl3 */ + { 0x00000e83, 0x0000 }, /* R3715 (0xE83) - DRC1 ctrl4 */ + { 0x00000e84, 0x0000 }, /* R3716 (0xE84) - DRC1 ctrl5 */ + { 0x00000e88, 0x0018 }, /* R3720 (0xE88) - DRC2 ctrl1 */ + { 0x00000e89, 0x0933 }, /* R3721 (0xE89) - DRC2 ctrl2 */ + { 0x00000e8a, 0x0018 }, /* R3722 (0xE8A) - DRC2 ctrl3 */ + { 0x00000e8b, 0x0000 }, /* R3723 (0xE8B) - DRC2 ctrl4 */ + { 0x00000e8c, 0x0000 }, /* R3724 (0xE8C) - DRC2 ctrl5 */ + { 0x00000ec0, 0x0000 }, /* R3776 (0xEC0) - HPLPF1_1 */ + { 0x00000ec1, 0x0000 }, /* R3777 (0xEC1) - HPLPF1_2 */ + { 0x00000ec4, 0x0000 }, /* R3780 (0xEC4) - HPLPF2_1 */ + { 0x00000ec5, 0x0000 }, /* R3781 (0xEC5) - HPLPF2_2 */ + { 0x00000ec8, 0x0000 }, /* R3784 (0xEC8) - HPLPF3_1 */ + { 0x00000ec9, 0x0000 }, /* R3785 (0xEC9) - HPLPF3_2 */ + { 0x00000ecc, 0x0000 }, /* R3788 (0xECC) - HPLPF4_1 */ + { 0x00000ecd, 0x0000 }, /* R3789 (0xECD) - HPLPF4_2 */ + { 0x00000ed0, 0x0000 }, /* R3792 (0xED0) - ASRC2_ENABLE */ + { 0x00000ed2, 0x0000 }, /* R3794 (0xED2) - ASRC2_RATE1 */ + { 0x00000ed3, 0x4000 }, /* R3795 (0xED3) - ASRC2_RATE2 */ + { 0x00000ee0, 0x0000 }, /* R3808 (0xEE0) - ASRC1_ENABLE */ + { 0x00000ee2, 0x0000 }, /* R3810 (0xEE2) - ASRC1_RATE1 */ + { 0x00000ee3, 0x4000 }, /* R3811 (0xEE3) - ASRC1_RATE2 */ + { 0x00000ef0, 0x0000 }, /* R3824 (0xEF0) - ISRC 1 CTRL 1 */ + { 0x00000ef1, 0x0001 }, /* R3825 (0xEF1) - ISRC 1 CTRL 2 */ + { 0x00000ef2, 0x0000 }, /* R3826 (0xEF2) - ISRC 1 CTRL 3 */ + { 0x00000ef3, 0x0000 }, /* R3827 (0xEF3) - ISRC 2 CTRL 1 */ + { 0x00000ef4, 0x0001 }, /* R3828 (0xEF4) - ISRC 2 CTRL 2 */ + { 0x00000ef5, 0x0000 }, /* R3829 (0xEF5) - ISRC 2 CTRL 3 */ + { 0x00000ef6, 0x0000 }, /* R3830 (0xEF6) - ISRC 3 CTRL 1 */ + { 0x00000ef7, 0x0001 }, /* R3831 (0xEF7) - ISRC 3 CTRL 2 */ + { 0x00000ef8, 0x0000 }, /* R3832 (0xEF8) - ISRC 3 CTRL 3 */ + { 0x00000ef9, 0x0000 }, /* R3833 - ISRC 4 CTRL 1 */ + { 0x00000efa, 0x0001 }, /* R3834 - ISRC 4 CTRL 2 */ + { 0x00000efb, 0x0000 }, /* R3835 - ISRC 4 CTRL 3 */ + { 0x00000F01, 0x0000 }, /* R3841 - ANC_SRC */ + { 0x00000F02, 0x0000 }, /* R3842 - Arizona DSP Status */ + { 0x00000F08, 0x001c }, /* R3848 - ANC Coefficient */ + { 0x00000F09, 0x0000 }, /* R3849 - ANC Coefficient */ + { 0x00000F0A, 0x0000 }, /* R3850 - ANC Coefficient */ + { 0x00000F0B, 0x0000 }, /* R3851 - ANC Coefficient */ + { 0x00000F0C, 0x0000 }, /* R3852 - ANC Coefficient */ + { 0x00000F0D, 0x0000 }, /* R3853 - ANC Coefficient */ + { 0x00000F0E, 0x0000 }, /* R3854 - ANC Coefficient */ + { 0x00000F0F, 0x0000 }, /* R3855 - ANC Coefficient */ + { 0x00000F10, 0x0000 }, /* R3856 - ANC Coefficient */ + { 0x00000F11, 0x0000 }, /* R3857 - ANC Coefficient */ + { 0x00000F12, 0x0000 }, /* R3858 - ANC Coefficient */ + { 0x00000F15, 0x0000 }, /* R3861 - FCL Filter Control */ + { 0x00000F17, 0x0004 }, /* R3863 - FCL ADC Reformatter Control */ + { 0x00000F18, 0x0004 }, /* R3864 - ANC Coefficient */ + { 0x00000F19, 0x0002 }, /* R3865 - ANC Coefficient */ + { 0x00000F1A, 0x0000 }, /* R3866 - ANC Coefficient */ + { 0x00000F1B, 0x0010 }, /* R3867 - ANC Coefficient */ + { 0x00000F1C, 0x0000 }, /* R3868 - ANC Coefficient */ + { 0x00000F1D, 0x0000 }, /* R3869 - ANC Coefficient */ + { 0x00000F1E, 0x0000 }, /* R3870 - ANC Coefficient */ + { 0x00000F1F, 0x0000 }, /* R3871 - ANC Coefficient */ + { 0x00000F20, 0x0000 }, /* R3872 - ANC Coefficient */ + { 0x00000F21, 0x0000 }, /* R3873 - ANC Coefficient */ + { 0x00000F22, 0x0000 }, /* R3874 - ANC Coefficient */ + { 0x00000F23, 0x0000 }, /* R3875 - ANC Coefficient */ + { 0x00000F24, 0x0000 }, /* R3876 - ANC Coefficient */ + { 0x00000F25, 0x0000 }, /* R3877 - ANC Coefficient */ + { 0x00000F26, 0x0000 }, /* R3878 - ANC Coefficient */ + { 0x00000F27, 0x0000 }, /* R3879 - ANC Coefficient */ + { 0x00000F28, 0x0000 }, /* R3880 - ANC Coefficient */ + { 0x00000F29, 0x0000 }, /* R3881 - ANC Coefficient */ + { 0x00000F2A, 0x0000 }, /* R3882 - ANC Coefficient */ + { 0x00000F2B, 0x0000 }, /* R3883 - ANC Coefficient */ + { 0x00000F2C, 0x0000 }, /* R3884 - ANC Coefficient */ + { 0x00000F2D, 0x0000 }, /* R3885 - ANC Coefficient */ + { 0x00000F2E, 0x0000 }, /* R3886 - ANC Coefficient */ + { 0x00000F2F, 0x0000 }, /* R3887 - ANC Coefficient */ + { 0x00000F30, 0x0000 }, /* R3888 - ANC Coefficient */ + { 0x00000F31, 0x0000 }, /* R3889 - ANC Coefficient */ + { 0x00000F32, 0x0000 }, /* R3890 - ANC Coefficient */ + { 0x00000F33, 0x0000 }, /* R3891 - ANC Coefficient */ + { 0x00000F34, 0x0000 }, /* R3892 - ANC Coefficient */ + { 0x00000F35, 0x0000 }, /* R3893 - ANC Coefficient */ + { 0x00000F36, 0x0000 }, /* R3894 - ANC Coefficient */ + { 0x00000F37, 0x0000 }, /* R3895 - ANC Coefficient */ + { 0x00000F38, 0x0000 }, /* R3896 - ANC Coefficient */ + { 0x00000F39, 0x0000 }, /* R3897 - ANC Coefficient */ + { 0x00000F3A, 0x0000 }, /* R3898 - ANC Coefficient */ + { 0x00000F3B, 0x0000 }, /* R3899 - ANC Coefficient */ + { 0x00000F3C, 0x0000 }, /* R3900 - ANC Coefficient */ + { 0x00000F3D, 0x0000 }, /* R3901 - ANC Coefficient */ + { 0x00000F3E, 0x0000 }, /* R3902 - ANC Coefficient */ + { 0x00000F3F, 0x0000 }, /* R3903 - ANC Coefficient */ + { 0x00000F40, 0x0000 }, /* R3904 - ANC Coefficient */ + { 0x00000F41, 0x0000 }, /* R3905 - ANC Coefficient */ + { 0x00000F42, 0x0000 }, /* R3906 - ANC Coefficient */ + { 0x00000F43, 0x0000 }, /* R3907 - ANC Coefficient */ + { 0x00000F44, 0x0000 }, /* R3908 - ANC Coefficient */ + { 0x00000F45, 0x0000 }, /* R3909 - ANC Coefficient */ + { 0x00000F46, 0x0000 }, /* R3910 - ANC Coefficient */ + { 0x00000F47, 0x0000 }, /* R3911 - ANC Coefficient */ + { 0x00000F48, 0x0000 }, /* R3912 - ANC Coefficient */ + { 0x00000F49, 0x0000 }, /* R3913 - ANC Coefficient */ + { 0x00000F4A, 0x0000 }, /* R3914 - ANC Coefficient */ + { 0x00000F4B, 0x0000 }, /* R3915 - ANC Coefficient */ + { 0x00000F4C, 0x0000 }, /* R3916 - ANC Coefficient */ + { 0x00000F4D, 0x0000 }, /* R3917 - ANC Coefficient */ + { 0x00000F4E, 0x0000 }, /* R3918 - ANC Coefficient */ + { 0x00000F4F, 0x0000 }, /* R3919 - ANC Coefficient */ + { 0x00000F50, 0x0000 }, /* R3920 - ANC Coefficient */ + { 0x00000F51, 0x0000 }, /* R3921 - ANC Coefficient */ + { 0x00000F52, 0x0000 }, /* R3922 - ANC Coefficient */ + { 0x00000F53, 0x0000 }, /* R3923 - ANC Coefficient */ + { 0x00000F54, 0x0000 }, /* R3924 - ANC Coefficient */ + { 0x00000F55, 0x0000 }, /* R3925 - ANC Coefficient */ + { 0x00000F56, 0x0000 }, /* R3926 - ANC Coefficient */ + { 0x00000F57, 0x0000 }, /* R3927 - ANC Coefficient */ + { 0x00000F58, 0x0000 }, /* R3928 - ANC Coefficient */ + { 0x00000F59, 0x0000 }, /* R3929 - ANC Coefficient */ + { 0x00000F5A, 0x0000 }, /* R3930 - ANC Coefficient */ + { 0x00000F5B, 0x0000 }, /* R3931 - ANC Coefficient */ + { 0x00000F5C, 0x0000 }, /* R3932 - ANC Coefficient */ + { 0x00000F5D, 0x0000 }, /* R3933 - ANC Coefficient */ + { 0x00000F5E, 0x0000 }, /* R3934 - ANC Coefficient */ + { 0x00000F5F, 0x0000 }, /* R3935 - ANC Coefficient */ + { 0x00000F60, 0x0000 }, /* R3936 - ANC Coefficient */ + { 0x00000F61, 0x0000 }, /* R3937 - ANC Coefficient */ + { 0x00000F62, 0x0000 }, /* R3938 - ANC Coefficient */ + { 0x00000F63, 0x0000 }, /* R3939 - ANC Coefficient */ + { 0x00000F64, 0x0000 }, /* R3940 - ANC Coefficient */ + { 0x00000F65, 0x0000 }, /* R3941 - ANC Coefficient */ + { 0x00000F66, 0x0000 }, /* R3942 - ANC Coefficient */ + { 0x00000F67, 0x0000 }, /* R3943 - ANC Coefficient */ + { 0x00000F68, 0x0000 }, /* R3944 - ANC Coefficient */ + { 0x00000F69, 0x0000 }, /* R3945 - ANC Coefficient */ + { 0x00000F71, 0x0000 }, /* R3953 - FCR Filter Control */ + { 0x00000F73, 0x0004 }, /* R3955 - FCR ADC Reformatter Control */ + { 0x00000F74, 0x0004 }, /* R3956 - ANC Coefficient */ + { 0x00000F75, 0x0002 }, /* R3957 - ANC Coefficient */ + { 0x00000F76, 0x0000 }, /* R3958 - ANC Coefficient */ + { 0x00000F77, 0x0010 }, /* R3959 - ANC Coefficient */ + { 0x00000F78, 0x0000 }, /* R3960 - ANC Coefficient */ + { 0x00000F79, 0x0000 }, /* R3961 - ANC Coefficient */ + { 0x00000F7A, 0x0000 }, /* R3962 - ANC Coefficient */ + { 0x00000F7B, 0x0000 }, /* R3963 - ANC Coefficient */ + { 0x00000F7C, 0x0000 }, /* R3964 - ANC Coefficient */ + { 0x00000F7D, 0x0000 }, /* R3965 - ANC Coefficient */ + { 0x00000F7E, 0x0000 }, /* R3966 - ANC Coefficient */ + { 0x00000F7F, 0x0000 }, /* R3967 - ANC Coefficient */ + { 0x00000F80, 0x0000 }, /* R3968 - ANC Coefficient */ + { 0x00000F81, 0x0000 }, /* R3969 - ANC Coefficient */ + { 0x00000F82, 0x0000 }, /* R3970 - ANC Coefficient */ + { 0x00000F83, 0x0000 }, /* R3971 - ANC Coefficient */ + { 0x00000F84, 0x0000 }, /* R3972 - ANC Coefficient */ + { 0x00000F85, 0x0000 }, /* R3973 - ANC Coefficient */ + { 0x00000F86, 0x0000 }, /* R3974 - ANC Coefficient */ + { 0x00000F87, 0x0000 }, /* R3975 - ANC Coefficient */ + { 0x00000F88, 0x0000 }, /* R3976 - ANC Coefficient */ + { 0x00000F89, 0x0000 }, /* R3977 - ANC Coefficient */ + { 0x00000F8A, 0x0000 }, /* R3978 - ANC Coefficient */ + { 0x00000F8B, 0x0000 }, /* R3979 - ANC Coefficient */ + { 0x00000F8C, 0x0000 }, /* R3980 - ANC Coefficient */ + { 0x00000F8D, 0x0000 }, /* R3981 - ANC Coefficient */ + { 0x00000F8E, 0x0000 }, /* R3982 - ANC Coefficient */ + { 0x00000F8F, 0x0000 }, /* R3983 - ANC Coefficient */ + { 0x00000F90, 0x0000 }, /* R3984 - ANC Coefficient */ + { 0x00000F91, 0x0000 }, /* R3985 - ANC Coefficient */ + { 0x00000F92, 0x0000 }, /* R3986 - ANC Coefficient */ + { 0x00000F93, 0x0000 }, /* R3987 - ANC Coefficient */ + { 0x00000F94, 0x0000 }, /* R3988 - ANC Coefficient */ + { 0x00000F95, 0x0000 }, /* R3989 - ANC Coefficient */ + { 0x00000F96, 0x0000 }, /* R3990 - ANC Coefficient */ + { 0x00000F97, 0x0000 }, /* R3991 - ANC Coefficient */ + { 0x00000F98, 0x0000 }, /* R3992 - ANC Coefficient */ + { 0x00000F99, 0x0000 }, /* R3993 - ANC Coefficient */ + { 0x00000F9A, 0x0000 }, /* R3994 - ANC Coefficient */ + { 0x00000F9B, 0x0000 }, /* R3995 - ANC Coefficient */ + { 0x00000F9C, 0x0000 }, /* R3996 - ANC Coefficient */ + { 0x00000F9D, 0x0000 }, /* R3997 - ANC Coefficient */ + { 0x00000F9E, 0x0000 }, /* R3998 - ANC Coefficient */ + { 0x00000F9F, 0x0000 }, /* R3999 - ANC Coefficient */ + { 0x00000FA0, 0x0000 }, /* R4000 - ANC Coefficient */ + { 0x00000FA1, 0x0000 }, /* R4001 - ANC Coefficient */ + { 0x00000FA2, 0x0000 }, /* R4002 - ANC Coefficient */ + { 0x00000FA3, 0x0000 }, /* R4003 - ANC Coefficient */ + { 0x00000FA4, 0x0000 }, /* R4004 - ANC Coefficient */ + { 0x00000FA5, 0x0000 }, /* R4005 - ANC Coefficient */ + { 0x00000FA6, 0x0000 }, /* R4006 - ANC Coefficient */ + { 0x00000FA7, 0x0000 }, /* R4007 - ANC Coefficient */ + { 0x00000FA8, 0x0000 }, /* R4008 - ANC Coefficient */ + { 0x00000FA9, 0x0000 }, /* R4009 - ANC Coefficient */ + { 0x00000FAA, 0x0000 }, /* R4010 - ANC Coefficient */ + { 0x00000FAB, 0x0000 }, /* R4011 - ANC Coefficient */ + { 0x00000FAC, 0x0000 }, /* R4012 - ANC Coefficient */ + { 0x00000FAD, 0x0000 }, /* R4013 - ANC Coefficient */ + { 0x00000FAE, 0x0000 }, /* R4014 - ANC Coefficient */ + { 0x00000FAF, 0x0000 }, /* R4015 - ANC Coefficient */ + { 0x00000FB0, 0x0000 }, /* R4016 - ANC Coefficient */ + { 0x00000FB1, 0x0000 }, /* R4017 - ANC Coefficient */ + { 0x00000FB2, 0x0000 }, /* R4018 - ANC Coefficient */ + { 0x00000FB3, 0x0000 }, /* R4019 - ANC Coefficient */ + { 0x00000FB4, 0x0000 }, /* R4020 - ANC Coefficient */ + { 0x00000FB5, 0x0000 }, /* R4021 - ANC Coefficient */ + { 0x00000FB6, 0x0000 }, /* R4022 - ANC Coefficient */ + { 0x00000FB7, 0x0000 }, /* R4023 - ANC Coefficient */ + { 0x00000FB8, 0x0000 }, /* R4024 - ANC Coefficient */ + { 0x00000FB9, 0x0000 }, /* R4025 - ANC Coefficient */ + { 0x00000FBA, 0x0000 }, /* R4026 - ANC Coefficient */ + { 0x00000FBB, 0x0000 }, /* R4027 - ANC Coefficient */ + { 0x00000FBC, 0x0000 }, /* R4028 - ANC Coefficient */ + { 0x00000FBD, 0x0000 }, /* R4029 - ANC Coefficient */ + { 0x00000FBE, 0x0000 }, /* R4030 - ANC Coefficient */ + { 0x00000FBF, 0x0000 }, /* R4031 - ANC Coefficient */ + { 0x00000FC0, 0x0000 }, /* R4032 - ANC Coefficient */ + { 0x00000FC1, 0x0000 }, /* R4033 - ANC Coefficient */ + { 0x00000FC2, 0x0000 }, /* R4034 - ANC Coefficient */ + { 0x00000FC3, 0x0000 }, /* R4035 - ANC Coefficient */ + { 0x00000FC4, 0x0000 }, /* R4036 - ANC Coefficient */ + { 0x00000FC5, 0x0000 }, /* R4037 - ANC Coefficient */ + { 0x00001300, 0x050E }, /* R4864 - DAC Comp 1 */ + { 0x00001302, 0x0101 }, /* R4866 - DAC Comp 2 */ + { 0x00001380, 0x0425 }, + { 0x00001381, 0xF6D8 }, + { 0x00001382, 0x0632 }, + { 0x00001383, 0xFEC8 }, + { 0x00001390, 0x042F }, + { 0x00001391, 0xF6CA }, + { 0x00001392, 0x0637 }, + { 0x00001393, 0xFEC8 }, + { 0x000013a0, 0x0000 }, + { 0x000013a1, 0x0000 }, + { 0x000013a2, 0x0000 }, + { 0x000013a3, 0x0000 }, + { 0x000013b0, 0x0000 }, + { 0x000013b1, 0x0000 }, + { 0x000013b2, 0x0000 }, + { 0x000013b3, 0x0000 }, + { 0x000013c0, 0x0000 }, + { 0x000013c1, 0x0000 }, + { 0x000013c2, 0x0000 }, + { 0x000013c3, 0x0000 }, + { 0x000013d0, 0x0000 }, + { 0x000013d1, 0x0000 }, + { 0x000013d2, 0x0000 }, + { 0x000013d3, 0x0000 }, + { 0x00001400, 0x0000 }, + { 0x00001401, 0x0000 }, + { 0x00001402, 0x0000 }, + { 0x00001403, 0x0000 }, + { 0x00001410, 0x0000 }, + { 0x00001411, 0x0000 }, + { 0x00001412, 0x0000 }, + { 0x00001413, 0x0000 }, + { 0x00001480, 0x0000 }, /*R5248 - DFC1_CTRL*/ + { 0x00001482, 0x1F00 }, /*R5250 - DFC1_RX*/ + { 0x00001484, 0x1F00 }, /*R5252 - DFC1_TX*/ + { 0x00001486, 0x0000 }, + { 0x00001488, 0x1F00 }, + { 0x0000148A, 0x1F00 }, + { 0x0000148C, 0x0000 }, + { 0x0000148E, 0x1F00 }, + { 0x00001490, 0x1F00 }, + { 0x00001492, 0x0000 }, + { 0x00001494, 0x1F00 }, + { 0x00001496, 0x1F00 }, + { 0x00001498, 0x0000 }, + { 0x0000149A, 0x1F00 }, + { 0x0000149C, 0x1F00 }, + { 0x0000149E, 0x0000 }, + { 0x000014A0, 0x1F00 }, + { 0x000014A2, 0x1F00 }, + { 0x000014A4, 0x0000 }, + { 0x000014A6, 0x1F00 }, + { 0x000014A8, 0x1F00 }, + { 0x000014AA, 0x0000 }, + { 0x000014AC, 0x1F00 }, + { 0x000014AE, 0x1F00 }, /*R5294 - DFC8_TX */ + { 0x00001701, 0xF000 }, /* R5889 - GPIO1 Control 2 */ + { 0x00001703, 0xF000 }, /* R5891 - GPIO2 Control 2 */ + { 0x00001705, 0xF000 }, /* R5893 - GPIO3 Control 2 */ + { 0x00001707, 0xF000 }, /* R5895 - GPIO4 Control 2 */ + { 0x00001709, 0xF000 }, /* R5897 - GPIO5 Control 2 */ + { 0x0000170B, 0xF000 }, /* R5899 - GPIO6 Control 2 */ + { 0x0000170D, 0xF000 }, /* R5901 - GPIO7 Control 2 */ + { 0x0000170F, 0xF000 }, /* R5903 - GPIO8 Control 2 */ + { 0x00001711, 0xF000 }, /* R5905 - GPIO9 Control 2 */ + { 0x00001713, 0xF000 }, /* R5907 - GPIO10 Control 2 */ + { 0x00001715, 0xF000 }, /* R5909 - GPIO11 Control 2 */ + { 0x00001717, 0xF000 }, /* R5911 - GPIO12 Control 2 */ + { 0x00001719, 0xF000 }, /* R5913 - GPIO13 Control 2 */ + { 0x0000171B, 0xF000 }, /* R5915 - GPIO14 Control 2 */ + { 0x0000171D, 0xF000 }, /* R5917 - GPIO15 Control 2 */ + { 0x0000171F, 0xF000 }, /* R5919 - GPIO16 Control 2 */ + { 0x00001721, 0xF000 }, /* R5921 - GPIO17 Control 2 */ + { 0x00001723, 0xF000 }, /* R5923 - GPIO18 Control 2 */ + { 0x00001725, 0xF000 }, /* R5925 - GPIO19 Control 2 */ + { 0x00001727, 0xF000 }, /* R5927 - GPIO20 Control 2 */ + { 0x00001729, 0xF000 }, /* R5929 - GPIO21 Control 2 */ + { 0x0000172B, 0xF000 }, /* R5931 - GPIO22 Control 2 */ + { 0x0000172D, 0xF000 }, /* R5933 - GPIO23 Control 2 */ + { 0x0000172F, 0xF000 }, /* R5935 - GPIO24 Control 2 */ + { 0x00001731, 0xF000 }, /* R5937 - GPIO25 Control 2 */ + { 0x00001733, 0xF000 }, /* R5939 - GPIO26 Control 2 */ + { 0x00001735, 0xF000 }, /* R5941 - GPIO27 Control 2 */ + { 0x00001737, 0xF000 }, /* R5943 - GPIO28 Control 2 */ + { 0x00001739, 0xF000 }, /* R5945 - GPIO29 Control 2 */ + { 0x0000173B, 0xF000 }, /* R5947 - GPIO30 Control 2 */ + { 0x0000173D, 0xF000 }, /* R5949 - GPIO31 Control 2 */ + { 0x0000173F, 0xF000 }, /* R5951 - GPIO32 Control 2 */ + { 0x00001741, 0xF000 }, /* R5953 - GPIO33 Control 2 */ + { 0x00001743, 0xF000 }, /* R5955 - GPIO34 Control 2 */ + { 0x00001745, 0xF000 }, /* R5957 - GPIO35 Control 2 */ + { 0x00001747, 0xF000 }, /* R5959 - GPIO36 Control 2 */ + { 0x00001749, 0xF000 }, /* R5961 - GPIO37 Control 2 */ + { 0x0000174B, 0xF000 }, /* R5963 - GPIO38 Control 2 */ + { 0x00001840, 0x9200 }, /* R6208 - IRQ1 Mask 1 */ + { 0x00001841, 0xFB00 }, /* R6209 - IRQ1 Mask 2 */ + { 0x00001842, 0xFFFF }, /* R6210 - IRQ1 Mask 3 */ + { 0x00001843, 0xFFFF }, /* R6211 - IRQ1 Mask 4 */ + { 0x00001844, 0xFFFF }, /* R6212 - IRQ1 Mask 5 */ + { 0x00001845, 0x0301 }, /* R6213 - IRQ1 Mask 6 */ + { 0x00001846, 0x003F }, /* R6214 - IRQ1 Mask 7 */ + { 0x00001847, 0xFFFF }, /* R6215 - IRQ1 Mask 8 */ + { 0x00001848, 0x0F07 }, /* R6216 - IRQ1 Mask 9 */ + { 0x00001849, 0xFFFF }, /* R6217 - IRQ1 Mask 10 */ + { 0x0000184A, 0xFFFF }, /* R6218 - IRQ1 Mask 11 */ + { 0x0000184B, 0x003F }, /* R6219 - IRQ1 Mask 12 */ + { 0x0000184C, 0x003F }, /* R6220 - IRQ1 Mask 13 */ + { 0x0000184D, 0x003F }, /* R6221 - IRQ1 Mask 14 */ + { 0x0000184E, 0xFFFF }, /* R6222 - IRQ1 Mask 15 */ + { 0x0000184F, 0xFFFF }, /* R6223 - IRQ1 Mask 16 */ + { 0x00001850, 0xFFFF }, /* R6224 - IRQ1 Mask 17 */ + { 0x00001851, 0xFFFF }, /* R6225 - IRQ1 Mask 18 */ + { 0x00001852, 0x003F }, /* R6226 - IRQ1 Mask 19 */ + { 0x00001853, 0xFFFF }, /* R6227 - IRQ1 Mask 20 */ + { 0x00001854, 0x00FF }, /* R6228 - IRQ1 Mask 21 */ + { 0x00001855, 0x00FF }, /* R6229 - IRQ1 Mask 22 */ + { 0x00001856, 0x00FF }, /* R6230 - IRQ1 Mask 23 */ + { 0x00001857, 0x00FF }, /* R6231 - IRQ1 Mask 24 */ + { 0x00001858, 0x007F }, /* R6232 - IRQ1 Mask 25 */ + { 0x00001859, 0xFFFF }, /* R6233 - IRQ1 Mask 26 */ + { 0x0000185A, 0x007F }, /* R6234 - IRQ1 Mask 27 */ + { 0x0000185B, 0x007F }, /* R6235 - IRQ1 Mask 28 */ + { 0x0000185C, 0xFFFF }, /* R6236 - IRQ1 Mask 29 */ + { 0x0000185D, 0x007F }, /* R6237 - IRQ1 Mask 30 */ + { 0x0000185E, 0x0007 }, /* R6238 - IRQ1 Mask 31 */ + { 0x0000185F, 0x0007 }, /* R6239 - IRQ1 Mask 32 */ + { 0x00001860, 0x007F }, /* R6240 - IRQ1 Mask 33 */ + { 0x00001948, 0x0F07 }, /* R6472 - IRQ2 Mask 9 */ + { 0x00001A06, 0x0000 }, /* R6662 - Interrupt Debounce 7 */ + { 0x00001A80, 0x4400 }, /* R6784 - IRQ1 CTRL */ +}; + +static bool moon_is_adsp_memory(struct device *dev, unsigned int reg) +{ + if ((reg >= 0x080000 && reg <= 0x088ffe) || + (reg >= 0x0a0000 && reg <= 0x0a9ffe) || + (reg >= 0x0c0000 && reg <= 0x0c3ffe) || + (reg >= 0x0e0000 && reg <= 0x0e1ffe) || + (reg >= 0x100000 && reg <= 0x10effe) || + (reg >= 0x120000 && reg <= 0x12bffe) || + (reg >= 0x136000 && reg <= 0x137ffe) || + (reg >= 0x140000 && reg <= 0x14bffe) || + (reg >= 0x160000 && reg <= 0x161ffe) || + (reg >= 0x180000 && reg <= 0x18effe) || + (reg >= 0x1a0000 && reg <= 0x1b1ffe) || + (reg >= 0x1b6000 && reg <= 0x1b7ffe) || + (reg >= 0x1c0000 && reg <= 0x1cbffe) || + (reg >= 0x1e0000 && reg <= 0x1e1ffe) || + (reg >= 0x200000 && reg <= 0x208ffe) || + (reg >= 0x220000 && reg <= 0x229ffe) || + (reg >= 0x240000 && reg <= 0x243ffe) || + (reg >= 0x260000 && reg <= 0x261ffe) || + (reg >= 0x280000 && reg <= 0x288ffe) || + (reg >= 0x2a0000 && reg <= 0x2a9ffe) || + (reg >= 0x2c0000 && reg <= 0x2c3ffe) || + (reg >= 0x2e0000 && reg <= 0x2e1ffe) || + (reg >= 0x300000 && reg <= 0x308ffe) || + (reg >= 0x320000 && reg <= 0x333ffe) || + (reg >= 0x340000 && reg <= 0x353ffe) || + (reg >= 0x360000 && reg <= 0x361ffe) || + (reg >= 0x380000 && reg <= 0x388ffe) || + (reg >= 0x3a0000 && reg <= 0x3b3ffe) || + (reg >= 0x3c0000 && reg <= 0x3d3ffe) || + (reg >= 0x3e0000 && reg <= 0x3e1ffe)) + return true; + else + return false; +} + +static bool moon_16bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_SPI_CFG_1: + case ARIZONA_CTRL_IF_I2C1_CFG_1: + case ARIZONA_CTRL_IF_I2C2_CFG_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case CLEARWATER_COMFORT_NOISE_GENERATOR: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_CLOCK_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case CLEARWATER_DSP_CLOCK_1: + case CLEARWATER_DSP_CLOCK_2: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_OUTPUT_ASYNC_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_CONTROL_7: + case ARIZONA_FLL1_EFS_2: + case ARIZONA_FLL1_LOOP_FILTER_TEST_1: + case ARIZONA_FLL1_NCO_TEST_0: + case ARIZONA_FLL1_SYNCHRONISER_1: + case ARIZONA_FLL1_SYNCHRONISER_2: + case ARIZONA_FLL1_SYNCHRONISER_3: + case ARIZONA_FLL1_SYNCHRONISER_4: + case ARIZONA_FLL1_SYNCHRONISER_5: + case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SYNCHRONISER_7: + case ARIZONA_FLL1_SPREAD_SPECTRUM: + case ARIZONA_FLL1_GPIO_CLOCK: + case ARIZONA_FLL2_CONTROL_1: + case ARIZONA_FLL2_CONTROL_2: + case ARIZONA_FLL2_CONTROL_3: + case ARIZONA_FLL2_CONTROL_4: + case ARIZONA_FLL2_CONTROL_5: + case ARIZONA_FLL2_CONTROL_6: + case ARIZONA_FLL2_CONTROL_7: + case ARIZONA_FLL2_EFS_2: + case ARIZONA_FLL2_LOOP_FILTER_TEST_1: + case ARIZONA_FLL2_NCO_TEST_0: + case ARIZONA_FLL2_SYNCHRONISER_1: + case ARIZONA_FLL2_SYNCHRONISER_2: + case ARIZONA_FLL2_SYNCHRONISER_3: + case ARIZONA_FLL2_SYNCHRONISER_4: + case ARIZONA_FLL2_SYNCHRONISER_5: + case ARIZONA_FLL2_SYNCHRONISER_6: + case ARIZONA_FLL2_SYNCHRONISER_7: + case ARIZONA_FLL2_SPREAD_SPECTRUM: + case ARIZONA_FLL2_GPIO_CLOCK: + case MOON_FLLAO_CONTROL_1: + case MOON_FLLAO_CONTROL_2: + case MOON_FLLAO_CONTROL_3: + case MOON_FLLAO_CONTROL_4: + case MOON_FLLAO_CONTROL_5: + case MOON_FLLAO_CONTROL_6: + case MOON_FLLAO_CONTROL_7: + case MOON_FLLAO_CONTROL_8: + case MOON_FLLAO_CONTROL_9: + case MOON_FLLAO_CONTROL_10: + case MOON_FLLAO_CONTROL_11: + case ARIZONA_MIC_CHARGE_PUMP_1: + case ARIZONA_LDO2_CONTROL_1: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_2: + case ARIZONA_MIC_BIAS_CTRL_5: + case ARIZONA_MIC_BIAS_CTRL_6: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HP_CTRL_2L: + case ARIZONA_HP_CTRL_2R: + case ARIZONA_HP_CTRL_3L: + case ARIZONA_HP_CTRL_3R: + case CLEARWATER_EDRE_HP_STEREO_CONTROL: + case ARIZONA_ACCESSORY_DETECT_MODE_1: + case MOON_HEADPHONE_DETECT_0: + case ARIZONA_HEADPHONE_DETECT_1: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case CLEARWATER_MICD_CLAMP_CONTROL: + case MOON_MIC_DETECT_0: + case ARIZONA_MIC_DETECT_1: + case ARIZONA_MIC_DETECT_2: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_MIC_DETECT_LEVEL_1: + case ARIZONA_MIC_DETECT_LEVEL_2: + case ARIZONA_MIC_DETECT_LEVEL_3: + case ARIZONA_MIC_DETECT_LEVEL_4: + case MOON_MICDET2_CONTROL_0: + case MOON_MICDET2_CONTROL_1: + case MOON_MICDET2_CONTROL_2: + case MOON_MICDET2_CONTROL_3: + case MOON_MICDET2_CONTROL_4: + case MOON_MICDET2_LEVEL_1: + case MOON_MICDET2_LEVEL_2: + case MOON_MICDET2_LEVEL_3: + case MOON_MICDET2_LEVEL_4: + case CLEARWATER_GP_SWITCH_1: + case ARIZONA_JACK_DETECT_ANALOGUE: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case MOON_IN1L_RATE_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case MOON_IN1R_RATE_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case MOON_IN2L_RATE_CONTROL: + case ARIZONA_IN2R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2R: + case ARIZONA_DMIC2R_CONTROL: + case MOON_IN2R_RATE_CONTROL: + case ARIZONA_IN3L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_3L: + case ARIZONA_DMIC3L_CONTROL: + case MOON_IN3L_RATE_CONTROL: + case ARIZONA_IN3R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_3R: + case ARIZONA_DMIC3R_CONTROL: + case MOON_IN3R_RATE_CONTROL: + case ARIZONA_IN4L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_4L: + case ARIZONA_DMIC4L_CONTROL: + case MOON_IN4L_RATE_CONTROL: + case ARIZONA_IN4R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_4R: + case ARIZONA_DMIC4R_CONTROL: + case MOON_IN4R_RATE_CONTROL: + case ARIZONA_IN5L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_5L: + case ARIZONA_DMIC5L_CONTROL: + case MOON_IN5L_RATE_CONTROL: + case ARIZONA_IN5R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_5R: + case ARIZONA_DMIC5R_CONTROL: + case MOON_IN5R_RATE_CONTROL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case MOON_OUT1_CONFIG: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_OUTPUT_PATH_CONFIG_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case ARIZONA_OUTPUT_PATH_CONFIG_2L: + case ARIZONA_DAC_DIGITAL_VOLUME_2L: + case MOON_OUT2_CONFIG: + case ARIZONA_NOISE_GATE_SELECT_2L: + case ARIZONA_OUTPUT_PATH_CONFIG_2R: + case ARIZONA_DAC_DIGITAL_VOLUME_2R: + case ARIZONA_NOISE_GATE_SELECT_2R: + case ARIZONA_OUTPUT_PATH_CONFIG_3L: + case ARIZONA_DAC_DIGITAL_VOLUME_3L: + case ARIZONA_NOISE_GATE_SELECT_3L: + case ARIZONA_OUTPUT_PATH_CONFIG_3R: + case ARIZONA_DAC_DIGITAL_VOLUME_3R: + case ARIZONA_NOISE_GATE_SELECT_3R: + case ARIZONA_OUTPUT_PATH_CONFIG_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5L: + case ARIZONA_NOISE_GATE_SELECT_5L: + case ARIZONA_OUTPUT_PATH_CONFIG_5R: + case ARIZONA_DAC_DIGITAL_VOLUME_5R: + case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_DRE_ENABLE: + case CLEARWATER_EDRE_ENABLE: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_PDM_SPK1_CTRL_1: + case ARIZONA_PDM_SPK1_CTRL_2: + case ARIZONA_HP1_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP2_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP3_SHORT_CIRCUIT_CTRL: + case ARIZONA_HP_TEST_CTRL_5: + case ARIZONA_HP_TEST_CTRL_6: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_TX_BCLK_RATE: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_9: + case ARIZONA_AIF1_FRAME_CTRL_10: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_FRAME_CTRL_17: + case ARIZONA_AIF1_FRAME_CTRL_18: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_TX_BCLK_RATE: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_5: + case ARIZONA_AIF2_FRAME_CTRL_6: + case ARIZONA_AIF2_FRAME_CTRL_7: + case ARIZONA_AIF2_FRAME_CTRL_8: + case ARIZONA_AIF2_FRAME_CTRL_9: + case ARIZONA_AIF2_FRAME_CTRL_10: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_FRAME_CTRL_13: + case ARIZONA_AIF2_FRAME_CTRL_14: + case ARIZONA_AIF2_FRAME_CTRL_15: + case ARIZONA_AIF2_FRAME_CTRL_16: + case ARIZONA_AIF2_FRAME_CTRL_17: + case ARIZONA_AIF2_FRAME_CTRL_18: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_AIF3_BCLK_CTRL: + case ARIZONA_AIF3_TX_PIN_CTRL: + case ARIZONA_AIF3_RX_PIN_CTRL: + case ARIZONA_AIF3_RATE_CTRL: + case ARIZONA_AIF3_FORMAT: + case ARIZONA_AIF3_TX_BCLK_RATE: + case ARIZONA_AIF3_RX_BCLK_RATE: + case ARIZONA_AIF3_FRAME_CTRL_1: + case ARIZONA_AIF3_FRAME_CTRL_2: + case ARIZONA_AIF3_FRAME_CTRL_3: + case ARIZONA_AIF3_FRAME_CTRL_4: + case ARIZONA_AIF3_FRAME_CTRL_11: + case ARIZONA_AIF3_FRAME_CTRL_12: + case ARIZONA_AIF3_TX_ENABLES: + case ARIZONA_AIF3_RX_ENABLES: + case ARIZONA_AIF4_BCLK_CTRL: + case ARIZONA_AIF4_TX_PIN_CTRL: + case ARIZONA_AIF4_RX_PIN_CTRL: + case ARIZONA_AIF4_RATE_CTRL: + case ARIZONA_AIF4_FORMAT: + case ARIZONA_AIF4_TX_BCLK_RATE: + case ARIZONA_AIF4_RX_BCLK_RATE: + case ARIZONA_AIF4_FRAME_CTRL_1: + case ARIZONA_AIF4_FRAME_CTRL_2: + case ARIZONA_AIF4_FRAME_CTRL_3: + case ARIZONA_AIF4_FRAME_CTRL_4: + case ARIZONA_AIF4_FRAME_CTRL_11: + case ARIZONA_AIF4_FRAME_CTRL_12: + case ARIZONA_AIF4_TX_ENABLES: + case ARIZONA_AIF4_RX_ENABLES: + case ARIZONA_SPD1_TX_CONTROL: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_FRAMER_REF_GEAR: + case ARIZONA_SLIMBUS_RATES_1: + case ARIZONA_SLIMBUS_RATES_2: + case ARIZONA_SLIMBUS_RATES_3: + case ARIZONA_SLIMBUS_RATES_4: + case ARIZONA_SLIMBUS_RATES_5: + case ARIZONA_SLIMBUS_RATES_6: + case ARIZONA_SLIMBUS_RATES_7: + case ARIZONA_SLIMBUS_RATES_8: + case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT3RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT3RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX7MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX7MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX8MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX8MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF4TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF4TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF4TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF4TX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME: + case ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_2_SOURCE: + case ARIZONA_EQ1MIX_INPUT_2_VOLUME: + case ARIZONA_EQ1MIX_INPUT_3_SOURCE: + case ARIZONA_EQ1MIX_INPUT_3_VOLUME: + case ARIZONA_EQ1MIX_INPUT_4_SOURCE: + case ARIZONA_EQ1MIX_INPUT_4_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_2_SOURCE: + case ARIZONA_EQ2MIX_INPUT_2_VOLUME: + case ARIZONA_EQ2MIX_INPUT_3_SOURCE: + case ARIZONA_EQ2MIX_INPUT_3_VOLUME: + case ARIZONA_EQ2MIX_INPUT_4_SOURCE: + case ARIZONA_EQ2MIX_INPUT_4_VOLUME: + case ARIZONA_EQ3MIX_INPUT_1_SOURCE: + case ARIZONA_EQ3MIX_INPUT_1_VOLUME: + case ARIZONA_EQ3MIX_INPUT_2_SOURCE: + case ARIZONA_EQ3MIX_INPUT_2_VOLUME: + case ARIZONA_EQ3MIX_INPUT_3_SOURCE: + case ARIZONA_EQ3MIX_INPUT_3_VOLUME: + case ARIZONA_EQ3MIX_INPUT_4_SOURCE: + case ARIZONA_EQ3MIX_INPUT_4_VOLUME: + case ARIZONA_EQ4MIX_INPUT_1_SOURCE: + case ARIZONA_EQ4MIX_INPUT_1_VOLUME: + case ARIZONA_EQ4MIX_INPUT_2_SOURCE: + case ARIZONA_EQ4MIX_INPUT_2_VOLUME: + case ARIZONA_EQ4MIX_INPUT_3_SOURCE: + case ARIZONA_EQ4MIX_INPUT_3_VOLUME: + case ARIZONA_EQ4MIX_INPUT_4_SOURCE: + case ARIZONA_EQ4MIX_INPUT_4_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC2RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC2RMIX_INPUT_4_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP1RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP1RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP2RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP2RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP3RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP3RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_1_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_1_VOLUME: + case ARIZONA_DSP4LMIX_INPUT_2_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_2_VOLUME: + case ARIZONA_DSP4LMIX_INPUT_3_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_3_VOLUME: + case ARIZONA_DSP4LMIX_INPUT_4_SOURCE: + case ARIZONA_DSP4LMIX_INPUT_4_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_1_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_1_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_2_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_2_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_3_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_3_VOLUME: + case ARIZONA_DSP4RMIX_INPUT_4_SOURCE: + case ARIZONA_DSP4RMIX_INPUT_4_VOLUME: + case ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE: + case ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP5LMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP5LMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP5LMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP5LMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP5RMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP5RMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP5AUX1MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX3MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX4MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX5MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP5AUX6MIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_1RMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC1_2RMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_1RMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE: + case CLEARWATER_ASRC2_2RMIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC4INT2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP6LMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP6LMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP6LMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP6LMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP6RMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP6RMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP6AUX1MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX3MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX4MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX5MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP6AUX6MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP7LMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP7LMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP7LMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP7LMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_1_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_2_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_2_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_3_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_3_VOLUME: + case CLEARWATER_DSP7RMIX_INPUT_4_SOURCE: + case CLEARWATER_DSP7RMIX_INPUT_4_VOLUME: + case CLEARWATER_DSP7AUX1MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX2MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX3MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX4MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX5MIX_INPUT_1_SOURCE: + case CLEARWATER_DSP7AUX6MIX_INPUT_1_SOURCE: + case MOON_DFC1MIX_INPUT_1_SOURCE: + case MOON_DFC2MIX_INPUT_1_SOURCE: + case MOON_DFC3MIX_INPUT_1_SOURCE: + case MOON_DFC4MIX_INPUT_1_SOURCE: + case MOON_DFC5MIX_INPUT_1_SOURCE: + case MOON_DFC6MIX_INPUT_1_SOURCE: + case MOON_DFC7MIX_INPUT_1_SOURCE: + case MOON_DFC8MIX_INPUT_1_SOURCE: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_EQ3_1: + case ARIZONA_EQ3_2: + case ARIZONA_EQ3_3: + case ARIZONA_EQ3_4: + case ARIZONA_EQ3_5: + case ARIZONA_EQ3_6: + case ARIZONA_EQ3_7: + case ARIZONA_EQ3_8: + case ARIZONA_EQ3_9: + case ARIZONA_EQ3_10: + case ARIZONA_EQ3_11: + case ARIZONA_EQ3_12: + case ARIZONA_EQ3_13: + case ARIZONA_EQ3_14: + case ARIZONA_EQ3_15: + case ARIZONA_EQ3_16: + case ARIZONA_EQ3_17: + case ARIZONA_EQ3_18: + case ARIZONA_EQ3_19: + case ARIZONA_EQ3_20: + case ARIZONA_EQ3_21: + case ARIZONA_EQ4_1: + case ARIZONA_EQ4_2: + case ARIZONA_EQ4_3: + case ARIZONA_EQ4_4: + case ARIZONA_EQ4_5: + case ARIZONA_EQ4_6: + case ARIZONA_EQ4_7: + case ARIZONA_EQ4_8: + case ARIZONA_EQ4_9: + case ARIZONA_EQ4_10: + case ARIZONA_EQ4_11: + case ARIZONA_EQ4_12: + case ARIZONA_EQ4_13: + case ARIZONA_EQ4_14: + case ARIZONA_EQ4_15: + case ARIZONA_EQ4_16: + case ARIZONA_EQ4_17: + case ARIZONA_EQ4_18: + case ARIZONA_EQ4_19: + case ARIZONA_EQ4_20: + case ARIZONA_EQ4_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case CLEARWATER_DRC2_CTRL1: + case CLEARWATER_DRC2_CTRL2: + case CLEARWATER_DRC2_CTRL3: + case CLEARWATER_DRC2_CTRL4: + case CLEARWATER_DRC2_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case CLEARWATER_ASRC1_ENABLE: + case CLEARWATER_ASRC1_STATUS: + case CLEARWATER_ASRC1_RATE1: + case CLEARWATER_ASRC1_RATE2: + case CLEARWATER_ASRC2_ENABLE: + case CLEARWATER_ASRC2_STATUS: + case CLEARWATER_ASRC2_RATE1: + case CLEARWATER_ASRC2_RATE2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + case ARIZONA_ISRC_3_CTRL_1: + case ARIZONA_ISRC_3_CTRL_2: + case ARIZONA_ISRC_3_CTRL_3: + case ARIZONA_ISRC_4_CTRL_1: + case ARIZONA_ISRC_4_CTRL_2: + case ARIZONA_ISRC_4_CTRL_3: + case ARIZONA_CLOCK_CONTROL: + case ARIZONA_ANC_SRC: + case ARIZONA_DSP_STATUS: + case ARIZONA_ANC_COEFF_START ... ARIZONA_ANC_COEFF_END: + case ARIZONA_FCL_FILTER_CONTROL: + case ARIZONA_FCL_ADC_REFORMATTER_CONTROL: + case ARIZONA_FCL_COEFF_START ... ARIZONA_FCL_COEFF_END: + case CLEARWATER_FCR_FILTER_CONTROL: + case CLEARWATER_FCR_ADC_REFORMATTER_CONTROL: + case CLEARWATER_FCR_COEFF_START ... CLEARWATER_FCR_COEFF_END: + case CLEARWATER_DAC_COMP_1: + case CLEARWATER_DAC_COMP_2: + case CLEARWATER_FRF_COEFFICIENT_1L_1: + case CLEARWATER_FRF_COEFFICIENT_1L_2: + case CLEARWATER_FRF_COEFFICIENT_1L_3: + case CLEARWATER_FRF_COEFFICIENT_1L_4: + case CLEARWATER_FRF_COEFFICIENT_1R_1: + case CLEARWATER_FRF_COEFFICIENT_1R_2: + case CLEARWATER_FRF_COEFFICIENT_1R_3: + case CLEARWATER_FRF_COEFFICIENT_1R_4: + case CLEARWATER_FRF_COEFFICIENT_2L_1: + case CLEARWATER_FRF_COEFFICIENT_2L_2: + case CLEARWATER_FRF_COEFFICIENT_2L_3: + case CLEARWATER_FRF_COEFFICIENT_2L_4: + case CLEARWATER_FRF_COEFFICIENT_2R_1: + case CLEARWATER_FRF_COEFFICIENT_2R_2: + case CLEARWATER_FRF_COEFFICIENT_2R_3: + case CLEARWATER_FRF_COEFFICIENT_2R_4: + case CLEARWATER_FRF_COEFFICIENT_3L_1: + case CLEARWATER_FRF_COEFFICIENT_3L_2: + case CLEARWATER_FRF_COEFFICIENT_3L_3: + case CLEARWATER_FRF_COEFFICIENT_3L_4: + case CLEARWATER_FRF_COEFFICIENT_3R_1: + case CLEARWATER_FRF_COEFFICIENT_3R_2: + case CLEARWATER_FRF_COEFFICIENT_3R_3: + case CLEARWATER_FRF_COEFFICIENT_3R_4: + case CLEARWATER_FRF_COEFFICIENT_5L_1: + case CLEARWATER_FRF_COEFFICIENT_5L_2: + case CLEARWATER_FRF_COEFFICIENT_5L_3: + case CLEARWATER_FRF_COEFFICIENT_5L_4: + case CLEARWATER_FRF_COEFFICIENT_5R_1: + case CLEARWATER_FRF_COEFFICIENT_5R_2: + case CLEARWATER_FRF_COEFFICIENT_5R_3: + case CLEARWATER_FRF_COEFFICIENT_5R_4: + case MOON_DFC1_CTRL: + case MOON_DFC1_RX: + case MOON_DFC1_TX: + case MOON_DFC2_CTRL: + case MOON_DFC2_RX: + case MOON_DFC2_TX: + case MOON_DFC3_CTRL: + case MOON_DFC3_RX: + case MOON_DFC3_TX: + case MOON_DFC4_CTRL: + case MOON_DFC4_RX: + case MOON_DFC4_TX: + case MOON_DFC5_CTRL: + case MOON_DFC5_RX: + case MOON_DFC5_TX: + case MOON_DFC6_CTRL: + case MOON_DFC6_RX: + case MOON_DFC6_TX: + case MOON_DFC7_CTRL: + case MOON_DFC7_RX: + case MOON_DFC7_TX: + case MOON_DFC8_CTRL: + case MOON_DFC8_RX: + case MOON_DFC8_TX: + case MOON_DFC_STATUS: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO1_CTRL_2: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO2_CTRL_2: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO3_CTRL_2: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO4_CTRL_2: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO5_CTRL_2: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO6_CTRL_2: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO7_CTRL_2: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO8_CTRL_2: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO9_CTRL_2: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO10_CTRL_2: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO11_CTRL_2: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO12_CTRL_2: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO13_CTRL_2: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO14_CTRL_2: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO15_CTRL_2: + case CLEARWATER_GPIO16_CTRL_1: + case CLEARWATER_GPIO16_CTRL_2: + case CLEARWATER_GPIO17_CTRL_1: + case CLEARWATER_GPIO17_CTRL_2: + case CLEARWATER_GPIO18_CTRL_1: + case CLEARWATER_GPIO18_CTRL_2: + case CLEARWATER_GPIO19_CTRL_1: + case CLEARWATER_GPIO19_CTRL_2: + case CLEARWATER_GPIO20_CTRL_1: + case CLEARWATER_GPIO20_CTRL_2: + case CLEARWATER_GPIO21_CTRL_1: + case CLEARWATER_GPIO21_CTRL_2: + case CLEARWATER_GPIO22_CTRL_1: + case CLEARWATER_GPIO22_CTRL_2: + case CLEARWATER_GPIO23_CTRL_1: + case CLEARWATER_GPIO23_CTRL_2: + case CLEARWATER_GPIO24_CTRL_1: + case CLEARWATER_GPIO24_CTRL_2: + case CLEARWATER_GPIO25_CTRL_1: + case CLEARWATER_GPIO25_CTRL_2: + case CLEARWATER_GPIO26_CTRL_1: + case CLEARWATER_GPIO26_CTRL_2: + case CLEARWATER_GPIO27_CTRL_1: + case CLEARWATER_GPIO27_CTRL_2: + case CLEARWATER_GPIO28_CTRL_1: + case CLEARWATER_GPIO28_CTRL_2: + case CLEARWATER_GPIO29_CTRL_1: + case CLEARWATER_GPIO29_CTRL_2: + case CLEARWATER_GPIO30_CTRL_1: + case CLEARWATER_GPIO30_CTRL_2: + case CLEARWATER_GPIO31_CTRL_1: + case CLEARWATER_GPIO31_CTRL_2: + case CLEARWATER_GPIO32_CTRL_1: + case CLEARWATER_GPIO32_CTRL_2: + case CLEARWATER_GPIO33_CTRL_1: + case CLEARWATER_GPIO33_CTRL_2: + case CLEARWATER_GPIO34_CTRL_1: + case CLEARWATER_GPIO34_CTRL_2: + case CLEARWATER_GPIO35_CTRL_1: + case CLEARWATER_GPIO35_CTRL_2: + case CLEARWATER_GPIO36_CTRL_1: + case CLEARWATER_GPIO36_CTRL_2: + case CLEARWATER_GPIO37_CTRL_1: + case CLEARWATER_GPIO37_CTRL_2: + case CLEARWATER_GPIO38_CTRL_1: + case CLEARWATER_GPIO38_CTRL_2: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case MOON_IRQ1_STATUS_33: + case CLEARWATER_IRQ1_MASK_1: + case CLEARWATER_IRQ1_MASK_2: + case CLEARWATER_IRQ1_MASK_3: + case CLEARWATER_IRQ1_MASK_4: + case CLEARWATER_IRQ1_MASK_5: + case CLEARWATER_IRQ1_MASK_6: + case CLEARWATER_IRQ1_MASK_7: + case CLEARWATER_IRQ1_MASK_8: + case CLEARWATER_IRQ1_MASK_9: + case CLEARWATER_IRQ1_MASK_10: + case CLEARWATER_IRQ1_MASK_11: + case CLEARWATER_IRQ1_MASK_12: + case CLEARWATER_IRQ1_MASK_13: + case CLEARWATER_IRQ1_MASK_14: + case CLEARWATER_IRQ1_MASK_15: + case MOON_IRQ1_MASK_16: + case CLEARWATER_IRQ1_MASK_17: + case CLEARWATER_IRQ1_MASK_18: + case CLEARWATER_IRQ1_MASK_19: + case MOON_IRQ1_MASK_20: + case CLEARWATER_IRQ1_MASK_21: + case CLEARWATER_IRQ1_MASK_22: + case CLEARWATER_IRQ1_MASK_23: + case CLEARWATER_IRQ1_MASK_24: + case CLEARWATER_IRQ1_MASK_25: + case MOON_IRQ1_MASK_26: + case CLEARWATER_IRQ1_MASK_27: + case CLEARWATER_IRQ1_MASK_28: + case MOON_IRQ1_MASK_29: + case CLEARWATER_IRQ1_MASK_30: + case CLEARWATER_IRQ1_MASK_31: + case CLEARWATER_IRQ1_MASK_32: + case MOON_IRQ1_MASK_33: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_11: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_18: + case CLEARWATER_IRQ1_RAW_STATUS_19: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_MASK_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + case CLEARWATER_INTERRUPT_DEBOUNCE_7: + case CLEARWATER_IRQ1_CTRL: + return true; + default: + return false; + } +} + +static bool moon_16bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HP_CTRL_2L: + case ARIZONA_HP_CTRL_2R: + case ARIZONA_HP_CTRL_3L: + case ARIZONA_HP_CTRL_3R: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case MOON_MICDET2_CONTROL_3: + case MOON_MICDET2_CONTROL_4: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_HEADPHONE_DETECT_3: + case ARIZONA_HP_DACVAL: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_FX_CTRL2: + case CLEARWATER_ASRC2_STATUS: + case CLEARWATER_ASRC1_STATUS: + case ARIZONA_CLOCK_CONTROL: + case MOON_DFC_STATUS: + case CLEARWATER_GPIO1_CTRL_1: + case CLEARWATER_GPIO2_CTRL_1: + case CLEARWATER_GPIO3_CTRL_1: + case CLEARWATER_GPIO4_CTRL_1: + case CLEARWATER_GPIO5_CTRL_1: + case CLEARWATER_GPIO6_CTRL_1: + case CLEARWATER_GPIO7_CTRL_1: + case CLEARWATER_GPIO8_CTRL_1: + case CLEARWATER_GPIO9_CTRL_1: + case CLEARWATER_GPIO10_CTRL_1: + case CLEARWATER_GPIO11_CTRL_1: + case CLEARWATER_GPIO12_CTRL_1: + case CLEARWATER_GPIO13_CTRL_1: + case CLEARWATER_GPIO14_CTRL_1: + case CLEARWATER_GPIO15_CTRL_1: + case CLEARWATER_GPIO16_CTRL_1: + case CLEARWATER_GPIO17_CTRL_1: + case CLEARWATER_GPIO18_CTRL_1: + case CLEARWATER_GPIO19_CTRL_1: + case CLEARWATER_GPIO20_CTRL_1: + case CLEARWATER_GPIO21_CTRL_1: + case CLEARWATER_GPIO22_CTRL_1: + case CLEARWATER_GPIO23_CTRL_1: + case CLEARWATER_GPIO24_CTRL_1: + case CLEARWATER_GPIO25_CTRL_1: + case CLEARWATER_GPIO26_CTRL_1: + case CLEARWATER_GPIO27_CTRL_1: + case CLEARWATER_GPIO28_CTRL_1: + case CLEARWATER_GPIO29_CTRL_1: + case CLEARWATER_GPIO30_CTRL_1: + case CLEARWATER_GPIO31_CTRL_1: + case CLEARWATER_GPIO32_CTRL_1: + case CLEARWATER_GPIO33_CTRL_1: + case CLEARWATER_GPIO34_CTRL_1: + case CLEARWATER_GPIO35_CTRL_1: + case CLEARWATER_GPIO36_CTRL_1: + case CLEARWATER_GPIO37_CTRL_1: + case CLEARWATER_GPIO38_CTRL_1: + case CLEARWATER_IRQ1_STATUS_1: + case CLEARWATER_IRQ1_STATUS_2: + case CLEARWATER_IRQ1_STATUS_3: + case CLEARWATER_IRQ1_STATUS_4: + case CLEARWATER_IRQ1_STATUS_5: + case CLEARWATER_IRQ1_STATUS_6: + case CLEARWATER_IRQ1_STATUS_7: + case CLEARWATER_IRQ1_STATUS_8: + case CLEARWATER_IRQ1_STATUS_9: + case CLEARWATER_IRQ1_STATUS_10: + case CLEARWATER_IRQ1_STATUS_11: + case CLEARWATER_IRQ1_STATUS_12: + case CLEARWATER_IRQ1_STATUS_13: + case CLEARWATER_IRQ1_STATUS_14: + case CLEARWATER_IRQ1_STATUS_15: + case CLEARWATER_IRQ1_STATUS_16: + case CLEARWATER_IRQ1_STATUS_17: + case CLEARWATER_IRQ1_STATUS_18: + case CLEARWATER_IRQ1_STATUS_19: + case CLEARWATER_IRQ1_STATUS_20: + case CLEARWATER_IRQ1_STATUS_21: + case CLEARWATER_IRQ1_STATUS_22: + case CLEARWATER_IRQ1_STATUS_23: + case CLEARWATER_IRQ1_STATUS_24: + case CLEARWATER_IRQ1_STATUS_25: + case CLEARWATER_IRQ1_STATUS_26: + case CLEARWATER_IRQ1_STATUS_27: + case CLEARWATER_IRQ1_STATUS_28: + case CLEARWATER_IRQ1_STATUS_29: + case CLEARWATER_IRQ1_STATUS_30: + case CLEARWATER_IRQ1_STATUS_31: + case CLEARWATER_IRQ1_STATUS_32: + case MOON_IRQ1_STATUS_33: + case CLEARWATER_IRQ1_RAW_STATUS_1: + case CLEARWATER_IRQ1_RAW_STATUS_2: + case CLEARWATER_IRQ1_RAW_STATUS_7: + case CLEARWATER_IRQ1_RAW_STATUS_9: + case CLEARWATER_IRQ1_RAW_STATUS_11: + case CLEARWATER_IRQ1_RAW_STATUS_12: + case CLEARWATER_IRQ1_RAW_STATUS_13: + case CLEARWATER_IRQ1_RAW_STATUS_14: + case CLEARWATER_IRQ1_RAW_STATUS_15: + case CLEARWATER_IRQ1_RAW_STATUS_17: + case CLEARWATER_IRQ1_RAW_STATUS_18: + case CLEARWATER_IRQ1_RAW_STATUS_19: + case CLEARWATER_IRQ1_RAW_STATUS_21: + case CLEARWATER_IRQ1_RAW_STATUS_22: + case CLEARWATER_IRQ1_RAW_STATUS_23: + case CLEARWATER_IRQ1_RAW_STATUS_24: + case CLEARWATER_IRQ1_RAW_STATUS_25: + case CLEARWATER_IRQ1_RAW_STATUS_30: + case CLEARWATER_IRQ1_RAW_STATUS_31: + case CLEARWATER_IRQ1_RAW_STATUS_32: + case CLEARWATER_IRQ2_STATUS_9: + case CLEARWATER_IRQ2_RAW_STATUS_9: + return true; + default: + return false; + } +} + +static bool moon_32bit_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_508: + case MOON_OTP_HPDET_CALIB_1 ... MOON_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP2_CONFIG ... MOON_DSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP3_CONFIG ... MOON_DSP3_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP4_CONFIG ... MOON_DSP4_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP5_CONFIG ... MOON_DSP5_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP6_CONFIG ... MOON_DSP6_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP7_CONFIG ... MOON_DSP7_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + return true; + default: + return moon_is_adsp_memory(dev, reg); + } +} + +static bool moon_32bit_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_WSEQ_SEQUENCE_1 ... ARIZONA_WSEQ_SEQUENCE_508: + case MOON_OTP_HPDET_CALIB_1 ... MOON_OTP_HPDET_CALIB_2: + case CLEARWATER_DSP1_CONFIG ... MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP2_CONFIG ... MOON_DSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP3_CONFIG ... MOON_DSP3_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP4_CONFIG ... MOON_DSP4_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP5_CONFIG ... MOON_DSP5_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP6_CONFIG ... MOON_DSP6_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + case CLEARWATER_DSP7_CONFIG ... MOON_DSP7_PMEM_ERR_ADDR_XMEM_ERR_ADDR: + return true; + default: + return moon_is_adsp_memory(dev, reg); + } +} + +const struct regmap_config moon_16bit_spi_regmap = { + .name = "moon_16bit", + .reg_bits = 32, + .pad_bits = 16, + .val_bits = 16, + + .max_register = CLEARWATER_INTERRUPT_RAW_STATUS_1, + .readable_reg = moon_16bit_readable_register, + .volatile_reg = moon_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = moon_reg_default, + .num_reg_defaults = ARRAY_SIZE(moon_reg_default), +}; +EXPORT_SYMBOL_GPL(moon_16bit_spi_regmap); + +const struct regmap_config moon_16bit_i2c_regmap = { + .name = "moon_16bit", + .reg_bits = 32, + .val_bits = 16, + + .max_register = CLEARWATER_INTERRUPT_RAW_STATUS_1, + .readable_reg = moon_16bit_readable_register, + .volatile_reg = moon_16bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = moon_reg_default, + .num_reg_defaults = ARRAY_SIZE(moon_reg_default), +}; +EXPORT_SYMBOL_GPL(moon_16bit_i2c_regmap); + +const struct regmap_config moon_32bit_spi_regmap = { + .name = "moon_32bit", + .reg_bits = 32, + .reg_stride = 2, + .pad_bits = 16, + .val_bits = 32, + + .max_register = MOON_DSP7_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + .readable_reg = moon_32bit_readable_register, + .volatile_reg = moon_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(moon_32bit_spi_regmap); + +const struct regmap_config moon_32bit_i2c_regmap = { + .name = "moon_32bit", + .reg_bits = 32, + .reg_stride = 2, + .val_bits = 32, + + .max_register = MOON_DSP7_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + .readable_reg = moon_32bit_readable_register, + .volatile_reg = moon_32bit_volatile_register, + + .cache_type = REGCACHE_RBTREE, +}; +EXPORT_SYMBOL_GPL(moon_32bit_i2c_regmap); diff --git a/drivers/mfd/vegas-tables.c b/drivers/mfd/vegas-tables.c new file mode 100644 index 00000000000..5dd9ebda804 --- /dev/null +++ b/drivers/mfd/vegas-tables.c @@ -0,0 +1,1584 @@ +/* + * vegas-tables.c -- data tables for vegas-class codecs + * + * Copyright 2014-2015 Cirrus Logic + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include +#include + +#include "arizona.h" + +#define VEGAS_NUM_AOD_ISR 2 +#define VEGAS_NUM_ISR 5 + +static const struct reg_sequence vegas_rev_a_patch[] = { + { 0x0212, 0x0000 }, + { 0x0211, 0x0014 }, + { 0x04E4, 0x0E0D }, + { 0x04E5, 0x0E0D }, + { 0x04E6, 0x0E0D }, + { 0x04EB, 0x060E }, + { 0x0441, 0xC759 }, + { 0x0442, 0x2A08 }, + { 0x0443, 0x5CFA }, + { 0x026E, 0x0064 }, + { 0x026F, 0x00EA }, + { 0x0270, 0x1F16 }, + { 0x0410, 0x2080 }, + { 0x0418, 0x2080 }, + { 0x0420, 0x2080 }, + { 0x04B8, 0x1120 }, + { 0x047E, 0x080E }, + { 0x0448, 0x03EF }, +}; + +/* We use a function so we can use ARRAY_SIZE() */ +int vegas_patch(struct arizona *arizona) +{ + return regmap_register_patch(arizona->regmap, + vegas_rev_a_patch, + ARRAY_SIZE(vegas_rev_a_patch)); +} +EXPORT_SYMBOL_GPL(vegas_patch); + +static const struct regmap_irq vegas_aod_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_MICD_CLAMP_FALL] = { + .mask = ARIZONA_MICD_CLAMP_FALL_EINT1 + }, + [ARIZONA_IRQ_MICD_CLAMP_RISE] = { + .mask = ARIZONA_MICD_CLAMP_RISE_EINT1 + }, + [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, + [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, + [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, + [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, +}; + +struct regmap_irq_chip vegas_aod = { + .name = "vegas AOD", + .status_base = ARIZONA_AOD_IRQ1, + .mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1, + .ack_base = ARIZONA_AOD_IRQ1, + .num_regs = 1, + .irqs = vegas_aod_irqs, + .num_irqs = ARRAY_SIZE(vegas_aod_irqs), +}; +EXPORT_SYMBOL_GPL(vegas_aod); + +static const struct regmap_irq vegas_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, + [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, + [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, + [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 + }, + [ARIZONA_IRQ_SPK_OVERHEAT] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 + }, + [ARIZONA_IRQ_HPDET] = { + .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 + }, + [ARIZONA_IRQ_MICDET] = { + .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 + }, + [ARIZONA_IRQ_WSEQ_DONE] = { + .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 + }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { + .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 + }, + [ARIZONA_IRQ_ASRC2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 + }, + [ARIZONA_IRQ_ASRC1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 + }, + [ARIZONA_IRQ_UNDERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_OVERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_FLL2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 + }, + [ARIZONA_IRQ_FLL1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 + }, + + [ARIZONA_IRQ_ASRC_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_AIF3_ERR] = { + .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 + }, + [ARIZONA_IRQ_AIF2_ERR] = { + .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 + }, + [ARIZONA_IRQ_AIF1_ERR] = { + .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 + }, + [ARIZONA_IRQ_CTRLIF_ERR] = { + .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 + }, + [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = { + .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 + }, + [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_SYSCLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_ISRC1_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_ISRC2_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 + }, + + [ARIZONA_IRQ_BOOT_DONE] = { + .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 + }, + [ARIZONA_IRQ_FLL2_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 + }, + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 + }, +}; + +struct regmap_irq_chip vegas_irq = { + .name = "vegas IRQ", + .status_base = ARIZONA_INTERRUPT_STATUS_1, + .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK, + .ack_base = ARIZONA_INTERRUPT_STATUS_1, + .num_regs = 5, + .irqs = vegas_irqs, + .num_irqs = ARRAY_SIZE(vegas_irqs), +}; +EXPORT_SYMBOL_GPL(vegas_irq); + +static const struct reg_default vegas_reg_default[] = { + { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */ + { 0x0000000B, 0x001A }, /* R11 - Ctrl IF I2C1 CFG 2 */ + { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */ + { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */ + { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */ + { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */ + { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */ + { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */ + { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */ + { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */ + { 0x00000040, 0x0000 }, /* R64 - Wake control */ + { 0x00000041, 0x0000 }, /* R65 - Sequence control */ + { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */ + { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ + { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ + { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ + { 0x00000066, 0x01FF }, /* R102 - Always On Triggers Sequence Select 1 */ + { 0x00000067, 0x01FF }, /* R103 - Always On Triggers Sequence Select 2 */ + { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */ + { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */ + { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */ + { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */ + { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ + { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */ + { 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */ + { 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */ + { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */ + { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */ + { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */ + { 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */ + { 0x00000101, 0x0304 }, /* R257 - System Clock 1 */ + { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */ + { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */ + { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */ + { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */ + { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */ + { 0x00000114, 0x0011 }, /* R276 - Async sample rate 2 */ + { 0x00000149, 0x0000 }, /* R329 - Output system clock */ + { 0x0000014A, 0x0000 }, /* R330 - Output async clock */ + { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */ + { 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */ + { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */ + { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */ + { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */ + { 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */ + { 0x00000171, 0x0002 }, /* R369 - FLL1 Control 1 */ + { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */ + { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */ + { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */ + { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */ + { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */ + { 0x00000179, 0x0000 }, /* R377 - FLL1 Control 7 */ + { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */ + { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */ + { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */ + { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */ + { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */ + { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */ + { 0x00000187, 0x0001 }, /* R391 - FLL1 Synchroniser 7 */ + { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */ + { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */ + { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */ + { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */ + { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */ + { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */ + { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */ + { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */ + { 0x00000199, 0x0000 }, /* R409 - FLL2 Control 7 */ + { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */ + { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */ + { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */ + { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */ + { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */ + { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */ + { 0x000001A7, 0x0001 }, /* R423 - FLL2 Synchroniser 7 */ + { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */ + { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */ + { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */ + { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */ + { 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */ + { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */ + { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */ + { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */ + { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */ + { 0x00000293, 0x0080 }, /* R659 - Accessory Detect Mode 1 */ + { 0x0000029B, 0x0000 }, /* R667 - Headphone Detect 1 */ + { 0x000002A2, 0x0000 }, /* R674 - Micd Clamp control */ + { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */ + { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */ + { 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */ + { 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */ + { 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */ + { 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */ + { 0x000002CB, 0x0000 }, /* R715 - Isolation control */ + { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */ + { 0x00000300, 0x0000 }, /* R768 - Input Enables */ + { 0x00000308, 0x0000 }, /* R776 - Input Rate */ + { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ + { 0x0000030C, 0x0002 }, /* R780 - HPF Control */ + { 0x00000310, 0x2080 }, /* R784 - IN1L Control */ + { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ + { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ + { 0x00000314, 0x0080 }, /* R788 - IN1R Control */ + { 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */ + { 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */ + { 0x00000318, 0x2080 }, /* R792 - IN2L Control */ + { 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */ + { 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */ + { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ + { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */ + { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */ + { 0x00000410, 0x2080 }, /* R1040 - Output Path Config 1L */ + { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */ + { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */ + { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */ + { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */ + { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */ + { 0x00000418, 0x2080 }, /* R1048 - Output Path Config 2L */ + { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */ + { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */ + { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */ + { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */ + { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */ + { 0x00000420, 0x2080 }, /* R1056 - Output Path Config 3L */ + { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */ + { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */ + { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */ + { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */ + { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */ + { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */ + { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */ + { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */ + { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */ + { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */ + { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */ + { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */ + { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */ + { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */ + { 0x00000440, 0x002F }, /* R1088 - DRE Enable */ + { 0x00000441, 0xC759 }, /* R1089 - DRE Control 1 */ + { 0x00000442, 0x2A08 }, /* R1089 - DRE Control 2 */ + { 0x00000443, 0x5CFA }, /* R1089 - DRE Control 3 */ + { 0x00000448, 0x03EF }, /* R1096 - EDRE Enable */ + { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ + { 0x00000451, 0x0000 }, /* R1105 - DAC AEC Control 2 */ + { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ + { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */ + { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */ + { 0x0000049A, 0x0000 }, /* R1178 - HP_TEST_CTRL_13 */ + { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ + { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ + { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ + { 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */ + { 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */ + { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */ + { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ + { 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */ + { 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */ + { 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */ + { 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */ + { 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */ + { 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */ + { 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */ + { 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */ + { 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */ + { 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */ + { 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */ + { 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */ + { 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */ + { 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */ + { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */ + { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */ + { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ + { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */ + { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */ + { 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */ + { 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */ + { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */ + { 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */ + { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */ + { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */ + { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */ + { 0x0000054B, 0x0002 }, /* R1355 - AIF2 Frame Ctrl 5 */ + { 0x0000054C, 0x0003 }, /* R1356 - AIF2 Frame Ctrl 6 */ + { 0x0000054D, 0x0004 }, /* R1357 - AIF2 Frame Ctrl 7 */ + { 0x0000054E, 0x0005 }, /* R1358 - AIF2 Frame Ctrl 8 */ + { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */ + { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */ + { 0x00000553, 0x0002 }, /* R1363 - AIF2 Frame Ctrl 13 */ + { 0x00000554, 0x0003 }, /* R1364 - AIF2 Frame Ctrl 14 */ + { 0x00000555, 0x0004 }, /* R1365 - AIF2 Frame Ctrl 15 */ + { 0x00000556, 0x0005 }, /* R1366 - AIF2 Frame Ctrl 16 */ + { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */ + { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */ + { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ + { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */ + { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */ + { 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */ + { 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */ + { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */ + { 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */ + { 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */ + { 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */ + { 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */ + { 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */ + { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */ + { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */ + { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */ + { 0x000005C2, 0x0000 }, /* R1474 - SPD1 TX Control */ + { 0x000005C3, 0x0000 }, /* R1475 - SPD1 TX Channel Status 1 */ + { 0x000005C4, 0x0B01 }, /* R1476 - SPD1 TX Channel Status 2 */ + { 0x000005C5, 0x0000 }, /* R1477 - SPD1 TX Channel Status 3 */ + { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */ + { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */ + { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */ + { 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */ + { 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */ + { 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */ + { 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */ + { 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */ + { 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */ + { 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */ + { 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */ + { 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */ + { 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */ + { 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */ + { 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */ + { 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */ + { 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */ + { 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */ + { 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */ + { 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */ + { 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */ + { 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */ + { 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */ + { 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */ + { 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */ + { 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */ + { 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */ + { 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */ + { 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */ + { 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */ + { 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */ + { 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */ + { 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */ + { 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */ + { 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */ + { 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */ + { 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */ + { 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */ + { 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */ + { 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */ + { 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */ + { 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */ + { 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */ + { 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */ + { 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */ + { 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */ + { 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */ + { 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */ + { 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */ + { 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */ + { 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */ + { 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */ + { 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */ + { 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */ + { 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */ + { 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */ + { 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */ + { 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */ + { 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */ + { 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */ + { 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */ + { 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */ + { 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */ + { 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */ + { 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */ + { 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */ + { 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */ + { 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */ + { 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */ + { 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */ + { 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */ + { 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */ + { 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */ + { 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */ + { 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */ + { 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */ + { 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */ + { 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */ + { 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */ + { 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */ + { 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */ + { 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */ + { 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */ + { 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */ + { 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */ + { 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */ + { 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */ + { 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */ + { 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */ + { 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */ + { 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */ + { 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */ + { 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */ + { 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */ + { 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */ + { 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */ + { 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */ + { 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */ + { 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */ + { 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */ + { 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */ + { 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */ + { 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */ + { 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */ + { 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */ + { 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */ + { 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */ + { 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */ + { 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */ + { 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */ + { 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */ + { 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */ + { 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */ + { 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */ + { 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */ + { 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */ + { 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */ + { 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */ + { 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */ + { 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */ + { 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */ + { 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */ + { 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */ + { 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */ + { 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */ + { 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */ + { 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */ + { 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */ + { 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */ + { 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */ + { 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */ + { 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */ + { 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */ + { 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */ + { 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */ + { 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */ + { 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */ + { 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */ + { 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */ + { 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */ + { 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */ + { 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */ + { 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */ + { 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */ + { 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */ + { 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */ + { 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */ + { 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */ + { 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */ + { 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */ + { 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */ + { 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */ + { 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */ + { 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */ + { 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */ + { 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */ + { 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */ + { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ + { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ + { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ + { 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */ + { 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */ + { 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */ + { 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */ + { 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */ + { 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */ + { 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */ + { 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */ + { 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */ + { 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */ + { 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */ + { 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */ + { 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */ + { 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */ + { 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */ + { 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */ + { 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */ + { 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */ + { 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */ + { 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */ + { 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */ + { 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */ + { 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */ + { 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */ + { 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */ + { 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */ + { 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */ + { 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */ + { 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */ + { 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */ + { 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */ + { 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */ + { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */ + { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */ + { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */ + { 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */ + { 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */ + { 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */ + { 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */ + { 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */ + { 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */ + { 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */ + { 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */ + { 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */ + { 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */ + { 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */ + { 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */ + { 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */ + { 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */ + { 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */ + { 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */ + { 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */ + { 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */ + { 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */ + { 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */ + { 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */ + { 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */ + { 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */ + { 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */ + { 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */ + { 0x00000800, 0x0000 }, /* R2048 - SPDIF1TX1MIX Input 1 Source */ + { 0x00000801, 0x0080 }, /* R2049 - SPDIF1TX1MIX Input 1 Volume */ + { 0x00000808, 0x0000 }, /* R2056 - SPDIF1TX2MIX Input 1 Source */ + { 0x00000809, 0x0080 }, /* R2057 - SPDIF1TX2MIX Input 1 Volume */ + { 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */ + { 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */ + { 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */ + { 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */ + { 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */ + { 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */ + { 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */ + { 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */ + { 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */ + { 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */ + { 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */ + { 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */ + { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */ + { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */ + { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */ + { 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */ + { 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */ + { 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */ + { 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */ + { 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */ + { 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */ + { 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */ + { 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */ + { 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */ + { 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */ + { 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */ + { 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */ + { 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */ + { 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */ + { 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */ + { 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */ + { 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */ + { 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */ + { 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */ + { 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */ + { 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */ + { 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */ + { 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */ + { 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */ + { 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */ + { 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */ + { 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */ + { 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */ + { 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */ + { 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */ + { 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */ + { 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */ + { 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */ + { 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */ + { 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */ + { 0x00000B10, 0x0000 }, /* R2832 - ISRC1DEC3MIX Input 1 Source */ + { 0x00000B18, 0x0000 }, /* R2840 - ISRC1DEC4MIX Input 1 Source */ + { 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */ + { 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */ + { 0x00000B30, 0x0000 }, /* R2864 - ISRC1INT3MIX Input 1 Source */ + { 0x00000B38, 0x0000 }, /* R2872 - ISRC1INT4MIX Input 1 Source */ + { 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */ + { 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */ + { 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */ + { 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */ + { 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */ + { 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */ + { 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */ + { 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */ + { 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */ + { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */ + { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */ + { 0x00000C18, 0x0000 }, /* R3096 - GP Switch 1 */ + { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */ + { 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */ + { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */ + { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */ + { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */ + { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */ + { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */ + { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */ + { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */ + { 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */ + { 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */ + { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */ + { 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */ + { 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */ + { 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */ + { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */ + { 0x00000D1C, 0xFEFF }, /* R3356 - IRQ2 Status 5 Mask */ + { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */ + { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */ + { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */ + { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */ + { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */ + { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */ + { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */ + { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */ + { 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */ + { 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */ + { 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */ + { 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */ + { 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */ + { 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */ + { 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */ + { 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */ + { 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */ + { 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */ + { 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */ + { 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */ + { 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */ + { 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */ + { 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */ + { 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */ + { 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */ + { 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */ + { 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */ + { 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */ + { 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */ + { 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */ + { 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */ + { 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */ + { 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */ + { 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */ + { 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */ + { 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */ + { 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */ + { 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */ + { 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */ + { 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */ + { 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */ + { 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */ + { 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */ + { 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */ + { 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */ + { 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */ + { 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */ + { 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */ + { 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */ + { 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */ + { 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */ + { 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */ + { 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */ + { 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */ + { 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */ + { 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */ + { 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */ + { 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */ + { 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */ + { 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */ + { 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */ + { 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */ + { 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */ + { 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */ + { 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */ + { 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */ + { 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */ + { 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */ + { 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */ + { 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */ + { 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */ + { 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */ + { 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */ + { 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */ + { 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */ + { 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */ + { 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */ + { 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */ + { 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */ + { 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */ + { 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */ + { 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */ + { 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */ + { 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */ + { 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */ + { 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */ + { 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */ + { 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */ + { 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */ + { 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */ + { 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */ + { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */ + { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */ + { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */ + { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */ + { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */ + { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */ + { 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */ + { 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */ + { 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */ + { 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */ + { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ + { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */ + { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */ + { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */ + { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */ + { 0x00000EF1, 0x0001 }, /* R3825 - ISRC 1 CTRL 2 */ + { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */ + { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */ + { 0x00000EF4, 0x0001 }, /* R3828 - ISRC 2 CTRL 2 */ + { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */ + { 0x00001700, 0x0000 }, /* R5888 - FRF_COEFF_1 */ + { 0x00001701, 0x0000 }, /* R5889 - FRF_COEFF_2 */ + { 0x00001702, 0x0000 }, /* R5890 - FRF_COEFF_3 */ + { 0x00001703, 0x0000 }, /* R5891 - FRF_COEFF_4 */ + { 0x00001704, 0x0000 }, /* R5892 - DAC_COMP_1 */ + { 0x00001705, 0x0000 }, /* R5893 - DAC_COMP_2 */ +}; + +static bool vegas_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_I2C1_CFG_1: + case ARIZONA_CTRL_IF_I2C1_CFG_2: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_WAKE_CONTROL: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_CLOCK_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_OUTPUT_ASYNC_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_DYNAMIC_FREQUENCY_SCALING_1: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_CONTROL_7: + case ARIZONA_FLL1_SYNCHRONISER_1: + case ARIZONA_FLL1_SYNCHRONISER_2: + case ARIZONA_FLL1_SYNCHRONISER_3: + case ARIZONA_FLL1_SYNCHRONISER_4: + case ARIZONA_FLL1_SYNCHRONISER_5: + case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SYNCHRONISER_7: + case ARIZONA_FLL1_SPREAD_SPECTRUM: + case ARIZONA_FLL1_GPIO_CLOCK: + case ARIZONA_FLL2_CONTROL_1: + case ARIZONA_FLL2_CONTROL_2: + case ARIZONA_FLL2_CONTROL_3: + case ARIZONA_FLL2_CONTROL_4: + case ARIZONA_FLL2_CONTROL_5: + case ARIZONA_FLL2_CONTROL_6: + case ARIZONA_FLL2_CONTROL_7: + case ARIZONA_FLL2_SYNCHRONISER_1: + case ARIZONA_FLL2_SYNCHRONISER_2: + case ARIZONA_FLL2_SYNCHRONISER_3: + case ARIZONA_FLL2_SYNCHRONISER_4: + case ARIZONA_FLL2_SYNCHRONISER_5: + case ARIZONA_FLL2_SYNCHRONISER_6: + case ARIZONA_FLL2_SYNCHRONISER_7: + case ARIZONA_FLL2_SPREAD_SPECTRUM: + case ARIZONA_FLL2_GPIO_CLOCK: + case ARIZONA_MIC_CHARGE_PUMP_1: + case ARIZONA_LDO1_CONTROL_1: + case ARIZONA_LDO1_CONTROL_2: + case ARIZONA_LDO2_CONTROL_1: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_2: + case ARIZONA_MIC_BIAS_CTRL_3: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_ACCESSORY_DETECT_MODE_1: + case ARIZONA_HEADPHONE_DETECT_1: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_MICD_CLAMP_CONTROL: + case ARIZONA_MIC_DETECT_1: + case ARIZONA_MIC_DETECT_2: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_MIC_DETECT_LEVEL_1: + case ARIZONA_MIC_DETECT_LEVEL_2: + case ARIZONA_MIC_DETECT_LEVEL_3: + case ARIZONA_MIC_DETECT_LEVEL_4: + case ARIZONA_ISOLATION_CONTROL: + case ARIZONA_JACK_DETECT_ANALOGUE: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_HPF_CONTROL: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_OUTPUT_PATH_CONFIG_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case ARIZONA_OUTPUT_PATH_CONFIG_2L: + case ARIZONA_DAC_DIGITAL_VOLUME_2L: + case ARIZONA_NOISE_GATE_SELECT_2L: + case ARIZONA_OUTPUT_PATH_CONFIG_2R: + case ARIZONA_DAC_DIGITAL_VOLUME_2R: + case ARIZONA_NOISE_GATE_SELECT_2R: + case ARIZONA_OUTPUT_PATH_CONFIG_3L: + case ARIZONA_DAC_DIGITAL_VOLUME_3L: + case ARIZONA_NOISE_GATE_SELECT_3L: + case ARIZONA_OUTPUT_PATH_CONFIG_4L: + case ARIZONA_DAC_DIGITAL_VOLUME_4L: + case ARIZONA_NOISE_GATE_SELECT_4L: + case ARIZONA_OUTPUT_PATH_CONFIG_4R: + case ARIZONA_DAC_DIGITAL_VOLUME_4R: + case ARIZONA_NOISE_GATE_SELECT_4R: + case ARIZONA_OUTPUT_PATH_CONFIG_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5L: + case ARIZONA_NOISE_GATE_SELECT_5L: + case ARIZONA_OUTPUT_PATH_CONFIG_5R: + case ARIZONA_DAC_DIGITAL_VOLUME_5R: + case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_DRE_ENABLE: + case ARIZONA_DRE_CONTROL_1: + case ARIZONA_DRE_CONTROL_2: + case ARIZONA_DRE_CONTROL_3: + case CLEARWATER_EDRE_ENABLE: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_DAC_AEC_CONTROL_2: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_PDM_SPK1_CTRL_1: + case ARIZONA_PDM_SPK1_CTRL_2: + case ARIZONA_HP_TEST_CTRL_13: + case ARIZONA_SPK_CTRL_5: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_TX_BCLK_RATE: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_5: + case ARIZONA_AIF2_FRAME_CTRL_6: + case ARIZONA_AIF2_FRAME_CTRL_7: + case ARIZONA_AIF2_FRAME_CTRL_8: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_FRAME_CTRL_13: + case ARIZONA_AIF2_FRAME_CTRL_14: + case ARIZONA_AIF2_FRAME_CTRL_15: + case ARIZONA_AIF2_FRAME_CTRL_16: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_AIF3_BCLK_CTRL: + case ARIZONA_AIF3_TX_PIN_CTRL: + case ARIZONA_AIF3_RX_PIN_CTRL: + case ARIZONA_AIF3_RATE_CTRL: + case ARIZONA_AIF3_FORMAT: + case ARIZONA_AIF3_RX_BCLK_RATE: + case ARIZONA_AIF3_FRAME_CTRL_1: + case ARIZONA_AIF3_FRAME_CTRL_2: + case ARIZONA_AIF3_FRAME_CTRL_3: + case ARIZONA_AIF3_FRAME_CTRL_4: + case ARIZONA_AIF3_FRAME_CTRL_11: + case ARIZONA_AIF3_FRAME_CTRL_12: + case ARIZONA_AIF3_TX_ENABLES: + case ARIZONA_AIF3_RX_ENABLES: + case ARIZONA_SPD1_TX_CONTROL: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_1: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_2: + case ARIZONA_SPD1_TX_CHANNEL_STATUS_3: + case ARIZONA_SLIMBUS_FRAMER_REF_GEAR: + case ARIZONA_SLIMBUS_RATES_1: + case ARIZONA_SLIMBUS_RATES_2: + case ARIZONA_SLIMBUS_RATES_5: + case ARIZONA_SLIMBUS_RATES_6: + case ARIZONA_SLIMBUS_RATES_7: + case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT2LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT2LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT2RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT2RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME: + case ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ3MIX_INPUT_1_SOURCE: + case ARIZONA_EQ3MIX_INPUT_1_VOLUME: + case ARIZONA_EQ4MIX_INPUT_1_SOURCE: + case ARIZONA_EQ4MIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE: + case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_GPIO1_CTRL: + case ARIZONA_GPIO2_CTRL: + case ARIZONA_GPIO3_CTRL: + case ARIZONA_GPIO4_CTRL: + case ARIZONA_GPIO5_CTRL: + case ARIZONA_IRQ_CTRL_1: + case ARIZONA_GPIO_DEBOUNCE_CONFIG: + case ARIZONA_GP_SWITCH_1: + case ARIZONA_MISC_PAD_CTRL_1: + case ARIZONA_MISC_PAD_CTRL_2: + case ARIZONA_MISC_PAD_CTRL_3: + case ARIZONA_MISC_PAD_CTRL_4: + case ARIZONA_MISC_PAD_CTRL_5: + case ARIZONA_MISC_PAD_CTRL_6: + case ARIZONA_INTERRUPT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_2: + case ARIZONA_INTERRUPT_STATUS_3: + case ARIZONA_INTERRUPT_STATUS_4: + case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_INTERRUPT_STATUS_1_MASK: + case ARIZONA_INTERRUPT_STATUS_2_MASK: + case ARIZONA_INTERRUPT_STATUS_3_MASK: + case ARIZONA_INTERRUPT_STATUS_4_MASK: + case ARIZONA_INTERRUPT_STATUS_5_MASK: + case ARIZONA_INTERRUPT_CONTROL: + case ARIZONA_IRQ2_STATUS_1: + case ARIZONA_IRQ2_STATUS_2: + case ARIZONA_IRQ2_STATUS_3: + case ARIZONA_IRQ2_STATUS_4: + case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_IRQ2_STATUS_1_MASK: + case ARIZONA_IRQ2_STATUS_2_MASK: + case ARIZONA_IRQ2_STATUS_3_MASK: + case ARIZONA_IRQ2_STATUS_4_MASK: + case ARIZONA_IRQ2_STATUS_5_MASK: + case ARIZONA_IRQ2_CONTROL: + case ARIZONA_INTERRUPT_RAW_STATUS_2: + case ARIZONA_INTERRUPT_RAW_STATUS_3: + case ARIZONA_INTERRUPT_RAW_STATUS_4: + case ARIZONA_INTERRUPT_RAW_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_7: + case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_AOD_WKUP_AND_TRIG: + case ARIZONA_AOD_IRQ1: + case ARIZONA_AOD_IRQ2: + case ARIZONA_AOD_IRQ_MASK_IRQ1: + case ARIZONA_AOD_IRQ_MASK_IRQ2: + case ARIZONA_AOD_IRQ_RAW_STATUS: + case ARIZONA_JACK_DETECT_DEBOUNCE: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_EQ3_1: + case ARIZONA_EQ3_2: + case ARIZONA_EQ3_3: + case ARIZONA_EQ3_4: + case ARIZONA_EQ3_5: + case ARIZONA_EQ3_6: + case ARIZONA_EQ3_7: + case ARIZONA_EQ3_8: + case ARIZONA_EQ3_9: + case ARIZONA_EQ3_10: + case ARIZONA_EQ3_11: + case ARIZONA_EQ3_12: + case ARIZONA_EQ3_13: + case ARIZONA_EQ3_14: + case ARIZONA_EQ3_15: + case ARIZONA_EQ3_16: + case ARIZONA_EQ3_17: + case ARIZONA_EQ3_18: + case ARIZONA_EQ3_19: + case ARIZONA_EQ3_20: + case ARIZONA_EQ3_21: + case ARIZONA_EQ4_1: + case ARIZONA_EQ4_2: + case ARIZONA_EQ4_3: + case ARIZONA_EQ4_4: + case ARIZONA_EQ4_5: + case ARIZONA_EQ4_6: + case ARIZONA_EQ4_7: + case ARIZONA_EQ4_8: + case ARIZONA_EQ4_9: + case ARIZONA_EQ4_10: + case ARIZONA_EQ4_11: + case ARIZONA_EQ4_12: + case ARIZONA_EQ4_13: + case ARIZONA_EQ4_14: + case ARIZONA_EQ4_15: + case ARIZONA_EQ4_16: + case ARIZONA_EQ4_17: + case ARIZONA_EQ4_18: + case ARIZONA_EQ4_19: + case ARIZONA_EQ4_20: + case ARIZONA_EQ4_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case ARIZONA_ASRC_ENABLE: + case ARIZONA_ASRC_STATUS: + case ARIZONA_ASRC_RATE1: + case ARIZONA_ASRC_RATE2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + case ARIZONA_FRF_COEFF_1: + case ARIZONA_FRF_COEFF_2: + case ARIZONA_FRF_COEFF_3: + case ARIZONA_FRF_COEFF_4: + case ARIZONA_V2_DAC_COMP_1: + case ARIZONA_V2_DAC_COMP_2: + return true; + default: + return false; + } +} + +static bool vegas_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_DETECT_4: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_INTERRUPT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_2: + case ARIZONA_INTERRUPT_STATUS_3: + case ARIZONA_INTERRUPT_STATUS_4: + case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_IRQ2_STATUS_1: + case ARIZONA_IRQ2_STATUS_2: + case ARIZONA_IRQ2_STATUS_3: + case ARIZONA_IRQ2_STATUS_4: + case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_2: + case ARIZONA_INTERRUPT_RAW_STATUS_3: + case ARIZONA_INTERRUPT_RAW_STATUS_4: + case ARIZONA_INTERRUPT_RAW_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_7: + case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_AOD_WKUP_AND_TRIG: + case ARIZONA_AOD_IRQ1: + case ARIZONA_AOD_IRQ2: + case ARIZONA_AOD_IRQ_RAW_STATUS: + case ARIZONA_FX_CTRL2: + case ARIZONA_ASRC_STATUS: + return true; + default: + return false; + } +} + +#define VEGAS_MAX_REGISTER 0x31ff + +const struct regmap_config vegas_i2c_regmap = { + .reg_bits = 32, + .val_bits = 16, + + .max_register = VEGAS_MAX_REGISTER, + .readable_reg = vegas_readable_register, + .volatile_reg = vegas_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = vegas_reg_default, + .num_reg_defaults = ARRAY_SIZE(vegas_reg_default), +}; +EXPORT_SYMBOL_GPL(vegas_i2c_regmap); diff --git a/drivers/mfd/wcd9335-regmap.c b/drivers/mfd/wcd9335-regmap.c index 391563b3c32..86683c86d52 100644 --- a/drivers/mfd/wcd9335-regmap.c +++ b/drivers/mfd/wcd9335-regmap.c @@ -18,7 +18,7 @@ #include #include "wcd9xxx-regmap.h" -static const struct reg_default wcd9335_1_x_defaults[] = { +static const struct reg_sequence wcd9335_1_x_defaults[] = { { WCD9335_CODEC_RPM_CLK_GATE , 0x03 }, { WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN , 0x1f }, { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 , 0x00 }, @@ -153,7 +153,7 @@ static const struct reg_default wcd9335_1_x_defaults[] = { { WCD9335_TEST_DEBUG_NPL_DLY_TEST_2 , 0x00 }, }; -static const struct reg_default wcd9335_2_0_defaults[] = { +static const struct reg_sequence wcd9335_2_0_defaults[] = { { WCD9335_CODEC_RPM_CLK_GATE , 0x07 }, { WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN , 0x3f }, { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 , 0x01 }, diff --git a/drivers/mfd/wm5102-tables.c b/drivers/mfd/wm5102-tables.c index 155c4a1a6a9..21db329f10f 100644 --- a/drivers/mfd/wm5102-tables.c +++ b/drivers/mfd/wm5102-tables.c @@ -21,7 +21,7 @@ #define WM5102_NUM_AOD_ISR 2 #define WM5102_NUM_ISR 5 -static const struct reg_default wm5102_reva_patch[] = { +static const struct reg_sequence wm5102_reva_patch[] = { { 0x80, 0x0003 }, { 0x221, 0x0090 }, { 0x211, 0x0014 }, @@ -57,7 +57,7 @@ static const struct reg_default wm5102_reva_patch[] = { { 0x80, 0x0000 }, }; -static const struct reg_default wm5102_revb_patch[] = { +static const struct reg_sequence wm5102_revb_patch[] = { { 0x19, 0x0001 }, { 0x80, 0x0003 }, { 0x081, 0xE022 }, @@ -65,46 +65,112 @@ static const struct reg_default wm5102_revb_patch[] = { { 0x418, 0xa080 }, { 0x420, 0xa080 }, { 0x428, 0xe000 }, - { 0x443, 0xDC1A }, + { 0x442, 0x3F0A }, + { 0x443, 0xDC1F }, { 0x4B0, 0x0066 }, { 0x458, 0x000b }, { 0x212, 0x0000 }, { 0x171, 0x0000 }, { 0x35E, 0x000C }, { 0x2D4, 0x0000 }, + { 0x4DC, 0x0900 }, { 0x80, 0x0000 }, }; +static const struct reg_sequence wm5102t_pwr_1[] = { + { 0x46C, 0xC01 }, + { 0x46E, 0xC01 }, + { 0x470, 0xC01 }, +}; + +static const struct reg_sequence wm5102t_pwr_2[] = { + { 0x462, 0xC00 }, + { 0x464, 0xC00 }, + { 0x466, 0xC00 }, + { 0x468, 0xC00 }, + { 0x46a, 0xC00 }, + { 0x46c, 0xC00 }, + { 0x46e, 0xC00 }, + { 0x470, 0xC00 }, + { 0x476, 0x806 }, +}; + +static const struct reg_sequence wm5102t_pwr_3[] = { + { 0x462, 0xC00 }, + { 0x464, 0xC00 }, + { 0x466, 0xC00 }, + { 0x468, 0xC00 }, + { 0x46a, 0xC00 }, + { 0x46c, 0xC00 }, + { 0x46e, 0xC00 }, + { 0x470, 0xC00 }, + { 0x472, 0xC00 }, + { 0x47c, 0x806 }, + { 0x47e, 0x80e }, +}; + +static const struct reg_sequence wm5102t_pwr_4[] = { + { 0x462, 0xC00 }, + { 0x464, 0xC00 }, + { 0x466, 0xC00 }, + { 0x468, 0xC00 }, + { 0x46a, 0xC00 }, + { 0x46c, 0xC00 }, + { 0x46e, 0xC00 }, + { 0x470, 0xC00 }, + { 0x472, 0xC00 }, + { 0x474, 0xC00 }, + { 0x476, 0xC00 }, + { 0x478, 0xC00 }, + { 0x47a, 0xC00 }, + { 0x47c, 0xC00 }, + { 0x47e, 0xC00 }, +}; + +static const struct { + const struct reg_sequence *patch; + int size; +} wm5102t_pwr[] = { + { NULL, 0 }, + { wm5102t_pwr_1, ARRAY_SIZE(wm5102t_pwr_1) }, + { wm5102t_pwr_2, ARRAY_SIZE(wm5102t_pwr_2) }, + { wm5102t_pwr_3, ARRAY_SIZE(wm5102t_pwr_3) }, + { wm5102t_pwr_4, ARRAY_SIZE(wm5102t_pwr_4) }, +}; + /* We use a function so we can use ARRAY_SIZE() */ int wm5102_patch(struct arizona *arizona) { - const struct reg_default *wm5102_patch; - int ret = 0; - int i, patch_size; + const struct reg_sequence *wm5102_patch; + int ret; + int patch_size; + int pwr_index = arizona->pdata.wm5102t_output_pwr; switch (arizona->rev) { case 0: wm5102_patch = wm5102_reva_patch; patch_size = ARRAY_SIZE(wm5102_reva_patch); + break; default: wm5102_patch = wm5102_revb_patch; patch_size = ARRAY_SIZE(wm5102_revb_patch); + break; } - regcache_cache_bypass(arizona->regmap, true); + ret = regmap_multi_reg_write_bypassed(arizona->regmap, + wm5102_patch, + patch_size); + if (ret != 0) + goto out; - for (i = 0; i < patch_size; i++) { - ret = regmap_write(arizona->regmap, wm5102_patch[i].reg, - wm5102_patch[i].def); - if (ret != 0) { - dev_err(arizona->dev, "Failed to write %x = %x: %d\n", - wm5102_patch[i].reg, wm5102_patch[i].def, ret); - goto out; - } - } + if (pwr_index < ARRAY_SIZE(wm5102t_pwr)) + ret = regmap_multi_reg_write_bypassed(arizona->regmap, + wm5102t_pwr[pwr_index].patch, + wm5102t_pwr[pwr_index].size); + else + dev_err(arizona->dev, "Invalid wm5102t output power\n"); out: - regcache_cache_bypass(arizona->regmap, false); return ret; } @@ -149,11 +215,11 @@ static const struct regmap_irq wm5102_irqs[ARIZONA_NUM_IRQ] = { .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 }, - [ARIZONA_IRQ_SPK_SHUTDOWN_WARN] = { - .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_WARN_EINT1 + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 }, - [ARIZONA_IRQ_SPK_SHUTDOWN] = { - .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 + [ARIZONA_IRQ_SPK_OVERHEAT] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 }, [ARIZONA_IRQ_HPDET] = { .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 @@ -256,9 +322,6 @@ const struct regmap_irq_chip wm5102_irq = { static const struct reg_default wm5102_reg_default[] = { { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */ { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */ - { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */ - { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */ - { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */ { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */ { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */ { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */ @@ -279,8 +342,6 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */ { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */ { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */ - { 0x0000006E, 0x01FF }, /* R110 - Trigger Sequence Select 32 */ - { 0x0000006F, 0x01FF }, /* R111 - Trigger Sequence Select 33 */ { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ @@ -312,8 +373,6 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */ { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */ { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */ - { 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */ - { 0x00000178, 0x0000 }, /* R376 - FLL1 NCO Test 0 */ { 0x00000179, 0x0000 }, /* R377 - FLL1 Control 7 */ { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */ { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */ @@ -330,8 +389,6 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */ { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */ { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */ - { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */ - { 0x00000198, 0x0000 }, /* R408 - FLL2 NCO Test 0 */ { 0x00000199, 0x0000 }, /* R409 - FLL2 Control 7 */ { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */ { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */ @@ -344,23 +401,18 @@ static const struct reg_default wm5102_reg_default[] = { { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */ { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */ { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */ - { 0x00000212, 0x0001 }, /* R530 - LDO1 Control 2 */ + { 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */ { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */ { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */ { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */ { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */ - { 0x00000225, 0x0400 }, /* R549 - HP Ctrl 1L */ - { 0x00000226, 0x0400 }, /* R550 - HP Ctrl 1R */ { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */ { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */ - { 0x0000029C, 0x0000 }, /* R668 - Headphone Detect 2 */ - { 0x0000029F, 0x0000 }, /* R671 - Headphone Detect Test */ { 0x000002A2, 0x0000 }, /* R674 - Micd clamp control */ { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */ { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */ - { 0x000002A5, 0x0000 }, /* R677 - Mic Detect 3 */ { 0x000002A6, 0x3737 }, /* R678 - Mic Detect Level 1 */ - { 0x000002A7, 0x372C }, /* R679 - Mic Detect Level 2 */ + { 0x000002A7, 0x2C37 }, /* R679 - Mic Detect Level 2 */ { 0x000002A8, 0x1422 }, /* R680 - Mic Detect Level 3 */ { 0x000002A9, 0x030A }, /* R681 - Mic Detect Level 4 */ { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */ @@ -424,6 +476,9 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */ { 0x00000436, 0x0081 }, /* R1078 - DAC Volume Limit 5R */ { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */ + { 0x00000440, 0x0FFF }, /* R1088 - DRE Enable */ + { 0x00000442, 0x3F0A }, /* R1090 - DRE Control 2 */ + { 0x00000443, 0xDC1F }, /* R1090 - DRE Control 3 */ { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ { 0x00000458, 0x000B }, /* R1112 - Noise Gate Control */ { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */ @@ -882,7 +937,7 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */ { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */ { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */ - { 0x00000C21, 0x8001 }, /* R3105 - Misc Pad Ctrl 2 */ + { 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */ { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */ { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */ { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */ @@ -899,12 +954,11 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */ { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */ { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */ - { 0x00000D50, 0x0000 }, /* R3408 - AOD wkup and trig */ + { 0x00000D41, 0x0000 }, /* R3393 - ADSP2 IRQ0 */ { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */ { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */ { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */ { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */ - { 0x00000E01, 0x0000 }, /* R3585 - FX_Ctrl2 */ { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */ { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */ { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */ @@ -1004,6 +1058,7 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */ { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */ + { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */ { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */ { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */ { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */ @@ -1011,7 +1066,6 @@ static const struct reg_default wm5102_reg_default[] = { { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */ { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */ { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */ - { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */ }; static bool wm5102_readable_register(struct device *dev, unsigned int reg) @@ -1021,11 +1075,10 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DEVICE_REVISION: case ARIZONA_CTRL_IF_SPI_CFG_1: case ARIZONA_CTRL_IF_I2C1_CFG_1: - case ARIZONA_CTRL_IF_STATUS_1: case ARIZONA_WRITE_SEQUENCER_CTRL_0: case ARIZONA_WRITE_SEQUENCER_CTRL_1: case ARIZONA_WRITE_SEQUENCER_CTRL_2: - case ARIZONA_WRITE_SEQUENCER_PROM: + case ARIZONA_WRITE_SEQUENCER_CTRL_3: case ARIZONA_TONE_GENERATOR_1: case ARIZONA_TONE_GENERATOR_2: case ARIZONA_TONE_GENERATOR_3: @@ -1067,6 +1120,8 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_ASYNC_CLOCK_1: case ARIZONA_ASYNC_SAMPLE_RATE_1: case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_2: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: case ARIZONA_OUTPUT_SYSTEM_CLOCK: case ARIZONA_OUTPUT_ASYNC_CLOCK: case ARIZONA_RATE_ESTIMATOR_1: @@ -1081,8 +1136,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_FLL1_CONTROL_4: case ARIZONA_FLL1_CONTROL_5: case ARIZONA_FLL1_CONTROL_6: - case ARIZONA_FLL1_LOOP_FILTER_TEST_1: - case ARIZONA_FLL1_NCO_TEST_0: case ARIZONA_FLL1_CONTROL_7: case ARIZONA_FLL1_SYNCHRONISER_1: case ARIZONA_FLL1_SYNCHRONISER_2: @@ -1099,8 +1152,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_FLL2_CONTROL_4: case ARIZONA_FLL2_CONTROL_5: case ARIZONA_FLL2_CONTROL_6: - case ARIZONA_FLL2_LOOP_FILTER_TEST_1: - case ARIZONA_FLL2_NCO_TEST_0: case ARIZONA_FLL2_CONTROL_7: case ARIZONA_FLL2_SYNCHRONISER_1: case ARIZONA_FLL2_SYNCHRONISER_2: @@ -1118,6 +1169,8 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_MIC_BIAS_CTRL_1: case ARIZONA_MIC_BIAS_CTRL_2: case ARIZONA_MIC_BIAS_CTRL_3: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: case ARIZONA_ACCESSORY_DETECT_MODE_1: case ARIZONA_HEADPHONE_DETECT_1: case ARIZONA_HEADPHONE_DETECT_2: @@ -1178,14 +1231,10 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DAC_DIGITAL_VOLUME_3L: case ARIZONA_DAC_VOLUME_LIMIT_3L: case ARIZONA_NOISE_GATE_SELECT_3L: - case ARIZONA_OUTPUT_PATH_CONFIG_3R: - case ARIZONA_DAC_DIGITAL_VOLUME_3R: - case ARIZONA_DAC_VOLUME_LIMIT_3R: case ARIZONA_OUTPUT_PATH_CONFIG_4L: case ARIZONA_DAC_DIGITAL_VOLUME_4L: case ARIZONA_OUT_VOLUME_4L: case ARIZONA_NOISE_GATE_SELECT_4L: - case ARIZONA_OUTPUT_PATH_CONFIG_4R: case ARIZONA_DAC_DIGITAL_VOLUME_4R: case ARIZONA_OUT_VOLUME_4R: case ARIZONA_NOISE_GATE_SELECT_4R: @@ -1193,16 +1242,17 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DAC_DIGITAL_VOLUME_5L: case ARIZONA_DAC_VOLUME_LIMIT_5L: case ARIZONA_NOISE_GATE_SELECT_5L: - case ARIZONA_OUTPUT_PATH_CONFIG_5R: case ARIZONA_DAC_DIGITAL_VOLUME_5R: case ARIZONA_DAC_VOLUME_LIMIT_5R: case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_DRE_ENABLE: + case ARIZONA_DRE_CONTROL_2: + case ARIZONA_DRE_CONTROL_3: case ARIZONA_DAC_AEC_CONTROL_1: case ARIZONA_NOISE_GATE_CONTROL: case ARIZONA_PDM_SPK1_CTRL_1: case ARIZONA_PDM_SPK1_CTRL_2: - case ARIZONA_SPK_CTRL_2: - case ARIZONA_SPK_CTRL_3: + case ARIZONA_SPK_CTRL_5: case ARIZONA_DAC_COMP_1: case ARIZONA_DAC_COMP_2: case ARIZONA_DAC_COMP_3: @@ -1234,7 +1284,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_AIF1_FRAME_CTRL_18: case ARIZONA_AIF1_TX_ENABLES: case ARIZONA_AIF1_RX_ENABLES: - case ARIZONA_AIF1_FORCE_WRITE: case ARIZONA_AIF2_BCLK_CTRL: case ARIZONA_AIF2_TX_PIN_CTRL: case ARIZONA_AIF2_RX_PIN_CTRL: @@ -1250,7 +1299,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_AIF2_FRAME_CTRL_12: case ARIZONA_AIF2_TX_ENABLES: case ARIZONA_AIF2_RX_ENABLES: - case ARIZONA_AIF2_FORCE_WRITE: case ARIZONA_AIF3_BCLK_CTRL: case ARIZONA_AIF3_TX_PIN_CTRL: case ARIZONA_AIF3_RX_PIN_CTRL: @@ -1266,7 +1314,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_AIF3_FRAME_CTRL_12: case ARIZONA_AIF3_TX_ENABLES: case ARIZONA_AIF3_RX_ENABLES: - case ARIZONA_AIF3_FORCE_WRITE: case ARIZONA_SLIMBUS_FRAMER_REF_GEAR: case ARIZONA_SLIMBUS_RATES_1: case ARIZONA_SLIMBUS_RATES_2: @@ -1592,22 +1639,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: - case ARIZONA_DRC2LMIX_INPUT_1_SOURCE: - case ARIZONA_DRC2LMIX_INPUT_1_VOLUME: - case ARIZONA_DRC2LMIX_INPUT_2_SOURCE: - case ARIZONA_DRC2LMIX_INPUT_2_VOLUME: - case ARIZONA_DRC2LMIX_INPUT_3_SOURCE: - case ARIZONA_DRC2LMIX_INPUT_3_VOLUME: - case ARIZONA_DRC2LMIX_INPUT_4_SOURCE: - case ARIZONA_DRC2LMIX_INPUT_4_VOLUME: - case ARIZONA_DRC2RMIX_INPUT_1_SOURCE: - case ARIZONA_DRC2RMIX_INPUT_1_VOLUME: - case ARIZONA_DRC2RMIX_INPUT_2_SOURCE: - case ARIZONA_DRC2RMIX_INPUT_2_VOLUME: - case ARIZONA_DRC2RMIX_INPUT_3_SOURCE: - case ARIZONA_DRC2RMIX_INPUT_3_VOLUME: - case ARIZONA_DRC2RMIX_INPUT_4_SOURCE: - case ARIZONA_DRC2RMIX_INPUT_4_VOLUME: case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: @@ -1816,11 +1847,6 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_DRC1_CTRL3: case ARIZONA_DRC1_CTRL4: case ARIZONA_DRC1_CTRL5: - case ARIZONA_DRC2_CTRL1: - case ARIZONA_DRC2_CTRL2: - case ARIZONA_DRC2_CTRL3: - case ARIZONA_DRC2_CTRL4: - case ARIZONA_DRC2_CTRL5: case ARIZONA_HPLPF1_1: case ARIZONA_HPLPF1_2: case ARIZONA_HPLPF2_1: @@ -1838,14 +1864,28 @@ static bool wm5102_readable_register(struct device *dev, unsigned int reg) case ARIZONA_ISRC_2_CTRL_1: case ARIZONA_ISRC_2_CTRL_2: case ARIZONA_ISRC_2_CTRL_3: - case ARIZONA_ISRC_3_CTRL_1: - case ARIZONA_ISRC_3_CTRL_2: - case ARIZONA_ISRC_3_CTRL_3: case ARIZONA_DSP1_CONTROL_1: case ARIZONA_DSP1_CLOCKING_1: case ARIZONA_DSP1_STATUS_1: case ARIZONA_DSP1_STATUS_2: case ARIZONA_DSP1_STATUS_3: + case ARIZONA_DSP1_WDMA_BUFFER_1: + case ARIZONA_DSP1_WDMA_BUFFER_2: + case ARIZONA_DSP1_WDMA_BUFFER_3: + case ARIZONA_DSP1_WDMA_BUFFER_4: + case ARIZONA_DSP1_WDMA_BUFFER_5: + case ARIZONA_DSP1_WDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_BUFFER_7: + case ARIZONA_DSP1_WDMA_BUFFER_8: + case ARIZONA_DSP1_RDMA_BUFFER_1: + case ARIZONA_DSP1_RDMA_BUFFER_2: + case ARIZONA_DSP1_RDMA_BUFFER_3: + case ARIZONA_DSP1_RDMA_BUFFER_4: + case ARIZONA_DSP1_RDMA_BUFFER_5: + case ARIZONA_DSP1_RDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_CONFIG_1: + case ARIZONA_DSP1_WDMA_CONFIG_2: + case ARIZONA_DSP1_RDMA_CONFIG_1: case ARIZONA_DSP1_SCRATCH_0: case ARIZONA_DSP1_SCRATCH_1: case ARIZONA_DSP1_SCRATCH_2: @@ -1867,8 +1907,11 @@ static bool wm5102_volatile_register(struct device *dev, unsigned int reg) switch (reg) { case ARIZONA_SOFTWARE_RESET: case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_WRITE_SEQUENCER_CTRL_3: case ARIZONA_OUTPUT_STATUS_1: - case ARIZONA_RAW_OUTPUT_STATUS_1: case ARIZONA_SLIMBUS_RX_PORT_STATUS: case ARIZONA_SLIMBUS_TX_PORT_STATUS: case ARIZONA_SAMPLE_RATE_1_STATUS: @@ -1876,8 +1919,11 @@ static bool wm5102_volatile_register(struct device *dev, unsigned int reg) case ARIZONA_SAMPLE_RATE_3_STATUS: case ARIZONA_HAPTICS_STATUS: case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: - case ARIZONA_FLL1_NCO_TEST_0: - case ARIZONA_FLL2_NCO_TEST_0: + case ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS: + case ARIZONA_DAC_COMP_1: + case ARIZONA_DAC_COMP_2: + case ARIZONA_DAC_COMP_3: + case ARIZONA_DAC_COMP_4: case ARIZONA_FX_CTRL2: case ARIZONA_INTERRUPT_STATUS_1: case ARIZONA_INTERRUPT_STATUS_2: @@ -1901,13 +1947,33 @@ static bool wm5102_volatile_register(struct device *dev, unsigned int reg) case ARIZONA_AOD_IRQ1: case ARIZONA_AOD_IRQ2: case ARIZONA_AOD_IRQ_RAW_STATUS: + case ARIZONA_DSP1_CLOCKING_1: case ARIZONA_DSP1_STATUS_1: case ARIZONA_DSP1_STATUS_2: case ARIZONA_DSP1_STATUS_3: + case ARIZONA_DSP1_WDMA_BUFFER_1: + case ARIZONA_DSP1_WDMA_BUFFER_2: + case ARIZONA_DSP1_WDMA_BUFFER_3: + case ARIZONA_DSP1_WDMA_BUFFER_4: + case ARIZONA_DSP1_WDMA_BUFFER_5: + case ARIZONA_DSP1_WDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_BUFFER_7: + case ARIZONA_DSP1_WDMA_BUFFER_8: + case ARIZONA_DSP1_RDMA_BUFFER_1: + case ARIZONA_DSP1_RDMA_BUFFER_2: + case ARIZONA_DSP1_RDMA_BUFFER_3: + case ARIZONA_DSP1_RDMA_BUFFER_4: + case ARIZONA_DSP1_RDMA_BUFFER_5: + case ARIZONA_DSP1_RDMA_BUFFER_6: + case ARIZONA_DSP1_WDMA_CONFIG_1: + case ARIZONA_DSP1_WDMA_CONFIG_2: + case ARIZONA_DSP1_RDMA_CONFIG_1: case ARIZONA_DSP1_SCRATCH_0: case ARIZONA_DSP1_SCRATCH_1: case ARIZONA_DSP1_SCRATCH_2: case ARIZONA_DSP1_SCRATCH_3: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: case ARIZONA_HEADPHONE_DETECT_2: case ARIZONA_HP_DACVAL: case ARIZONA_MIC_DETECT_3: diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c index 00e4fe2f3c7..8fe019cf0fc 100644 --- a/drivers/mfd/wm8994-core.c +++ b/drivers/mfd/wm8994-core.c @@ -377,21 +377,21 @@ static int wm8994_ldo_in_use(struct wm8994_pdata *pdata, int ldo) } #endif -static const struct reg_default wm8994_revc_patch[] = { +static const struct reg_sequence wm8994_revc_patch[] = { { 0x102, 0x3 }, { 0x56, 0x3 }, { 0x817, 0x0 }, { 0x102, 0x0 }, }; -static const struct reg_default wm8958_reva_patch[] = { +static const struct reg_sequence wm8958_reva_patch[] = { { 0x102, 0x3 }, { 0xcb, 0x81 }, { 0x817, 0x0 }, { 0x102, 0x0 }, }; -static const struct reg_default wm1811_reva_patch[] = { +static const struct reg_sequence wm1811_reva_patch[] = { { 0x102, 0x3 }, { 0x56, 0xc07 }, { 0x5d, 0x7e }, @@ -460,7 +460,7 @@ static int wm8994_device_init(struct wm8994 *wm8994, int irq) { struct wm8994_pdata *pdata; struct regmap_config *regmap_config; - const struct reg_default *regmap_patch = NULL; + const struct reg_sequence *regmap_patch = NULL; const char *devname; int ret, i, patch_regs = 0; int pulls = 0; diff --git a/drivers/mfd/wm8997-tables.c b/drivers/mfd/wm8997-tables.c new file mode 100644 index 00000000000..ddbc186ef89 --- /dev/null +++ b/drivers/mfd/wm8997-tables.c @@ -0,0 +1,1532 @@ +/* + * wm8997-tables.c -- WM8997 data tables + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Charles Keepax + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "arizona.h" + +static const struct reg_sequence wm8997_reva_patch[] = { + { 0x80, 0x0003 }, + { 0x214, 0x0008 }, + { 0x458, 0x0000 }, + { 0x0081, 0xE022 }, + { 0x294, 0x0000 }, + { 0x80, 0x0000 }, + { 0x171, 0x0000 }, +}; + +/* We use a function so we can use ARRAY_SIZE() */ +int wm8997_patch(struct arizona *arizona) +{ + switch (arizona->rev) { + case 0: + return regmap_register_patch(arizona->regmap, + wm8997_reva_patch, + ARRAY_SIZE(wm8997_reva_patch)); + default: + return 0; + } +} +EXPORT_SYMBOL_GPL(wm8997_patch); + +static const struct regmap_irq wm8997_aod_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, + [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, + [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, + [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, +}; + +const struct regmap_irq_chip wm8997_aod = { + .name = "wm8997 AOD", + .status_base = ARIZONA_AOD_IRQ1, + .mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1, + .ack_base = ARIZONA_AOD_IRQ1, + .num_regs = 1, + .irqs = wm8997_aod_irqs, + .num_irqs = ARRAY_SIZE(wm8997_aod_irqs), +}; +EXPORT_SYMBOL_GPL(wm8997_aod); + +static const struct regmap_irq wm8997_irqs[ARIZONA_NUM_IRQ] = { + [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, + [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, + [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, + [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, + + [ARIZONA_IRQ_SPK_OVERHEAT_WARN] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 + }, + [ARIZONA_IRQ_SPK_OVERHEAT] = { + .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 + }, + [ARIZONA_IRQ_HPDET] = { + .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 + }, + [ARIZONA_IRQ_MICDET] = { + .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 + }, + [ARIZONA_IRQ_WSEQ_DONE] = { + .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 + }, + [ARIZONA_IRQ_DRC1_SIG_DET] = { + .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 + }, + [ARIZONA_IRQ_UNDERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_OVERCLOCKED] = { + .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 + }, + [ARIZONA_IRQ_FLL2_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 + }, + [ARIZONA_IRQ_FLL1_LOCK] = { + .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 + }, + [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = { + .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 + }, + + [ARIZONA_IRQ_AIF2_ERR] = { + .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 + }, + [ARIZONA_IRQ_AIF1_ERR] = { + .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 + }, + [ARIZONA_IRQ_CTRLIF_ERR] = { + .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 + }, + [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = { + .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 + }, + [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_SYSCLK_ENA_LOW] = { + .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 + }, + [ARIZONA_IRQ_ISRC1_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 + }, + [ARIZONA_IRQ_ISRC2_CFG_ERR] = { + .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 + }, + + [ARIZONA_IRQ_BOOT_DONE] = { + .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 + }, + [ARIZONA_IRQ_DCS_DAC_DONE] = { + .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1 + }, + [ARIZONA_IRQ_DCS_HP_DONE] = { + .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1 + }, + [ARIZONA_IRQ_FLL2_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 + }, + [ARIZONA_IRQ_FLL1_CLOCK_OK] = { + .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 + }, +}; + +const struct regmap_irq_chip wm8997_irq = { + .name = "wm8997 IRQ", + .status_base = ARIZONA_INTERRUPT_STATUS_1, + .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK, + .ack_base = ARIZONA_INTERRUPT_STATUS_1, + .num_regs = 5, + .irqs = wm8997_irqs, + .num_irqs = ARRAY_SIZE(wm8997_irqs), +}; +EXPORT_SYMBOL_GPL(wm8997_irq); + +static const struct reg_default wm8997_reg_default[] = { + { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */ + { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */ + { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */ + { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */ + { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */ + { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */ + { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */ + { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */ + { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */ + { 0x00000040, 0x0000 }, /* R64 - Wake control */ + { 0x00000041, 0x0000 }, /* R65 - Sequence control */ + { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */ + { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */ + { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */ + { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */ + { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 3 */ + { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 4 */ + { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 5 */ + { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 6 */ + { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */ + { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */ + { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */ + { 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */ + { 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */ + { 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */ + { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */ + { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */ + { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */ + { 0x00000100, 0x0002 }, /* R256 - Clock 32k 1 */ + { 0x00000101, 0x0304 }, /* R257 - System Clock 1 */ + { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */ + { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */ + { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */ + { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */ + { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */ + { 0x00000149, 0x0000 }, /* R329 - Output system clock */ + { 0x0000014A, 0x0000 }, /* R330 - Output async clock */ + { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */ + { 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */ + { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */ + { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */ + { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */ + { 0x00000161, 0x0000 }, /* R353 - Dynamic Frequency Scaling 1 */ + { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */ + { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */ + { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */ + { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */ + { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */ + { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */ + { 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */ + { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */ + { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */ + { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */ + { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */ + { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */ + { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */ + { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */ + { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */ + { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */ + { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */ + { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */ + { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */ + { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */ + { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */ + { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */ + { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */ + { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */ + { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */ + { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */ + { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */ + { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */ + { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */ + { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */ + { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */ + { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */ + { 0x00000212, 0x0000 }, /* R530 - LDO1 Control 2 */ + { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */ + { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */ + { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */ + { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */ + { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */ + { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */ + { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */ + { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */ + { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */ + { 0x000002CB, 0x0000 }, /* R715 - Isolation control */ + { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */ + { 0x00000300, 0x0000 }, /* R768 - Input Enables */ + { 0x00000308, 0x0000 }, /* R776 - Input Rate */ + { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ + { 0x00000310, 0x2080 }, /* R784 - IN1L Control */ + { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ + { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ + { 0x00000314, 0x0080 }, /* R788 - IN1R Control */ + { 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */ + { 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */ + { 0x00000318, 0x2080 }, /* R792 - IN2L Control */ + { 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */ + { 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */ + { 0x0000031C, 0x0080 }, /* R796 - IN2R Control */ + { 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */ + { 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */ + { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ + { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */ + { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */ + { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */ + { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */ + { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */ + { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */ + { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */ + { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */ + { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */ + { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */ + { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */ + { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */ + { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */ + { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */ + { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */ + { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */ + { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */ + { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */ + { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */ + { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */ + { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */ + { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */ + { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */ + { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */ + { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */ + { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ + { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ + { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */ + { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */ + { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ + { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ + { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ + { 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */ + { 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */ + { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */ + { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ + { 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */ + { 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */ + { 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */ + { 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */ + { 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */ + { 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */ + { 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */ + { 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */ + { 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */ + { 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */ + { 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */ + { 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */ + { 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */ + { 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */ + { 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */ + { 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */ + { 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */ + { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */ + { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */ + { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */ + { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ + { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */ + { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */ + { 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */ + { 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */ + { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */ + { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */ + { 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */ + { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */ + { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */ + { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */ + { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */ + { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */ + { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */ + { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */ + { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */ + { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */ + { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */ + { 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */ + { 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */ + { 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */ + { 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */ + { 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */ + { 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */ + { 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */ + { 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */ + { 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */ + { 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */ + { 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */ + { 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */ + { 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */ + { 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */ + { 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */ + { 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */ + { 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */ + { 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */ + { 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */ + { 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */ + { 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */ + { 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */ + { 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */ + { 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */ + { 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */ + { 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */ + { 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */ + { 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */ + { 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */ + { 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */ + { 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */ + { 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */ + { 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */ + { 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */ + { 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */ + { 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */ + { 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */ + { 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */ + { 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */ + { 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */ + { 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */ + { 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */ + { 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */ + { 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */ + { 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */ + { 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */ + { 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */ + { 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */ + { 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */ + { 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */ + { 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */ + { 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */ + { 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */ + { 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */ + { 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */ + { 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */ + { 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */ + { 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */ + { 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */ + { 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */ + { 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */ + { 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */ + { 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */ + { 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */ + { 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */ + { 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */ + { 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */ + { 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */ + { 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */ + { 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */ + { 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */ + { 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */ + { 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */ + { 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */ + { 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */ + { 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */ + { 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */ + { 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */ + { 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */ + { 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */ + { 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */ + { 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */ + { 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */ + { 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */ + { 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */ + { 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */ + { 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */ + { 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */ + { 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */ + { 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */ + { 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */ + { 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */ + { 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */ + { 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */ + { 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */ + { 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */ + { 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */ + { 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */ + { 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */ + { 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */ + { 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */ + { 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */ + { 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */ + { 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */ + { 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */ + { 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */ + { 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */ + { 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */ + { 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */ + { 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */ + { 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */ + { 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */ + { 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */ + { 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */ + { 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */ + { 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */ + { 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */ + { 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */ + { 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */ + { 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */ + { 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */ + { 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */ + { 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */ + { 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */ + { 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */ + { 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */ + { 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */ + { 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */ + { 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */ + { 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */ + { 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */ + { 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */ + { 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */ + { 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */ + { 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */ + { 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */ + { 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */ + { 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */ + { 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */ + { 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */ + { 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */ + { 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */ + { 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */ + { 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */ + { 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */ + { 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */ + { 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */ + { 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */ + { 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */ + { 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */ + { 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */ + { 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */ + { 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */ + { 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */ + { 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */ + { 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */ + { 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */ + { 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */ + { 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */ + { 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */ + { 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */ + { 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */ + { 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */ + { 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */ + { 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */ + { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ + { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ + { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ + { 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */ + { 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */ + { 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */ + { 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */ + { 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */ + { 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */ + { 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */ + { 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */ + { 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */ + { 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */ + { 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */ + { 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */ + { 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */ + { 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */ + { 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */ + { 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */ + { 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */ + { 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */ + { 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */ + { 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */ + { 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */ + { 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */ + { 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */ + { 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */ + { 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */ + { 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */ + { 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */ + { 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */ + { 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */ + { 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */ + { 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */ + { 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */ + { 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */ + { 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */ + { 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */ + { 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */ + { 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */ + { 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */ + { 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */ + { 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */ + { 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */ + { 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */ + { 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */ + { 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */ + { 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */ + { 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */ + { 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */ + { 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */ + { 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */ + { 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */ + { 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */ + { 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */ + { 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */ + { 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */ + { 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */ + { 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */ + { 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */ + { 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */ + { 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */ + { 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */ + { 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */ + { 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */ + { 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */ + { 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */ + { 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */ + { 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */ + { 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */ + { 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */ + { 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */ + { 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */ + { 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */ + { 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */ + { 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */ + { 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */ + { 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */ + { 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */ + { 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */ + { 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */ + { 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */ + { 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */ + { 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */ + { 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */ + { 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */ + { 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */ + { 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */ + { 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */ + { 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */ + { 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */ + { 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */ + { 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */ + { 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */ + { 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */ + { 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */ + { 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */ + { 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */ + { 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */ + { 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */ + { 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */ + { 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */ + { 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */ + { 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */ + { 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */ + { 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */ + { 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */ + { 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */ + { 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */ + { 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */ + { 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */ + { 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */ + { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */ + { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */ + { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */ + { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */ + { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */ + { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */ + { 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */ + { 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */ + { 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */ + { 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */ + { 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */ + { 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */ + { 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */ + { 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */ + { 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */ + { 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */ + { 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */ + { 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */ + { 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */ + { 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */ + { 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */ + { 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */ + { 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */ + { 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */ + { 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */ + { 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */ + { 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */ + { 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */ + { 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */ + { 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */ + { 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */ + { 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */ + { 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */ + { 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */ + { 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */ + { 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */ + { 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */ + { 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */ + { 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */ + { 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */ + { 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */ + { 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */ + { 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */ + { 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */ + { 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */ + { 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */ + { 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */ + { 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */ + { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */ + { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */ + { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */ + { 0x00000C21, 0x0001 }, /* R3105 - Misc Pad Ctrl 2 */ + { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */ + { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */ + { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */ + { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */ + { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */ + { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */ + { 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */ + { 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */ + { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */ + { 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */ + { 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */ + { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */ + { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */ + { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */ + { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */ + { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */ + { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */ + { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */ + { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */ + { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */ + { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */ + { 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */ + { 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */ + { 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */ + { 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */ + { 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */ + { 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */ + { 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */ + { 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */ + { 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */ + { 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */ + { 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */ + { 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */ + { 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */ + { 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */ + { 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */ + { 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */ + { 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */ + { 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */ + { 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */ + { 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */ + { 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */ + { 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */ + { 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */ + { 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */ + { 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */ + { 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */ + { 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */ + { 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */ + { 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */ + { 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */ + { 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */ + { 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */ + { 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */ + { 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */ + { 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */ + { 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */ + { 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */ + { 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */ + { 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */ + { 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */ + { 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */ + { 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */ + { 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */ + { 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */ + { 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */ + { 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */ + { 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */ + { 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */ + { 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */ + { 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */ + { 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */ + { 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */ + { 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */ + { 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */ + { 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */ + { 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */ + { 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */ + { 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */ + { 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */ + { 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */ + { 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */ + { 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */ + { 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */ + { 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */ + { 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */ + { 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */ + { 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */ + { 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */ + { 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */ + { 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */ + { 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */ + { 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */ + { 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */ + { 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */ + { 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */ + { 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */ + { 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */ + { 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */ + { 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */ + { 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */ + { 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */ + { 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */ + { 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */ + { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */ + { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */ + { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */ + { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */ + { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */ + { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */ + { 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */ + { 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */ + { 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */ + { 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */ + { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ + { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */ + { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */ + { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */ + { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */ + { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */ + { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */ +}; + +static bool wm8997_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_CTRL_IF_I2C1_CFG_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_TONE_GENERATOR_1: + case ARIZONA_TONE_GENERATOR_2: + case ARIZONA_TONE_GENERATOR_3: + case ARIZONA_TONE_GENERATOR_4: + case ARIZONA_TONE_GENERATOR_5: + case ARIZONA_PWM_DRIVE_1: + case ARIZONA_PWM_DRIVE_2: + case ARIZONA_PWM_DRIVE_3: + case ARIZONA_WAKE_CONTROL: + case ARIZONA_SEQUENCE_CONTROL: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3: + case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5: + case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6: + case ARIZONA_COMFORT_NOISE_GENERATOR: + case ARIZONA_HAPTICS_CONTROL_1: + case ARIZONA_HAPTICS_CONTROL_2: + case ARIZONA_HAPTICS_PHASE_1_INTENSITY: + case ARIZONA_HAPTICS_PHASE_1_DURATION: + case ARIZONA_HAPTICS_PHASE_2_INTENSITY: + case ARIZONA_HAPTICS_PHASE_2_DURATION: + case ARIZONA_HAPTICS_PHASE_3_INTENSITY: + case ARIZONA_HAPTICS_PHASE_3_DURATION: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_CLOCK_32K_1: + case ARIZONA_SYSTEM_CLOCK_1: + case ARIZONA_SAMPLE_RATE_1: + case ARIZONA_SAMPLE_RATE_2: + case ARIZONA_SAMPLE_RATE_3: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_CLOCK_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_OUTPUT_SYSTEM_CLOCK: + case ARIZONA_OUTPUT_ASYNC_CLOCK: + case ARIZONA_RATE_ESTIMATOR_1: + case ARIZONA_RATE_ESTIMATOR_2: + case ARIZONA_RATE_ESTIMATOR_3: + case ARIZONA_RATE_ESTIMATOR_4: + case ARIZONA_RATE_ESTIMATOR_5: + case ARIZONA_DYNAMIC_FREQUENCY_SCALING_1: + case ARIZONA_FLL1_CONTROL_1: + case ARIZONA_FLL1_CONTROL_2: + case ARIZONA_FLL1_CONTROL_3: + case ARIZONA_FLL1_CONTROL_4: + case ARIZONA_FLL1_CONTROL_5: + case ARIZONA_FLL1_CONTROL_6: + case ARIZONA_FLL1_LOOP_FILTER_TEST_1: + case ARIZONA_FLL1_NCO_TEST_0: + case ARIZONA_FLL1_SYNCHRONISER_1: + case ARIZONA_FLL1_SYNCHRONISER_2: + case ARIZONA_FLL1_SYNCHRONISER_3: + case ARIZONA_FLL1_SYNCHRONISER_4: + case ARIZONA_FLL1_SYNCHRONISER_5: + case ARIZONA_FLL1_SYNCHRONISER_6: + case ARIZONA_FLL1_SPREAD_SPECTRUM: + case ARIZONA_FLL1_GPIO_CLOCK: + case ARIZONA_FLL2_CONTROL_1: + case ARIZONA_FLL2_CONTROL_2: + case ARIZONA_FLL2_CONTROL_3: + case ARIZONA_FLL2_CONTROL_4: + case ARIZONA_FLL2_CONTROL_5: + case ARIZONA_FLL2_CONTROL_6: + case ARIZONA_FLL2_LOOP_FILTER_TEST_1: + case ARIZONA_FLL2_NCO_TEST_0: + case ARIZONA_FLL2_SYNCHRONISER_1: + case ARIZONA_FLL2_SYNCHRONISER_2: + case ARIZONA_FLL2_SYNCHRONISER_3: + case ARIZONA_FLL2_SYNCHRONISER_4: + case ARIZONA_FLL2_SYNCHRONISER_5: + case ARIZONA_FLL2_SYNCHRONISER_6: + case ARIZONA_FLL2_SPREAD_SPECTRUM: + case ARIZONA_FLL2_GPIO_CLOCK: + case ARIZONA_MIC_CHARGE_PUMP_1: + case ARIZONA_LDO1_CONTROL_1: + case ARIZONA_LDO1_CONTROL_2: + case ARIZONA_LDO2_CONTROL_1: + case ARIZONA_MIC_BIAS_CTRL_1: + case ARIZONA_MIC_BIAS_CTRL_2: + case ARIZONA_MIC_BIAS_CTRL_3: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_ACCESSORY_DETECT_MODE_1: + case ARIZONA_HEADPHONE_DETECT_1: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_MIC_DETECT_1: + case ARIZONA_MIC_DETECT_2: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_MIC_NOISE_MIX_CONTROL_1: + case ARIZONA_ISOLATION_CONTROL: + case ARIZONA_JACK_DETECT_ANALOGUE: + case ARIZONA_INPUT_ENABLES: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_INPUT_RATE: + case ARIZONA_INPUT_VOLUME_RAMP: + case ARIZONA_IN1L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1L: + case ARIZONA_DMIC1L_CONTROL: + case ARIZONA_IN1R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_1R: + case ARIZONA_DMIC1R_CONTROL: + case ARIZONA_IN2L_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2L: + case ARIZONA_DMIC2L_CONTROL: + case ARIZONA_IN2R_CONTROL: + case ARIZONA_ADC_DIGITAL_VOLUME_2R: + case ARIZONA_DMIC2R_CONTROL: + case ARIZONA_OUTPUT_ENABLES_1: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_OUTPUT_RATE_1: + case ARIZONA_OUTPUT_VOLUME_RAMP: + case ARIZONA_OUTPUT_PATH_CONFIG_1L: + case ARIZONA_DAC_DIGITAL_VOLUME_1L: + case ARIZONA_DAC_VOLUME_LIMIT_1L: + case ARIZONA_NOISE_GATE_SELECT_1L: + case ARIZONA_OUTPUT_PATH_CONFIG_1R: + case ARIZONA_DAC_DIGITAL_VOLUME_1R: + case ARIZONA_DAC_VOLUME_LIMIT_1R: + case ARIZONA_NOISE_GATE_SELECT_1R: + case ARIZONA_OUTPUT_PATH_CONFIG_3L: + case ARIZONA_DAC_DIGITAL_VOLUME_3L: + case ARIZONA_DAC_VOLUME_LIMIT_3L: + case ARIZONA_NOISE_GATE_SELECT_3L: + case ARIZONA_OUTPUT_PATH_CONFIG_4L: + case ARIZONA_DAC_DIGITAL_VOLUME_4L: + case ARIZONA_OUT_VOLUME_4L: + case ARIZONA_NOISE_GATE_SELECT_4L: + case ARIZONA_OUTPUT_PATH_CONFIG_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5L: + case ARIZONA_DAC_VOLUME_LIMIT_5L: + case ARIZONA_NOISE_GATE_SELECT_5L: + case ARIZONA_DAC_DIGITAL_VOLUME_5R: + case ARIZONA_DAC_VOLUME_LIMIT_5R: + case ARIZONA_NOISE_GATE_SELECT_5R: + case ARIZONA_DAC_AEC_CONTROL_1: + case ARIZONA_NOISE_GATE_CONTROL: + case ARIZONA_PDM_SPK1_CTRL_1: + case ARIZONA_PDM_SPK1_CTRL_2: + case ARIZONA_SPK_CTRL_5: + case ARIZONA_AIF1_BCLK_CTRL: + case ARIZONA_AIF1_TX_PIN_CTRL: + case ARIZONA_AIF1_RX_PIN_CTRL: + case ARIZONA_AIF1_RATE_CTRL: + case ARIZONA_AIF1_FORMAT: + case ARIZONA_AIF1_TX_BCLK_RATE: + case ARIZONA_AIF1_RX_BCLK_RATE: + case ARIZONA_AIF1_FRAME_CTRL_1: + case ARIZONA_AIF1_FRAME_CTRL_2: + case ARIZONA_AIF1_FRAME_CTRL_3: + case ARIZONA_AIF1_FRAME_CTRL_4: + case ARIZONA_AIF1_FRAME_CTRL_5: + case ARIZONA_AIF1_FRAME_CTRL_6: + case ARIZONA_AIF1_FRAME_CTRL_7: + case ARIZONA_AIF1_FRAME_CTRL_8: + case ARIZONA_AIF1_FRAME_CTRL_9: + case ARIZONA_AIF1_FRAME_CTRL_10: + case ARIZONA_AIF1_FRAME_CTRL_11: + case ARIZONA_AIF1_FRAME_CTRL_12: + case ARIZONA_AIF1_FRAME_CTRL_13: + case ARIZONA_AIF1_FRAME_CTRL_14: + case ARIZONA_AIF1_FRAME_CTRL_15: + case ARIZONA_AIF1_FRAME_CTRL_16: + case ARIZONA_AIF1_FRAME_CTRL_17: + case ARIZONA_AIF1_FRAME_CTRL_18: + case ARIZONA_AIF1_TX_ENABLES: + case ARIZONA_AIF1_RX_ENABLES: + case ARIZONA_AIF2_BCLK_CTRL: + case ARIZONA_AIF2_TX_PIN_CTRL: + case ARIZONA_AIF2_RX_PIN_CTRL: + case ARIZONA_AIF2_RATE_CTRL: + case ARIZONA_AIF2_FORMAT: + case ARIZONA_AIF2_TX_BCLK_RATE: + case ARIZONA_AIF2_RX_BCLK_RATE: + case ARIZONA_AIF2_FRAME_CTRL_1: + case ARIZONA_AIF2_FRAME_CTRL_2: + case ARIZONA_AIF2_FRAME_CTRL_3: + case ARIZONA_AIF2_FRAME_CTRL_4: + case ARIZONA_AIF2_FRAME_CTRL_11: + case ARIZONA_AIF2_FRAME_CTRL_12: + case ARIZONA_AIF2_TX_ENABLES: + case ARIZONA_AIF2_RX_ENABLES: + case ARIZONA_SLIMBUS_FRAMER_REF_GEAR: + case ARIZONA_SLIMBUS_RATES_1: + case ARIZONA_SLIMBUS_RATES_2: + case ARIZONA_SLIMBUS_RATES_3: + case ARIZONA_SLIMBUS_RATES_4: + case ARIZONA_SLIMBUS_RATES_5: + case ARIZONA_SLIMBUS_RATES_6: + case ARIZONA_SLIMBUS_RATES_7: + case ARIZONA_SLIMBUS_RATES_8: + case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_PWM1MIX_INPUT_1_SOURCE: + case ARIZONA_PWM1MIX_INPUT_1_VOLUME: + case ARIZONA_PWM1MIX_INPUT_2_SOURCE: + case ARIZONA_PWM1MIX_INPUT_2_VOLUME: + case ARIZONA_PWM1MIX_INPUT_3_SOURCE: + case ARIZONA_PWM1MIX_INPUT_3_VOLUME: + case ARIZONA_PWM1MIX_INPUT_4_SOURCE: + case ARIZONA_PWM1MIX_INPUT_4_VOLUME: + case ARIZONA_PWM2MIX_INPUT_1_SOURCE: + case ARIZONA_PWM2MIX_INPUT_1_VOLUME: + case ARIZONA_PWM2MIX_INPUT_2_SOURCE: + case ARIZONA_PWM2MIX_INPUT_2_VOLUME: + case ARIZONA_PWM2MIX_INPUT_3_SOURCE: + case ARIZONA_PWM2MIX_INPUT_3_VOLUME: + case ARIZONA_PWM2MIX_INPUT_4_SOURCE: + case ARIZONA_PWM2MIX_INPUT_4_VOLUME: + case ARIZONA_MICMIX_INPUT_1_SOURCE: + case ARIZONA_MICMIX_INPUT_1_VOLUME: + case ARIZONA_MICMIX_INPUT_2_SOURCE: + case ARIZONA_MICMIX_INPUT_2_VOLUME: + case ARIZONA_MICMIX_INPUT_3_SOURCE: + case ARIZONA_MICMIX_INPUT_3_VOLUME: + case ARIZONA_MICMIX_INPUT_4_SOURCE: + case ARIZONA_MICMIX_INPUT_4_VOLUME: + case ARIZONA_NOISEMIX_INPUT_1_SOURCE: + case ARIZONA_NOISEMIX_INPUT_1_VOLUME: + case ARIZONA_NOISEMIX_INPUT_2_SOURCE: + case ARIZONA_NOISEMIX_INPUT_2_VOLUME: + case ARIZONA_NOISEMIX_INPUT_3_SOURCE: + case ARIZONA_NOISEMIX_INPUT_3_VOLUME: + case ARIZONA_NOISEMIX_INPUT_4_SOURCE: + case ARIZONA_NOISEMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT1RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT1RMIX_INPUT_4_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT3LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT3LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT4LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT4LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5LMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5LMIX_INPUT_4_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_1_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_1_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_2_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_2_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_3_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_3_VOLUME: + case ARIZONA_OUT5RMIX_INPUT_4_SOURCE: + case ARIZONA_OUT5RMIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME: + case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE: + case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: + case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: + case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME: + case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE: + case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME: + case ARIZONA_EQ1MIX_INPUT_1_SOURCE: + case ARIZONA_EQ1MIX_INPUT_1_VOLUME: + case ARIZONA_EQ1MIX_INPUT_2_SOURCE: + case ARIZONA_EQ1MIX_INPUT_2_VOLUME: + case ARIZONA_EQ1MIX_INPUT_3_SOURCE: + case ARIZONA_EQ1MIX_INPUT_3_VOLUME: + case ARIZONA_EQ1MIX_INPUT_4_SOURCE: + case ARIZONA_EQ1MIX_INPUT_4_VOLUME: + case ARIZONA_EQ2MIX_INPUT_1_SOURCE: + case ARIZONA_EQ2MIX_INPUT_1_VOLUME: + case ARIZONA_EQ2MIX_INPUT_2_SOURCE: + case ARIZONA_EQ2MIX_INPUT_2_VOLUME: + case ARIZONA_EQ2MIX_INPUT_3_SOURCE: + case ARIZONA_EQ2MIX_INPUT_3_VOLUME: + case ARIZONA_EQ2MIX_INPUT_4_SOURCE: + case ARIZONA_EQ2MIX_INPUT_4_VOLUME: + case ARIZONA_EQ3MIX_INPUT_1_SOURCE: + case ARIZONA_EQ3MIX_INPUT_1_VOLUME: + case ARIZONA_EQ3MIX_INPUT_2_SOURCE: + case ARIZONA_EQ3MIX_INPUT_2_VOLUME: + case ARIZONA_EQ3MIX_INPUT_3_SOURCE: + case ARIZONA_EQ3MIX_INPUT_3_VOLUME: + case ARIZONA_EQ3MIX_INPUT_4_SOURCE: + case ARIZONA_EQ3MIX_INPUT_4_VOLUME: + case ARIZONA_EQ4MIX_INPUT_1_SOURCE: + case ARIZONA_EQ4MIX_INPUT_1_VOLUME: + case ARIZONA_EQ4MIX_INPUT_2_SOURCE: + case ARIZONA_EQ4MIX_INPUT_2_VOLUME: + case ARIZONA_EQ4MIX_INPUT_3_SOURCE: + case ARIZONA_EQ4MIX_INPUT_3_VOLUME: + case ARIZONA_EQ4MIX_INPUT_4_SOURCE: + case ARIZONA_EQ4MIX_INPUT_4_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1LMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1LMIX_INPUT_4_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_1_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_1_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_2_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_2_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_3_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_3_VOLUME: + case ARIZONA_DRC1RMIX_INPUT_4_SOURCE: + case ARIZONA_DRC1RMIX_INPUT_4_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP1MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP1MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP2MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP2MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP3MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP3MIX_INPUT_4_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_1_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_1_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_2_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_2_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_3_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_3_VOLUME: + case ARIZONA_HPLP4MIX_INPUT_4_SOURCE: + case ARIZONA_HPLP4MIX_INPUT_4_VOLUME: + case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE: + case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE: + case ARIZONA_GPIO1_CTRL: + case ARIZONA_GPIO2_CTRL: + case ARIZONA_GPIO3_CTRL: + case ARIZONA_GPIO4_CTRL: + case ARIZONA_GPIO5_CTRL: + case ARIZONA_IRQ_CTRL_1: + case ARIZONA_GPIO_DEBOUNCE_CONFIG: + case ARIZONA_MISC_PAD_CTRL_1: + case ARIZONA_MISC_PAD_CTRL_2: + case ARIZONA_MISC_PAD_CTRL_3: + case ARIZONA_MISC_PAD_CTRL_4: + case ARIZONA_MISC_PAD_CTRL_5: + case ARIZONA_INTERRUPT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_2: + case ARIZONA_INTERRUPT_STATUS_3: + case ARIZONA_INTERRUPT_STATUS_4: + case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_INTERRUPT_STATUS_1_MASK: + case ARIZONA_INTERRUPT_STATUS_2_MASK: + case ARIZONA_INTERRUPT_STATUS_3_MASK: + case ARIZONA_INTERRUPT_STATUS_4_MASK: + case ARIZONA_INTERRUPT_STATUS_5_MASK: + case ARIZONA_INTERRUPT_CONTROL: + case ARIZONA_IRQ2_STATUS_1: + case ARIZONA_IRQ2_STATUS_3: + case ARIZONA_IRQ2_STATUS_4: + case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_IRQ2_STATUS_1_MASK: + case ARIZONA_IRQ2_STATUS_3_MASK: + case ARIZONA_IRQ2_STATUS_4_MASK: + case ARIZONA_IRQ2_STATUS_5_MASK: + case ARIZONA_IRQ2_CONTROL: + case ARIZONA_INTERRUPT_RAW_STATUS_3: + case ARIZONA_INTERRUPT_RAW_STATUS_4: + case ARIZONA_INTERRUPT_RAW_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_7: + case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_AOD_WKUP_AND_TRIG: + case ARIZONA_AOD_IRQ1: + case ARIZONA_AOD_IRQ2: + case ARIZONA_AOD_IRQ_MASK_IRQ1: + case ARIZONA_AOD_IRQ_MASK_IRQ2: + case ARIZONA_AOD_IRQ_RAW_STATUS: + case ARIZONA_JACK_DETECT_DEBOUNCE: + case ARIZONA_FX_CTRL1: + case ARIZONA_FX_CTRL2: + case ARIZONA_EQ1_1: + case ARIZONA_EQ1_2: + case ARIZONA_EQ1_3: + case ARIZONA_EQ1_4: + case ARIZONA_EQ1_5: + case ARIZONA_EQ1_6: + case ARIZONA_EQ1_7: + case ARIZONA_EQ1_8: + case ARIZONA_EQ1_9: + case ARIZONA_EQ1_10: + case ARIZONA_EQ1_11: + case ARIZONA_EQ1_12: + case ARIZONA_EQ1_13: + case ARIZONA_EQ1_14: + case ARIZONA_EQ1_15: + case ARIZONA_EQ1_16: + case ARIZONA_EQ1_17: + case ARIZONA_EQ1_18: + case ARIZONA_EQ1_19: + case ARIZONA_EQ1_20: + case ARIZONA_EQ1_21: + case ARIZONA_EQ2_1: + case ARIZONA_EQ2_2: + case ARIZONA_EQ2_3: + case ARIZONA_EQ2_4: + case ARIZONA_EQ2_5: + case ARIZONA_EQ2_6: + case ARIZONA_EQ2_7: + case ARIZONA_EQ2_8: + case ARIZONA_EQ2_9: + case ARIZONA_EQ2_10: + case ARIZONA_EQ2_11: + case ARIZONA_EQ2_12: + case ARIZONA_EQ2_13: + case ARIZONA_EQ2_14: + case ARIZONA_EQ2_15: + case ARIZONA_EQ2_16: + case ARIZONA_EQ2_17: + case ARIZONA_EQ2_18: + case ARIZONA_EQ2_19: + case ARIZONA_EQ2_20: + case ARIZONA_EQ2_21: + case ARIZONA_EQ3_1: + case ARIZONA_EQ3_2: + case ARIZONA_EQ3_3: + case ARIZONA_EQ3_4: + case ARIZONA_EQ3_5: + case ARIZONA_EQ3_6: + case ARIZONA_EQ3_7: + case ARIZONA_EQ3_8: + case ARIZONA_EQ3_9: + case ARIZONA_EQ3_10: + case ARIZONA_EQ3_11: + case ARIZONA_EQ3_12: + case ARIZONA_EQ3_13: + case ARIZONA_EQ3_14: + case ARIZONA_EQ3_15: + case ARIZONA_EQ3_16: + case ARIZONA_EQ3_17: + case ARIZONA_EQ3_18: + case ARIZONA_EQ3_19: + case ARIZONA_EQ3_20: + case ARIZONA_EQ3_21: + case ARIZONA_EQ4_1: + case ARIZONA_EQ4_2: + case ARIZONA_EQ4_3: + case ARIZONA_EQ4_4: + case ARIZONA_EQ4_5: + case ARIZONA_EQ4_6: + case ARIZONA_EQ4_7: + case ARIZONA_EQ4_8: + case ARIZONA_EQ4_9: + case ARIZONA_EQ4_10: + case ARIZONA_EQ4_11: + case ARIZONA_EQ4_12: + case ARIZONA_EQ4_13: + case ARIZONA_EQ4_14: + case ARIZONA_EQ4_15: + case ARIZONA_EQ4_16: + case ARIZONA_EQ4_17: + case ARIZONA_EQ4_18: + case ARIZONA_EQ4_19: + case ARIZONA_EQ4_20: + case ARIZONA_EQ4_21: + case ARIZONA_DRC1_CTRL1: + case ARIZONA_DRC1_CTRL2: + case ARIZONA_DRC1_CTRL3: + case ARIZONA_DRC1_CTRL4: + case ARIZONA_DRC1_CTRL5: + case ARIZONA_HPLPF1_1: + case ARIZONA_HPLPF1_2: + case ARIZONA_HPLPF2_1: + case ARIZONA_HPLPF2_2: + case ARIZONA_HPLPF3_1: + case ARIZONA_HPLPF3_2: + case ARIZONA_HPLPF4_1: + case ARIZONA_HPLPF4_2: + case ARIZONA_ISRC_1_CTRL_1: + case ARIZONA_ISRC_1_CTRL_2: + case ARIZONA_ISRC_1_CTRL_3: + case ARIZONA_ISRC_2_CTRL_1: + case ARIZONA_ISRC_2_CTRL_2: + case ARIZONA_ISRC_2_CTRL_3: + return true; + default: + return false; + } +} + +static bool wm8997_volatile_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ARIZONA_SOFTWARE_RESET: + case ARIZONA_DEVICE_REVISION: + case ARIZONA_WRITE_SEQUENCER_CTRL_0: + case ARIZONA_WRITE_SEQUENCER_CTRL_1: + case ARIZONA_WRITE_SEQUENCER_CTRL_2: + case ARIZONA_HAPTICS_STATUS: + case ARIZONA_SAMPLE_RATE_1_STATUS: + case ARIZONA_SAMPLE_RATE_2_STATUS: + case ARIZONA_SAMPLE_RATE_3_STATUS: + case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS: + case ARIZONA_FLL1_NCO_TEST_0: + case ARIZONA_FLL2_NCO_TEST_0: + case ARIZONA_HP_CTRL_1L: + case ARIZONA_HP_CTRL_1R: + case ARIZONA_MIC_DETECT_3: + case ARIZONA_HEADPHONE_DETECT_2: + case ARIZONA_INPUT_ENABLES_STATUS: + case ARIZONA_OUTPUT_STATUS_1: + case ARIZONA_RAW_OUTPUT_STATUS_1: + case ARIZONA_SLIMBUS_RX_PORT_STATUS: + case ARIZONA_SLIMBUS_TX_PORT_STATUS: + case ARIZONA_INTERRUPT_STATUS_1: + case ARIZONA_INTERRUPT_STATUS_2: + case ARIZONA_INTERRUPT_STATUS_3: + case ARIZONA_INTERRUPT_STATUS_4: + case ARIZONA_INTERRUPT_STATUS_5: + case ARIZONA_IRQ2_STATUS_1: + case ARIZONA_IRQ2_STATUS_3: + case ARIZONA_IRQ2_STATUS_4: + case ARIZONA_IRQ2_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_3: + case ARIZONA_INTERRUPT_RAW_STATUS_4: + case ARIZONA_INTERRUPT_RAW_STATUS_5: + case ARIZONA_INTERRUPT_RAW_STATUS_6: + case ARIZONA_INTERRUPT_RAW_STATUS_7: + case ARIZONA_INTERRUPT_RAW_STATUS_8: + case ARIZONA_IRQ_PIN_STATUS: + case ARIZONA_AOD_WKUP_AND_TRIG: + case ARIZONA_AOD_IRQ1: + case ARIZONA_AOD_IRQ2: + case ARIZONA_AOD_IRQ_RAW_STATUS: + case ARIZONA_FX_CTRL2: + return true; + default: + return false; + } +} + +#define WM8997_MAX_REGISTER 0x31ff + +const struct regmap_config wm8997_i2c_regmap = { + .reg_bits = 32, + .val_bits = 16, + + .max_register = WM8997_MAX_REGISTER, + .readable_reg = wm8997_readable_register, + .volatile_reg = wm8997_volatile_register, + + .cache_type = REGCACHE_RBTREE, + .reg_defaults = wm8997_reg_default, + .num_reg_defaults = ARRAY_SIZE(wm8997_reg_default), +}; +EXPORT_SYMBOL_GPL(wm8997_i2c_regmap); diff --git a/drivers/regulator/arizona-ldo1.c b/drivers/regulator/arizona-ldo1.c index b1b35f38d11..9ae686f7e5e 100644 --- a/drivers/regulator/arizona-ldo1.c +++ b/drivers/regulator/arizona-ldo1.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -76,11 +77,6 @@ static int arizona_ldo1_hc_set_voltage_sel(struct regulator_dev *rdev, if (ret != 0) return ret; - ret = regmap_update_bits(regmap, ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, - ARIZONA_SUBSYS_MAX_FREQ, val); - if (ret != 0) - return ret; - if (val) return 0; @@ -111,6 +107,17 @@ static int arizona_ldo1_hc_get_voltage_sel(struct regulator_dev *rdev) return (val & ARIZONA_LDO1_VSEL_MASK) >> ARIZONA_LDO1_VSEL_SHIFT; } +static int arizona_ldo1_hc_set_voltage_time_sel(struct regulator_dev *rdev, + unsigned int old_selector, + unsigned int new_selector) +{ + /* if moving to 1.8v allow time for it to reach voltage */ + if (new_selector == rdev->desc->n_voltages - 1) + return 25; + else + return 0; +} + static struct regulator_ops arizona_ldo1_hc_ops = { .list_voltage = arizona_ldo1_hc_list_voltage, .map_voltage = arizona_ldo1_hc_map_voltage, @@ -118,6 +125,7 @@ static struct regulator_ops arizona_ldo1_hc_ops = { .set_voltage_sel = arizona_ldo1_hc_set_voltage_sel, .get_bypass = regulator_get_bypass_regmap, .set_bypass = regulator_set_bypass_regmap, + .set_voltage_time_sel = arizona_ldo1_hc_set_voltage_time_sel, }; static const struct regulator_desc arizona_ldo1_hc = { @@ -151,12 +159,10 @@ static const struct regulator_desc arizona_ldo1 = { .vsel_reg = ARIZONA_LDO1_CONTROL_1, .vsel_mask = ARIZONA_LDO1_VSEL_MASK, - .bypass_reg = ARIZONA_LDO1_CONTROL_1, - .bypass_mask = ARIZONA_LDO1_BYPASS, .min_uV = 900000, - .uV_step = 50000, - .n_voltages = 7, - .enable_time = 500, + .uV_step = 25000, + .n_voltages = 13, + .enable_time = 3000, .owner = THIS_MODULE, }; @@ -173,11 +179,51 @@ static const struct regulator_init_data arizona_ldo1_dvfs = { static const struct regulator_init_data arizona_ldo1_default = { .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .min_uV = 1175000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_VOLTAGE, }, .num_consumer_supplies = 1, }; +static int arizona_ldo1_of_get_pdata(struct arizona *arizona, + struct regulator_config *config) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_ldo1 *ldo1 = config->driver_data; + struct device_node *init_node, *dcvdd_node; + struct regulator_init_data *init_data; + + init_node = of_get_child_by_name(arizona->dev->of_node, "ldo1"); + dcvdd_node = of_parse_phandle(arizona->dev->of_node, "DCVDD-supply", 0); + + if (init_node) { + config->of_node = init_node; + + init_data = of_get_regulator_init_data(arizona->dev, init_node); + + if (init_data) { + init_data->consumer_supplies = &ldo1->supply; + init_data->num_consumer_supplies = 1; + + if (dcvdd_node && dcvdd_node != init_node) + arizona->external_dcvdd = true; + + pdata->ldo1 = init_data; + } + } else if (dcvdd_node) { + arizona->external_dcvdd = true; + } + + if (!(arizona->external_dcvdd)) + pdata->ldoena = arizona_of_get_named_gpio(arizona, "wlf,ldoena", true); + + of_node_put(dcvdd_node); + + return 0; +} + static int arizona_ldo1_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); @@ -186,6 +232,8 @@ static int arizona_ldo1_probe(struct platform_device *pdev) struct arizona_ldo1 *ldo1; int ret; + arizona->external_dcvdd = false; + ldo1 = devm_kzalloc(&pdev->dev, sizeof(*ldo1), GFP_KERNEL); if (ldo1 == NULL) { dev_err(&pdev->dev, "Unable to allocate private data\n"); @@ -201,6 +249,9 @@ static int arizona_ldo1_probe(struct platform_device *pdev) */ switch (arizona->type) { case WM5102: + case WM8997: + case WM8998: + case WM1814: desc = &arizona_ldo1_hc; ldo1->init_data = arizona_ldo1_dvfs; break; @@ -217,14 +268,41 @@ static int arizona_ldo1_probe(struct platform_device *pdev) config.dev = arizona->dev; config.driver_data = ldo1; config.regmap = arizona->regmap; + + if (IS_ENABLED(CONFIG_OF)) { + if (!dev_get_platdata(arizona->dev)) { + ret = arizona_ldo1_of_get_pdata(arizona, &config); + if (ret < 0) + return ret; + } + } + + /* Note - we use 0 to mean invalid in pdata so that if it's not + * explicitly set to a value we will ignore it. Convert this to an + * invalid value before using it + */ + if (arizona->pdata.ldoena == 0) + arizona->pdata.ldoena = -1; + config.ena_gpio = arizona->pdata.ldoena; + config.ena_gpio_flags = GPIOF_OUT_INIT_LOW; if (arizona->pdata.ldo1) config.init_data = arizona->pdata.ldo1; else config.init_data = &ldo1->init_data; + /* + * LDO1 can only be used to supply DCVDD so if it has no + * consumers then DCVDD is supplied externally. + */ + if (config.init_data->num_consumer_supplies == 0) + arizona->external_dcvdd = true; + ldo1->regulator = regulator_register(desc, &config); + + of_node_put(config.of_node); + if (IS_ERR(ldo1->regulator)) { ret = PTR_ERR(ldo1->regulator); dev_err(arizona->dev, "Failed to register LDO1 supply: %d\n", diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c index e87536bf0be..d3af1ea8015 100644 --- a/drivers/regulator/arizona-micsupp.c +++ b/drivers/regulator/arizona-micsupp.c @@ -15,10 +15,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -30,6 +32,9 @@ #define ARIZONA_MICSUPP_MAX_SELECTOR 0x1f +#define ARIZONA_MICSUPP_RANGE1_MAX_SELECTOR 0x14 +#define ARIZONA_MICSUPP_RANGE2_MAX_SELECTOR 0x27 + struct arizona_micsupp { struct regulator_dev *regulator; struct arizona *arizona; @@ -40,8 +45,7 @@ struct arizona_micsupp { struct work_struct check_cp_work; }; -static int arizona_micsupp_list_voltage(struct regulator_dev *rdev, - unsigned int selector) +static int arizona_micsupp_sel_to_voltage(unsigned int selector) { if (selector > ARIZONA_MICSUPP_MAX_SELECTOR) return -EINVAL; @@ -52,28 +56,33 @@ static int arizona_micsupp_list_voltage(struct regulator_dev *rdev, return (selector * 50000) + 1700000; } -static int arizona_micsupp_map_voltage(struct regulator_dev *rdev, - int min_uV, int max_uV) +static int arizona_micsupp_ext_sel_to_voltage(unsigned int selector) { - unsigned int voltage; - int selector; - - if (min_uV < 1700000) - min_uV = 1700000; - - if (min_uV > 3200000) - selector = ARIZONA_MICSUPP_MAX_SELECTOR; - else - selector = DIV_ROUND_UP(min_uV - 1700000, 50000); - - if (selector < 0) + if (selector > ARIZONA_MICSUPP_RANGE2_MAX_SELECTOR) return -EINVAL; - voltage = arizona_micsupp_list_voltage(rdev, selector); - if (voltage < min_uV || voltage > max_uV) - return -EINVAL; + if (selector < ARIZONA_MICSUPP_RANGE1_MAX_SELECTOR) { + return (selector * 25000) + 900000; + } else { + selector -= ARIZONA_MICSUPP_RANGE1_MAX_SELECTOR; + return (selector * 100000) + 1400000; + } +} - return selector; +static int arizona_micsupp_list_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + struct arizona_micsupp *micsupp = rdev_get_drvdata(rdev); + + switch (micsupp->arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + return arizona_micsupp_sel_to_voltage(selector); + default: + return arizona_micsupp_ext_sel_to_voltage(selector); + } } static void arizona_micsupp_check_cp(struct work_struct *work) @@ -93,11 +102,19 @@ static void arizona_micsupp_check_cp(struct work_struct *work) } if (dapm) { + mutex_lock_nested(&dapm->card->dapm_mutex, + SND_SOC_DAPM_CLASS_RUNTIME); + if ((reg & (ARIZONA_CPMIC_ENA | ARIZONA_CPMIC_BYPASS)) == - ARIZONA_CPMIC_ENA) + ARIZONA_CPMIC_ENA) { snd_soc_dapm_force_enable_pin(dapm, "MICSUPP"); - else + arizona->micvdd_regulated = true; + } else { snd_soc_dapm_disable_pin(dapm, "MICSUPP"); + arizona->micvdd_regulated = false; + } + + mutex_unlock(&dapm->card->dapm_mutex); snd_soc_dapm_sync(dapm); } @@ -134,6 +151,7 @@ static int arizona_micsupp_set_bypass(struct regulator_dev *rdev, bool ena) int ret; ret = regulator_set_bypass_regmap(rdev, ena); + udelay(1000); if (ret == 0) schedule_work(&micsupp->check_cp_work); @@ -146,7 +164,7 @@ static struct regulator_ops arizona_micsupp_ops = { .is_enabled = regulator_is_enabled_regmap, .list_voltage = arizona_micsupp_list_voltage, - .map_voltage = arizona_micsupp_map_voltage, + .map_voltage = regulator_map_voltage_ascend, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, @@ -169,6 +187,25 @@ static const struct regulator_desc arizona_micsupp = { .bypass_reg = ARIZONA_MIC_CHARGE_PUMP_1, .bypass_mask = ARIZONA_CPMIC_BYPASS, + .enable_time = 6000, + + .owner = THIS_MODULE, +}; + +static const struct regulator_desc arizona_micsupp_ext = { + .name = "MICVDD", + .supply_name = "CPVDD", + .type = REGULATOR_VOLTAGE, + .n_voltages = ARIZONA_MICSUPP_RANGE2_MAX_SELECTOR + 1, + .ops = &arizona_micsupp_ops, + + .vsel_reg = ARIZONA_LDO2_CONTROL_1, + .vsel_mask = ARIZONA_LDO2_VSEL_MASK, + .enable_reg = ARIZONA_MIC_CHARGE_PUMP_1, + .enable_mask = ARIZONA_CPMIC_ENA, + .bypass_reg = ARIZONA_MIC_CHARGE_PUMP_1, + .bypass_mask = ARIZONA_CPMIC_BYPASS, + .enable_time = 3000, .owner = THIS_MODULE, @@ -186,12 +223,82 @@ static const struct regulator_init_data arizona_micsupp_default = { .num_consumer_supplies = 1, }; +static const struct regulator_init_data arizona_micsupp_ext_default = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_BYPASS, + .min_uV = 900000, + .max_uV = 3300000, + }, + + .num_consumer_supplies = 1, +}; + +static int arizona_micsupp_of_get_pdata(struct arizona *arizona, + struct regulator_config *config) +{ + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_micsupp *micsupp = config->driver_data; + struct device_node *np; + struct regulator_init_data *init_data; + + np = of_get_child_by_name(arizona->dev->of_node, "micvdd"); + + if (np) { + config->of_node = np; + + init_data = of_get_regulator_init_data(arizona->dev, np); + + if (init_data) { + init_data->consumer_supplies = &micsupp->supply; + init_data->num_consumer_supplies = 1; + + init_data->constraints.valid_ops_mask |= + REGULATOR_CHANGE_BYPASS; + + pdata->micvdd = init_data; + } + } + + return 0; +} + +static unsigned int arizona_get_max_micbias(struct arizona *arizona) +{ + unsigned int num_micbias, i, max_micbias, micbias_mv; + int ret; + + arizona_get_num_micbias(arizona, &num_micbias, NULL); + + max_micbias = 0; + for (i = 0; i < num_micbias; i++) { + ret = regmap_read(arizona->regmap, + ARIZONA_MIC_BIAS_CTRL_1 + i, &micbias_mv); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read micbias level: %d\n", ret); + return 0; + } + + micbias_mv = (micbias_mv & ARIZONA_MICB1_LVL_MASK) >> + ARIZONA_MICB1_LVL_SHIFT; + micbias_mv = (1500) + (100 * micbias_mv); + if (micbias_mv > max_micbias) + max_micbias = micbias_mv; + } + + return max_micbias * 1000; +} + static int arizona_micsupp_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + const struct regulator_desc *desc; struct regulator_config config = { }; struct arizona_micsupp *micsupp; int ret; + unsigned int max_micbias; micsupp = devm_kzalloc(&pdev->dev, sizeof(*micsupp), GFP_KERNEL); if (micsupp == NULL) { @@ -207,7 +314,19 @@ static int arizona_micsupp_probe(struct platform_device *pdev) * default init_data for it. This will be overridden with * platform data if provided. */ - micsupp->init_data = arizona_micsupp_default; + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + desc = &arizona_micsupp; + micsupp->init_data = arizona_micsupp_default; + break; + default: + desc = &arizona_micsupp_ext; + micsupp->init_data = arizona_micsupp_ext_default; + break; + } micsupp->init_data.consumer_supplies = &micsupp->supply; micsupp->supply.supply = "MICVDD"; micsupp->supply.dev_name = dev_name(arizona->dev); @@ -216,16 +335,46 @@ static int arizona_micsupp_probe(struct platform_device *pdev) config.driver_data = micsupp; config.regmap = arizona->regmap; + if (IS_ENABLED(CONFIG_OF)) { + if (!dev_get_platdata(arizona->dev)) { + ret = arizona_micsupp_of_get_pdata(arizona, &config); + if (ret < 0) + return ret; + } + } + + max_micbias = arizona_get_max_micbias(arizona); + if (max_micbias) { + /* micvdd must be 200mV more than maximum micbias */ + max_micbias += 200000; + if (micsupp->init_data.constraints.max_uV >= max_micbias) { + micsupp->init_data.constraints.max_uV = max_micbias; + micsupp->init_data.constraints.min_uV = max_micbias; + micsupp->init_data.constraints.apply_uV = true; + micsupp->init_data.constraints.valid_ops_mask &= + ~REGULATOR_CHANGE_VOLTAGE; + } + } + if (arizona->pdata.micvdd) config.init_data = arizona->pdata.micvdd; else config.init_data = &micsupp->init_data; + if (max_micbias) { + if (config.init_data->constraints.max_uV < max_micbias) + dev_err(arizona->dev, "micvdd must be atleast set to %duV\n", + max_micbias); + } + /* Default to regulated mode until the API supports bypass */ regmap_update_bits(arizona->regmap, ARIZONA_MIC_CHARGE_PUMP_1, ARIZONA_CPMIC_BYPASS, 0); - micsupp->regulator = regulator_register(&arizona_micsupp, &config); + micsupp->regulator = regulator_register(desc, &config); + + of_node_put(config.of_node); + if (IS_ERR(micsupp->regulator)) { ret = PTR_ERR(micsupp->regulator); dev_err(arizona->dev, "Failed to register mic supply: %d\n", diff --git a/drivers/switch/Kconfig b/drivers/switch/Kconfig index 19404b6f777..98026a093b7 100644 --- a/drivers/switch/Kconfig +++ b/drivers/switch/Kconfig @@ -12,4 +12,12 @@ config SWITCH_GPIO help Say Y here to enable GPIO based switch support. +config SWITCH_ARIZONA + tristate "Wolfson Arizona Switch support" + depends on MFD_ARIZONA && INPUT && SND_SOC + help + Say Y here to enable support for external accessory detection + with Wolfson Arizona devices. These are audio CODECs with + advanced audio accessory detection support. + endif # SWITCH diff --git a/drivers/switch/Makefile b/drivers/switch/Makefile index f7606ed4a71..2fd6461ffc9 100644 --- a/drivers/switch/Makefile +++ b/drivers/switch/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_SWITCH) += switch_class.o obj-$(CONFIG_SWITCH_GPIO) += switch_gpio.o +obj-$(CONFIG_SWITCH_ARIZONA) += switch-arizona.o diff --git a/drivers/switch/switch-arizona.c b/drivers/switch/switch-arizona.c new file mode 100644 index 00000000000..a4ef9a2583f --- /dev/null +++ b/drivers/switch/switch-arizona.c @@ -0,0 +1,4132 @@ +/* + * extcon-arizona.c - Extcon driver Wolfson Arizona devices + * + * Copyright (C) 2012-2014 Wolfson Microelectronics plc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define ARIZONA_MAX_MICD_RANGE 8 + +#define ARIZONA_ACCDET_MODE_MIC 0 +#define ARIZONA_ACCDET_MODE_HPL 1 +#define ARIZONA_ACCDET_MODE_HPR 2 +#define ARIZONA_ACCDET_MODE_HPM 4 +#define ARIZONA_ACCDET_MODE_ADC 7 +#define ARIZONA_ACCDET_MODE_INVALID 8 + +#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4 +#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5 + +/* GP5 is analogous to JD2 (for systems without a dedicated second JD pin) */ +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5L 0x8 +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9 +#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb + +#define ARIZONA_HPDET_MAX 1000000 /* 10,000 ohms */ + +#define HPDET_DEBOUNCE 500 +#define DEFAULT_MICD_TIMEOUT 2000 + +#define MICROPHONE_MIN_OHM 1258 +#define MICROPHONE_MAX_OHM 30000 + +#define HP_NORMAL_IMPEDANCE 0 +#define HP_LOW_IMPEDANCE 1 +#define HP_HIGH_IMPEDANCE 2 + +#define HP_LOW_IMPEDANCE_LIMIT 13 + +#define ARIZONA_MIC_MUTE 1 +#define ARIZONA_MIC_UNMUTE 0 + +#define ARIZONA_HP_TUNING_INVALID -1 + +#define MOON_HP_LOW_IMPEDANCE_LIMIT 14 +#define MOON_HP_MEDIUM_IMPEDANCE_LIMIT 24 + +#define CS47L15_HP_LOW_IMPEDANCE_LIMIT 16 +#define CS47L15_HP_MEDIUM_IMPEDANCE_LIMIT 32 + +#define MOON_HPD_SENSE_MICDET1 0 +#define MOON_HPD_SENSE_MICDET2 1 +#define MOON_HPD_SENSE_MICDET3 2 +#define MOON_HPD_SENSE_MICDET4 3 +#define MOON_HPD_SENSE_HPDET1 4 +#define MOON_HPD_SENSE_HPDET2 5 +#define MOON_HPD_SENSE_JD1 6 +#define MOON_HPD_SENSE_JD2 7 + +#define MOON_HPD_GND_MICDET1 0 +#define MOON_HPD_GND_MICDET2 1 +#define MOON_HPD_GND_MICDET3 2 +#define MOON_HPD_GND_MICDET4 3 + +#define MOON_HPD_OUT_OUT1L 0 +#define MOON_HPD_OUT_OUT1R 1 +#define MOON_HPD_OUT_OUT2L 2 +#define MOON_HPD_OUT_OUT2R 3 + +#define MOON_MICD1_SENSE_MICDET1 0 +#define MOON_MICD1_SENSE_MICDET2 1 +#define MOON_MICD1_SENSE_MICDET3 2 +#define MOON_MICD1_SENSE_MICDET4 3 + +#define MOON_MICD1_GND_MICDET1 0 +#define MOON_MICD1_GND_MICDET2 1 +#define MOON_MICD1_GND_MICDET3 2 +#define MOON_MICD1_GND_MICDET4 3 + +#define MOON_MICD_BIAS_SRC_MICBIAS1A 0x0 +#define MOON_MICD_BIAS_SRC_MICBIAS1B 0x1 +#define MOON_MICD_BIAS_SRC_MICBIAS1C 0x2 +#define MOON_MICD_BIAS_SRC_MICBIAS1D 0x3 +#define MOON_MICD_BIAS_SRC_MICBIAS2A 0x4 +#define MOON_MICD_BIAS_SRC_MICBIAS2B 0x5 +#define MOON_MICD_BIAS_SRC_MICBIAS2C 0x6 +#define MOON_MICD_BIAS_SRC_MICBIAS2D 0x7 +#define MOON_MICD_BIAS_SRC_MICVDD 0xF + +struct arizona_hpdet_calibration_data { + int min; + int max; + s64 C0; /* value * 1000000 */ + s64 C1; /* value * 1000000 */ + s64 C2; /* not multiplied */ + s64 C3; /* value * 1000000 */ + s64 C4_x_C3; /* value * 1000000 */ + s64 C5; /* value * 1000000 */ + s64 dacval_adjust; +}; + +struct arizona_hpdet_d_trims { + int off_x4; + int grad_x4; +}; + +struct arizona_micd_bias { + unsigned int bias; + bool enabled; +}; + +struct arizona_extcon_info { + struct device *dev; + struct arizona *arizona; + struct mutex lock; + struct regulator *micvdd; + struct input_dev *input; + + u16 last_jackdet; + + int micd_mode; + const struct arizona_micd_config *micd_modes; + int micd_num_modes; + + struct arizona_micd_range *micd_ranges; + int num_micd_ranges; + + bool micd_reva; + bool micd_clamp; + int micd_res_old; + int micd_debounce; + int micd_count; + + struct delayed_work hpdet_work; + struct delayed_work micd_detect_work; + struct delayed_work micd_clear_work; + bool first_clear; + + bool hpdet_retried; + int hp_imp_level; + + int num_hpdet_res; + unsigned int hpdet_res[3]; + + bool mic; + bool detecting; + int jack_flips; + + int hpdet_ip_version; + const struct arizona_hpdet_d_trims *hpdet_d_trims; + const struct arizona_hpdet_calibration_data *calib_data; + int calib_data_size; + + struct switch_dev edev; + + const struct arizona_jd_state *state; + const struct arizona_jd_state *old_state; + struct delayed_work state_timeout_work; + + struct wakeup_source detection_wake_lock; + + int mic_impedance; + struct completion manual_mic_completion; + + int accdet_ip; + + struct arizona_micd_bias micd_bias; +}; + +static const struct arizona_micd_config micd_default_modes[] = { + { ARIZONA_ACCDET_SRC, ARIZONA_ACCDET_SRC, 1, 0 }, + { 0, 0, 2, 1 }, +}; + +static const struct arizona_micd_config moon_micd_default_modes[] = { + { MOON_MICD1_SENSE_MICDET1, MOON_MICD1_SENSE_MICDET2, + MOON_MICD_BIAS_SRC_MICBIAS1A, 0 }, + { MOON_MICD1_SENSE_MICDET2, MOON_MICD1_SENSE_MICDET1, + MOON_MICD_BIAS_SRC_MICBIAS1B, 1 }, +}; + +static struct arizona_micd_range micd_default_ranges[] = { + { .max = 11, .key = BTN_0 }, + { .max = 28, .key = BTN_1 }, + { .max = 54, .key = BTN_2 }, + { .max = 100, .key = BTN_3 }, + { .max = 186, .key = BTN_4 }, + { .max = 430, .key = BTN_5 }, + { .max = -1, .key = -1 }, + { .max = -1, .key = -1 }, +}; + +/* The number of levels in arizona_micd_levels valid for button thresholds */ +#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64 + +static const int arizona_micd_levels[] = { + 3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46, + 49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100, + 105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245, + 270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071, + 1257, 30000, +}; + +/* These values are copied from Android WiredAccessoryObserver */ +enum headset_state { + BIT_NO_HEADSET = 0, + BIT_HEADSET = (1 << 0), + BIT_HEADSET_NO_MIC = (1 << 1), +}; + +static ssize_t arizona_extcon_show(struct device *dev, + struct device_attribute *attr, + char *buf); +static DEVICE_ATTR(hp_impedance, S_IRUGO, arizona_extcon_show, NULL); + +static ssize_t arizona_extcon_mic_show(struct device *dev, + struct device_attribute *attr, + char *buf); +static DEVICE_ATTR(mic_impedance, S_IRUGO, arizona_extcon_mic_show, NULL); + +inline void arizona_extcon_report(struct arizona_extcon_info *info, int state) +{ + dev_dbg(info->arizona->dev, "Switch Report: %d\n", state); + switch_set_state(&info->edev, state); +} +EXPORT_SYMBOL_GPL(arizona_extcon_report); + +static int arizona_jds_get_mode(struct arizona_extcon_info *info) +{ + int mode = ARIZONA_ACCDET_MODE_INVALID; + + if (info->state) + mode = info->state->mode; + + return mode; +} + +int arizona_jds_set_state(struct arizona_extcon_info *info, + const struct arizona_jd_state *new_state) +{ + int ret = 0; + + if (new_state != info->state) { + if (info->state) + info->state->stop(info); + + info->state = new_state; + + if (info->state) { + ret = info->state->start(info); + if (ret < 0) + info->state = NULL; + } + } + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_jds_set_state); + +static void arizona_jds_reading(struct arizona_extcon_info *info, int val) +{ + int ret; + + ret = info->state->reading(info, val); + + if (ret == -EAGAIN && info->state->restart) + info->state->restart(info); +} + +static inline bool arizona_jds_cancel_timeout(struct arizona_extcon_info *info) +{ + return cancel_delayed_work_sync(&info->state_timeout_work); +} + +static void arizona_jds_start_timeout(struct arizona_extcon_info *info) +{ + const struct arizona_jd_state *state = info->state; + + if (!state) + return; + + if (state->timeout_ms && state->timeout) { + int ms = state->timeout_ms(info); + + schedule_delayed_work(&info->state_timeout_work, + msecs_to_jiffies(ms)); + } +} + +static void arizona_jds_timeout_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = + container_of(work, struct arizona_extcon_info, + state_timeout_work.work); + + mutex_lock(&info->lock); + + if (!info->state) { + dev_warn(info->arizona->dev, "Spurious timeout in idle state\n"); + } else if (!info->state->timeout) { + dev_warn(info->arizona->dev, "Spurious timeout state.mode=%d\n", + info->state->mode); + } else { + info->state->timeout(info); + arizona_jds_start_timeout(info); + } + + mutex_unlock(&info->lock); +} + +static void arizona_extcon_hp_clamp(struct arizona_extcon_info *info, + bool clamp) +{ + struct arizona *arizona = info->arizona; + unsigned int mask, val = 0; + unsigned int cap_sel = 0; + unsigned int edre_reg = 0, edre_val = 0; + unsigned int ep_sel = 0; + int ret; + + mutex_lock_nested(&arizona->dapm->card->dapm_mutex, + SND_SOC_DAPM_CLASS_RUNTIME); + + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + mask = ARIZONA_RMV_SHRT_HP1L; + if (clamp) + val = ARIZONA_RMV_SHRT_HP1L; + break; + case WM8280: + case WM5110: + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) { + val = ARIZONA_HP1L_SHRTO; + cap_sel = 1; + } else { + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + cap_sel = 3; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_TEST_CTRL_1, + ARIZONA_HP1_TST_CAP_SEL_MASK, + cap_sel); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to set TST_CAP_SEL: %d\n", + ret); + break; + case CS47L35: + /* check whether audio is routed to EPOUT, do not disable OUT1 + * in that case */ + regmap_read(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, &ep_sel); + ep_sel &= ARIZONA_EP_SEL_MASK; + /* fall through to next step to set common variables */ + case WM8285: + case WM1840: + edre_reg = CLEARWATER_EDRE_MANUAL; + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) { + val = ARIZONA_HP1L_SHRTO; + edre_val = 0x3; + } else { + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + edre_val = 0; + } + break; + case CS47L15: + regmap_read(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, &ep_sel); + ep_sel &= ARIZONA_EP_SEL_MASK; + /* fall through to CS47L90 case to set common variables */ + case CS47L90: + case CS47L91: + mask = MOON_HPD_OVD_ENA_SEL_MASK; + if (clamp) + val = MOON_HPD_OVD_ENA_SEL_MASK; + else + val = 0; + break; + default: + mask = 0; + break; + }; + + arizona->hpdet_clamp = clamp; + + /* Keep the HP output stages disabled while doing the clamp */ + if (clamp && !ep_sel) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable headphone outputs: %d\n", + ret); + } + + if (edre_reg && !ep_sel) { + ret = regmap_write(arizona->regmap, edre_reg, edre_val); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to set EDRE Manual: %d\n", + ret); + } + + if (mask) { + switch (info->accdet_ip) { + case 0: + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_CTRL_1L, mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_CTRL_1R, mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + break; + default: + ret = regmap_update_bits(arizona->regmap, + MOON_HEADPHONE_DETECT_0, + MOON_HPD_OVD_ENA_SEL_MASK, + val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + break; + } + } + + /* Restore the desired state while not doing the clamp */ + if (!clamp && (HOHM_TO_OHM(arizona->hp_impedance_x100) > + arizona->pdata.hpdet_short_circuit_imp) && !ep_sel) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, arizona->hp_ena); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to restore headphone outputs: %d\n", + ret); + } + + mutex_unlock(&arizona->dapm->card->dapm_mutex); +} + +static const char *arizona_extcon_get_micbias_src( + struct arizona_extcon_info *info, unsigned int bias) +{ + struct arizona *arizona = info->arizona; + + switch (arizona->type) { + case CS47L15: + switch (bias) { + case 0: + case 1: + case 2: + return "MICBIAS1"; + default: + return "MICVDD"; + } + break; + case CS47L90: + case CS47L91: + switch (bias) { + case 0: + case 1: + case 2: + case 3: + return "MICBIAS1"; + case 4: + case 5: + case 6: + case 7: + return "MICBIAS2"; + default: + return "MICVDD"; + } + break; + default: + return NULL; + } +} + +static int arizona_extcon_set_micd_bias(struct arizona_extcon_info *info, + unsigned int bias, bool enable) +{ + struct arizona *arizona = info->arizona; + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct arizona_micd_bias *micd_bias = &(info->micd_bias); + const char *old_widget = + arizona_extcon_get_micbias_src(info, micd_bias->bias); + const char *new_widget = arizona_extcon_get_micbias_src(info, bias); + bool same_bias_src; + int ret = 0; + + switch (arizona->type) { + case CS47L15: + case CS47L90: + case CS47L91: + break; + default: + return 0; + }; + + micd_bias->bias = bias; + same_bias_src = !strcmp(old_widget, new_widget); + + if ((same_bias_src) && + (micd_bias->enabled == enable)) + return 0; + + if (micd_bias->enabled) { + dev_dbg(arizona->dev, "disabling %s\n", old_widget); + + mutex_lock(&dapm->card->dapm_mutex); + + ret = snd_soc_dapm_disable_pin(dapm, old_widget); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + old_widget, ret); + mutex_unlock(&dapm->card->dapm_mutex); + snd_soc_dapm_sync(dapm); + } + + if (enable) { + dev_dbg(arizona->dev, "enabling %s\n", new_widget); + + mutex_lock(&dapm->card->dapm_mutex); + + ret = snd_soc_dapm_force_enable_pin(dapm, new_widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to enable %s: %d\n", + new_widget, ret); + mutex_unlock(&dapm->card->dapm_mutex); + snd_soc_dapm_sync(dapm); + } + + micd_bias->enabled = enable; + + return ret; +} + +static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) +{ + struct arizona *arizona = info->arizona; + + if (arizona->pdata.micd_pol_gpio > 0) + gpio_set_value_cansleep(arizona->pdata.micd_pol_gpio, + info->micd_modes[mode].gpio); + + switch (info->accdet_ip) { + case 0: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_SRC_MASK, + info->micd_modes[mode].bias << + ARIZONA_MICD_BIAS_SRC_SHIFT); + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[mode].src); + break; + default: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + MOON_MICD_BIAS_SRC_MASK, + info->micd_modes[mode].bias << + MOON_MICD_BIAS_SRC_SHIFT); + regmap_update_bits(arizona->regmap, MOON_MIC_DETECT_0, + MOON_MICD1_SENSE_MASK, + info->micd_modes[mode].src << + MOON_MICD1_SENSE_SHIFT); + regmap_update_bits(arizona->regmap, MOON_MIC_DETECT_0, + MOON_MICD1_GND_MASK, + info->micd_modes[mode].gnd << + MOON_MICD1_GND_SHIFT); + regmap_update_bits(arizona->regmap, MOON_OUT1_CONFIG, + MOON_HP1_GND_SEL_MASK, + info->micd_modes[mode].gnd << + MOON_HP1_GND_SEL_SHIFT); + break; + } + + info->micd_mode = mode; + + dev_dbg(arizona->dev, "Set jack polarity to %d\n", mode); +} + +static const char *arizona_extcon_get_micbias(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + + switch (arizona->type) { + case CS47L15: + switch (info->micd_modes[info->micd_mode].bias) { + case 0: + return "MICBIAS1A"; + case 1: + return "MICBIAS1B"; + case 2: + return "MICBIAS1C"; + default: + return "MICVDD"; + } + break; + case CS47L35: + switch (info->micd_modes[info->micd_mode].bias) { + case 1: + return "MICBIAS1A"; + case 2: + return "MICBIAS1B"; + case 3: + return "MICBIAS2A"; + default: + return "MICVDD"; + } + case CS47L90: + case CS47L91: + switch (info->micd_modes[info->micd_mode].bias) { + case 0: + return "MICBIAS1A"; + case 1: + return "MICBIAS1B"; + case 2: + return "MICBIAS1C"; + case 3: + return "MICBIAS1D"; + case 4: + return "MICBIAS2A"; + case 5: + return "MICBIAS2B"; + case 6: + return "MICBIAS2C"; + case 7: + return "MICBIAS2D"; + default: + return "MICVDD"; + } + break; + default: + switch (info->micd_modes[info->micd_mode].bias) { + case 1: + return "MICBIAS1"; + case 2: + return "MICBIAS2"; + case 3: + return "MICBIAS3"; + case 4: + return "MICBIAS4"; + default: + return "MICVDD"; + } + } +} + +static void arizona_extcon_pulse_micbias(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + int ret; + + dev_dbg(arizona->dev, "enabling %s\n", widget); + + mutex_lock(&dapm->card->dapm_mutex); + + ret = snd_soc_dapm_force_enable_pin(dapm, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to enable %s: %d\n", + widget, ret); + + mutex_unlock(&dapm->card->dapm_mutex); + + snd_soc_dapm_sync(dapm); + + if (arizona->pdata.micd_force_micbias_initial && info->detecting) + return; + + if (!arizona->pdata.micd_force_micbias) { + dev_dbg(arizona->dev, "disabling %s\n", widget); + + mutex_lock(&dapm->card->dapm_mutex); + + ret = snd_soc_dapm_disable_pin(arizona->dapm, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to disable %s: %d\n", + widget, ret); + + mutex_unlock(&dapm->card->dapm_mutex); + + snd_soc_dapm_sync(dapm); + } +} + +static void arizona_extcon_change_mode(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int old_mode = info->micd_mode; + int new_mode = (info->micd_mode + 1) % info->micd_num_modes; + bool change_bias = false; + const char *widget; + int ret; + + dev_dbg(arizona->dev, "change micd mode %d->%d (bias %d->%d\n)", + old_mode, new_mode, + info->micd_modes[old_mode].bias, + info->micd_modes[new_mode].bias); + + if (info->micd_modes[old_mode].bias != + info->micd_modes[new_mode].bias) { + change_bias = true; + + if ((arizona->pdata.micd_force_micbias) || + (arizona->pdata.micd_force_micbias_initial && + info->detecting)) { + widget = arizona_extcon_get_micbias(info); + dev_dbg(arizona->dev, "disabling %s\n", widget); + + ret = snd_soc_dapm_disable_pin(arizona->dapm, widget); + if (ret) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(arizona->dapm); + } + } + + arizona_extcon_set_mode(info, new_mode); + + if (change_bias) { + arizona_extcon_set_micd_bias(info, + info->micd_modes[new_mode].bias, + info->micd_bias.enabled); + arizona_extcon_pulse_micbias(info); + } +} + +static int arizona_micd_adc_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val = 0; + int ret; + + regmap_read(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, &val); + val &= ARIZONA_ACCDET_MODE_MASK; + + /* Must disable MICD before we read the ADCVAL */ + ret = regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to disable MICD: %d\n", + ret); + return ret; + } + + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET_ADCVAL: %d\n", + ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET_ADCVAL: 0x%x\n", val); + + val &= ARIZONA_MICDET_ADCVAL_MASK; + if (val < ARRAY_SIZE(arizona_micd_levels)) + val = arizona_micd_levels[val]; + else + val = INT_MAX; + + return val; +} + +static int arizona_micd_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val = 0; + int ret, i; + + for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET: %d\n", + ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET: 0x%x\n", val); + + if (!(val & ARIZONA_MICD_VALID)) { + dev_warn(arizona->dev, + "Microphone detection state invalid\n"); + return -EINVAL; + } + } + + if (i == 10 && !(val & MICD_LVL_0_TO_8)) { + dev_err(arizona->dev, "Failed to get valid MICDET value\n"); + return -EINVAL; + } + + if (!(val & ARIZONA_MICD_STS)) { + val = INT_MAX; + } else if (!(val & MICD_LVL_0_TO_7)) { + val = arizona_micd_levels[ARRAY_SIZE(arizona_micd_levels) - 1]; + } else { + int lvl; + + lvl = (val & ARIZONA_MICD_LVL_MASK) >> ARIZONA_MICD_LVL_SHIFT; + lvl = ffs(lvl) - 1; + + if (lvl < info->num_micd_ranges) { + val = info->micd_ranges[lvl].max; + } else { + i = ARRAY_SIZE(arizona_micd_levels) - 2; + val = arizona_micd_levels[i]; + } + } + + return val; +} + +static struct { + unsigned int threshold; + unsigned int factor_a; + unsigned int factor_b; +} arizona_hpdet_b_ranges[] = { + { 100, 5528, 362464 }, + { 169, 11084, 6186851 }, + { 169, 11065, 65460395 }, +}; + +#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb + +static struct { + int min; + int max; +} arizona_hpdet_c_ranges[] = { + { 0, 3000 }, + { 800, 10000 }, + { 10000, 100000 }, + { 100000, 1000000 }, +}; + +static const struct arizona_hpdet_calibration_data arizona_hpdet_d_ranges[] = { + { 0, 3000, 1007000, -7200, 4003, 69300000, 381150, + 250000, 1500000}, + { 800, 10000, 1007000, -7200, 7975, 69600000, 382800, + 250000, 1500000}, + { 10000, 100000, 9696000, -79500, 7300, 62900000, 345950, + 250000, 1500000}, + { 100000, 1000000, 100684000, -949400, 7300, 63200000, 347600, + 250000, 1500000}, +}; + +static const struct arizona_hpdet_calibration_data arizona_hpdet_clearwater_ranges[] = { + { 400, 3000, 1007000, -7200, 4003, 69300000, 381150, + 250000, 500000}, + { 800, 10000, 1007000, -7200, 7975, 69600000, 382800, + 250000, 500000}, + { 10000, 100000, 9696000, -79500, 7300, 62900000, 345950, + 250000, 500000}, + { 100000, 1000000, 100684000, -949400, 7300, 63200000, 347600, + 250000, 500000}, +}; + +static const struct arizona_hpdet_calibration_data + arizona_hpdet_moon_ranges[] = { + { 400, 3000, 1014000, -4300, 3950, 69300000, 381150, 700000, + 500000}, + { 800, 10000, 1014000, -8600, 7975, 69600000, 382800, 700000, + 500000}, + { 10000, 100000, 9744000, -79500, 7300, 62900000, 345950, 700000, + 500000}, + { 100000, 1000000, 101158000, -949400, 7300, 63200000, 347600, 700000, + 500000}, +}; + +static const struct arizona_hpdet_calibration_data + arizona_hpdet_gaines_ranges[] = { + {}, + { 3300, 12300, 1000000, -4300, 7975, 69600000, 382800, 33350000, + 500000}, + { 12300, 103300, 9633000, -79500, 7300, 62900000, 283050, 33350000, + 500000}, + { 103300, 1003300, 100684000, -949400, 7300, 63200000, 284400, 33350000, + 500000}, +}; + +static int arizona_hpdet_d_calibrate(const struct arizona_extcon_info *info, + int dacval, int range) +{ + int grad_x4 = info->hpdet_d_trims[range].grad_x4; + int off_x4 = info->hpdet_d_trims[range].off_x4; + s64 val = dacval; + s64 n; + + dev_dbg(info->arizona->dev, "hpdet_d calib range %d dac %d\n", range, dacval); + + val = (val * 1000000) + info->calib_data[range].dacval_adjust; + val = div64_s64(val, info->calib_data[range].C2); + + n = div_s64(1000000000000LL, info->calib_data[range].C3 + + ((info->calib_data[range].C4_x_C3 * grad_x4) / 4)); + n = val - n; + if (n <= 0) + return ARIZONA_HPDET_MAX; + + val = info->calib_data[range].C0 + + ((info->calib_data[range].C1 * off_x4) / 4); + val *= 1000000; + + val = div_s64(val, n); + val -= info->calib_data[range].C5; + + /* Round up */ + val += 5000; + val = div_s64(val, 10000); + + if (val < 0) + return 0; + else if (val > ARIZONA_HPDET_MAX) + return ARIZONA_HPDET_MAX; + + return (int)val; +} + +static int arizona_hpdet_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val, range, sense_pin; + int ret; + unsigned int val_down; + bool is_jdx_micdetx_pin = false; + + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HPDET status: %d\n", + ret); + return ret; + } + + switch (info->accdet_ip) { + case 0: + break; + default: + regmap_read(arizona->regmap, MOON_HEADPHONE_DETECT_0, + &sense_pin); + sense_pin = (sense_pin & MOON_HPD_SENSE_SEL_MASK) + >> MOON_HPD_SENSE_SEL_SHIFT; + switch (sense_pin) { + case MOON_HPD_SENSE_HPDET1: + case MOON_HPD_SENSE_HPDET2: + is_jdx_micdetx_pin = false; + break; + default: + is_jdx_micdetx_pin = true;; + } + break; + } + + switch (info->hpdet_ip_version) { + case 0: + if (!(val & ARIZONA_HP_DONE)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_MASK; + val = OHM_TO_HOHM(val); + break; + + case 1: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP value: %d\n", + ret); + return -EAGAIN; + } + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 && + (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d\n", + range); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + /* If we go out of range report top of range */ + if (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX) { + dev_dbg(arizona->dev, "Measurement out of range\n"); + return ARIZONA_HPDET_MAX; + } + + dev_dbg(arizona->dev, "HPDET read %d in range %d\n", + val, range); + + /* Multiply numerator to get hundredths of an ohm. */ + val = (arizona_hpdet_b_ranges[range].factor_b * 100) + / ((val * 100) - + arizona_hpdet_b_ranges[range].factor_a); + break; + + default: + dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", + info->hpdet_ip_version); + case 2: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to hundredths of an ohm, the value is currently in + 0.5 ohm increments */ + val *= 50; + + if (is_jdx_micdetx_pin) + goto exit; + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + /* Skip up a range, or report? */ + if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 && + (val >= arizona_hpdet_c_ranges[range].max)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", + arizona_hpdet_c_ranges[range].min, + arizona_hpdet_c_ranges[range].max); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + if (range && + (val < arizona_hpdet_c_ranges[range].min)) { + dev_dbg(arizona->dev, "Reporting range boundary %d\n", + arizona_hpdet_c_ranges[range].min); + val = arizona_hpdet_c_ranges[range].min; + } + break; + + case 3: + case 4: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to hundredths of an ohm, the value is currently in + 0.5 ohm increments */ + val *= 50; + + if (is_jdx_micdetx_pin) + goto exit; + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) >> + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + /* Skip up a range, or report? */ + if (range < info->calib_data_size - 1 && + (val >= info->calib_data[range].max)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", + info->calib_data[range].min, + info->calib_data[range].max); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + ret = regmap_read(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_3, + &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP value: %d\n", + ret); + return -EAGAIN; + } + val = (val >> ARIZONA_HP_DACVAL_SHIFT) & ARIZONA_HP_DACVAL_MASK; + + if (info->hpdet_ip_version == 4) { + switch (arizona->type) { + case CS47L35: + case WM8285: + case WM1840: + ret = regmap_read(arizona->regmap, + ARIZONA_HP_DACVAL, + &val_down); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read HP DACVAL value: %d\n", + ret); + return -EAGAIN; + } + val_down = (val_down >> + ARIZONA_HP_DACVAL_DOWN_SHIFT) & + ARIZONA_HP_DACVAL_DOWN_MASK; + val = (val + val_down) / 2; + break; + default: + break; + } + } + val = arizona_hpdet_d_calibrate(info, val, range); + + break; + } + + if (info->arizona->pdata.hpdet_ext_res) { + + if (OHM_TO_HOHM(info->arizona->pdata.hpdet_ext_res) >= val) { + dev_dbg(arizona->dev, + "External resistor (%d) >= measurement (%d)\n", + info->arizona->pdata.hpdet_ext_res, + HOHM_TO_OHM(val)); + val = 0; /* treat as a short */ + } else { + dev_dbg(arizona->dev, + "Compensating for external %d ohm resistor\n", + info->arizona->pdata.hpdet_ext_res); + + val -= OHM_TO_HOHM(info->arizona->pdata.hpdet_ext_res); + } + } + +exit: + dev_dbg(arizona->dev, "HP impedance %d.%02d ohms\n", (val / 100), + (val % 100)); + return val; +} + +static const struct reg_default wm5110_low_impedance_patch[] = { + { 0x460, 0x0C21 }, + { 0x461, 0xA000 }, + { 0x462, 0x0C41 }, + { 0x463, 0x50E5 }, + { 0x464, 0x0C41 }, + { 0x465, 0x4040 }, + { 0x466, 0x0C41 }, + { 0x467, 0x3940 }, + { 0x468, 0x0C41 }, + { 0x469, 0x2418 }, + { 0x46A, 0x0846 }, + { 0x46B, 0x1990 }, + { 0x46C, 0x08C6 }, + { 0x46D, 0x1450 }, + { 0x46E, 0x04CE }, + { 0x46F, 0x1020 }, + { 0x470, 0x04CE }, + { 0x471, 0x0CD0 }, + { 0x472, 0x04CE }, + { 0x473, 0x0A30 }, + { 0x474, 0x044E }, + { 0x475, 0x0660 }, + { 0x476, 0x044E }, + { 0x477, 0x0510 }, + { 0x478, 0x04CE }, + { 0x479, 0x0400 }, + { 0x47A, 0x04CE }, + { 0x47B, 0x0330 }, + { 0x47C, 0x05DF }, + { 0x47D, 0x0001 }, + { 0x47E, 0x07FF }, + { 0x483, 0x0021 }, +}; + +static const struct reg_default wm5110_normal_impedance_patch[] = { + { 0x460, 0x0C40 }, + { 0x461, 0xA000 }, + { 0x462, 0x0C42 }, + { 0x463, 0x50E5 }, + { 0x464, 0x0842 }, + { 0x465, 0x4040 }, + { 0x466, 0x0842 }, + { 0x467, 0x3940 }, + { 0x468, 0x0846 }, + { 0x469, 0x2418 }, + { 0x46A, 0x0442 }, + { 0x46B, 0x1990 }, + { 0x46C, 0x04C6 }, + { 0x46D, 0x1450 }, + { 0x46E, 0x04CE }, + { 0x46F, 0x1020 }, + { 0x470, 0x04CE }, + { 0x471, 0x0CD0 }, + { 0x472, 0x04CE }, + { 0x473, 0x0A30 }, + { 0x474, 0x044E }, + { 0x475, 0x0660 }, + { 0x476, 0x044E }, + { 0x477, 0x0510 }, + { 0x478, 0x04CE }, + { 0x479, 0x0400 }, + { 0x47A, 0x04CE }, + { 0x47B, 0x0330 }, + { 0x47C, 0x05DF }, + { 0x47D, 0x0001 }, + { 0x47E, 0x07FF }, + { 0x483, 0x0021 }, +}; + +static const struct reg_default wm1814_low_impedance_patch[] = { + { 0x46C, 0x0C01 }, + { 0x46E, 0x0C01 }, + { 0x470, 0x0C01 }, +}; + +static const struct reg_default wm1814_normal_impedance_patch[] = { + { 0x46C, 0x0801 }, + { 0x46E, 0x0801 }, + { 0x470, 0x0801 }, +}; + +static const struct reg_default clearwater_low_impedance_patch[] = { + { 0x465, 0x4C6D }, + { 0x467, 0x3950 }, + { 0x469, 0x2D86 }, + { 0x46B, 0x1E6D }, + { 0x46D, 0x199A }, + { 0x46F, 0x1456 }, + { 0x483, 0x0826 }, +}; + +static const struct reg_default clearwater_normal_impedance_patch[] = { + { 0x465, 0x8A43 }, + { 0x467, 0x7259 }, + { 0x469, 0x65EA }, + { 0x46B, 0x50F4 }, + { 0x46D, 0x41CD }, + { 0x46F, 0x199A }, + { 0x483, 0x0023 }, +}; + +static const struct reg_default marley_low_impedance_patch[] = { + { 0x460, 0x0C40 }, + { 0x461, 0xCD1A }, + { 0x462, 0x0C40 }, + { 0x463, 0xB53B }, + { 0x464, 0x0C41 }, + { 0x465, 0x4826 }, + { 0x466, 0x0C41 }, + { 0x467, 0x2EDA }, + { 0x468, 0x0C41 }, + { 0x469, 0x203A }, + { 0x46A, 0x0841 }, + { 0x46B, 0x121F }, + { 0x46C, 0x0446 }, + { 0x46D, 0x0B6F }, + { 0x46E, 0x0446 }, + { 0x46F, 0x0818 }, + { 0x470, 0x04C6 }, + { 0x471, 0x05BB }, + { 0x472, 0x04C6 }, + { 0x473, 0x040F }, + { 0x474, 0x04CE }, + { 0x475, 0x0339 }, + { 0x476, 0x05DF }, + { 0x477, 0x028F }, + { 0x478, 0x05DF }, + { 0x479, 0x0209 }, + { 0x47A, 0x05DF }, + { 0x47B, 0x00CF }, + { 0x47C, 0x05DF }, + { 0x47D, 0x0001 }, + { 0x47E, 0x07FF }, +}; + +static const struct reg_default marley_normal_impedance_patch[] = { + { 0x460, 0x0C40 }, + { 0x461, 0xCD1A }, + { 0x462, 0x0C40 }, + { 0x463, 0xB53B }, + { 0x464, 0x0C40 }, + { 0x465, 0x7503 }, + { 0x466, 0x0C40 }, + { 0x467, 0x4A41 }, + { 0x468, 0x0041 }, + { 0x469, 0x3491 }, + { 0x46A, 0x0841 }, + { 0x46B, 0x1F50 }, + { 0x46C, 0x0446 }, + { 0x46D, 0x14ED }, + { 0x46E, 0x0446 }, + { 0x46F, 0x1455 }, + { 0x470, 0x04C6 }, + { 0x471, 0x1220 }, + { 0x472, 0x04C6 }, + { 0x473, 0x040F }, + { 0x474, 0x04CE }, + { 0x475, 0x0339 }, + { 0x476, 0x05DF }, + { 0x477, 0x028F }, + { 0x478, 0x05DF }, + { 0x479, 0x0209 }, + { 0x47A, 0x05DF }, + { 0x47B, 0x00CF }, + { 0x47C, 0x05DF }, + { 0x47D, 0x0001 }, + { 0x47E, 0x07FF }, +}; + +static const struct reg_default moon_low_impedance_patch[] = { + { 0x460, 0x0C21 }, + { 0x461, 0xB53C }, + { 0x462, 0x0C21 }, + { 0x463, 0xA186 }, + { 0x464, 0x0C21 }, + { 0x465, 0x8FF6 }, + { 0x466, 0x0C24 }, + { 0x467, 0x804E }, + { 0x468, 0x0C24 }, + { 0x469, 0x725A }, + { 0x46A, 0x0C24 }, + { 0x46B, 0x5AD5 }, + { 0x46C, 0x0C28 }, + { 0x46D, 0x50F4 }, + { 0x46E, 0x0C2C }, + { 0x46F, 0x4827 }, + { 0x470, 0x0C31 }, + { 0x471, 0x404E }, + { 0x472, 0x0020 }, + { 0x473, 0x3950 }, + { 0x474, 0x0028 }, + { 0x475, 0x3314 }, + { 0x476, 0x0030 }, + { 0x477, 0x2893 }, + { 0x478, 0x003F }, + { 0x479, 0x2429 }, + { 0x47A, 0x0830 }, + { 0x47B, 0x203A }, + { 0x47C, 0x0420 }, + { 0x47D, 0x1027 }, + { 0x47E, 0x0430 }, +}; + +static const struct reg_default moon_normal_impedance_patch[] = { + { 0x460, 0x0C21 }, + { 0x461, 0xB53C }, + { 0x462, 0x0C25 }, + { 0x463, 0xA186 }, + { 0x464, 0x0C26 }, + { 0x465, 0x8FF6 }, + { 0x466, 0x0C28 }, + { 0x467, 0x804E }, + { 0x468, 0x0C30 }, + { 0x469, 0x725A }, + { 0x46A, 0x0C30 }, + { 0x46B, 0x65EA }, + { 0x46C, 0x0028 }, + { 0x46D, 0x5AD5 }, + { 0x46E, 0x0028 }, + { 0x46F, 0x50F4 }, + { 0x470, 0x0030 }, + { 0x471, 0x4827 }, + { 0x472, 0x0030 }, + { 0x473, 0x404E }, + { 0x474, 0x003F }, + { 0x475, 0x3950 }, + { 0x476, 0x0830 }, + { 0x477, 0x3314 }, + { 0x478, 0x0420 }, + { 0x479, 0x2D86 }, + { 0x47A, 0x0428 }, + { 0x47B, 0x2893 }, + { 0x47C, 0x0428 }, + { 0x47D, 0x203A }, + { 0x47E, 0x0428 }, +}; + +static const struct reg_default moon_high_impedance_patch[] = { + { 0x460, 0x0C21 }, + { 0x461, 0xB53C }, + { 0x462, 0x0C26 }, + { 0x463, 0xA186 }, + { 0x464, 0x0C28 }, + { 0x465, 0x8FF6 }, + { 0x466, 0x0C2A }, + { 0x467, 0x804E }, + { 0x468, 0x0025 }, + { 0x469, 0x725A }, + { 0x46A, 0x0030 }, + { 0x46B, 0x65EA }, + { 0x46C, 0x0030 }, + { 0x46D, 0x5AD5 }, + { 0x46E, 0x003F }, + { 0x46F, 0x50F4 }, + { 0x470, 0x003F }, + { 0x471, 0x4827 }, + { 0x472, 0x0830 }, + { 0x473, 0x404E }, + { 0x474, 0x083F }, + { 0x475, 0x3950 }, + { 0x476, 0x0420 }, + { 0x477, 0x3314 }, + { 0x478, 0x0430 }, + { 0x479, 0x2D86 }, + { 0x47A, 0x0430 }, + { 0x47B, 0x2893 }, + { 0x47C, 0x0430 }, + { 0x47D, 0x203A }, + { 0x47E, 0x0430 }, +}; + +static const struct reg_default cs47l15_low_impedance_patch[] = { + { 0x460, 0x0C00 }, + { 0x461, 0xCB59 }, + { 0x462, 0x0C00 }, + { 0x463, 0x6037 }, + { 0x464, 0x0C01 }, + { 0x465, 0x2D86 }, + { 0x466, 0x0801 }, + { 0x467, 0x264E }, + { 0x468, 0x0801 }, + { 0x469, 0x1E6D }, + { 0x46A, 0x0802 }, + { 0x46B, 0x199A }, + { 0x46C, 0x0802 }, + { 0x46D, 0x1220 }, + { 0x46E, 0x0802 }, + { 0x46F, 0x0E65 }, + { 0x470, 0x0806 }, + { 0x471, 0x0A31 }, + { 0x472, 0x080E }, + { 0x473, 0x040F }, + { 0x474, 0x080E }, + { 0x475, 0x0339 }, + { 0x476, 0x080E }, + { 0x477, 0x028F }, + { 0x478, 0x080E }, + { 0x479, 0x0209 }, + { 0x47A, 0x080E }, + { 0x47B, 0x00CF }, + { 0x47C, 0x080E }, + { 0x47D, 0x0001 }, + { 0x47E, 0x081F }, +}; + +static const struct reg_default cs47l15_normal_impedance_patch[] = { + { 0x460, 0x0C00 }, + { 0x461, 0xCB59 }, + { 0x462, 0x0C00 }, + { 0x463, 0xB53C }, + { 0x464, 0x0C01 }, + { 0x465, 0x4827 }, + { 0x466, 0x0801 }, + { 0x467, 0x3950 }, + { 0x468, 0x0801 }, + { 0x469, 0x264E }, + { 0x46A, 0x0802 }, + { 0x46B, 0x1E6D }, + { 0x46C, 0x0802 }, + { 0x46D, 0x199A }, + { 0x46E, 0x0802 }, + { 0x46F, 0x1456 }, + { 0x470, 0x0806 }, + { 0x471, 0x1220 }, + { 0x472, 0x080E }, + { 0x473, 0x040F }, + { 0x474, 0x080E }, + { 0x475, 0x0339 }, + { 0x476, 0x080E }, + { 0x477, 0x028F }, + { 0x478, 0x080E }, + { 0x479, 0x0209 }, + { 0x47A, 0x080E }, + { 0x47B, 0x00CF }, + { 0x47C, 0x080E }, + { 0x47D, 0x0001 }, + { 0x47E, 0x081F }, +}; + +static const struct reg_default cs47l15_high_impedance_patch[] = { + { 0x460, 0x0C00 }, + { 0x461, 0xCB59 }, + { 0x462, 0x0C00 }, + { 0x463, 0xB53C }, + { 0x464, 0x0C01 }, + { 0x465, 0x6037 }, + { 0x466, 0x0801 }, + { 0x467, 0x4827 }, + { 0x468, 0x0801 }, + { 0x469, 0x3950 }, + { 0x46A, 0x0802 }, + { 0x46B, 0x264E }, + { 0x46C, 0x0802 }, + { 0x46D, 0x1E6D }, + { 0x46E, 0x0802 }, + { 0x46F, 0x199A }, + { 0x470, 0x0806 }, + { 0x471, 0x1220 }, + { 0x472, 0x080E }, + { 0x473, 0x040F }, + { 0x474, 0x080E }, + { 0x475, 0x0339 }, + { 0x476, 0x080E }, + { 0x477, 0x028F }, + { 0x478, 0x080E }, + { 0x479, 0x0209 }, + { 0x47A, 0x080E }, + { 0x47B, 0x00CF }, + { 0x47C, 0x080E }, + { 0x47D, 0x0001 }, + { 0x47E, 0x081F }, +}; + +static void arizona_hs_mic_control(struct arizona *arizona, int state) +{ + unsigned int addr = ARIZONA_ADC_DIGITAL_VOLUME_1L; + int val; + + if (!arizona->pdata.hs_mic) + return; + + addr += (arizona->pdata.hs_mic - 1) * 4; + + switch (state) { + case ARIZONA_MIC_MUTE: + dev_dbg(arizona->dev, "Mute headset mic: 0x%04x\n", + addr); + val = ARIZONA_MIC_MUTE; + break; + case ARIZONA_MIC_UNMUTE: + dev_dbg(arizona->dev, "Unmute headset mic: 0x%04x\n", + addr); + val = ARIZONA_MIC_UNMUTE; + break; + default: + dev_err(arizona->dev, + "Unknown headset mic control state: %d\n", state); + return; + } + + val <<= ARIZONA_IN1L_MUTE_SHIFT; + regmap_update_bits(arizona->regmap, addr, ARIZONA_IN1L_MUTE_MASK, val); +} + +static int arizona_wm5110_tune_headphone(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + const struct reg_default *patch; + int i, ret, size; + + if (reading <= arizona->pdata.hpdet_short_circuit_imp) { + /* Headphones are always off here so just mark them */ + dev_warn(arizona->dev, "Possible HP short, disabling\n"); + return 0; + } else if (reading <= HP_LOW_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_LOW_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_LOW_IMPEDANCE; + + regmap_update_bits(arizona->regmap, + ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_MASK, 0); + + patch = wm5110_low_impedance_patch; + size = ARRAY_SIZE(wm5110_low_impedance_patch); + } else { + if (info->hp_imp_level == HP_NORMAL_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_NORMAL_IMPEDANCE; + + regmap_update_bits(arizona->regmap, + ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_MASK, + ARIZONA_HP1_SC_ENA_MASK); + + patch = wm5110_normal_impedance_patch; + size = ARRAY_SIZE(wm5110_normal_impedance_patch); + } + + for (i = 0; i < size; ++i) { + ret = regmap_write(arizona->regmap, + patch[i].reg, patch[i].def); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to write headphone patch: %x <= %x\n", + patch[i].reg, patch[i].def); + } + + return 0; +} + +static int arizona_wm1814_tune_headphone(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + const struct reg_default *patch; + int i, ret, size; + + if (reading <= arizona->pdata.hpdet_short_circuit_imp) { + /* Headphones are always off here so just mark them */ + dev_warn(arizona->dev, "Possible HP short, disabling\n"); + return 0; + } else if (reading < 15) { + if (info->hp_imp_level == HP_LOW_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_LOW_IMPEDANCE; + + patch = wm1814_low_impedance_patch; + size = ARRAY_SIZE(wm1814_low_impedance_patch); + } else { + if (info->hp_imp_level == HP_NORMAL_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_NORMAL_IMPEDANCE; + + patch = wm1814_normal_impedance_patch; + size = ARRAY_SIZE(wm1814_normal_impedance_patch); + } + + for (i = 0; i < size; ++i) { + ret = regmap_write(arizona->regmap, + patch[i].reg, patch[i].def); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to write headphone patch: %x <= %x\n", + patch[i].reg, patch[i].def); + } + + return 0; +} + +static int arizona_clearwater_tune_headphone(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + const struct reg_default *patch; + int i, ret, size; + + if (reading <= arizona->pdata.hpdet_short_circuit_imp) { + /* Headphones are always off here so just mark them */ + dev_warn(arizona->dev, "Possible HP short, disabling\n"); + return 0; + } else if (reading <= HP_LOW_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_LOW_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_LOW_IMPEDANCE; + + patch = clearwater_low_impedance_patch; + size = ARRAY_SIZE(clearwater_low_impedance_patch); + } else { + if (info->hp_imp_level == HP_NORMAL_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_NORMAL_IMPEDANCE; + + patch = clearwater_normal_impedance_patch; + size = ARRAY_SIZE(clearwater_normal_impedance_patch); + } + + for (i = 0; i < size; ++i) { + ret = regmap_write(arizona->regmap, + patch[i].reg, patch[i].def); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to write headphone patch: %x <= %x\n", + patch[i].reg, patch[i].def); + } + + return 0; +} + +static int arizona_marley_tune_headphone(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + const struct reg_default *patch; + int i, ret, size; + + if (reading <= arizona->pdata.hpdet_short_circuit_imp) { + /* Headphones are always off here so just mark them */ + dev_warn(arizona->dev, "Possible HP short, disabling\n"); + return 0; + } else if (reading <= HP_LOW_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_LOW_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_LOW_IMPEDANCE; + + patch = marley_low_impedance_patch; + size = ARRAY_SIZE(marley_low_impedance_patch); + } else { + if (info->hp_imp_level == HP_NORMAL_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_NORMAL_IMPEDANCE; + + patch = marley_normal_impedance_patch; + size = ARRAY_SIZE(marley_normal_impedance_patch); + } + + for (i = 0; i < size; ++i) { + ret = regmap_write(arizona->regmap, + patch[i].reg, patch[i].def); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to write headphone patch: %x <= %x\n", + patch[i].reg, patch[i].def); + } + + return 0; +} + +static int arizona_moon_tune_headphone(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + const struct reg_default *patch; + int i, ret, size; + + if (reading <= arizona->pdata.hpdet_short_circuit_imp) { + /* Headphones are always off here so just mark them */ + dev_warn(arizona->dev, "Possible HP short, disabling\n"); + return 0; + } else if (reading <= MOON_HP_LOW_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_LOW_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_LOW_IMPEDANCE; + + patch = moon_low_impedance_patch; + size = ARRAY_SIZE(moon_low_impedance_patch); + } else if (reading <= MOON_HP_MEDIUM_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_NORMAL_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_NORMAL_IMPEDANCE; + + patch = moon_normal_impedance_patch; + size = ARRAY_SIZE(moon_normal_impedance_patch); + } else { + if (info->hp_imp_level == HP_HIGH_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_HIGH_IMPEDANCE; + + patch = moon_high_impedance_patch; + size = ARRAY_SIZE(moon_high_impedance_patch); + } + + for (i = 0; i < size; ++i) { + ret = regmap_write(arizona->regmap, + patch[i].reg, patch[i].def); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to write headphone patch: %x <= %x\n", + patch[i].reg, patch[i].def); + } + + return 0; +} + +static int arizona_cs47l15_tune_headphone(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + const struct reg_default *patch; + int i, ret, size; + + if (reading <= arizona->pdata.hpdet_short_circuit_imp) { + /* Headphones are always off here so just mark them */ + dev_warn(arizona->dev, "Possible HP short, disabling\n"); + return 0; + } else if (reading <= CS47L15_HP_LOW_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_LOW_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_LOW_IMPEDANCE; + + patch = cs47l15_low_impedance_patch; + size = ARRAY_SIZE(cs47l15_low_impedance_patch); + } else if (reading <= CS47L15_HP_MEDIUM_IMPEDANCE_LIMIT) { + if (info->hp_imp_level == HP_NORMAL_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_NORMAL_IMPEDANCE; + + patch = cs47l15_normal_impedance_patch; + size = ARRAY_SIZE(cs47l15_normal_impedance_patch); + } else { + if (info->hp_imp_level == HP_HIGH_IMPEDANCE) + return 0; + + info->hp_imp_level = HP_HIGH_IMPEDANCE; + + patch = cs47l15_high_impedance_patch; + size = ARRAY_SIZE(cs47l15_high_impedance_patch); + } + + for (i = 0; i < size; ++i) { + ret = regmap_write(arizona->regmap, + patch[i].reg, patch[i].def); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to write headphone patch: %x <= %x\n", + patch[i].reg, patch[i].def); + } + + return 0; +} + +void arizona_set_headphone_imp(struct arizona_extcon_info *info, int imp) +{ + struct arizona *arizona = info->arizona; + + arizona->hp_impedance_x100 = imp; + + if (arizona->pdata.hpdet_cb) + arizona->pdata.hpdet_cb(HOHM_TO_OHM(imp)); + + switch (arizona->type) { + case WM5110: + arizona_wm5110_tune_headphone(info, HOHM_TO_OHM(imp)); + break; + case WM1814: + arizona_wm1814_tune_headphone(info, HOHM_TO_OHM(imp)); + break; + case WM8285: + case WM1840: + arizona_clearwater_tune_headphone(info, HOHM_TO_OHM(imp)); + break; + case CS47L35: + arizona_marley_tune_headphone(info, HOHM_TO_OHM(imp)); + break; + case CS47L90: + case CS47L91: + arizona_moon_tune_headphone(info, HOHM_TO_OHM(imp)); + break; + case CS47L15: + arizona_cs47l15_tune_headphone(info, HOHM_TO_OHM(imp)); + break; + default: + break; + } +} +EXPORT_SYMBOL_GPL(arizona_set_headphone_imp); + +static void arizona_hpdet_start_micd(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + + regmap_update_bits(arizona->regmap, CLEARWATER_IRQ1_MASK_6, + CLEARWATER_IM_MICDET_EINT1, + CLEARWATER_IM_MICDET_EINT1); + + regmap_update_bits(arizona->regmap, MOON_MIC_DETECT_0, + MOON_MICD1_ADC_MODE_MASK, + MOON_MICD1_ADC_MODE_MASK); + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK | + ARIZONA_MICD_RATE_MASK | + ARIZONA_MICD_DBTIME_MASK | + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA); +} + +static void arizona_hpdet_stop_micd(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int start_time = 1, dbtime = 1, rate = 1; + + if (arizona->pdata.micd_bias_start_time) + start_time = arizona->pdata.micd_bias_start_time; + + if (arizona->pdata.micd_rate) + rate = arizona->pdata.micd_rate; + + if (arizona->pdata.micd_dbtime) + dbtime = arizona->pdata.micd_dbtime; + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK | + ARIZONA_MICD_RATE_MASK | + ARIZONA_MICD_DBTIME_MASK | + ARIZONA_MICD_ENA, + start_time << ARIZONA_MICD_BIAS_STARTTIME_SHIFT | + rate << ARIZONA_MICD_RATE_SHIFT | + dbtime << ARIZONA_MICD_DBTIME_SHIFT); + + udelay(100); + + /* Clear any spurious IRQs that have happened */ + regmap_write(arizona->regmap, CLEARWATER_IRQ1_STATUS_6, + CLEARWATER_MICDET_EINT1); + regmap_update_bits(arizona->regmap, CLEARWATER_IRQ1_MASK_6, + CLEARWATER_IM_MICDET_EINT1, 0); +} + +static void arizona_hpdet_reset(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int init_range; + + switch (arizona->type) { + case CS47L15: + /* all measurements are offset by 33 ohms + * so can never be in range 0 + */ + init_range = 1 << ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + break; + default: + init_range = 0; + break; + } + + /* Stop HPDET and reset to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | + ARIZONA_HP_POLL, init_range); +} + +int arizona_hpdet_start(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + unsigned int hpd_sense, hpd_clamp, val, hpd_gnd; + + dev_dbg(arizona->dev, "Starting HPDET\n"); + + /* If we specified to assume a fixed impedance skip HPDET */ + if (info->arizona->pdata.fixed_hpdet_imp) { + int imp = info->arizona->pdata.fixed_hpdet_imp; + + arizona_set_headphone_imp(info, OHM_TO_HOHM(imp)); + + ret = -EEXIST; + goto skip; + } + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get_sync(info->dev); + + switch (info->accdet_ip) { + case 0: + arizona_extcon_hp_clamp(info, true); + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, + info->state->mode); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode (%d): %d\n", + info->state->mode, ret); + goto err; + } + break; + default: + if (info->state->mode == ARIZONA_ACCDET_MODE_HPL) { + hpd_clamp = arizona->pdata.hpd_l_pins.clamp_pin; + hpd_sense = arizona->pdata.hpd_l_pins.impd_pin; + } else { + hpd_clamp = arizona->pdata.hpd_r_pins.clamp_pin; + hpd_sense = arizona->pdata.hpd_r_pins.impd_pin; + } + + hpd_gnd = info->micd_modes[info->micd_mode].gnd; + + val = (hpd_sense << MOON_HPD_SENSE_SEL_SHIFT) | + (hpd_clamp << MOON_HPD_OUT_SEL_SHIFT) | + (hpd_sense << MOON_HPD_FRC_SEL_SHIFT) | + (hpd_gnd << MOON_HPD_GND_SEL_SHIFT); + ret = regmap_update_bits(arizona->regmap, + MOON_HEADPHONE_DETECT_0, + MOON_HPD_GND_SEL_MASK | + MOON_HPD_SENSE_SEL_MASK | + MOON_HPD_FRC_SEL_MASK | + MOON_HPD_OUT_SEL_MASK, + val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET sense: %d\n", + ret); + goto err; + } + arizona_extcon_hp_clamp(info, true); + + arizona_hpdet_start_micd(info); + break; + } + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, "Can't start HPDET measurement: %d\n", + ret); + goto err; + } + + return 0; + +err: + arizona_extcon_hp_clamp(info, false); + + pm_runtime_put_autosuspend(info->dev); + +skip: + return ret; +} +EXPORT_SYMBOL_GPL(arizona_hpdet_start); + +void arizona_hpdet_restart(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + arizona_hpdet_reset(info); + + switch (info->accdet_ip) { + case 0: + break; + default: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA); + break; + } + + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); +} +EXPORT_SYMBOL_GPL(arizona_hpdet_restart); + +void arizona_hpdet_stop(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + + /* Reset back to starting range */ + arizona_hpdet_stop_micd(info); + arizona_hpdet_reset(info); + + switch (info->accdet_ip) { + case 0: + /* Reset to default mode */ + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, 0); + break; + default: + break; + } + + arizona_extcon_hp_clamp(info, false); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +} +EXPORT_SYMBOL_GPL(arizona_hpdet_stop); + +int arizona_hpdet_reading(struct arizona_extcon_info *info, int val) +{ + if (val < 0) + return val; + + arizona_set_headphone_imp(info, val); + + if (info->mic) { + arizona_extcon_report(info, BIT_HEADSET); + arizona_jds_set_state(info, &arizona_micd_button); + } else { + arizona_extcon_report(info, BIT_HEADSET_NO_MIC); + arizona_jds_set_state(info, NULL); + } + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_hpdet_reading); + +int arizona_micd_start(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + unsigned int micd_mode; + + /* Microphone detection can't use idle mode */ + pm_runtime_get_sync(info->dev); + + if (info->micd_clamp) { + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + break; + default: + dev_dbg(arizona->dev, "Disabling MICD_OVD\n"); + regmap_update_bits(arizona->regmap, + CLEARWATER_MICD_CLAMP_CONTROL, + CLEARWATER_MICD_CLAMP_OVD_MASK, 0); + break; + } + } + + ret = regulator_enable(info->micvdd); + if (ret != 0) { + dev_err(arizona->dev, "Failed to enable MICVDD: %d\n", + ret); + } + + if (info->micd_reva) { + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + regmap_write(arizona->regmap, 0x294, 0); + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + } + + switch (info->accdet_ip) { + case 0: + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, info->state->mode); + break; + default: + if (info->state->mode == ARIZONA_ACCDET_MODE_ADC) + micd_mode = MOON_MICD1_ADC_MODE_MASK; + else + micd_mode = 0; + + regmap_update_bits(arizona->regmap, MOON_MIC_DETECT_0, + MOON_MICD1_ADC_MODE_MASK, micd_mode); + break; + } + + arizona_extcon_set_micd_bias(info, + info->micd_modes[info->micd_mode].bias, true); + + arizona_extcon_pulse_micbias(info); + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA); + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_micd_start); + +void arizona_micd_stop(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + int ret; + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + + dev_dbg(arizona->dev, "disabling %s\n", widget); + + mutex_lock(&dapm->card->dapm_mutex); + + ret = snd_soc_dapm_disable_pin(dapm, widget); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + widget, ret); + + mutex_unlock(&dapm->card->dapm_mutex); + + snd_soc_dapm_sync(dapm); + + arizona_extcon_set_micd_bias(info, + info->micd_modes[info->micd_mode].bias, false); + + if (info->micd_reva) { + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + regmap_write(arizona->regmap, 0x294, 2); + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + } + + switch (info->accdet_ip) { + case 0: + /* Reset to default mode */ + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, 0); + break; + default: + break; + } + + regulator_disable(info->micvdd); + + if (info->micd_clamp) { + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + break; + default: + dev_dbg(arizona->dev, "Enabling MICD_OVD\n"); + regmap_update_bits(arizona->regmap, + CLEARWATER_MICD_CLAMP_CONTROL, + CLEARWATER_MICD_CLAMP_OVD_MASK, + CLEARWATER_MICD_CLAMP_OVD); + break; + } + } + + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); +} +EXPORT_SYMBOL_GPL(arizona_micd_stop); + +static void arizona_micd_restart(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA); +} + +static int arizona_micd_button_debounce(struct arizona_extcon_info *info, + int val) +{ + struct arizona *arizona = info->arizona; + int debounce_lim = arizona->pdata.micd_manual_debounce; + + if (debounce_lim) { + if (info->micd_debounce != val) + info->micd_count = 0; + + info->micd_debounce = val; + info->micd_count++; + + if (info->micd_count == debounce_lim) { + info->micd_count = 0; + if (val == info->micd_res_old) + return 0; + + info->micd_res_old = val; + } else { + dev_dbg(arizona->dev, "Software debounce: %d,%x\n", + info->micd_count, val); + arizona_micd_restart(info); + return -EAGAIN; + } + } + + return 0; +} + +static int arizona_micd_button_process(struct arizona_extcon_info *info, + int val) +{ + struct arizona *arizona = info->arizona; + int i, key; + + if (val < MICROPHONE_MIN_OHM) { + dev_dbg(arizona->dev, "Mic button detected\n"); + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + + for (i = 0; i < info->num_micd_ranges; i++) { + if (val <= info->micd_ranges[i].max) { + key = info->micd_ranges[i].key; + input_report_key(info->input, key, 1); + input_sync(info->input); + break; + } + } + + if (i == info->num_micd_ranges) + dev_warn(arizona->dev, + "Button level %u out of range\n", val); + } else { + dev_dbg(arizona->dev, "Mic button released\n"); + arizona_hs_mic_control(arizona, ARIZONA_MIC_UNMUTE); + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + arizona_extcon_pulse_micbias(info); + } + + return 0; +} + +int arizona_micd_button_reading(struct arizona_extcon_info *info, + int val) +{ + int ret; + + if (val < 0) + return val; + + ret = arizona_micd_button_debounce(info, val); + if (ret < 0) + return ret; + + return arizona_micd_button_process(info, val); +} +EXPORT_SYMBOL_GPL(arizona_micd_button_reading); + + +int arizona_micd_mic_start(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + info->detecting = true; + + ret = regulator_allow_bypass(info->micvdd, false); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to regulate MICVDD: %d\n", + ret); + } + + return arizona_micd_start(info); +} +EXPORT_SYMBOL_GPL(arizona_micd_mic_start); + +void arizona_micd_mic_stop(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + arizona_micd_stop(info); + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + info->detecting = false; +} +EXPORT_SYMBOL_GPL(arizona_micd_mic_stop); + +int arizona_micd_mic_reading(struct arizona_extcon_info *info, int val) +{ + struct arizona *arizona = info->arizona; + int ret; + + if (val < 0) + return val; + + /* Due to jack detect this should never happen */ + if (val > MICROPHONE_MAX_OHM) { + dev_warn(arizona->dev, "Detected open circuit\n"); + info->mic = arizona->pdata.micd_open_circuit_declare; + goto done; + } + + /* If we got a high impedence we should have a headset, report it. */ + if (val >= MICROPHONE_MIN_OHM) { + dev_dbg(arizona->dev, "Detected headset\n"); + info->mic = true; + + arizona_hs_mic_control(arizona, ARIZONA_MIC_UNMUTE); + + goto done; + } + + /* If we detected a lower impedence during initial startup + * then we probably have the wrong polarity, flip it. Don't + * do this for the lowest impedences to speed up detection of + * plain headphones. If both polarities report a low + * impedence then give up and report headphones. + */ + if (val > info->micd_ranges[0].max && + info->micd_num_modes > 1) { + if (info->jack_flips >= info->micd_num_modes * 10) { + dev_dbg(arizona->dev, "Detected HP/line\n"); + goto done; + } else { + arizona_extcon_change_mode(info); + + info->jack_flips++; + + return -EAGAIN; + } + } + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. + */ + dev_dbg(arizona->dev, "Headphone detected\n"); + +done: + pm_runtime_mark_last_busy(info->dev); + + if (arizona->pdata.hpdet_channel) + ret = arizona_jds_set_state(info, &arizona_hpdet_right); + else + ret = arizona_jds_set_state(info, &arizona_hpdet_left); + if (ret < 0) { + if (info->mic) + arizona_extcon_report(info, BIT_HEADSET); + else + arizona_extcon_report(info, BIT_HEADSET_NO_MIC); + } + + if (arizona->pdata.micd_cb) + arizona->pdata.micd_cb(info->mic); + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_micd_mic_reading); + +int arizona_micd_mic_timeout_ms(struct arizona_extcon_info *info) +{ + if (info->arizona->pdata.micd_timeout) + return info->arizona->pdata.micd_timeout; + else + return DEFAULT_MICD_TIMEOUT; +} +EXPORT_SYMBOL_GPL(arizona_micd_mic_timeout_ms); + +void arizona_micd_mic_timeout(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + dev_dbg(info->arizona->dev, "MICD timed out, reporting HP\n"); + + if (arizona->pdata.hpdet_channel) + ret = arizona_jds_set_state(info, &arizona_hpdet_right); + else + ret = arizona_jds_set_state(info, &arizona_hpdet_left); + if (ret < 0) + arizona_extcon_report(info, BIT_HEADSET_NO_MIC); +} +EXPORT_SYMBOL_GPL(arizona_micd_mic_timeout); + +static int arizona_hpdet_acc_id_reading(struct arizona_extcon_info *info, + int reading) +{ + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + + if (reading < 0) + return reading; + + reading = HOHM_TO_OHM(reading); /* Extra precision not required. */ + + /* + * When we're using HPDET for accessory identification we need + * to take multiple measurements, step through them in sequence. + */ + info->hpdet_res[info->num_hpdet_res++] = reading; + + /* Only check the mic directly if we didn't already ID it */ + if (id_gpio && info->num_hpdet_res == 1) { + dev_dbg(arizona->dev, "Measuring mic\n"); + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | + ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + ARIZONA_ACCDET_MODE_HPR); + gpio_set_value_cansleep(id_gpio, 1); + + return -EAGAIN; + } + + /* OK, got both. Now, compare... */ + dev_dbg(arizona->dev, "HPDET measured %d %d\n", + info->hpdet_res[0], info->hpdet_res[1]); + + /* Take the headphone impedance for the main report */ + reading = info->hpdet_res[0]; + + /* Sometimes we get false readings due to slow insert */ + if (reading >= HOHM_TO_OHM(ARIZONA_HPDET_MAX) && !info->hpdet_retried) { + dev_dbg(arizona->dev, "Retrying high impedance\n"); + + info->num_hpdet_res = 0; + info->hpdet_retried = true; + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | + ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + ARIZONA_ACCDET_MODE_HPL); + + return -EAGAIN; + } + + if (!id_gpio || info->hpdet_res[1] > 50) { + dev_dbg(arizona->dev, "Detected mic\n"); + + arizona_jds_set_state(info, &arizona_micd_microphone); + } else { + dev_dbg(arizona->dev, "Detected headphone\n"); + + arizona_extcon_report(info, BIT_HEADSET_NO_MIC); + + arizona_jds_set_state(info, NULL); + } + + return 0; +} + +static int arizona_hpdet_acc_id_start(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int hp_reading = 32; + int ret; + + switch (info->accdet_ip) { + case 0: + break; + default: + return -EINVAL; + } + + dev_dbg(arizona->dev, "Starting identification via HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get_sync(info->dev); + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + ARIZONA_ACCDET_MODE_HPL); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDETL mode: %d\n", ret); + goto err; + } + + if (arizona->pdata.hpdet_acc_id_line) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, + "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + } else { + /** + * If we are not identifying line outputs fake the first + * reading at 32 ohms + */ + arizona_hpdet_acc_id_reading(info, OHM_TO_HOHM(hp_reading)); + } + + return 0; + +err: + arizona_extcon_hp_clamp(info, false); + + pm_runtime_put_autosuspend(info->dev); + /* Just report headphone */ + arizona_extcon_report(info, BIT_HEADSET_NO_MIC); + + return ret; +} + +static void arizona_hpdet_acc_id_stop(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + + /* Make sure everything is reset back to the real polarity */ + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, + info->micd_modes[0].src); + + if (id_gpio) + gpio_set_value_cansleep(id_gpio, 0); + + /* Rest of the clean is identical to standard hpdet */ + arizona_hpdet_stop(info); +} + +static int arizona_jack_present(struct arizona_extcon_info *info, + unsigned int *jack_val) +{ + struct arizona *arizona = info->arizona; + unsigned int reg, val = 0; + unsigned int mask, present; + int ret; + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + if (arizona->pdata.jd_gpio5) { + mask = ARIZONA_MICD_CLAMP_STS; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + reg = ARIZONA_AOD_IRQ_RAW_STATUS; + break; + default: + if (arizona->pdata.jd_gpio5) { + mask = CLEARWATER_MICD_CLAMP_RISE_STS1; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + reg = CLEARWATER_IRQ1_RAW_STATUS_7; + break; + } + + ret = regmap_read(arizona->regmap, reg, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read jackdet status: %d\n", + ret); + return ret; + } + + val &= mask; + + if (jack_val) + *jack_val = val; + + if (val == present) + return 1; + else + return 0; +} + +static irqreturn_t arizona_hpdet_handler(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int ret; + + arizona_jds_cancel_timeout(info); + + mutex_lock(&info->lock); + + switch (arizona_jds_get_mode(info)) { + case ARIZONA_ACCDET_MODE_HPL: + case ARIZONA_ACCDET_MODE_HPR: + case ARIZONA_ACCDET_MODE_HPM: + /* Fall through to spurious if no jack present */ + if (arizona_jack_present(info, NULL) > 0) + break; + default: + dev_warn(arizona->dev, "Spurious HPDET IRQ\n"); + arizona_jds_start_timeout(info); + mutex_unlock(&info->lock); + return IRQ_NONE; + } + + ret = arizona_hpdet_read(info); + if (ret == -EAGAIN) + goto out; + + arizona_jds_reading(info, ret); + +out: + arizona_jds_start_timeout(info); + + pm_runtime_mark_last_busy(info->dev); + + mutex_unlock(&info->lock); + + return IRQ_HANDLED; +} + +static void arizona_micd_handler(struct work_struct *work) +{ + struct arizona_extcon_info *info = + container_of(work, + struct arizona_extcon_info, + micd_detect_work.work); + struct arizona *arizona = info->arizona; + int mode; + int ret; + + arizona_jds_cancel_timeout(info); + + mutex_lock(&info->lock); + + /* Must check that we are in a micd state before accessing + * any codec registers + */ + mode = arizona_jds_get_mode(info); + switch (mode) { + case ARIZONA_ACCDET_MODE_MIC: + case ARIZONA_ACCDET_MODE_ADC: + break; + default: + goto spurious; + } + + if (arizona_jack_present(info, NULL) <= 0) + goto spurious; + + arizona_hs_mic_control(arizona, ARIZONA_MIC_MUTE); + + switch (mode) { + case ARIZONA_ACCDET_MODE_MIC: + ret = arizona_micd_read(info); + break; + case ARIZONA_ACCDET_MODE_ADC: + ret = arizona_micd_adc_read(info); + break; + default: /* we can't get here but compiler still warns */ + ret = 0; + break; + } + + if (ret == -EAGAIN) + goto out; + + dev_dbg(arizona->dev, "Mic impedance %d ohms\n", ret); + + arizona_jds_reading(info, ret); + +out: + arizona_jds_start_timeout(info); + + pm_runtime_mark_last_busy(info->dev); + + mutex_unlock(&info->lock); + + return; + +spurious: + dev_warn(arizona->dev, "Spurious MICDET IRQ\n"); + arizona_jds_start_timeout(info); + mutex_unlock(&info->lock); +} + +static void arizona_micd_input_clear(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_clear_work.work); + struct arizona *arizona = info->arizona; + + arizona_florida_clear_input(arizona); + + mutex_lock(&info->lock); + if (info->first_clear) { + schedule_delayed_work(&info->micd_clear_work, + msecs_to_jiffies(900)); + info->first_clear = false; + } + mutex_unlock(&info->lock); +} + +static irqreturn_t arizona_micdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int debounce = arizona->pdata.micd_detect_debounce; + + cancel_delayed_work_sync(&info->micd_detect_work); + cancel_delayed_work_sync(&info->micd_clear_work); + + mutex_lock(&info->lock); + + if (!info->detecting) + debounce = 0; + + switch (arizona->type) { + case WM8280: + case WM5110: + if (arizona->rev < 6) { + info->first_clear = true; + schedule_delayed_work(&info->micd_clear_work, + msecs_to_jiffies(80)); + } + break; + default: + break; + } + + mutex_unlock(&info->lock); + + /* Defer to the workqueue to ensure serialization + * and prevent race conditions if an IRQ occurs while + * running the delayed work + */ + schedule_delayed_work(&info->micd_detect_work, + msecs_to_jiffies(debounce)); + + return IRQ_HANDLED; +} + +const struct arizona_jd_state arizona_hpdet_left = { + .mode = ARIZONA_ACCDET_MODE_HPL, + .start = arizona_hpdet_start, + .reading = arizona_hpdet_reading, + .stop = arizona_hpdet_stop, +}; +EXPORT_SYMBOL_GPL(arizona_hpdet_left); + +const struct arizona_jd_state arizona_hpdet_right = { + .mode = ARIZONA_ACCDET_MODE_HPR, + .start = arizona_hpdet_start, + .reading = arizona_hpdet_reading, + .stop = arizona_hpdet_stop, +}; +EXPORT_SYMBOL_GPL(arizona_hpdet_right); + +const struct arizona_jd_state arizona_micd_button = { + .mode = ARIZONA_ACCDET_MODE_MIC, + .start = arizona_micd_start, + .reading = arizona_micd_button_reading, + .stop = arizona_micd_stop, +}; +EXPORT_SYMBOL_GPL(arizona_micd_button); + +const struct arizona_jd_state arizona_micd_adc_mic = { + .mode = ARIZONA_ACCDET_MODE_ADC, + .start = arizona_micd_mic_start, + .restart = arizona_micd_restart, + .reading = arizona_micd_mic_reading, + .stop = arizona_micd_mic_stop, + + .timeout_ms = arizona_micd_mic_timeout_ms, + .timeout = arizona_micd_mic_timeout, +}; +EXPORT_SYMBOL_GPL(arizona_micd_adc_mic); + +const struct arizona_jd_state arizona_micd_microphone = { + .mode = ARIZONA_ACCDET_MODE_MIC, + .start = arizona_micd_mic_start, + .reading = arizona_micd_mic_reading, + .stop = arizona_micd_mic_stop, + + .timeout_ms = arizona_micd_mic_timeout_ms, + .timeout = arizona_micd_mic_timeout, +}; +EXPORT_SYMBOL_GPL(arizona_micd_microphone); + +const struct arizona_jd_state arizona_hpdet_acc_id = { + .mode = ARIZONA_ACCDET_MODE_HPL, + .start = arizona_hpdet_acc_id_start, + .restart = arizona_hpdet_restart, + .reading = arizona_hpdet_acc_id_reading, + .stop = arizona_hpdet_acc_id_stop, +}; +EXPORT_SYMBOL_GPL(arizona_hpdet_acc_id); + +static void arizona_hpdet_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + hpdet_work.work); + + mutex_lock(&info->lock); + arizona_jds_set_state(info, &arizona_hpdet_acc_id); + mutex_unlock(&info->lock); +} + +static irqreturn_t arizona_jackdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + unsigned int reg, val, mask; + bool cancelled_hp, cancelled_state; + int i, present; + + cancelled_hp = cancel_delayed_work_sync(&info->hpdet_work); + cancelled_state = arizona_jds_cancel_timeout(info); + + pm_runtime_get_sync(info->dev); + + mutex_lock(&info->lock); + + val = 0; + present = arizona_jack_present(info, &val); + if (present < 0) { + mutex_unlock(&info->lock); + pm_runtime_put_autosuspend(info->dev); + return IRQ_NONE; + } + + if (val == info->last_jackdet) { + dev_dbg(arizona->dev, "Suppressing duplicate JACKDET\n"); + if (cancelled_hp) + schedule_delayed_work(&info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + + if (cancelled_state) + arizona_jds_start_timeout(info); + + goto out; + } + info->last_jackdet = val; + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + reg = ARIZONA_JACK_DETECT_DEBOUNCE; + mask = ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB; + break; + default: + reg = CLEARWATER_INTERRUPT_DEBOUNCE_7; + mask = CLEARWATER_MICD_CLAMP_DB | CLEARWATER_JD1_DB; + if (arizona->pdata.jd_gpio5) + mask |= CLEARWATER_JD2_DB; + break; + } + + if (present) { + dev_dbg(arizona->dev, "Detected jack\n"); + + if (arizona->pdata.jd_wake_time) + __pm_wakeup_event(&info->detection_wake_lock, + arizona->pdata.jd_wake_time); + + if (!arizona->pdata.hpdet_acc_id) { + info->mic = false; + info->jack_flips = 0; + + if (arizona->pdata.init_mic_delay) + msleep(arizona->pdata.init_mic_delay); + + if (arizona->pdata.custom_jd) + arizona_jds_set_state(info, + arizona->pdata.custom_jd); + else if (arizona->pdata.micd_software_compare) + arizona_jds_set_state(info, + &arizona_micd_adc_mic); + else + arizona_jds_set_state(info, + &arizona_micd_microphone); + + arizona_jds_start_timeout(info); + } else { + schedule_delayed_work(&info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + } + + regmap_update_bits(arizona->regmap, reg, mask, 0); + } else { + dev_dbg(arizona->dev, "Detected jack removal\n"); + + arizona_hs_mic_control(arizona, ARIZONA_MIC_MUTE); + + info->num_hpdet_res = 0; + for (i = 0; i < ARRAY_SIZE(info->hpdet_res); i++) + info->hpdet_res[i] = 0; + info->mic = false; + info->hpdet_retried = false; + info->micd_res_old = 0; + info->micd_debounce = 0; + info->micd_count = 0; + arizona_jds_set_state(info, NULL); + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + + arizona_extcon_report(info, BIT_NO_HEADSET); + + regmap_update_bits(arizona->regmap, reg, mask, mask); + + arizona_set_headphone_imp(info, ARIZONA_HP_Z_OPEN); + + if (arizona->pdata.micd_cb) + arizona->pdata.micd_cb(false); + } + +out: + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + /* Clear trig_sts to make sure DCVDD is not forced up */ + regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, + ARIZONA_MICD_CLAMP_FALL_TRIG_STS | + ARIZONA_MICD_CLAMP_RISE_TRIG_STS | + ARIZONA_JD1_FALL_TRIG_STS | + ARIZONA_JD1_RISE_TRIG_STS); + break; + default: + break; + } + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + return IRQ_HANDLED; +} + +/* Map a level onto a slot in the register bank */ +static void arizona_micd_set_level(struct arizona *arizona, int index, + unsigned int level) +{ + int reg; + unsigned int mask; + + reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2); + + if (!(index % 2)) { + mask = 0x3f00; + level <<= 8; + } else { + mask = 0x3f; + } + + /* Program the level itself */ + regmap_update_bits(arizona->regmap, reg, mask, level); +} + +static int arizona_add_micd_levels(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int i, j; + int ret =0; + + /* Disable all buttons by default */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + ARIZONA_MICD_LVL_SEL_MASK, 0x81); + + /* Set up all the buttons the user specified */ + for (i = 0; i < info->num_micd_ranges; i++) { + for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++) + if (arizona_micd_levels[j] >= info->micd_ranges[i].max) + break; + + if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) { + dev_err(arizona->dev, "Unsupported MICD level %d\n", + info->micd_ranges[i].max); + ret = -EINVAL; + goto err_input; + } + + dev_dbg(arizona->dev, "%d ohms for MICD threshold %d\n", + arizona_micd_levels[j], i); + + arizona_micd_set_level(arizona, i, j); + if (info->micd_ranges[i].key > 0) + input_set_capability(info->input, EV_KEY, + info->micd_ranges[i].key); + + /* Enable reporting of that range */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + 1 << i, 1 << i); + } + + /* Set all the remaining keys to a maximum */ + for (; i < ARIZONA_MAX_MICD_RANGE; i++) + arizona_micd_set_level(arizona, i, 0x3f); + +err_input: + return ret; +} + +#ifdef CONFIG_OF +static int arizona_extcon_of_get_pdata(struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + + arizona_of_read_s32(arizona, "wlf,micd-detect-debounce", false, + &pdata->micd_detect_debounce); + + arizona_of_read_s32(arizona, "wlf,micd-manual-debounce", false, + &pdata->micd_manual_debounce); + + + pdata->micd_pol_gpio = arizona_of_get_named_gpio(arizona, + "wlf,micd-pol-gpio", + false); + + arizona_of_read_s32(arizona, "wlf,micd-bias-start-time", false, + &pdata->micd_bias_start_time); + + arizona_of_read_s32(arizona, "wlf,micd-rate", false, + &pdata->micd_rate); + + arizona_of_read_s32(arizona, "wlf,micd-dbtime", false, + &pdata->micd_dbtime); + + arizona_of_read_s32(arizona, "wlf,micd-timeout", false, + &pdata->micd_timeout); + + pdata->micd_force_micbias = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-force-micbias"); + + pdata->micd_force_micbias_initial = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-force-micbias-initial"); + pdata->micd_software_compare = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-software-compare"); + + pdata->micd_open_circuit_declare = + of_property_read_bool(arizona->dev->of_node, + "wlf,micd-open-circuit-declare"); + + pdata->jd_gpio5 = of_property_read_bool(arizona->dev->of_node, + "wlf,use-jd-gpio"); + + pdata->jd_gpio5_nopull = of_property_read_bool(arizona->dev->of_node, + "wlf,jd-gpio-nopull"); + + pdata->jd_invert = of_property_read_bool(arizona->dev->of_node, + "wlf,jd-invert"); + + arizona_of_read_u32(arizona, "wlf,gpsw", false, &pdata->gpsw); + + arizona_of_read_s32(arizona, "wlf,init-mic-delay", false, + &pdata->init_mic_delay); + + arizona_of_read_s32(arizona, "wlf,fixed-hpdet-imp", false, + &pdata->fixed_hpdet_imp); + + arizona_of_read_s32(arizona, "wlf,hpdet-short-circuit-imp", false, + &pdata->hpdet_short_circuit_imp); + + arizona_of_read_s32(arizona, "wlf,hpdet-channel", false, + &pdata->hpdet_channel); + + arizona_of_read_s32(arizona, "wlf,jd-wake-time", false, + &pdata->jd_wake_time); + + arizona_of_read_u32(arizona, "wlf,micd-clamp-mode", false, + &pdata->micd_clamp_mode); + + arizona_of_read_u32(arizona, "wlf,hs-mic", false, + &pdata->hs_mic); + if (pdata->hs_mic > ARIZONA_MAX_INPUT) + pdata->hs_mic = 0; + + pdata->hpd_l_pins.clamp_pin = MOON_HPD_OUT_OUT1L; + pdata->hpd_l_pins.impd_pin = MOON_HPD_SENSE_HPDET1; + of_property_read_u32_index(arizona->dev->of_node, + "wlf,hpd-left-pins", 0, + &(pdata->hpd_l_pins.clamp_pin)); + of_property_read_u32_index(arizona->dev->of_node, + "wlf,hpd-left-pins", 1, + &(pdata->hpd_l_pins.impd_pin)); + + pdata->hpd_r_pins.clamp_pin = MOON_HPD_OUT_OUT1R; + pdata->hpd_r_pins.impd_pin = MOON_HPD_SENSE_HPDET1; + of_property_read_u32_index(arizona->dev->of_node, + "wlf,hpd-right-pins", 0, + &(pdata->hpd_r_pins.clamp_pin)); + of_property_read_u32_index(arizona->dev->of_node, + "wlf,hpd-right-pins", 1, + &(pdata->hpd_r_pins.impd_pin)); + + return 0; +} +#else +static inline int arizona_extcon_of_get_pdata(struct arizona *arizona) +{ + return 0; +} +#endif + +static ssize_t arizona_extcon_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + + return scnprintf(buf, PAGE_SIZE, "%d\n", + HOHM_TO_OHM(info->arizona->hp_impedance_x100)); +} + +static void arizona_micd_manual_timeout(struct arizona_extcon_info *info) +{ + dev_dbg(info->arizona->dev, "Manual MICD timed out\n"); + + info->mic_impedance = -EINVAL; + + arizona_jds_set_state(info, info->old_state); + + complete(&info->manual_mic_completion); +} + +static int arizona_micd_manual_reading(struct arizona_extcon_info *info, int val) +{ + info->mic_impedance = val; + + arizona_jds_set_state(info, info->old_state); + + complete(&info->manual_mic_completion); + + return val; +} + +static const struct arizona_jd_state arizona_micd_manual = { + .mode = ARIZONA_ACCDET_MODE_ADC, + .start = arizona_micd_mic_start, + .reading = arizona_micd_manual_reading, + .stop = arizona_micd_mic_stop, + + .timeout_ms = arizona_micd_mic_timeout_ms, + .timeout = arizona_micd_manual_timeout, +}; + +int arizona_extcon_take_manual_mic_reading(struct arizona_extcon_info *info) +{ + mutex_lock(&info->lock); + info->old_state = info->state; + arizona_jds_set_state(info, &arizona_micd_manual); + mutex_unlock(&info->lock); + + wait_for_completion(&info->manual_mic_completion); + + return info->mic_impedance; +} +EXPORT_SYMBOL_GPL(arizona_extcon_take_manual_mic_reading); + +static ssize_t arizona_extcon_mic_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + int mic_impedance = arizona_extcon_take_manual_mic_reading(info); + + return scnprintf(buf, PAGE_SIZE, "%d\n", mic_impedance); +} + +static int arizona_hp_trim_signify(int raw, int value_mask) +{ + if (raw > value_mask) + return value_mask + 1 - raw; + else + return raw; +} + +static int arizona_hpdet_d_read_calibration(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + struct arizona_hpdet_d_trims *trims; + int off_range1; + int coeff_range0, coeff_range2, coeff_range3; + int grad_range1_0, grad_range3_2; + unsigned int v1, v2; + int ret = -EIO; + + ret = regmap_read(arizona->regmap, 0x0087, &v1); + if (ret >= 0) { + ret = regmap_read(arizona->regmap, 0x0088, &v2); + } + + if (ret < 0) { + dev_warn(arizona->dev, "Failed to read HP trims %d\n", ret); + return ret; + } + + if ((v1 == 0) || (v2 == 0) || (v1 == 0xFFFF) || (v2 == 0xFFFF)) { + dev_warn(arizona->dev, "No HP trims\n"); + return 0; + } + + trims = devm_kzalloc(info->dev, + 4 * sizeof(struct arizona_hpdet_d_trims), + GFP_KERNEL); + if (!trims) { + dev_err(arizona->dev, "Failed to alloc hpdet trims\n"); + return -ENOMEM; + } + + coeff_range0 = v1 & 0xf; + coeff_range0 = arizona_hp_trim_signify(coeff_range0, 0x7); + + coeff_range2 = (v1 >> 10) & 0xf; + coeff_range2 = arizona_hp_trim_signify(coeff_range2, 0x7); + + coeff_range3 = ((v1 >> 14) & 0x3) | ((v2 >> 12) & 0xc); + coeff_range3 = arizona_hp_trim_signify(coeff_range3, 0x7); + + off_range1 = (v1 >> 4) & 0x3f; + off_range1 = arizona_hp_trim_signify(off_range1, 0x1f); + + grad_range1_0 = v2 & 0x7f; + grad_range1_0 = arizona_hp_trim_signify(grad_range1_0, 0x3f); + + grad_range3_2 = (v2 >> 7) & 0x7f; + grad_range3_2 = arizona_hp_trim_signify(grad_range3_2, 0x3f); + + trims[0].off_x4 = (coeff_range0 + off_range1) * 4; + trims[1].off_x4 = off_range1 * 4; + trims[2].off_x4 = (coeff_range2 + off_range1) * 4; + trims[3].off_x4 = (coeff_range3 + off_range1) * 4; + trims[0].grad_x4 = grad_range1_0 * 4; + trims[1].grad_x4 = grad_range1_0 * 4; + trims[2].grad_x4 = grad_range3_2 * 4; + trims[3].grad_x4 = grad_range3_2 * 4; + + info->hpdet_d_trims = trims; + info->calib_data = arizona_hpdet_d_ranges; + info->calib_data_size = ARRAY_SIZE(arizona_hpdet_d_ranges); + + dev_dbg(arizona->dev, "Set trims %d,%d %d,%d %d,%d %d,%d\n", + trims[0].off_x4, + trims[0].grad_x4, + trims[1].off_x4, + trims[1].grad_x4, + trims[2].off_x4, + trims[2].grad_x4, + trims[3].off_x4, + trims[3].grad_x4); + return 0; +} + +#define ARIZONA_HPDET_CLEARWATER_OTP_MID_VAL 128 +static inline int arizona_hpdet_clearwater_convert_otp(unsigned int otp_val) +{ + return (ARIZONA_HPDET_CLEARWATER_OTP_MID_VAL - (int)otp_val); +} + +static int arizona_hpdet_clearwater_read_calibration(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + struct arizona_hpdet_d_trims *trims; + int ret = -EIO; + unsigned int offset, gradient, interim_val; + unsigned int otp_hpdet_calib_1, otp_hpdet_calib_2; + + switch (arizona->type) { + case WM8285: + case WM1840: + otp_hpdet_calib_1 = CLEARWATER_OTP_HPDET_CALIB_1; + otp_hpdet_calib_2 = CLEARWATER_OTP_HPDET_CALIB_2; + break; + case CS47L35: + otp_hpdet_calib_1 = MARLEY_OTP_HPDET_CALIB_1; + otp_hpdet_calib_2 = MARLEY_OTP_HPDET_CALIB_2; + break; + default: + otp_hpdet_calib_1 = MOON_OTP_HPDET_CALIB_1; + otp_hpdet_calib_2 = MOON_OTP_HPDET_CALIB_2; + break; + } + + ret = regmap_read(arizona->regmap_32bit, + otp_hpdet_calib_1, + &offset); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP CALIB OFFSET value: %d\n", + ret); + return ret; + } + + ret = regmap_read(arizona->regmap_32bit, + otp_hpdet_calib_2, + &gradient); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP CALIB GRADIENT value: %d\n", + ret); + return ret; + } + + if (((offset == 0) && (gradient == 0)) || + ((offset == 0xFFFFFFFF) && (gradient == 0xFFFFFFFF))) { + dev_warn(arizona->dev, "No HP trims\n"); + return 0; + } + + trims = devm_kzalloc(info->dev, + 4 * sizeof(struct arizona_hpdet_d_trims), + GFP_KERNEL); + if (!trims) { + dev_err(arizona->dev, "Failed to alloc hpdet trims\n"); + return -ENOMEM; + } + + interim_val = (offset & CLEARWATER_OTP_HPDET_CALIB_OFFSET_00_MASK) >> + CLEARWATER_OTP_HPDET_CALIB_OFFSET_00_SHIFT; + trims[0].off_x4 = arizona_hpdet_clearwater_convert_otp(interim_val); + + interim_val = (gradient & CLEARWATER_OTP_HPDET_GRADIENT_0X_MASK) >> + CLEARWATER_OTP_HPDET_GRADIENT_0X_SHIFT; + trims[0].grad_x4 = arizona_hpdet_clearwater_convert_otp(interim_val); + + interim_val = (offset & CLEARWATER_OTP_HPDET_CALIB_OFFSET_01_MASK) >> + CLEARWATER_OTP_HPDET_CALIB_OFFSET_01_SHIFT; + trims[1].off_x4 = arizona_hpdet_clearwater_convert_otp(interim_val); + + trims[1].grad_x4 = trims[0].grad_x4; + + interim_val = (offset & CLEARWATER_OTP_HPDET_CALIB_OFFSET_10_MASK) >> + CLEARWATER_OTP_HPDET_CALIB_OFFSET_10_SHIFT; + trims[2].off_x4 = arizona_hpdet_clearwater_convert_otp(interim_val); + + interim_val = (gradient & CLEARWATER_OTP_HPDET_GRADIENT_1X_MASK) >> + CLEARWATER_OTP_HPDET_GRADIENT_1X_SHIFT; + trims[2].grad_x4 = arizona_hpdet_clearwater_convert_otp(interim_val); + + interim_val = (offset & CLEARWATER_OTP_HPDET_CALIB_OFFSET_11_MASK) >> + CLEARWATER_OTP_HPDET_CALIB_OFFSET_11_SHIFT; + trims[3].off_x4 = arizona_hpdet_clearwater_convert_otp(interim_val); + + trims[3].grad_x4 = trims[2].grad_x4; + + info->hpdet_d_trims = trims; + switch (arizona->type) { + case WM8285: + case WM1840: + case CS47L35: + info->calib_data = arizona_hpdet_clearwater_ranges; + info->calib_data_size = + ARRAY_SIZE(arizona_hpdet_clearwater_ranges); + break; + case CS47L15: + info->calib_data = arizona_hpdet_gaines_ranges; + info->calib_data_size = + ARRAY_SIZE(arizona_hpdet_gaines_ranges); + break; + default: + info->calib_data = arizona_hpdet_moon_ranges; + info->calib_data_size = + ARRAY_SIZE(arizona_hpdet_moon_ranges); + break; + } + + return 0; +} + +static void arizona_extcon_set_micd_clamp_mode(struct arizona *arizona) +{ + unsigned int clamp_ctrl_reg, clamp_ctrl_mask, clamp_ctrl_val; + unsigned int clamp_db_reg, clamp_db_mask, clamp_db_val; + int val; + + /* Set up the regs */ + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + case WM5110: + clamp_ctrl_reg = ARIZONA_MICD_CLAMP_CONTROL; + clamp_ctrl_mask = ARIZONA_MICD_CLAMP_MODE_MASK; + + clamp_db_reg = ARIZONA_JACK_DETECT_DEBOUNCE; + clamp_db_mask = ARIZONA_MICD_CLAMP_DB; + clamp_db_val = ARIZONA_MICD_CLAMP_DB; + break; + default: + clamp_ctrl_reg = CLEARWATER_MICD_CLAMP_CONTROL; + clamp_ctrl_mask = ARIZONA_MICD_CLAMP_MODE_MASK; + + clamp_db_reg = CLEARWATER_INTERRUPT_DEBOUNCE_7; + clamp_db_mask = CLEARWATER_MICD_CLAMP_DB; + clamp_db_val = CLEARWATER_MICD_CLAMP_DB; + + break; + } + + /* If the user has supplied a micd_clamp_mode, assume they know + * what they are doing and just write it out + */ + if (arizona->pdata.micd_clamp_mode) { + clamp_ctrl_val = arizona->pdata.micd_clamp_mode; + goto out; + } + + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + case WM5110: + if (arizona->pdata.jd_gpio5) { + /* Put the GPIO into input mode with optional pull */ + val = 0xc101; + if (arizona->pdata.jd_gpio5_nopull) + val &= ~ARIZONA_GPN_PU; + + regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, + val); + + if (arizona->pdata.jd_invert) + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDL_GP5H; + } else { + if (arizona->pdata.jd_invert) + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDL; + } + break; + default: + if (arizona->pdata.jd_gpio5) { + if (arizona->pdata.jd_invert) + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_ctrl_val = + ARIZONA_MICD_CLAMP_MODE_JDL_GP5L; + } else { + if (arizona->pdata.jd_invert) + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_ctrl_val = ARIZONA_MICD_CLAMP_MODE_JDL; + } + break; + } + +out: + regmap_update_bits(arizona->regmap, + clamp_ctrl_reg, + clamp_ctrl_mask, + clamp_ctrl_val); + + regmap_update_bits(arizona->regmap, + clamp_db_reg, + clamp_db_mask, + clamp_db_val); +} + +static int arizona_extcon_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_extcon_info *info; + unsigned int reg; + int jack_irq_fall, jack_irq_rise; + int ret, mode, i; + int debounce_reg, debounce_val, analog_val; + + if (!arizona->dapm || !arizona->dapm->card) + return -EPROBE_DEFER; + + if (pdata->hpdet_short_circuit_imp < 1) + pdata->hpdet_short_circuit_imp = ARIZONA_HP_SHORT_IMPEDANCE; + else if (pdata->hpdet_short_circuit_imp >= HP_LOW_IMPEDANCE_LIMIT) + pdata->hpdet_short_circuit_imp = HP_LOW_IMPEDANCE_LIMIT - 1; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (IS_ENABLED(CONFIG_OF)) { + if (!dev_get_platdata(arizona->dev)) { + ret = arizona_extcon_of_get_pdata(arizona); + if (ret < 0) + return ret; + } + } + + /* Set of_node to parent from the SPI device to allow + * location regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + info->micvdd = devm_regulator_get(&pdev->dev, "MICVDD"); + if (IS_ERR(info->micvdd)) { + ret = PTR_ERR(info->micvdd); + dev_err(arizona->dev, "Failed to get MICVDD: %d\n", ret); + return ret; + } + + mutex_init(&info->lock); + init_completion(&info->manual_mic_completion); + wakeup_source_init(&info->detection_wake_lock, "arizona-jack-detection"); + info->arizona = arizona; + info->dev = &pdev->dev; + info->last_jackdet = ~(ARIZONA_MICD_CLAMP_STS | ARIZONA_JD1_STS); + INIT_DELAYED_WORK(&info->hpdet_work, arizona_hpdet_work); + INIT_DELAYED_WORK(&info->micd_detect_work, arizona_micd_handler); + INIT_DELAYED_WORK(&info->micd_clear_work, arizona_micd_input_clear); + INIT_DELAYED_WORK(&info->state_timeout_work, arizona_jds_timeout_work); + platform_set_drvdata(pdev, info); + arizona->extcon_info = info; + + switch (arizona->type) { + case WM8997: + break; + case WM5102: + switch (arizona->rev) { + case 0: + info->micd_reva = true; + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 1; + break; + } + break; + case WM8998: + case WM1814: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + case WM8280: + case WM5110: + switch (arizona->rev) { + case 0 ... 2: + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 3; + break; + } + break; + case CS47L35: + arizona->pdata.micd_force_micbias = true; + /* fall through to next case to set common properties */ + case WM8285: + case WM1840: + info->micd_clamp = true; + info->hpdet_ip_version = 4; + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 4; + info->accdet_ip = 1; + break; + } + + info->edev.name = "h2w"; + + ret = switch_dev_register(&info->edev); + if (ret < 0) { + dev_err(arizona->dev, "extcon_dev_register() failed: %d\n", + ret); + goto err_wakelock; + } + + info->input = devm_input_allocate_device(&pdev->dev); + if (!info->input) { + dev_err(arizona->dev, "Can't allocate input dev\n"); + ret = -ENOMEM; + goto err_register; + } + + info->input->name = "Headset"; + info->input->phys = "arizona/extcon"; + info->input->dev.parent = &pdev->dev; + + if (pdata->num_micd_configs) { + info->micd_modes = pdata->micd_configs; + info->micd_num_modes = pdata->num_micd_configs; + } else { + switch (info->accdet_ip) { + case 0: + info->micd_modes = micd_default_modes; + info->micd_num_modes = ARRAY_SIZE(micd_default_modes); + break; + default: + info->micd_modes = moon_micd_default_modes; + info->micd_num_modes = + ARRAY_SIZE(moon_micd_default_modes); + break; + } + } + + switch (arizona->type) { + case WM8997: + case WM5102: + case WM1814: + case WM8998: + case WM8280: + case WM5110: + reg = ARIZONA_GP_SWITCH_1; + break; + default: + reg = CLEARWATER_GP_SWITCH_1; + break; + } + + if (arizona->pdata.gpsw > 0) + regmap_update_bits(arizona->regmap, + reg, + ARIZONA_SW1_MODE_MASK, + arizona->pdata.gpsw); + + if (arizona->pdata.micd_pol_gpio > 0) { + if (info->micd_modes[0].gpio) + mode = GPIOF_OUT_INIT_HIGH; + else + mode = GPIOF_OUT_INIT_LOW; + + ret = devm_gpio_request_one(&pdev->dev, + arizona->pdata.micd_pol_gpio, + mode, + "MICD polarity"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + arizona->pdata.micd_pol_gpio, ret); + goto err_register; + } + } + + if (arizona->pdata.hpdet_id_gpio > 0) { + ret = devm_gpio_request_one(&pdev->dev, + arizona->pdata.hpdet_id_gpio, + GPIOF_OUT_INIT_LOW, + "HPDET"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + arizona->pdata.hpdet_id_gpio, ret); + goto err_register; + } + } + + if (arizona->pdata.micd_bias_start_time) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK, + arizona->pdata.micd_bias_start_time + << ARIZONA_MICD_BIAS_STARTTIME_SHIFT); + + if (arizona->pdata.micd_rate) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_RATE_MASK, + arizona->pdata.micd_rate + << ARIZONA_MICD_RATE_SHIFT); + + if (arizona->pdata.micd_dbtime) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, + arizona->pdata.micd_dbtime + << ARIZONA_MICD_DBTIME_SHIFT); + + BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) < + ARIZONA_NUM_MICD_BUTTON_LEVELS); + + info->micd_ranges = micd_default_ranges; + info->num_micd_ranges = ARRAY_SIZE(micd_default_ranges) - 2; + + if (arizona->pdata.num_micd_ranges) { + memcpy(info->micd_ranges, pdata->micd_ranges, + sizeof(struct arizona_micd_range) * pdata->num_micd_ranges); + info->num_micd_ranges = pdata->num_micd_ranges; + + for (i = info->num_micd_ranges; i < ARRAY_SIZE(micd_default_ranges); i++) { + info->micd_ranges[i].max = -1; + info->micd_ranges[i].key = -1; + } + } + + if (arizona->pdata.num_micd_ranges > ARIZONA_MAX_MICD_RANGE) { + dev_err(arizona->dev, "Too many MICD ranges: %d\n", + arizona->pdata.num_micd_ranges); + } + + if (info->num_micd_ranges > 1) { + for (i = 1; i < info->num_micd_ranges; i++) { + if (info->micd_ranges[i - 1].max > + info->micd_ranges[i].max) { + dev_err(arizona->dev, + "MICD ranges must be sorted\n"); + ret = -EINVAL; + goto err_input; + } + } + } + + ret = arizona_add_micd_levels(info); + if (ret < 0) + goto err_input; + + /* + * If we have a clamp use it, activating in conjunction with + * GPIO5 if that is connected for jack detect operation. + */ + if (info->micd_clamp) + arizona_extcon_set_micd_clamp_mode(arizona); + + arizona_extcon_set_mode(info, 0); + + /* Invalidate the tuning level so that the first detection + * will always apply a tuning */ + info->hp_imp_level = ARIZONA_HP_TUNING_INVALID; + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + switch (info->hpdet_ip_version) { + case 3: + arizona_hpdet_d_read_calibration(info); + if (!info->hpdet_d_trims) + info->hpdet_ip_version = 2; + break; + case 4: + arizona_hpdet_clearwater_read_calibration(info); + if (!info->hpdet_d_trims) { + info->hpdet_ip_version = 2; + + switch (arizona->type) { + case CS47L15: + /* if uncalibratied we must compensate for + * the internal 33 ohm offset + */ + pdata->hpdet_ext_res += 33; + break; + default: + break; + } + } else { + switch (arizona->type) { + case CS47L35: + case WM8285: + case WM1840: + /* as per the hardware steps - below bit needs + * to be set for clearwater for accurate HP + * impedance detection */ + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_POLARITY_INV_ENA_MASK, + 1 << ARIZONA_ACCDET_POLARITY_INV_ENA_SHIFT); + break; + default: + break; + } + } + break; + default: + break; + } + + if (arizona->pdata.jd_gpio5) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + ret = arizona_request_irq(arizona, jack_irq_rise, + "JACKDET rise", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", + ret); + goto err_input; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD rise IRQ wake: %d\n", + ret); + goto err_rise; + } + + ret = arizona_request_irq(arizona, jack_irq_fall, + "JACKDET fall", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JD fall IRQ: %d\n", ret); + goto err_rise_wake; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_fall, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD fall IRQ wake: %d\n", + ret); + goto err_fall; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_MICDET, + "MICDET", arizona_micdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get MICDET IRQ: %d\n", ret); + goto err_fall_wake; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_HPDET, + "HPDET", arizona_hpdet_handler, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get HPDET IRQ: %d\n", ret); + goto err_micdet; + } + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM1831: + case CS47L24: + debounce_reg = ARIZONA_JACK_DETECT_DEBOUNCE; + debounce_val = ARIZONA_JD1_DB; + analog_val = ARIZONA_JD1_ENA; + break; + default: + debounce_reg = CLEARWATER_INTERRUPT_DEBOUNCE_7; + + if (arizona->pdata.jd_gpio5) { + debounce_val = CLEARWATER_JD1_DB | CLEARWATER_JD2_DB; + analog_val = ARIZONA_JD1_ENA | ARIZONA_JD2_ENA; + } else { + debounce_val = CLEARWATER_JD1_DB; + analog_val = ARIZONA_JD1_ENA; + } + break; + }; + + regmap_update_bits(arizona->regmap, debounce_reg, + debounce_val, debounce_val); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + analog_val, analog_val); + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) + dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", + ret); + + pm_runtime_put(&pdev->dev); + + ret = input_register_device(info->input); + if (ret) { + dev_err(&pdev->dev, "Can't register input device: %d\n", ret); + goto err_hpdet; + } + + ret = device_create_file(&pdev->dev, &dev_attr_hp_impedance); + if (ret != 0) + dev_err(&pdev->dev, + "Failed to create sysfs node for hp_impedance %d\n", + ret); + + ret = device_create_file(&pdev->dev, &dev_attr_mic_impedance); + if (ret != 0) + dev_err(&pdev->dev, + "Failed to create sysfs node for mic_impedance %d\n", + ret); + + return 0; + +err_hpdet: + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); +err_micdet: + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); +err_fall_wake: + arizona_set_irq_wake(arizona, jack_irq_fall, 0); +err_fall: + arizona_free_irq(arizona, jack_irq_fall, info); +err_rise_wake: + arizona_set_irq_wake(arizona, jack_irq_rise, 0); +err_rise: + arizona_free_irq(arizona, jack_irq_rise, info); +err_input: +err_register: + pm_runtime_disable(&pdev->dev); + switch_dev_unregister(&info->edev); +err_wakelock: + wakeup_source_trash(&info->detection_wake_lock); + return ret; +} + +static int arizona_extcon_remove(struct platform_device *pdev) +{ + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + struct arizona *arizona = info->arizona; + int jack_irq_rise, jack_irq_fall; + + pm_runtime_disable(&pdev->dev); + + switch (arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + case WM8280: + case WM5110: + regmap_update_bits(arizona->regmap, ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + break; + default: + regmap_update_bits(arizona->regmap, CLEARWATER_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + break; + } + + if (arizona->pdata.jd_gpio5) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + arizona_set_irq_wake(arizona, jack_irq_rise, 0); + arizona_set_irq_wake(arizona, jack_irq_fall, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); + arizona_free_irq(arizona, jack_irq_rise, info); + arizona_free_irq(arizona, jack_irq_fall, info); + cancel_delayed_work_sync(&info->hpdet_work); + input_unregister_device(info->input); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA | ARIZONA_JD2_ENA, 0); + + device_remove_file(&pdev->dev, &dev_attr_hp_impedance); + device_remove_file(&pdev->dev, &dev_attr_mic_impedance); + switch_dev_unregister(&info->edev); + wakeup_source_trash(&info->detection_wake_lock); + kfree(info->hpdet_d_trims); + + return 0; +} + +static struct platform_driver arizona_extcon_driver = { + .driver = { + .name = "arizona-extcon", + .owner = THIS_MODULE, + }, + .probe = arizona_extcon_probe, + .remove = arizona_extcon_remove, +}; + +module_platform_driver(arizona_extcon_driver); + +MODULE_DESCRIPTION("Arizona Extcon driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:extcon-arizona"); diff --git a/include/dt-bindings/mfd/arizona.h b/include/dt-bindings/mfd/arizona.h new file mode 100644 index 00000000000..c7af7c7ef79 --- /dev/null +++ b/include/dt-bindings/mfd/arizona.h @@ -0,0 +1,93 @@ +/* + * Device Tree defines for Arizona devices + * + * Copyright 2015 Cirrus Logic Inc. + * + * Author: Charles Keepax + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_MFD_ARIZONA_H +#define _DT_BINDINGS_MFD_ARIZONA_H + +/* GPIO Function Definitions */ +#define ARIZONA_GP_FN_TXLRCLK 0x00 +#define ARIZONA_GP_FN_GPIO 0x01 +#define ARIZONA_GP_FN_IRQ1 0x02 +#define ARIZONA_GP_FN_IRQ2 0x03 +#define ARIZONA_GP_FN_OPCLK 0x04 +#define ARIZONA_GP_FN_FLL1_OUT 0x05 +#define ARIZONA_GP_FN_FLL2_OUT 0x06 +#define ARIZONA_GP_FN_PWM1 0x08 +#define ARIZONA_GP_FN_PWM2 0x09 +#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A +#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B +#define ARIZONA_GP_FN_FLL1_LOCK 0x0C +#define ARIZONA_GP_FN_FLL2_LOCK 0x0D +#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F +#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10 +#define ARIZONA_GP_FN_HEADPHONE_DET 0x12 +#define ARIZONA_GP_FN_MIC_DET 0x13 +#define ARIZONA_GP_FN_WSEQ_STATUS 0x15 +#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16 +#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A +#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B +#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C +#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D +#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E +#define ARIZONA_GP_FN_DRC1_DECAY 0x1F +#define ARIZONA_GP_FN_DRC1_NOISE 0x20 +#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21 +#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22 +#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23 +#define ARIZONA_GP_FN_DRC2_DECAY 0x24 +#define ARIZONA_GP_FN_DRC2_NOISE 0x25 +#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26 +#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27 +#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28 +#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29 +#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A +#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B +#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C +#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D +#define ARIZONA_GP_FN_OVERCLOCKED 0x2E +#define ARIZONA_GP_FN_DSP_IRQ1 0x35 +#define ARIZONA_GP_FN_DSP_IRQ2 0x36 +#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D +#define ARIZONA_GP_FN_BOOT_DONE 0x44 +#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45 +#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B +#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C + +/* GPIO Configuration Bits */ +#define ARIZONA_GPN_DIR 0x8000 +#define ARIZONA_GPN_PU 0x4000 +#define ARIZONA_GPN_PD 0x2000 +#define ARIZONA_GPN_LVL 0x0800 +#define ARIZONA_GPN_POL 0x0400 +#define ARIZONA_GPN_OP_CFG 0x0200 +#define ARIZONA_GPN_DB 0x0100 + +/* Provide some defines for the most common configs */ +#define ARIZONA_GP_DEFAULT 0xffffffff +#define ARIZONA_GP_OUTPUT (ARIZONA_GP_FN_GPIO) +#define ARIZONA_GP_INPUT (ARIZONA_GP_FN_GPIO | \ + ARIZONA_GPN_DIR) + +#define ARIZONA_32KZ_MCLK1 1 +#define ARIZONA_32KZ_MCLK2 2 +#define ARIZONA_32KZ_NONE 3 + +#define ARIZONA_DMIC_MICVDD 0 +#define ARIZONA_DMIC_MICBIAS1 1 +#define ARIZONA_DMIC_MICBIAS2 2 +#define ARIZONA_DMIC_MICBIAS3 3 + +#define ARIZONA_INMODE_DIFF 0 +#define ARIZONA_INMODE_SE 1 +#define ARIZONA_INMODE_DMIC 2 + +#endif diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h index cc281368dc5..d5ac69eae42 100644 --- a/include/linux/mfd/arizona/core.h +++ b/include/linux/mfd/arizona/core.h @@ -1,6 +1,7 @@ /* * Arizona MFD internals * + * Copyright 2014 CirrusLogic, Inc. * Copyright 2012 Wolfson Microelectronics plc * * Author: Mark Brown @@ -16,74 +17,135 @@ #include #include #include +#include #include -#define ARIZONA_MAX_CORE_SUPPLIES 3 +#define ARIZONA_MAX_CORE_SUPPLIES 2 enum arizona_type { WM5102 = 1, WM5110 = 2, + WM8997 = 3, + WM8280 = 4, + WM8998 = 5, + WM1814 = 6, + WM8285 = 7, + WM1840 = 8, + WM1831 = 9, + CS47L24 = 10, + CS47L35 = 11, + CS47L90 = 12, + CS47L91 = 13, + CS47L15 = 16, }; #define ARIZONA_IRQ_GP1 0 #define ARIZONA_IRQ_GP2 1 #define ARIZONA_IRQ_GP3 2 #define ARIZONA_IRQ_GP4 3 -#define ARIZONA_IRQ_GP5_FALL 4 -#define ARIZONA_IRQ_GP5_RISE 5 -#define ARIZONA_IRQ_JD_FALL 6 -#define ARIZONA_IRQ_JD_RISE 7 -#define ARIZONA_IRQ_DSP1_RAM_RDY 8 -#define ARIZONA_IRQ_DSP2_RAM_RDY 9 -#define ARIZONA_IRQ_DSP3_RAM_RDY 10 -#define ARIZONA_IRQ_DSP4_RAM_RDY 11 -#define ARIZONA_IRQ_DSP_IRQ1 12 -#define ARIZONA_IRQ_DSP_IRQ2 13 -#define ARIZONA_IRQ_DSP_IRQ3 14 -#define ARIZONA_IRQ_DSP_IRQ4 15 -#define ARIZONA_IRQ_DSP_IRQ5 16 -#define ARIZONA_IRQ_DSP_IRQ6 17 -#define ARIZONA_IRQ_DSP_IRQ7 18 -#define ARIZONA_IRQ_DSP_IRQ8 19 -#define ARIZONA_IRQ_SPK_SHUTDOWN_WARN 20 -#define ARIZONA_IRQ_SPK_SHUTDOWN 21 -#define ARIZONA_IRQ_MICDET 22 -#define ARIZONA_IRQ_HPDET 23 -#define ARIZONA_IRQ_WSEQ_DONE 24 -#define ARIZONA_IRQ_DRC2_SIG_DET 25 -#define ARIZONA_IRQ_DRC1_SIG_DET 26 -#define ARIZONA_IRQ_ASRC2_LOCK 27 -#define ARIZONA_IRQ_ASRC1_LOCK 28 -#define ARIZONA_IRQ_UNDERCLOCKED 29 -#define ARIZONA_IRQ_OVERCLOCKED 30 -#define ARIZONA_IRQ_FLL2_LOCK 31 -#define ARIZONA_IRQ_FLL1_LOCK 32 -#define ARIZONA_IRQ_CLKGEN_ERR 33 -#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 34 -#define ARIZONA_IRQ_ASRC_CFG_ERR 35 -#define ARIZONA_IRQ_AIF3_ERR 36 -#define ARIZONA_IRQ_AIF2_ERR 37 -#define ARIZONA_IRQ_AIF1_ERR 38 -#define ARIZONA_IRQ_CTRLIF_ERR 39 -#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 40 -#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 41 -#define ARIZONA_IRQ_SYSCLK_ENA_LOW 42 -#define ARIZONA_IRQ_ISRC1_CFG_ERR 43 -#define ARIZONA_IRQ_ISRC2_CFG_ERR 44 -#define ARIZONA_IRQ_BOOT_DONE 45 -#define ARIZONA_IRQ_DCS_DAC_DONE 46 -#define ARIZONA_IRQ_DCS_HP_DONE 47 -#define ARIZONA_IRQ_FLL2_CLOCK_OK 48 -#define ARIZONA_IRQ_FLL1_CLOCK_OK 49 -#define ARIZONA_IRQ_MICD_CLAMP_RISE 50 -#define ARIZONA_IRQ_MICD_CLAMP_FALL 51 - -#define ARIZONA_NUM_IRQ 52 +#define ARIZONA_IRQ_GP5 4 +#define ARIZONA_IRQ_GP6 5 +#define ARIZONA_IRQ_GP7 6 +#define ARIZONA_IRQ_GP8 7 +#define ARIZONA_IRQ_GP5_FALL 8 +#define ARIZONA_IRQ_GP5_RISE 9 +#define ARIZONA_IRQ_JD_FALL 10 +#define ARIZONA_IRQ_JD_RISE 11 +#define ARIZONA_IRQ_DSP1_RAM_RDY 12 +#define ARIZONA_IRQ_DSP2_RAM_RDY 13 +#define ARIZONA_IRQ_DSP3_RAM_RDY 14 +#define ARIZONA_IRQ_DSP4_RAM_RDY 15 +#define ARIZONA_IRQ_DSP_IRQ1 16 +#define ARIZONA_IRQ_DSP_IRQ2 17 +#define ARIZONA_IRQ_DSP_IRQ3 18 +#define ARIZONA_IRQ_DSP_IRQ4 19 +#define ARIZONA_IRQ_DSP_IRQ5 20 +#define ARIZONA_IRQ_DSP_IRQ6 21 +#define ARIZONA_IRQ_DSP_IRQ7 22 +#define ARIZONA_IRQ_DSP_IRQ8 23 +#define ARIZONA_IRQ_SPK_OVERHEAT_WARN 24 +#define ARIZONA_IRQ_SPK_OVERHEAT 25 +#define ARIZONA_IRQ_MICDET 26 +#define ARIZONA_IRQ_HPDET 27 +#define ARIZONA_IRQ_WSEQ_DONE 28 +#define ARIZONA_IRQ_DRC2_SIG_DET 29 +#define ARIZONA_IRQ_DRC1_SIG_DET 30 +#define ARIZONA_IRQ_ASRC2_LOCK 31 +#define ARIZONA_IRQ_ASRC1_LOCK 32 +#define ARIZONA_IRQ_UNDERCLOCKED 33 +#define ARIZONA_IRQ_OVERCLOCKED 34 +#define ARIZONA_IRQ_FLL2_LOCK 35 +#define ARIZONA_IRQ_FLL1_LOCK 36 +#define ARIZONA_IRQ_CLKGEN_ERR 37 +#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 38 +#define ARIZONA_IRQ_ASRC_CFG_ERR 39 +#define ARIZONA_IRQ_AIF3_ERR 40 +#define ARIZONA_IRQ_AIF2_ERR 41 +#define ARIZONA_IRQ_AIF1_ERR 42 +#define ARIZONA_IRQ_CTRLIF_ERR 43 +#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 44 +#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 45 +#define ARIZONA_IRQ_SYSCLK_ENA_LOW 46 +#define ARIZONA_IRQ_ISRC1_CFG_ERR 47 +#define ARIZONA_IRQ_ISRC2_CFG_ERR 48 +#define ARIZONA_IRQ_BOOT_DONE 49 +#define ARIZONA_IRQ_DCS_DAC_DONE 50 +#define ARIZONA_IRQ_DCS_HP_DONE 51 +#define ARIZONA_IRQ_FLL2_CLOCK_OK 52 +#define ARIZONA_IRQ_FLL1_CLOCK_OK 53 +#define ARIZONA_IRQ_MICD_CLAMP_RISE 54 +#define ARIZONA_IRQ_MICD_CLAMP_FALL 55 +#define ARIZONA_IRQ_HP3R_DONE 56 +#define ARIZONA_IRQ_HP3L_DONE 57 +#define ARIZONA_IRQ_HP2R_DONE 58 +#define ARIZONA_IRQ_HP2L_DONE 59 +#define ARIZONA_IRQ_HP1R_DONE 60 +#define ARIZONA_IRQ_HP1L_DONE 61 +#define ARIZONA_IRQ_ISRC3_CFG_ERR 62 +#define ARIZONA_IRQ_DSP_SHARED_WR_COLL 63 +#define ARIZONA_IRQ_SPK_SHUTDOWN 64 +#define ARIZONA_IRQ_SPK1R_SHORT 65 +#define ARIZONA_IRQ_SPK1L_SHORT 66 +#define ARIZONA_IRQ_HP3R_SC_NEG 67 +#define ARIZONA_IRQ_HP3R_SC_POS 68 +#define ARIZONA_IRQ_HP3L_SC_NEG 69 +#define ARIZONA_IRQ_HP3L_SC_POS 70 +#define ARIZONA_IRQ_HP2R_SC_NEG 71 +#define ARIZONA_IRQ_HP2R_SC_POS 72 +#define ARIZONA_IRQ_HP2L_SC_NEG 73 +#define ARIZONA_IRQ_HP2L_SC_POS 74 +#define ARIZONA_IRQ_HP1R_SC_NEG 75 +#define ARIZONA_IRQ_HP1R_SC_POS 76 +#define ARIZONA_IRQ_HP1L_SC_NEG 77 +#define ARIZONA_IRQ_HP1L_SC_POS 78 +#define ARIZONA_IRQ_FLL3_LOCK 79 +#define ARIZONA_IRQ_FLL3_CLOCK_OK 80 +#define MOON_IRQ_FLLAO_CLOCK_OK 81 +#define MOON_IRQ_MICDET2 82 +#define MOON_IRQ_DSP1_BUS_ERROR 83 +#define MOON_IRQ_DSP2_BUS_ERROR 84 +#define MOON_IRQ_DSP3_BUS_ERROR 85 +#define MOON_IRQ_DSP4_BUS_ERROR 86 +#define MOON_IRQ_DSP5_BUS_ERROR 87 +#define MOON_IRQ_DSP6_BUS_ERROR 88 +#define MOON_IRQ_DSP7_BUS_ERROR 89 + +#define ARIZONA_NUM_IRQ 90 + +#define ARIZONA_HP_SHORT_IMPEDANCE 4 + +/* Conversion between ohms and hundredths of an ohm. */ +#define HOHM_TO_OHM(X) ((X == INT_MAX || X == ARIZONA_HP_Z_OPEN) ? \ + X : (X + 50) / 100) +#define OHM_TO_HOHM(X) (X * 100) struct snd_soc_dapm_context; +struct arizona_extcon_info; struct arizona { struct regmap *regmap; + struct regmap *regmap_32bit; + struct device *dev; enum arizona_type type; @@ -92,32 +154,86 @@ struct arizona { int num_core_supplies; struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES]; struct regulator *dcvdd; + struct notifier_block dcvdd_notifier; struct arizona_pdata pdata; + unsigned int external_dcvdd:1; + + unsigned int irq_sem; int irq; struct irq_domain *virq; struct regmap_irq_chip_data *aod_irq_chip; struct regmap_irq_chip_data *irq_chip; - bool hpdet_magic; + bool hpdet_clamp; unsigned int hp_ena; + unsigned int hp_impedance_x100; + struct arizona_extcon_info *extcon_info; + struct mutex clk_lock; int clk32k_ref; struct snd_soc_dapm_context *dapm; + + struct mutex reg_setting_lock; + + int tdm_width[ARIZONA_MAX_AIF]; + int tdm_slots[ARIZONA_MAX_AIF]; + + uint16_t out_comp_coeff; + uint8_t out_comp_enabled; + + bool micvdd_regulated; + + struct mutex rate_lock; + struct mutex dspclk_ena_lock; }; int arizona_clk32k_enable(struct arizona *arizona); int arizona_clk32k_disable(struct arizona *arizona); -int arizona_request_irq(struct arizona *arizona, int irq, char *name, +int arizona_request_irq(struct arizona *arizona, int irq, const char *name, irq_handler_t handler, void *data); void arizona_free_irq(struct arizona *arizona, int irq, void *data); int arizona_set_irq_wake(struct arizona *arizona, int irq, int on); +int arizona_map_irq(struct arizona *arizona, int irq); +#ifdef CONFIG_MFD_WM5102 int wm5102_patch(struct arizona *arizona); -int wm5110_patch(struct arizona *arizona); +#else +static inline int wm5102_patch(struct arizona *arizona) +{ + return 0; +} +#endif +int florida_patch(struct arizona *arizona); +int wm8997_patch(struct arizona *arizona); +int vegas_patch(struct arizona *arizona); +int clearwater_patch(struct arizona *arizona); +int largo_patch(struct arizona *arizona); +int marley_patch(struct arizona *arizona); +int moon_patch(struct arizona *arizona); +int cs47l15_patch(struct arizona *arizona); + +extern int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop, + bool mandatory); +extern int arizona_of_read_u32_array(struct arizona *arizona, const char *prop, + bool mandatory, u32 *data, size_t num); +extern int arizona_of_read_u32(struct arizona *arizona, const char* prop, + bool mandatory, u32 *data); + +extern void arizona_florida_mute_analog(struct arizona* arizona, + unsigned int mute); +extern void arizona_florida_clear_input(struct arizona *arizona); +extern int arizona_get_num_micbias(struct arizona *arizona, + unsigned int *micbiases, unsigned int *child_micbiases); + +static inline int arizona_of_read_s32(struct arizona *arizona, const char *prop, + bool mandatory, s32 *data) +{ + return arizona_of_read_u32(arizona, prop, mandatory, (u32 *)data); +} #endif diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h index 80dead1f710..74f52ef4a63 100644 --- a/include/linux/mfd/arizona/pdata.h +++ b/include/linux/mfd/arizona/pdata.h @@ -8,34 +8,31 @@ * published by the Free Software Foundation. */ +#include + #ifndef _ARIZONA_PDATA_H #define _ARIZONA_PDATA_H -#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */ +#include + #define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */ #define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */ #define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */ -#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */ #define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */ #define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */ #define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */ -#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */ #define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */ #define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */ #define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */ -#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */ #define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */ #define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */ #define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */ -#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */ #define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */ #define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */ #define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */ -#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */ #define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */ #define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */ #define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */ -#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */ #define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */ #define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */ #define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */ @@ -43,46 +40,64 @@ #define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */ #define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */ -#define ARIZONA_MAX_GPIO 5 +#define CLEARWATER_GPN_LVL 0x8000 /* GPN_LVL */ +#define CLEARWATER_GPN_LVL_MASK 0x8000 /* GPN_LVL */ +#define CLEARWATER_GPN_LVL_SHIFT 15 /* GPN_LVL */ +#define CLEARWATER_GPN_LVL_WIDTH 1 /* GPN_LVL */ -#define ARIZONA_32KZ_MCLK1 1 -#define ARIZONA_32KZ_MCLK2 2 -#define ARIZONA_32KZ_NONE 3 +#define ARIZONA_MAX_GPIO_REGS 5 +#define CLEARWATER_MAX_GPIO_REGS 80 -#define ARIZONA_MAX_INPUT 4 +#define CLEARWATER_NUM_GPIOS 40 +#define MARLEY_NUM_GPIOS 16 +#define MOON_NUM_GPIOS 38 +#define CS47L15_NUM_GPIOS 15 -#define ARIZONA_DMIC_MICVDD 0 -#define ARIZONA_DMIC_MICBIAS1 1 -#define ARIZONA_DMIC_MICBIAS2 2 -#define ARIZONA_DMIC_MICBIAS3 3 +#define ARIZONA_MAX_INPUT 12 -#define ARIZONA_MAX_MICBIAS 3 +#define ARIZONA_MAX_MICBIAS 4 +#define ARIZONA_MAX_CHILD_MICBIAS 4 -#define ARIZONA_INMODE_DIFF 0 -#define ARIZONA_INMODE_SE 1 -#define ARIZONA_INMODE_DMIC 2 +#define WM5102_NUM_MICBIAS 3 +#define CLEARWATER_NUM_MICBIAS 4 +#define LARGO_NUM_MICBIAS 2 +#define MARLEY_NUM_MICBIAS 2 +#define MARLEY_NUM_CHILD_MICBIAS 2 +#define MOON_NUM_MICBIAS 2 +#define MOON_NUM_CHILD_MICBIAS 4 +#define CS47L15_NUM_MICBIAS 1 +#define CS47L15_NUM_CHILD_MICBIAS 3 #define ARIZONA_MAX_OUTPUT 6 -#define ARIZONA_MAX_AIF 3 +#define ARIZONA_MAX_AIF 4 #define ARIZONA_HAP_ACT_ERM 0 #define ARIZONA_HAP_ACT_LRA 2 #define ARIZONA_MAX_PDM_SPK 2 +/* Treat INT_MAX impedance as open circuit */ +#define ARIZONA_HP_Z_OPEN INT_MAX + +#define ARIZONA_MAX_DSP 7 + struct regulator_init_data; +struct arizona_jd_state; + struct arizona_micbias { int mV; /** Regulated voltage */ unsigned int ext_cap:1; /** External capacitor fitted */ - unsigned int discharge:1; /** Actively discharge */ - unsigned int fast_start:1; /** Enable aggressive startup ramp rate */ + /** Actively discharge */ + unsigned int discharge[ARIZONA_MAX_CHILD_MICBIAS]; + unsigned int soft_start:1; /** Disable aggressive startup ramp rate */ unsigned int bypass:1; /** Use bypass mode */ }; struct arizona_micd_config { unsigned int src; + unsigned int gnd; unsigned int bias; bool gpio; }; @@ -92,6 +107,11 @@ struct arizona_micd_range { int key; /** Key to report to input layer */ }; +struct arizona_hpd_pins { + unsigned int clamp_pin; + unsigned int impd_pin; +}; + struct arizona_pdata { int reset; /** GPIO controlling /RESET, if any */ int ldoena; /** GPIO controlling LODENA, if any */ @@ -111,8 +131,14 @@ struct arizona_pdata { /* Base GPIO */ int gpio_base; - /** Pin state for GPIO pins */ - int gpio_defaults[ARIZONA_MAX_GPIO]; + /** Pin state for GPIO pins + * Defines default pin function and state for each GPIO + * + * 0 = leave at chip default + * values 0x1..0xffff = set to this value + * >0xffff = set to 0 + */ + unsigned int gpio_defaults[CLEARWATER_MAX_GPIO_REGS]; /** * Maximum number of channels clocks will be generated for, @@ -121,12 +147,21 @@ struct arizona_pdata { */ int max_channels_clocked[ARIZONA_MAX_AIF]; + /** Time in milliseconds to keep wake lock during jack detection */ + int jd_wake_time; + /** GPIO5 is used for jack detection */ bool jd_gpio5; /** Internal pull on GPIO5 is disabled when used for jack detection */ bool jd_gpio5_nopull; + /** set to true if jackdet contact opens on insert */ + bool jd_invert; + + /** If non-zero don't run headphone detection, report this value */ + int fixed_hpdet_imp; + /** Use the headphone detect circuit to identify the accessory */ bool hpdet_acc_id; @@ -136,9 +171,32 @@ struct arizona_pdata { /** GPIO used for mic isolation with HPDET */ int hpdet_id_gpio; + /** Callback notifying HPDET result */ + void (*hpdet_cb)(unsigned int measurement); + + /** Callback notifying mic presence */ + void (*micd_cb)(bool mic); + + /** If non-zero, specifies the maximum impedance in ohms + * that will be considered as a short circuit. + */ + int hpdet_short_circuit_imp; + + /** + * Channel to use for headphone detection, valid values are 0 for + * left and 1 for right + */ + int hpdet_channel; + + /** Use software comparison to determine mic presence */ + bool micd_software_compare; + /** Extra debounce timeout used during initial mic detection (ms) */ int micd_detect_debounce; + /** Extra software debounces during button detection */ + int micd_manual_debounce; + /** GPIO for mic detection polarity */ int micd_pol_gpio; @@ -157,21 +215,54 @@ struct arizona_pdata { /** Force MICBIAS on for mic detect */ bool micd_force_micbias; + /** Force MICBIAS on for initial mic detect only, not button detect */ + bool micd_force_micbias_initial; + + /** Declare an open circuit as a 4 pole jack */ + bool micd_open_circuit_declare; + + /** Delay between jack detection and MICBIAS ramp */ + int init_mic_delay; + /** Mic detect level parameters */ const struct arizona_micd_range *micd_ranges; int num_micd_ranges; + /** Mic detect clamp function */ + unsigned int micd_clamp_mode; + /** Headset polarity configurations */ struct arizona_micd_config *micd_configs; int num_micd_configs; + /** + * [clamp_pin, impedance_measurement_pin] for HPL + * of 3.5mm Jack + */ + struct arizona_hpd_pins hpd_l_pins; + + /** + * [clamp_pin, impedance_measurement_pin] for HPR + * of 3.5mm Jack + */ + struct arizona_hpd_pins hpd_r_pins; + /** Reference voltage for DMIC inputs */ int dmic_ref[ARIZONA_MAX_INPUT]; + /** Clock Source for DMIC's */ + int dmic_clksrc[ARIZONA_MAX_INPUT]; + /** MICBIAS configurations */ struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS]; - /** Mode of input structures */ + /** + * Mode of input structures + * One of the ARIZONA_INMODE_xxx values + * For most codecs the entries are [0]=IN1 [1]=IN2 [2]=IN3 [3]=IN4 + * wm8998: [0]=IN1A [1]=IN2A [2]=IN1B [3]=IN2B + * cs47l85, wm8285: [0]=IN1L [1]=IN1R [2]=IN2L [3]=IN2R [4]=IN3L [5]=IN3R + */ int inmode[ARIZONA_MAX_INPUT]; /** Mode for outputs */ @@ -188,6 +279,37 @@ struct arizona_pdata { /** GPIO for primary IRQ (used for edge triggered emulation) */ int irq_gpio; + + /** General purpose switch control */ + unsigned int gpsw; + + /** Callback which is called when the trigger phrase is detected */ + void (*ez2ctrl_trigger)(void); + + /** wm5102t output power */ + unsigned int wm5102t_output_pwr; + + /** Override the normal jack detection */ + const struct arizona_jd_state *custom_jd; + + struct wm_adsp_fw_defs *fw_defs[ARIZONA_MAX_DSP]; + int num_fw_defs[ARIZONA_MAX_DSP]; + + /** Some platforms add a series resistor for hpdet to suppress pops */ + int hpdet_ext_res; + + /** Load firmwares for specific chip revisions */ + bool rev_specific_fw; + + /** + * Specify an input to mute during headset button presses and jack + * removal: 1 - IN1L, 2 - IN1R, ..., n - IN[n]R + */ + unsigned int hs_mic; + + /* If lrclk_adv is set then in dsp-a mode, + fsync is shifted left by half bclk */ + int lrclk_adv[ARIZONA_MAX_AIF]; }; #endif diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h index 715b6ba3d52..d04d9c5a582 100644 --- a/include/linux/mfd/arizona/registers.h +++ b/include/linux/mfd/arizona/registers.h @@ -27,6 +27,7 @@ #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17 #define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18 +#define ARIZONA_WRITE_SEQUENCER_CTRL_3 0x19 #define ARIZONA_WRITE_SEQUENCER_PROM 0x1A #define ARIZONA_TONE_GENERATOR_1 0x20 #define ARIZONA_TONE_GENERATOR_2 0x21 @@ -38,17 +39,22 @@ #define ARIZONA_PWM_DRIVE_3 0x32 #define ARIZONA_WAKE_CONTROL 0x40 #define ARIZONA_SEQUENCE_CONTROL 0x41 +#define ARIZONA_SPARE_TRIGGERS 0x42 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64 -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68 -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69 -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C -#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x66 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x67 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x68 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x69 +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6A +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6B +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_7 0x6C +#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_8 0x6D #define ARIZONA_COMFORT_NOISE_GENERATOR 0x70 +#define ARIZONA_HP_DETECT_CALIBRATION_1 0x87 +#define ARIZONA_HP_DETECT_CALIBRATION_2 0x88 #define ARIZONA_HAPTICS_CONTROL_1 0x90 #define ARIZONA_HAPTICS_CONTROL_2 0x91 #define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92 @@ -58,6 +64,7 @@ #define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96 #define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97 #define ARIZONA_HAPTICS_STATUS 0x98 +#define CLEARWATER_COMFORT_NOISE_GENERATOR 0xA0 #define ARIZONA_CLOCK_32K_1 0x100 #define ARIZONA_SYSTEM_CLOCK_1 0x101 #define ARIZONA_SAMPLE_RATE_1 0x102 @@ -68,7 +75,11 @@ #define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C #define ARIZONA_ASYNC_CLOCK_1 0x112 #define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113 +#define ARIZONA_ASYNC_SAMPLE_RATE_2 0x114 #define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B +#define ARIZONA_ASYNC_SAMPLE_RATE_2_STATUS 0x11C +#define CLEARWATER_DSP_CLOCK_1 0x120 +#define CLEARWATER_DSP_CLOCK_2 0x122 #define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149 #define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A #define ARIZONA_RATE_ESTIMATOR_1 0x152 @@ -86,6 +97,7 @@ #define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177 #define ARIZONA_FLL1_NCO_TEST_0 0x178 #define ARIZONA_FLL1_CONTROL_7 0x179 +#define ARIZONA_FLL1_EFS_2 0x17A #define ARIZONA_FLL1_SYNCHRONISER_1 0x181 #define ARIZONA_FLL1_SYNCHRONISER_2 0x182 #define ARIZONA_FLL1_SYNCHRONISER_3 0x183 @@ -95,6 +107,15 @@ #define ARIZONA_FLL1_SYNCHRONISER_7 0x187 #define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189 #define ARIZONA_FLL1_GPIO_CLOCK 0x18A +#define MARLEY_FLL1_SYNCHRONISER_1 0x17F +#define MARLEY_FLL1_SYNCHRONISER_2 0x180 +#define MARLEY_FLL1_SYNCHRONISER_3 0x181 +#define MARLEY_FLL1_SYNCHRONISER_4 0x182 +#define MARLEY_FLL1_SYNCHRONISER_5 0x183 +#define MARLEY_FLL1_SYNCHRONISER_6 0x184 +#define MARLEY_FLL1_SYNCHRONISER_7 0x185 +#define MARLEY_FLL1_SPREAD_SPECTRUM 0x187 +#define MARLEY_FLL1_GPIO_CLOCK 0x188 #define ARIZONA_FLL2_CONTROL_1 0x191 #define ARIZONA_FLL2_CONTROL_2 0x192 #define ARIZONA_FLL2_CONTROL_3 0x193 @@ -104,6 +125,7 @@ #define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197 #define ARIZONA_FLL2_NCO_TEST_0 0x198 #define ARIZONA_FLL2_CONTROL_7 0x199 +#define ARIZONA_FLL2_EFS_2 0x19A #define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1 #define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2 #define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3 @@ -113,63 +135,153 @@ #define ARIZONA_FLL2_SYNCHRONISER_7 0x1A7 #define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9 #define ARIZONA_FLL2_GPIO_CLOCK 0x1AA +#define ARIZONA_FLL3_CONTROL_1 0x1B1 +#define ARIZONA_FLL3_CONTROL_2 0x1B2 +#define ARIZONA_FLL3_CONTROL_3 0x1B3 +#define ARIZONA_FLL3_CONTROL_4 0x1B4 +#define ARIZONA_FLL3_CONTROL_5 0x1B5 +#define ARIZONA_FLL3_CONTROL_6 0x1B6 +#define ARIZONA_FLL3_LOOP_FILTER_TEST_1 0x1B7 +#define ARIZONA_FLL3_NCO_TEST_0 0x1B8 +#define ARIZONA_FLL3_CONTROL_7 0x1B9 +#define ARIZONA_FLL3_SYNCHRONISER_1 0x1C1 +#define ARIZONA_FLL3_SYNCHRONISER_2 0x1C2 +#define ARIZONA_FLL3_SYNCHRONISER_3 0x1C3 +#define ARIZONA_FLL3_SYNCHRONISER_4 0x1C4 +#define ARIZONA_FLL3_SYNCHRONISER_5 0x1C5 +#define ARIZONA_FLL3_SYNCHRONISER_6 0x1C6 +#define ARIZONA_FLL3_SYNCHRONISER_7 0x1C7 +#define ARIZONA_FLL3_SPREAD_SPECTRUM 0x1C9 +#define ARIZONA_FLL3_GPIO_CLOCK 0x1CA +#define MOON_FLLAO_CONTROL_1 0x1D1 +#define MOON_FLLAO_CONTROL_2 0x1D2 +#define MOON_FLLAO_CONTROL_3 0x1D3 +#define MOON_FLLAO_CONTROL_4 0x1D4 +#define MOON_FLLAO_CONTROL_5 0x1D5 +#define MOON_FLLAO_CONTROL_6 0x1D6 +#define MOON_FLLAO_CONTROL_7 0x1D8 +#define MOON_FLLAO_CONTROL_8 0x1DA +#define MOON_FLLAO_CONTROL_9 0x1DB +#define MOON_FLLAO_CONTROL_10 0x1DC +#define MOON_FLLAO_CONTROL_11 0x1DD #define ARIZONA_MIC_CHARGE_PUMP_1 0x200 +#define CLEARWATER_CP_MODE 0x20B #define ARIZONA_LDO1_CONTROL_1 0x210 #define ARIZONA_LDO1_CONTROL_2 0x212 #define ARIZONA_LDO2_CONTROL_1 0x213 #define ARIZONA_MIC_BIAS_CTRL_1 0x218 #define ARIZONA_MIC_BIAS_CTRL_2 0x219 #define ARIZONA_MIC_BIAS_CTRL_3 0x21A +#define ARIZONA_MIC_BIAS_CTRL_4 0x21B +#define ARIZONA_MIC_BIAS_CTRL_5 0x21C +#define ARIZONA_MIC_BIAS_CTRL_6 0x21E +#define ARIZONA_HP_CTRL_1L 0x225 +#define ARIZONA_HP_CTRL_1R 0x226 +#define ARIZONA_HP_CTRL_2L 0x227 +#define ARIZONA_HP_CTRL_2R 0x228 +#define ARIZONA_HP_CTRL_3L 0x229 +#define ARIZONA_HP_CTRL_3R 0x22A +#define ARIZONA_DCS_HP1L_CONTROL 0x232 +#define ARIZONA_DCS_HP1R_CONTROL 0x238 +#define CLEARWATER_EDRE_HP_STEREO_CONTROL 0x27E #define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293 +#define MOON_HEADPHONE_DETECT_0 0x299 #define ARIZONA_HEADPHONE_DETECT_1 0x29B #define ARIZONA_HEADPHONE_DETECT_2 0x29C -#define ARIZONA_HP_DACVAL 0x29F +#define ARIZONA_HEADPHONE_DETECT_3 0x29D +#define ARIZONA_HP_DACVAL 0x29F #define ARIZONA_MICD_CLAMP_CONTROL 0x2A2 +#define MOON_MIC_DETECT_0 0x2A2 #define ARIZONA_MIC_DETECT_1 0x2A3 #define ARIZONA_MIC_DETECT_2 0x2A4 #define ARIZONA_MIC_DETECT_3 0x2A5 -#define ARIZONA_MIC_DETECT_LEVEL_1 0x2A6 -#define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7 -#define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8 -#define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9 +#define ARIZONA_MIC_DETECT_LEVEL_1 0x2A6 +#define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7 +#define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8 +#define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9 +#define ARIZONA_MIC_DETECT_4 0x2AB +#define MOON_MICDET2_CONTROL_0 0x2B2 +#define MOON_MICDET2_CONTROL_1 0x2B3 +#define MOON_MICDET2_CONTROL_2 0x2B4 +#define MOON_MICDET2_CONTROL_3 0x2B5 +#define MOON_MICDET2_LEVEL_1 0x2B6 +#define MOON_MICDET2_LEVEL_2 0x2B7 +#define MOON_MICDET2_LEVEL_3 0x2B8 +#define MOON_MICDET2_LEVEL_4 0x2B9 +#define MOON_MICDET2_CONTROL_4 0x2BB #define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3 +#define CLEARWATER_MICD_CLAMP_CONTROL 0x2C6 #define ARIZONA_ISOLATION_CONTROL 0x2CB #define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3 #define ARIZONA_INPUT_ENABLES 0x300 #define ARIZONA_INPUT_ENABLES_STATUS 0x301 #define ARIZONA_INPUT_RATE 0x308 #define ARIZONA_INPUT_VOLUME_RAMP 0x309 +#define ARIZONA_HPF_CONTROL 0x30C #define ARIZONA_IN1L_CONTROL 0x310 #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311 #define ARIZONA_DMIC1L_CONTROL 0x312 +#define MOON_IN1L_RATE_CONTROL 0x313 #define ARIZONA_IN1R_CONTROL 0x314 #define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315 #define ARIZONA_DMIC1R_CONTROL 0x316 +#define MOON_IN1R_RATE_CONTROL 0x317 #define ARIZONA_IN2L_CONTROL 0x318 #define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319 #define ARIZONA_DMIC2L_CONTROL 0x31A +#define MOON_IN2L_RATE_CONTROL 0x31B #define ARIZONA_IN2R_CONTROL 0x31C #define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D #define ARIZONA_DMIC2R_CONTROL 0x31E +#define MOON_IN2R_RATE_CONTROL 0x31F #define ARIZONA_IN3L_CONTROL 0x320 #define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321 #define ARIZONA_DMIC3L_CONTROL 0x322 +#define MOON_IN3L_RATE_CONTROL 0x323 #define ARIZONA_IN3R_CONTROL 0x324 #define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325 #define ARIZONA_DMIC3R_CONTROL 0x326 +#define MOON_IN3R_RATE_CONTROL 0x327 #define ARIZONA_IN4L_CONTROL 0x328 #define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329 #define ARIZONA_DMIC4L_CONTROL 0x32A +#define MOON_IN4L_RATE_CONTROL 0x32B +#define ARIZONA_IN4R_CONTROL 0x32C #define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D #define ARIZONA_DMIC4R_CONTROL 0x32E +#define MOON_IN4R_RATE_CONTROL 0x32F +#define ARIZONA_IN5L_CONTROL 0x330 +#define ARIZONA_ADC_DIGITAL_VOLUME_5L 0x331 +#define ARIZONA_DMIC5L_CONTROL 0x332 +#define MOON_IN5L_RATE_CONTROL 0x333 +#define ARIZONA_IN5R_CONTROL 0x334 +#define ARIZONA_ADC_DIGITAL_VOLUME_5R 0x335 +#define ARIZONA_DMIC5R_CONTROL 0x336 +#define MOON_IN5R_RATE_CONTROL 0x337 +#define ARIZONA_IN6L_CONTROL 0x338 +#define ARIZONA_ADC_DIGITAL_VOLUME_6L 0x339 +#define ARIZONA_DMIC6L_CONTROL 0x33A +#define ARIZONA_IN6R_CONTROL 0x33C +#define ARIZONA_ADC_DIGITAL_VOLUME_6R 0x33D +#define ARIZONA_DMIC6R_CONTROL 0x33E +#define ARIZONA_ADC_VCO_CAL_4 0x393 +#define ARIZONA_ADC_VCO_CAL_5 0x394 +#define ARIZONA_ADC_VCO_CAL_6 0x395 +#define ARIZONA_ADC_VCO_CAL_7 0x396 +#define ARIZONA_ADC_VCO_CAL_8 0x397 +#define ARIZONA_ADC_VCO_CAL_9 0x398 +#define CS47L15_ADC_INT_BIAS 0x3A8 +#define CS47L15_PGA_BIAS_SEL 0x3C4 #define ARIZONA_OUTPUT_ENABLES_1 0x400 #define ARIZONA_OUTPUT_STATUS_1 0x401 +#define ARIZONA_OUTPUT_STANDBY_1 0x405 #define ARIZONA_RAW_OUTPUT_STATUS_1 0x406 #define ARIZONA_OUTPUT_RATE_1 0x408 #define ARIZONA_OUTPUT_VOLUME_RAMP 0x409 #define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410 #define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411 #define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412 +#define MOON_OUT1_CONFIG 0x412 #define ARIZONA_NOISE_GATE_SELECT_1L 0x413 #define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414 #define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415 @@ -178,6 +290,7 @@ #define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418 #define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419 #define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A +#define MOON_OUT2_CONFIG 0x41A #define ARIZONA_NOISE_GATE_SELECT_2L 0x41B #define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C #define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D @@ -215,14 +328,29 @@ #define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D #define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E #define ARIZONA_NOISE_GATE_SELECT_6R 0x43F +#define ARIZONA_DRE_ENABLE 0x440 +#define ARIZONA_DRE_CONTROL_1 0x441 +#define ARIZONA_DRE_CONTROL_2 0x442 +#define ARIZONA_DRE_CONTROL_3 0x443 +#define CLEARWATER_EDRE_ENABLE 0x448 +#define CLEARWATER_EDRE_MANUAL 0x44A #define ARIZONA_DAC_AEC_CONTROL_1 0x450 +#define ARIZONA_DAC_AEC_CONTROL_2 0x451 #define ARIZONA_NOISE_GATE_CONTROL 0x458 #define ARIZONA_PDM_SPK1_CTRL_1 0x490 #define ARIZONA_PDM_SPK1_CTRL_2 0x491 #define ARIZONA_PDM_SPK2_CTRL_1 0x492 #define ARIZONA_PDM_SPK2_CTRL_2 0x493 +#define ARIZONA_HP_TEST_CTRL_13 0x49A +#define ARIZONA_HP1_SHORT_CIRCUIT_CTRL 0x4A0 +#define ARIZONA_HP2_SHORT_CIRCUIT_CTRL 0x4A1 +#define ARIZONA_HP3_SHORT_CIRCUIT_CTRL 0x4A2 +#define ARIZONA_HP_TEST_CTRL_1 0x4A4 +#define ARIZONA_HP_TEST_CTRL_5 0x4A8 +#define ARIZONA_HP_TEST_CTRL_6 0x4A9 #define ARIZONA_SPK_CTRL_2 0x4B5 #define ARIZONA_SPK_CTRL_3 0x4B6 +#define ARIZONA_SPK_CTRL_5 0x4B8 #define ARIZONA_DAC_COMP_1 0x4DC #define ARIZONA_DAC_COMP_2 0x4DD #define ARIZONA_DAC_COMP_3 0x4DE @@ -266,8 +394,20 @@ #define ARIZONA_AIF2_FRAME_CTRL_2 0x548 #define ARIZONA_AIF2_FRAME_CTRL_3 0x549 #define ARIZONA_AIF2_FRAME_CTRL_4 0x54A +#define ARIZONA_AIF2_FRAME_CTRL_5 0x54B +#define ARIZONA_AIF2_FRAME_CTRL_6 0x54C +#define ARIZONA_AIF2_FRAME_CTRL_7 0x54D +#define ARIZONA_AIF2_FRAME_CTRL_8 0x54E +#define ARIZONA_AIF2_FRAME_CTRL_9 0x54F +#define ARIZONA_AIF2_FRAME_CTRL_10 0x550 #define ARIZONA_AIF2_FRAME_CTRL_11 0x551 #define ARIZONA_AIF2_FRAME_CTRL_12 0x552 +#define ARIZONA_AIF2_FRAME_CTRL_13 0x553 +#define ARIZONA_AIF2_FRAME_CTRL_14 0x554 +#define ARIZONA_AIF2_FRAME_CTRL_15 0x555 +#define ARIZONA_AIF2_FRAME_CTRL_16 0x556 +#define ARIZONA_AIF2_FRAME_CTRL_17 0x557 +#define ARIZONA_AIF2_FRAME_CTRL_18 0x558 #define ARIZONA_AIF2_TX_ENABLES 0x559 #define ARIZONA_AIF2_RX_ENABLES 0x55A #define ARIZONA_AIF2_FORCE_WRITE 0x55B @@ -287,6 +427,26 @@ #define ARIZONA_AIF3_TX_ENABLES 0x599 #define ARIZONA_AIF3_RX_ENABLES 0x59A #define ARIZONA_AIF3_FORCE_WRITE 0x59B +#define ARIZONA_AIF4_BCLK_CTRL 0x5A0 +#define ARIZONA_AIF4_TX_PIN_CTRL 0x5A1 +#define ARIZONA_AIF4_RX_PIN_CTRL 0x5A2 +#define ARIZONA_AIF4_RATE_CTRL 0x5A3 +#define ARIZONA_AIF4_FORMAT 0x5A4 +#define ARIZONA_AIF4_TX_BCLK_RATE 0x5A5 +#define ARIZONA_AIF4_RX_BCLK_RATE 0x5A6 +#define ARIZONA_AIF4_FRAME_CTRL_1 0x5A7 +#define ARIZONA_AIF4_FRAME_CTRL_2 0x5A8 +#define ARIZONA_AIF4_FRAME_CTRL_3 0x5A9 +#define ARIZONA_AIF4_FRAME_CTRL_4 0x5AA +#define ARIZONA_AIF4_FRAME_CTRL_11 0x5B1 +#define ARIZONA_AIF4_FRAME_CTRL_12 0x5B2 +#define ARIZONA_AIF4_TX_ENABLES 0x5B9 +#define ARIZONA_AIF4_RX_ENABLES 0x5BA +#define ARIZONA_AIF4_FORCE_WRITE 0x5BB +#define ARIZONA_SPD1_TX_CONTROL 0x5C2 +#define ARIZONA_SPD1_TX_CHANNEL_STATUS_1 0x5C3 +#define ARIZONA_SPD1_TX_CHANNEL_STATUS_2 0x5C4 +#define ARIZONA_SPD1_TX_CHANNEL_STATUS_3 0x5C5 #define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3 #define ARIZONA_SLIMBUS_RATES_1 0x5E5 #define ARIZONA_SLIMBUS_RATES_2 0x5E6 @@ -508,6 +668,54 @@ #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F +#define ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE 0x750 +#define ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME 0x751 +#define ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE 0x752 +#define ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME 0x753 +#define ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE 0x754 +#define ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME 0x755 +#define ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE 0x756 +#define ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME 0x757 +#define ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE 0x758 +#define ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME 0x759 +#define ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE 0x75A +#define ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME 0x75B +#define ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE 0x75C +#define ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME 0x75D +#define ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE 0x75E +#define ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME 0x75F +#define ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE 0x760 +#define ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME 0x761 +#define ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE 0x762 +#define ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME 0x763 +#define ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE 0x764 +#define ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME 0x765 +#define ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE 0x766 +#define ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME 0x767 +#define ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE 0x768 +#define ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME 0x769 +#define ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE 0x76A +#define ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME 0x76B +#define ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE 0x76C +#define ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME 0x76D +#define ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE 0x76E +#define ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME 0x76F +#define ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE 0x770 +#define ARIZONA_AIF2TX7MIX_INPUT_1_VOLUME 0x771 +#define ARIZONA_AIF2TX7MIX_INPUT_2_SOURCE 0x772 +#define ARIZONA_AIF2TX7MIX_INPUT_2_VOLUME 0x773 +#define ARIZONA_AIF2TX7MIX_INPUT_3_SOURCE 0x774 +#define ARIZONA_AIF2TX7MIX_INPUT_3_VOLUME 0x775 +#define ARIZONA_AIF2TX7MIX_INPUT_4_SOURCE 0x776 +#define ARIZONA_AIF2TX7MIX_INPUT_4_VOLUME 0x777 +#define ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE 0x778 +#define ARIZONA_AIF2TX8MIX_INPUT_1_VOLUME 0x779 +#define ARIZONA_AIF2TX8MIX_INPUT_2_SOURCE 0x77A +#define ARIZONA_AIF2TX8MIX_INPUT_2_VOLUME 0x77B +#define ARIZONA_AIF2TX8MIX_INPUT_3_SOURCE 0x77C +#define ARIZONA_AIF2TX8MIX_INPUT_3_VOLUME 0x77D +#define ARIZONA_AIF2TX8MIX_INPUT_4_SOURCE 0x77E +#define ARIZONA_AIF2TX8MIX_INPUT_4_VOLUME 0x77F #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780 #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781 #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782 @@ -524,6 +732,22 @@ #define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D #define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E #define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F +#define ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE 0x7A0 +#define ARIZONA_AIF4TX1MIX_INPUT_1_VOLUME 0x7A1 +#define ARIZONA_AIF4TX1MIX_INPUT_2_SOURCE 0x7A2 +#define ARIZONA_AIF4TX1MIX_INPUT_2_VOLUME 0x7A3 +#define ARIZONA_AIF4TX1MIX_INPUT_3_SOURCE 0x7A4 +#define ARIZONA_AIF4TX1MIX_INPUT_3_VOLUME 0x7A5 +#define ARIZONA_AIF4TX1MIX_INPUT_4_SOURCE 0x7A6 +#define ARIZONA_AIF4TX1MIX_INPUT_4_VOLUME 0x7A7 +#define ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE 0x7A8 +#define ARIZONA_AIF4TX2MIX_INPUT_1_VOLUME 0x7A9 +#define ARIZONA_AIF4TX2MIX_INPUT_2_SOURCE 0x7AA +#define ARIZONA_AIF4TX2MIX_INPUT_2_VOLUME 0x7AB +#define ARIZONA_AIF4TX2MIX_INPUT_3_SOURCE 0x7AC +#define ARIZONA_AIF4TX2MIX_INPUT_3_VOLUME 0x7AD +#define ARIZONA_AIF4TX2MIX_INPUT_4_SOURCE 0x7AE +#define ARIZONA_AIF4TX2MIX_INPUT_4_VOLUME 0x7AF #define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0 #define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1 #define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2 @@ -588,6 +812,10 @@ #define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD #define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE #define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF +#define ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE 0x800 +#define ARIZONA_SPDIFTX1MIX_INPUT_1_VOLUME 0x801 +#define ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE 0x808 +#define ARIZONA_SPDIFTX2MIX_INPUT_1_VOLUME 0x809 #define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880 #define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881 #define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882 @@ -772,10 +1000,40 @@ #define ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE 0xA28 #define ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE 0xA30 #define ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE 0xA38 +#define CLEARWATER_DSP5LMIX_INPUT_1_SOURCE 0xA40 +#define CLEARWATER_DSP5LMIX_INPUT_1_VOLUME 0xA41 +#define CLEARWATER_DSP5LMIX_INPUT_2_SOURCE 0xA42 +#define CLEARWATER_DSP5LMIX_INPUT_2_VOLUME 0xA43 +#define CLEARWATER_DSP5LMIX_INPUT_3_SOURCE 0xA44 +#define CLEARWATER_DSP5LMIX_INPUT_3_VOLUME 0xA45 +#define CLEARWATER_DSP5LMIX_INPUT_4_SOURCE 0xA46 +#define CLEARWATER_DSP5LMIX_INPUT_4_VOLUME 0xA47 +#define CLEARWATER_DSP5RMIX_INPUT_1_SOURCE 0xA48 +#define CLEARWATER_DSP5RMIX_INPUT_1_VOLUME 0xA49 +#define CLEARWATER_DSP5RMIX_INPUT_2_SOURCE 0xA4A +#define CLEARWATER_DSP5RMIX_INPUT_2_VOLUME 0xA4B +#define CLEARWATER_DSP5RMIX_INPUT_3_SOURCE 0xA4C +#define CLEARWATER_DSP5RMIX_INPUT_3_VOLUME 0xA4D +#define CLEARWATER_DSP5RMIX_INPUT_4_SOURCE 0xA4E +#define CLEARWATER_DSP5RMIX_INPUT_4_VOLUME 0xA4F +#define CLEARWATER_DSP5AUX1MIX_INPUT_1_SOURCE 0xA50 +#define CLEARWATER_DSP5AUX2MIX_INPUT_1_SOURCE 0xA58 +#define CLEARWATER_DSP5AUX3MIX_INPUT_1_SOURCE 0xA60 +#define CLEARWATER_DSP5AUX4MIX_INPUT_1_SOURCE 0xA68 +#define CLEARWATER_DSP5AUX5MIX_INPUT_1_SOURCE 0xA70 +#define CLEARWATER_DSP5AUX6MIX_INPUT_1_SOURCE 0xA78 #define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80 #define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88 #define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90 #define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98 +#define CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE 0xA80 +#define CLEARWATER_ASRC1_1RMIX_INPUT_1_SOURCE 0xA88 +#define CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE 0xA90 +#define CLEARWATER_ASRC1_2RMIX_INPUT_1_SOURCE 0xA98 +#define CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE 0xAA0 +#define CLEARWATER_ASRC2_1RMIX_INPUT_1_SOURCE 0xAA8 +#define CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE 0xAB0 +#define CLEARWATER_ASRC2_2RMIX_INPUT_1_SOURCE 0xAB8 #define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00 #define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08 #define ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10 @@ -786,12 +1044,6 @@ #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 -#define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 -#define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 -#define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 -#define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 -#define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 -#define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 #define ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50 #define ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58 #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 @@ -806,6 +1058,54 @@ #define ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE 0xBA8 #define ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE 0xBB0 #define ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE 0xBB8 +#define ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE 0xBC0 +#define ARIZONA_ISRC4DEC2MIX_INPUT_1_SOURCE 0xBC8 +#define ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE 0xBE0 +#define ARIZONA_ISRC4INT2MIX_INPUT_1_SOURCE 0xBE8 +#define CLEARWATER_DSP6LMIX_INPUT_1_SOURCE 0xC00 +#define CLEARWATER_DSP6LMIX_INPUT_1_VOLUME 0xC01 +#define CLEARWATER_DSP6LMIX_INPUT_2_SOURCE 0xC02 +#define CLEARWATER_DSP6LMIX_INPUT_2_VOLUME 0xC03 +#define CLEARWATER_DSP6LMIX_INPUT_3_SOURCE 0xC04 +#define CLEARWATER_DSP6LMIX_INPUT_3_VOLUME 0xC05 +#define CLEARWATER_DSP6LMIX_INPUT_4_SOURCE 0xC06 +#define CLEARWATER_DSP6LMIX_INPUT_4_VOLUME 0xC07 +#define CLEARWATER_DSP6RMIX_INPUT_1_SOURCE 0xC08 +#define CLEARWATER_DSP6RMIX_INPUT_1_VOLUME 0xC09 +#define CLEARWATER_DSP6RMIX_INPUT_2_SOURCE 0xC0A +#define CLEARWATER_DSP6RMIX_INPUT_2_VOLUME 0xC0B +#define CLEARWATER_DSP6RMIX_INPUT_3_SOURCE 0xC0C +#define CLEARWATER_DSP6RMIX_INPUT_3_VOLUME 0xC0D +#define CLEARWATER_DSP6RMIX_INPUT_4_SOURCE 0xC0E +#define CLEARWATER_DSP6RMIX_INPUT_4_VOLUME 0xC0F +#define CLEARWATER_DSP6AUX1MIX_INPUT_1_SOURCE 0xC10 +#define CLEARWATER_DSP6AUX2MIX_INPUT_1_SOURCE 0xC18 +#define CLEARWATER_DSP6AUX3MIX_INPUT_1_SOURCE 0xC20 +#define CLEARWATER_DSP6AUX4MIX_INPUT_1_SOURCE 0xC28 +#define CLEARWATER_DSP6AUX5MIX_INPUT_1_SOURCE 0xC30 +#define CLEARWATER_DSP6AUX6MIX_INPUT_1_SOURCE 0xC38 +#define CLEARWATER_DSP7LMIX_INPUT_1_SOURCE 0xC40 +#define CLEARWATER_DSP7LMIX_INPUT_1_VOLUME 0xC41 +#define CLEARWATER_DSP7LMIX_INPUT_2_SOURCE 0xC42 +#define CLEARWATER_DSP7LMIX_INPUT_2_VOLUME 0xC43 +#define CLEARWATER_DSP7LMIX_INPUT_3_SOURCE 0xC44 +#define CLEARWATER_DSP7LMIX_INPUT_3_VOLUME 0xC45 +#define CLEARWATER_DSP7LMIX_INPUT_4_SOURCE 0xC46 +#define CLEARWATER_DSP7LMIX_INPUT_4_VOLUME 0xC47 +#define CLEARWATER_DSP7RMIX_INPUT_1_SOURCE 0xC48 +#define CLEARWATER_DSP7RMIX_INPUT_1_VOLUME 0xC49 +#define CLEARWATER_DSP7RMIX_INPUT_2_SOURCE 0xC4A +#define CLEARWATER_DSP7RMIX_INPUT_2_VOLUME 0xC4B +#define CLEARWATER_DSP7RMIX_INPUT_3_SOURCE 0xC4C +#define CLEARWATER_DSP7RMIX_INPUT_3_VOLUME 0xC4D +#define CLEARWATER_DSP7RMIX_INPUT_4_SOURCE 0xC4E +#define CLEARWATER_DSP7RMIX_INPUT_4_VOLUME 0xC4F +#define CLEARWATER_DSP7AUX1MIX_INPUT_1_SOURCE 0xC50 +#define CLEARWATER_DSP7AUX2MIX_INPUT_1_SOURCE 0xC58 +#define CLEARWATER_DSP7AUX3MIX_INPUT_1_SOURCE 0xC60 +#define CLEARWATER_DSP7AUX4MIX_INPUT_1_SOURCE 0xC68 +#define CLEARWATER_DSP7AUX5MIX_INPUT_1_SOURCE 0xC70 +#define CLEARWATER_DSP7AUX6MIX_INPUT_1_SOURCE 0xC78 #define ARIZONA_GPIO1_CTRL 0xC00 #define ARIZONA_GPIO2_CTRL 0xC01 #define ARIZONA_GPIO3_CTRL 0xC02 @@ -813,6 +1113,8 @@ #define ARIZONA_GPIO5_CTRL 0xC04 #define ARIZONA_IRQ_CTRL_1 0xC0F #define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10 +#define ARIZONA_GP_SWITCH_1 0xC18 +#define CLEARWATER_GP_SWITCH_1 0x2C8 #define ARIZONA_MISC_PAD_CTRL_1 0xC20 #define ARIZONA_MISC_PAD_CTRL_2 0xC21 #define ARIZONA_MISC_PAD_CTRL_3 0xC22 @@ -836,22 +1138,26 @@ #define ARIZONA_INTERRUPT_STATUS_3 0xD02 #define ARIZONA_INTERRUPT_STATUS_4 0xD03 #define ARIZONA_INTERRUPT_STATUS_5 0xD04 +#define ARIZONA_INTERRUPT_STATUS_6 0xD05 #define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08 #define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09 #define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A #define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B #define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C +#define ARIZONA_INTERRUPT_STATUS_6_MASK 0xD0D #define ARIZONA_INTERRUPT_CONTROL 0xD0F #define ARIZONA_IRQ2_STATUS_1 0xD10 #define ARIZONA_IRQ2_STATUS_2 0xD11 #define ARIZONA_IRQ2_STATUS_3 0xD12 #define ARIZONA_IRQ2_STATUS_4 0xD13 #define ARIZONA_IRQ2_STATUS_5 0xD14 +#define ARIZONA_IRQ2_STATUS_6 0xD15 #define ARIZONA_IRQ2_STATUS_1_MASK 0xD18 #define ARIZONA_IRQ2_STATUS_2_MASK 0xD19 #define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A #define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B #define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C +#define ARIZONA_IRQ2_STATUS_6_MASK 0xD1D #define ARIZONA_IRQ2_CONTROL 0xD1F #define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20 #define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21 @@ -860,6 +1166,7 @@ #define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24 #define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25 #define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26 +#define ARIZONA_INTERRUPT_RAW_STATUS_9 0xD28 #define ARIZONA_IRQ_PIN_STATUS 0xD40 #define ARIZONA_ADSP2_IRQ0 0xD41 #define ARIZONA_AOD_WKUP_AND_TRIG 0xD50 @@ -869,6 +1176,14 @@ #define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54 #define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55 #define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56 +#define MOON_DFC1MIX_INPUT_1_SOURCE 0xDC0 +#define MOON_DFC2MIX_INPUT_1_SOURCE 0xDC8 +#define MOON_DFC3MIX_INPUT_1_SOURCE 0xDD0 +#define MOON_DFC4MIX_INPUT_1_SOURCE 0xDD8 +#define MOON_DFC5MIX_INPUT_1_SOURCE 0xDE0 +#define MOON_DFC6MIX_INPUT_1_SOURCE 0xDE8 +#define MOON_DFC7MIX_INPUT_1_SOURCE 0xDF0 +#define MOON_DFC8MIX_INPUT_1_SOURCE 0xDF8 #define ARIZONA_FX_CTRL1 0xE00 #define ARIZONA_FX_CTRL2 0xE01 #define ARIZONA_EQ1_1 0xE10 @@ -965,6 +1280,11 @@ #define ARIZONA_DRC2_CTRL3 0xE8B #define ARIZONA_DRC2_CTRL4 0xE8C #define ARIZONA_DRC2_CTRL5 0xE8D +#define CLEARWATER_DRC2_CTRL1 0xE88 +#define CLEARWATER_DRC2_CTRL2 0xE89 +#define CLEARWATER_DRC2_CTRL3 0xE8A +#define CLEARWATER_DRC2_CTRL4 0xE8B +#define CLEARWATER_DRC2_CTRL5 0xE8C #define ARIZONA_HPLPF1_1 0xEC0 #define ARIZONA_HPLPF1_2 0xEC1 #define ARIZONA_HPLPF2_1 0xEC4 @@ -973,6 +1293,14 @@ #define ARIZONA_HPLPF3_2 0xEC9 #define ARIZONA_HPLPF4_1 0xECC #define ARIZONA_HPLPF4_2 0xECD +#define CLEARWATER_ASRC2_ENABLE 0xED0 +#define CLEARWATER_ASRC2_STATUS 0xED1 +#define CLEARWATER_ASRC2_RATE1 0xED2 +#define CLEARWATER_ASRC2_RATE2 0xED3 +#define CLEARWATER_ASRC1_ENABLE 0xEE0 +#define CLEARWATER_ASRC1_STATUS 0xEE1 +#define CLEARWATER_ASRC1_RATE1 0xEE2 +#define CLEARWATER_ASRC1_RATE2 0xEE3 #define ARIZONA_ASRC_ENABLE 0xEE0 #define ARIZONA_ASRC_STATUS 0xEE1 #define ARIZONA_ASRC_RATE1 0xEE2 @@ -986,14 +1314,52 @@ #define ARIZONA_ISRC_3_CTRL_1 0xEF6 #define ARIZONA_ISRC_3_CTRL_2 0xEF7 #define ARIZONA_ISRC_3_CTRL_3 0xEF8 +#define ARIZONA_ISRC_4_CTRL_1 0xEF9 +#define ARIZONA_ISRC_4_CTRL_2 0xEFA +#define ARIZONA_ISRC_4_CTRL_3 0xEFB #define ARIZONA_CLOCK_CONTROL 0xF00 #define ARIZONA_ANC_SRC 0xF01 #define ARIZONA_DSP_STATUS 0xF02 +#define ARIZONA_ANC_COEFF_START 0xF08 +#define ARIZONA_ANC_COEFF_END 0xF12 +#define ARIZONA_FCL_FILTER_CONTROL 0xF15 +#define ARIZONA_FCL_ADC_REFORMATTER_CONTROL 0xF17 +#define ARIZONA_FCL_COEFF_START 0xF18 +#define ARIZONA_FCL_COEFF_END 0xF69 +#define ARIZONA_FCR_FILTER_CONTROL 0xF70 +#define CLEARWATER_FCR_FILTER_CONTROL 0xF71 +#define ARIZONA_FCR_ADC_REFORMATTER_CONTROL 0xF72 +#define CLEARWATER_FCR_ADC_REFORMATTER_CONTROL 0xF73 +#define ARIZONA_FCR_COEFF_START 0xF73 +#define ARIZONA_FCR_COEFF_END 0xFC4 +#define CLEARWATER_FCR_COEFF_START 0xF74 +#define CLEARWATER_FCR_COEFF_END 0xFC5 #define ARIZONA_DSP1_CONTROL_1 0x1100 #define ARIZONA_DSP1_CLOCKING_1 0x1101 #define ARIZONA_DSP1_STATUS_1 0x1104 #define ARIZONA_DSP1_STATUS_2 0x1105 #define ARIZONA_DSP1_STATUS_3 0x1106 +#define ARIZONA_DSP1_STATUS_4 0x1107 +#define ARIZONA_DSP1_WDMA_BUFFER_1 0x1110 +#define ARIZONA_DSP1_WDMA_BUFFER_2 0x1111 +#define ARIZONA_DSP1_WDMA_BUFFER_3 0x1112 +#define ARIZONA_DSP1_WDMA_BUFFER_4 0x1113 +#define ARIZONA_DSP1_WDMA_BUFFER_5 0x1114 +#define ARIZONA_DSP1_WDMA_BUFFER_6 0x1115 +#define ARIZONA_DSP1_WDMA_BUFFER_7 0x1116 +#define ARIZONA_DSP1_WDMA_BUFFER_8 0x1117 +#define ARIZONA_DSP1_RDMA_BUFFER_1 0x1120 +#define ARIZONA_DSP1_RDMA_BUFFER_2 0x1121 +#define ARIZONA_DSP1_RDMA_BUFFER_3 0x1122 +#define ARIZONA_DSP1_RDMA_BUFFER_4 0x1123 +#define ARIZONA_DSP1_RDMA_BUFFER_5 0x1124 +#define ARIZONA_DSP1_RDMA_BUFFER_6 0x1125 +#define ARIZONA_DSP1_WDMA_CONFIG_1 0x1130 +#define ARIZONA_DSP1_WDMA_CONFIG_2 0x1131 +#define ARIZONA_DSP1_WDMA_OFFSET_1 0x1132 +#define ARIZONA_DSP1_RDMA_CONFIG_1 0x1134 +#define ARIZONA_DSP1_RDMA_OFFSET_1 0x1135 +#define ARIZONA_DSP1_EXTERNAL_START_SELECT_1 0x1138 #define ARIZONA_DSP1_SCRATCH_0 0x1140 #define ARIZONA_DSP1_SCRATCH_1 0x1141 #define ARIZONA_DSP1_SCRATCH_2 0x1142 @@ -1002,26 +1368,1074 @@ #define ARIZONA_DSP2_CLOCKING_1 0x1201 #define ARIZONA_DSP2_STATUS_1 0x1204 #define ARIZONA_DSP2_STATUS_2 0x1205 +#define ARIZONA_DSP2_STATUS_3 0x1206 +#define ARIZONA_DSP2_STATUS_4 0x1207 +#define ARIZONA_DSP2_WDMA_BUFFER_1 0x1210 +#define ARIZONA_DSP2_WDMA_BUFFER_2 0x1211 +#define ARIZONA_DSP2_WDMA_BUFFER_3 0x1212 +#define ARIZONA_DSP2_WDMA_BUFFER_4 0x1213 +#define ARIZONA_DSP2_WDMA_BUFFER_5 0x1214 +#define ARIZONA_DSP2_WDMA_BUFFER_6 0x1215 +#define ARIZONA_DSP2_WDMA_BUFFER_7 0x1216 +#define ARIZONA_DSP2_WDMA_BUFFER_8 0x1217 +#define ARIZONA_DSP2_RDMA_BUFFER_1 0x1220 +#define ARIZONA_DSP2_RDMA_BUFFER_2 0x1221 +#define ARIZONA_DSP2_RDMA_BUFFER_3 0x1222 +#define ARIZONA_DSP2_RDMA_BUFFER_4 0x1223 +#define ARIZONA_DSP2_RDMA_BUFFER_5 0x1224 +#define ARIZONA_DSP2_RDMA_BUFFER_6 0x1225 +#define ARIZONA_DSP2_WDMA_CONFIG_1 0x1230 +#define ARIZONA_DSP2_WDMA_CONFIG_2 0x1231 +#define ARIZONA_DSP2_WDMA_OFFSET_1 0x1232 +#define ARIZONA_DSP2_RDMA_CONFIG_1 0x1234 +#define ARIZONA_DSP2_RDMA_OFFSET_1 0x1235 +#define ARIZONA_DSP2_EXTERNAL_START_SELECT_1 0x1238 #define ARIZONA_DSP2_SCRATCH_0 0x1240 #define ARIZONA_DSP2_SCRATCH_1 0x1241 #define ARIZONA_DSP2_SCRATCH_2 0x1242 #define ARIZONA_DSP2_SCRATCH_3 0x1243 #define ARIZONA_DSP3_CONTROL_1 0x1300 +#define CLEARWATER_DAC_COMP_1 0x1300 #define ARIZONA_DSP3_CLOCKING_1 0x1301 +#define CLEARWATER_DAC_COMP_2 0x1302 #define ARIZONA_DSP3_STATUS_1 0x1304 #define ARIZONA_DSP3_STATUS_2 0x1305 +#define ARIZONA_DSP3_STATUS_3 0x1306 +#define ARIZONA_DSP3_STATUS_4 0x1307 +#define ARIZONA_DSP3_WDMA_BUFFER_1 0x1310 +#define ARIZONA_DSP3_WDMA_BUFFER_2 0x1311 +#define ARIZONA_DSP3_WDMA_BUFFER_3 0x1312 +#define ARIZONA_DSP3_WDMA_BUFFER_4 0x1313 +#define ARIZONA_DSP3_WDMA_BUFFER_5 0x1314 +#define ARIZONA_DSP3_WDMA_BUFFER_6 0x1315 +#define ARIZONA_DSP3_WDMA_BUFFER_7 0x1316 +#define ARIZONA_DSP3_WDMA_BUFFER_8 0x1317 +#define ARIZONA_DSP3_RDMA_BUFFER_1 0x1320 +#define ARIZONA_DSP3_RDMA_BUFFER_2 0x1321 +#define ARIZONA_DSP3_RDMA_BUFFER_3 0x1322 +#define ARIZONA_DSP3_RDMA_BUFFER_4 0x1323 +#define ARIZONA_DSP3_RDMA_BUFFER_5 0x1324 +#define ARIZONA_DSP3_RDMA_BUFFER_6 0x1325 +#define ARIZONA_DSP3_WDMA_CONFIG_1 0x1330 +#define ARIZONA_DSP3_WDMA_CONFIG_2 0x1331 +#define ARIZONA_DSP3_WDMA_OFFSET_1 0x1332 +#define ARIZONA_DSP3_RDMA_CONFIG_1 0x1334 +#define ARIZONA_DSP3_RDMA_OFFSET_1 0x1335 +#define ARIZONA_DSP3_EXTERNAL_START_SELECT_1 0x1338 #define ARIZONA_DSP3_SCRATCH_0 0x1340 #define ARIZONA_DSP3_SCRATCH_1 0x1341 #define ARIZONA_DSP3_SCRATCH_2 0x1342 #define ARIZONA_DSP3_SCRATCH_3 0x1343 +#define CLEARWATER_FRF_COEFFICIENT_1L_1 0x1380 +#define CLEARWATER_FRF_COEFFICIENT_1L_2 0x1381 +#define CLEARWATER_FRF_COEFFICIENT_1L_3 0x1382 +#define CLEARWATER_FRF_COEFFICIENT_1L_4 0x1383 +#define CLEARWATER_FRF_COEFFICIENT_1R_1 0x1390 +#define CLEARWATER_FRF_COEFFICIENT_1R_2 0x1391 +#define CLEARWATER_FRF_COEFFICIENT_1R_3 0x1392 +#define CLEARWATER_FRF_COEFFICIENT_1R_4 0x1393 +#define CLEARWATER_FRF_COEFFICIENT_2L_1 0x13A0 +#define CLEARWATER_FRF_COEFFICIENT_2L_2 0x13A1 +#define CLEARWATER_FRF_COEFFICIENT_2L_3 0x13A2 +#define CLEARWATER_FRF_COEFFICIENT_2L_4 0x13A3 +#define CLEARWATER_FRF_COEFFICIENT_2R_1 0x13B0 +#define CLEARWATER_FRF_COEFFICIENT_2R_2 0x13B1 +#define CLEARWATER_FRF_COEFFICIENT_2R_3 0x13B2 +#define CLEARWATER_FRF_COEFFICIENT_2R_4 0x13B3 +#define CLEARWATER_FRF_COEFFICIENT_3L_1 0x13C0 +#define CLEARWATER_FRF_COEFFICIENT_3L_2 0x13C1 +#define CLEARWATER_FRF_COEFFICIENT_3L_3 0x13C2 +#define CLEARWATER_FRF_COEFFICIENT_3L_4 0x13C3 +#define CLEARWATER_FRF_COEFFICIENT_3R_1 0x13D0 +#define CLEARWATER_FRF_COEFFICIENT_3R_2 0x13D1 +#define CLEARWATER_FRF_COEFFICIENT_3R_3 0x13D2 +#define CLEARWATER_FRF_COEFFICIENT_3R_4 0x13D3 +#define CLEARWATER_FRF_COEFFICIENT_4L_1 0x13E0 +#define CLEARWATER_FRF_COEFFICIENT_4L_2 0x13E1 +#define CLEARWATER_FRF_COEFFICIENT_4L_3 0x13E2 +#define CLEARWATER_FRF_COEFFICIENT_4L_4 0x13E3 +#define CLEARWATER_FRF_COEFFICIENT_4R_1 0x13F0 +#define CLEARWATER_FRF_COEFFICIENT_4R_2 0x13F1 +#define CLEARWATER_FRF_COEFFICIENT_4R_3 0x13F2 +#define CLEARWATER_FRF_COEFFICIENT_4R_4 0x13F3 +#define CLEARWATER_FRF_COEFFICIENT_5L_1 0x1400 +#define CLEARWATER_FRF_COEFFICIENT_5L_2 0x1401 +#define CLEARWATER_FRF_COEFFICIENT_5L_3 0x1402 +#define CLEARWATER_FRF_COEFFICIENT_5L_4 0x1403 +#define CLEARWATER_FRF_COEFFICIENT_5R_1 0x1410 +#define CLEARWATER_FRF_COEFFICIENT_5R_2 0x1411 +#define CLEARWATER_FRF_COEFFICIENT_5R_3 0x1412 +#define CLEARWATER_FRF_COEFFICIENT_5R_4 0x1413 +#define CLEARWATER_FRF_COEFFICIENT_6L_1 0x1420 +#define CLEARWATER_FRF_COEFFICIENT_6L_2 0x1421 +#define CLEARWATER_FRF_COEFFICIENT_6L_3 0x1422 +#define CLEARWATER_FRF_COEFFICIENT_6L_4 0x1423 +#define CLEARWATER_FRF_COEFFICIENT_6R_1 0x1430 +#define CLEARWATER_FRF_COEFFICIENT_6R_2 0x1431 +#define CLEARWATER_FRF_COEFFICIENT_6R_3 0x1432 +#define CLEARWATER_FRF_COEFFICIENT_6R_4 0x1433 +#define MARLEY_FRF_COEFFICIENT_4L_1 0x13A0 +#define MARLEY_FRF_COEFFICIENT_4L_2 0x13A1 +#define MARLEY_FRF_COEFFICIENT_4L_3 0x13A2 +#define MARLEY_FRF_COEFFICIENT_4L_4 0x13A3 +#define MARLEY_FRF_COEFFICIENT_5L_1 0x13B0 +#define MARLEY_FRF_COEFFICIENT_5L_2 0x13B1 +#define MARLEY_FRF_COEFFICIENT_5L_3 0x13B2 +#define MARLEY_FRF_COEFFICIENT_5L_4 0x13B3 +#define MARLEY_FRF_COEFFICIENT_5R_1 0x13C0 +#define MARLEY_FRF_COEFFICIENT_5R_2 0x13C1 +#define MARLEY_FRF_COEFFICIENT_5R_3 0x13C2 +#define MARLEY_FRF_COEFFICIENT_5R_4 0x13C3 #define ARIZONA_DSP4_CONTROL_1 0x1400 #define ARIZONA_DSP4_CLOCKING_1 0x1401 #define ARIZONA_DSP4_STATUS_1 0x1404 #define ARIZONA_DSP4_STATUS_2 0x1405 +#define ARIZONA_DSP4_STATUS_3 0x1406 +#define ARIZONA_DSP4_STATUS_4 0x1407 +#define ARIZONA_DSP4_WDMA_BUFFER_1 0x1410 +#define ARIZONA_DSP4_WDMA_BUFFER_2 0x1411 +#define ARIZONA_DSP4_WDMA_BUFFER_3 0x1412 +#define ARIZONA_DSP4_WDMA_BUFFER_4 0x1413 +#define ARIZONA_DSP4_WDMA_BUFFER_5 0x1414 +#define ARIZONA_DSP4_WDMA_BUFFER_6 0x1415 +#define ARIZONA_DSP4_WDMA_BUFFER_7 0x1416 +#define ARIZONA_DSP4_WDMA_BUFFER_8 0x1417 +#define ARIZONA_DSP4_RDMA_BUFFER_1 0x1420 +#define ARIZONA_DSP4_RDMA_BUFFER_2 0x1421 +#define ARIZONA_DSP4_RDMA_BUFFER_3 0x1422 +#define ARIZONA_DSP4_RDMA_BUFFER_4 0x1423 +#define ARIZONA_DSP4_RDMA_BUFFER_5 0x1424 +#define ARIZONA_DSP4_RDMA_BUFFER_6 0x1425 +#define ARIZONA_DSP4_WDMA_CONFIG_1 0x1430 +#define ARIZONA_DSP4_WDMA_CONFIG_2 0x1431 +#define ARIZONA_DSP4_WDMA_OFFSET_1 0x1432 +#define ARIZONA_DSP4_RDMA_CONFIG_1 0x1434 +#define ARIZONA_DSP4_RDMA_OFFSET_1 0x1435 +#define ARIZONA_DSP4_EXTERNAL_START_SELECT_1 0x1438 #define ARIZONA_DSP4_SCRATCH_0 0x1440 #define ARIZONA_DSP4_SCRATCH_1 0x1441 #define ARIZONA_DSP4_SCRATCH_2 0x1442 #define ARIZONA_DSP4_SCRATCH_3 0x1443 +#define MOON_DFC1_CTRL 0x1480 +#define MOON_DFC1_RX 0x1482 +#define MOON_DFC1_TX 0x1484 +#define MOON_DFC2_CTRL 0x1486 +#define MOON_DFC2_RX 0x1488 +#define MOON_DFC2_TX 0x148A +#define MOON_DFC3_CTRL 0x148C +#define MOON_DFC3_RX 0x148E +#define MOON_DFC3_TX 0x1490 +#define MOON_DFC4_CTRL 0x1492 +#define MOON_DFC4_RX 0x1494 +#define MOON_DFC4_TX 0x1496 +#define MOON_DFC5_CTRL 0x1498 +#define MOON_DFC5_RX 0x149A +#define MOON_DFC5_TX 0x149C +#define MOON_DFC6_CTRL 0x149E +#define MOON_DFC6_RX 0x14A0 +#define MOON_DFC6_TX 0x14A2 +#define MOON_DFC7_CTRL 0x14A4 +#define MOON_DFC7_RX 0x14A6 +#define MOON_DFC7_TX 0x14A8 +#define MOON_DFC8_CTRL 0x14AA +#define MOON_DFC8_RX 0x14AC +#define MOON_DFC8_TX 0x14AE +#define MOON_DFC_STATUS 0x14B6 +#define ARIZONA_FRF_COEFF_1 0x1700 +#define ARIZONA_FRF_COEFF_2 0x1701 +#define ARIZONA_FRF_COEFF_3 0x1702 +#define ARIZONA_FRF_COEFF_4 0x1703 +#define ARIZONA_V2_DAC_COMP_1 0x1704 +#define ARIZONA_V2_DAC_COMP_2 0x1705 +#define CLEARWATER_ADSP2_IRQ0 0x1600 +#define CLEARWATER_ADSP2_IRQ1 0x1601 +#define CLEARWATER_ADSP2_IRQ2 0x1602 +#define CLEARWATER_ADSP2_IRQ3 0x1603 +#define CLEARWATER_ADSP2_IRQ4 0x1604 +#define CLEARWATER_ADSP2_IRQ5 0x1605 +#define CLEARWATER_ADSP2_IRQ6 0x1606 +#define CLEARWATER_ADSP2_IRQ7 0x1607 +#define CLEARWATER_GPIO1_CTRL_1 0x1700 +#define CLEARWATER_GPIO1_CTRL_2 0x1701 +#define CLEARWATER_GPIO2_CTRL_1 0x1702 +#define CLEARWATER_GPIO2_CTRL_2 0x1703 +#define CLEARWATER_GPIO3_CTRL_1 0x1704 +#define CLEARWATER_GPIO3_CTRL_2 0x1705 +#define CLEARWATER_GPIO4_CTRL_1 0x1706 +#define CLEARWATER_GPIO4_CTRL_2 0x1707 +#define CLEARWATER_GPIO5_CTRL_1 0x1708 +#define CLEARWATER_GPIO5_CTRL_2 0x1709 +#define CLEARWATER_GPIO6_CTRL_1 0x170A +#define CLEARWATER_GPIO6_CTRL_2 0x170B +#define CLEARWATER_GPIO7_CTRL_1 0x170C +#define CLEARWATER_GPIO7_CTRL_2 0x170D +#define CLEARWATER_GPIO8_CTRL_1 0x170E +#define CLEARWATER_GPIO8_CTRL_2 0x170F +#define CLEARWATER_GPIO9_CTRL_1 0x1710 +#define CLEARWATER_GPIO9_CTRL_2 0x1711 +#define CLEARWATER_GPIO10_CTRL_1 0x1712 +#define CLEARWATER_GPIO10_CTRL_2 0x1713 +#define CLEARWATER_GPIO11_CTRL_1 0x1714 +#define CLEARWATER_GPIO11_CTRL_2 0x1715 +#define CLEARWATER_GPIO12_CTRL_1 0x1716 +#define CLEARWATER_GPIO12_CTRL_2 0x1717 +#define CLEARWATER_GPIO13_CTRL_1 0x1718 +#define CLEARWATER_GPIO13_CTRL_2 0x1719 +#define CLEARWATER_GPIO14_CTRL_1 0x171A +#define CLEARWATER_GPIO14_CTRL_2 0x171B +#define CLEARWATER_GPIO15_CTRL_1 0x171C +#define CLEARWATER_GPIO15_CTRL_2 0x171D +#define CLEARWATER_GPIO16_CTRL_1 0x171E +#define CLEARWATER_GPIO16_CTRL_2 0x171F +#define CLEARWATER_GPIO17_CTRL_1 0x1720 +#define CLEARWATER_GPIO17_CTRL_2 0x1721 +#define CLEARWATER_GPIO18_CTRL_1 0x1722 +#define CLEARWATER_GPIO18_CTRL_2 0x1723 +#define CLEARWATER_GPIO19_CTRL_1 0x1724 +#define CLEARWATER_GPIO19_CTRL_2 0x1725 +#define CLEARWATER_GPIO20_CTRL_1 0x1726 +#define CLEARWATER_GPIO20_CTRL_2 0x1727 +#define CLEARWATER_GPIO21_CTRL_1 0x1728 +#define CLEARWATER_GPIO21_CTRL_2 0x1729 +#define CLEARWATER_GPIO22_CTRL_1 0x172A +#define CLEARWATER_GPIO22_CTRL_2 0x172B +#define CLEARWATER_GPIO23_CTRL_1 0x172C +#define CLEARWATER_GPIO23_CTRL_2 0x172D +#define CLEARWATER_GPIO24_CTRL_1 0x172E +#define CLEARWATER_GPIO24_CTRL_2 0x172F +#define CLEARWATER_GPIO25_CTRL_1 0x1730 +#define CLEARWATER_GPIO25_CTRL_2 0x1731 +#define CLEARWATER_GPIO26_CTRL_1 0x1732 +#define CLEARWATER_GPIO26_CTRL_2 0x1733 +#define CLEARWATER_GPIO27_CTRL_1 0x1734 +#define CLEARWATER_GPIO27_CTRL_2 0x1735 +#define CLEARWATER_GPIO28_CTRL_1 0x1736 +#define CLEARWATER_GPIO28_CTRL_2 0x1737 +#define CLEARWATER_GPIO29_CTRL_1 0x1738 +#define CLEARWATER_GPIO29_CTRL_2 0x1739 +#define CLEARWATER_GPIO30_CTRL_1 0x173A +#define CLEARWATER_GPIO30_CTRL_2 0x173B +#define CLEARWATER_GPIO31_CTRL_1 0x173C +#define CLEARWATER_GPIO31_CTRL_2 0x173D +#define CLEARWATER_GPIO32_CTRL_1 0x173E +#define CLEARWATER_GPIO32_CTRL_2 0x173F +#define CLEARWATER_GPIO33_CTRL_1 0x1740 +#define CLEARWATER_GPIO33_CTRL_2 0x1741 +#define CLEARWATER_GPIO34_CTRL_1 0x1742 +#define CLEARWATER_GPIO34_CTRL_2 0x1743 +#define CLEARWATER_GPIO35_CTRL_1 0x1744 +#define CLEARWATER_GPIO35_CTRL_2 0x1745 +#define CLEARWATER_GPIO36_CTRL_1 0x1746 +#define CLEARWATER_GPIO36_CTRL_2 0x1747 +#define CLEARWATER_GPIO37_CTRL_1 0x1748 +#define CLEARWATER_GPIO37_CTRL_2 0x1749 +#define CLEARWATER_GPIO38_CTRL_1 0x174A +#define CLEARWATER_GPIO38_CTRL_2 0x174B +#define CLEARWATER_GPIO39_CTRL_1 0x174C +#define CLEARWATER_GPIO39_CTRL_2 0x174D +#define CLEARWATER_GPIO40_CTRL_1 0x174E +#define CLEARWATER_GPIO40_CTRL_2 0x174F +#define CLEARWATER_IRQ1_STATUS_1 0x1800 +#define CLEARWATER_IRQ1_STATUS_2 0x1801 +#define CLEARWATER_IRQ1_STATUS_3 0x1802 +#define CLEARWATER_IRQ1_STATUS_4 0x1803 +#define CLEARWATER_IRQ1_STATUS_5 0x1804 +#define CLEARWATER_IRQ1_STATUS_6 0x1805 +#define CLEARWATER_IRQ1_STATUS_7 0x1806 +#define CLEARWATER_IRQ1_STATUS_8 0x1807 +#define CLEARWATER_IRQ1_STATUS_9 0x1808 +#define CLEARWATER_IRQ1_STATUS_10 0x1809 +#define CLEARWATER_IRQ1_STATUS_11 0x180A +#define CLEARWATER_IRQ1_STATUS_12 0x180B +#define CLEARWATER_IRQ1_STATUS_13 0x180C +#define CLEARWATER_IRQ1_STATUS_14 0x180D +#define CLEARWATER_IRQ1_STATUS_15 0x180E +#define CLEARWATER_IRQ1_STATUS_16 0x180F +#define CLEARWATER_IRQ1_STATUS_17 0x1810 +#define CLEARWATER_IRQ1_STATUS_18 0x1811 +#define CLEARWATER_IRQ1_STATUS_19 0x1812 +#define CLEARWATER_IRQ1_STATUS_20 0x1813 +#define CLEARWATER_IRQ1_STATUS_21 0x1814 +#define CLEARWATER_IRQ1_STATUS_22 0x1815 +#define CLEARWATER_IRQ1_STATUS_23 0x1816 +#define CLEARWATER_IRQ1_STATUS_24 0x1817 +#define CLEARWATER_IRQ1_STATUS_25 0x1818 +#define CLEARWATER_IRQ1_STATUS_26 0x1819 +#define CLEARWATER_IRQ1_STATUS_27 0x181A +#define CLEARWATER_IRQ1_STATUS_28 0x181B +#define CLEARWATER_IRQ1_STATUS_29 0x181C +#define CLEARWATER_IRQ1_STATUS_30 0x181D +#define CLEARWATER_IRQ1_STATUS_31 0x181E +#define CLEARWATER_IRQ1_STATUS_32 0x181F +#define MOON_IRQ1_STATUS_33 0x1820 +#define CLEARWATER_IRQ1_MASK_1 0x1840 +#define CLEARWATER_IRQ1_MASK_2 0x1841 +#define CLEARWATER_IRQ1_MASK_3 0x1842 +#define CLEARWATER_IRQ1_MASK_4 0x1843 +#define CLEARWATER_IRQ1_MASK_5 0x1844 +#define CLEARWATER_IRQ1_MASK_6 0x1845 +#define CLEARWATER_IRQ1_MASK_7 0x1846 +#define CLEARWATER_IRQ1_MASK_8 0x1847 +#define CLEARWATER_IRQ1_MASK_9 0x1848 +#define CLEARWATER_IRQ1_MASK_10 0x1849 +#define CLEARWATER_IRQ1_MASK_11 0x184A +#define CLEARWATER_IRQ1_MASK_12 0x184B +#define CLEARWATER_IRQ1_MASK_13 0x184C +#define CLEARWATER_IRQ1_MASK_14 0x184D +#define CLEARWATER_IRQ1_MASK_15 0x184E +#define MOON_IRQ1_MASK_16 0x184F +#define CLEARWATER_IRQ1_MASK_17 0x1850 +#define CLEARWATER_IRQ1_MASK_18 0x1851 +#define CLEARWATER_IRQ1_MASK_19 0x1852 +#define MOON_IRQ1_MASK_20 0x1853 +#define CLEARWATER_IRQ1_MASK_21 0x1854 +#define CLEARWATER_IRQ1_MASK_22 0x1855 +#define CLEARWATER_IRQ1_MASK_23 0x1856 +#define CLEARWATER_IRQ1_MASK_24 0x1857 +#define CLEARWATER_IRQ1_MASK_25 0x1858 +#define MOON_IRQ1_MASK_26 0x1859 +#define CLEARWATER_IRQ1_MASK_27 0x185A +#define CLEARWATER_IRQ1_MASK_28 0x185B +#define MOON_IRQ1_MASK_29 0x185C +#define CLEARWATER_IRQ1_MASK_30 0x185D +#define CLEARWATER_IRQ1_MASK_31 0x185E +#define CLEARWATER_IRQ1_MASK_32 0x185F +#define MOON_IRQ1_MASK_33 0x1860 +#define CLEARWATER_IRQ1_RAW_STATUS_1 0x1880 +#define CLEARWATER_IRQ1_RAW_STATUS_2 0x1881 +#define CLEARWATER_IRQ1_RAW_STATUS_6 0x1885 +#define CLEARWATER_IRQ1_RAW_STATUS_7 0x1886 +#define CLEARWATER_IRQ1_RAW_STATUS_9 0x1888 +#define CLEARWATER_IRQ1_RAW_STATUS_10 0x1889 +#define CLEARWATER_IRQ1_RAW_STATUS_11 0x188A +#define CLEARWATER_IRQ1_RAW_STATUS_12 0x188B +#define CLEARWATER_IRQ1_RAW_STATUS_13 0x188C +#define CLEARWATER_IRQ1_RAW_STATUS_14 0x188D +#define CLEARWATER_IRQ1_RAW_STATUS_15 0x188E +#define CLEARWATER_IRQ1_RAW_STATUS_17 0x1890 +#define CLEARWATER_IRQ1_RAW_STATUS_18 0x1891 +#define CLEARWATER_IRQ1_RAW_STATUS_19 0x1892 +#define CLEARWATER_IRQ1_RAW_STATUS_21 0x1894 +#define CLEARWATER_IRQ1_RAW_STATUS_22 0x1895 +#define CLEARWATER_IRQ1_RAW_STATUS_23 0x1896 +#define CLEARWATER_IRQ1_RAW_STATUS_24 0x1897 +#define CLEARWATER_IRQ1_RAW_STATUS_25 0x1898 +#define CLEARWATER_IRQ1_RAW_STATUS_30 0x189D +#define CLEARWATER_IRQ1_RAW_STATUS_31 0x189E +#define CLEARWATER_IRQ1_RAW_STATUS_32 0x189F +#define CLEARWATER_IRQ2_STATUS_1 0x1900 +#define CLEARWATER_IRQ2_STATUS_2 0x1901 +#define CLEARWATER_IRQ2_STATUS_6 0x1905 +#define CLEARWATER_IRQ2_STATUS_7 0x1906 +#define CLEARWATER_IRQ2_STATUS_9 0x1908 +#define CLEARWATER_IRQ2_STATUS_11 0x190A +#define CLEARWATER_IRQ2_STATUS_12 0x190B +#define CLEARWATER_IRQ2_STATUS_13 0x190C +#define CLEARWATER_IRQ2_STATUS_14 0x190D +#define CLEARWATER_IRQ2_STATUS_15 0x190E +#define CLEARWATER_IRQ2_STATUS_17 0x1910 +#define CLEARWATER_IRQ2_STATUS_18 0x1911 +#define CLEARWATER_IRQ2_STATUS_19 0x1912 +#define CLEARWATER_IRQ2_STATUS_21 0x1914 +#define CLEARWATER_IRQ2_STATUS_22 0x1915 +#define CLEARWATER_IRQ2_STATUS_23 0x1916 +#define CLEARWATER_IRQ2_STATUS_24 0x1917 +#define CLEARWATER_IRQ2_STATUS_25 0x1918 +#define CLEARWATER_IRQ2_STATUS_27 0x191A +#define CLEARWATER_IRQ2_STATUS_28 0x191B +#define CLEARWATER_IRQ2_STATUS_30 0x191D +#define CLEARWATER_IRQ2_STATUS_31 0x191E +#define CLEARWATER_IRQ2_STATUS_32 0x191F +#define CLEARWATER_IRQ2_MASK_1 0x1940 +#define CLEARWATER_IRQ2_MASK_2 0x1941 +#define CLEARWATER_IRQ2_MASK_6 0x1945 +#define CLEARWATER_IRQ2_MASK_7 0x1946 +#define CLEARWATER_IRQ2_MASK_9 0x1948 +#define CLEARWATER_IRQ2_MASK_11 0x194A +#define CLEARWATER_IRQ2_MASK_12 0x194B +#define CLEARWATER_IRQ2_MASK_13 0x194C +#define CLEARWATER_IRQ2_MASK_14 0x194D +#define CLEARWATER_IRQ2_MASK_15 0x194E +#define CLEARWATER_IRQ2_MASK_17 0x1950 +#define CLEARWATER_IRQ2_MASK_18 0x1951 +#define CLEARWATER_IRQ2_MASK_19 0x1952 +#define CLEARWATER_IRQ2_MASK_21 0x1954 +#define CLEARWATER_IRQ2_MASK_22 0x1955 +#define CLEARWATER_IRQ2_MASK_23 0x1956 +#define CLEARWATER_IRQ2_MASK_24 0x1957 +#define CLEARWATER_IRQ2_MASK_25 0x1958 +#define CLEARWATER_IRQ2_MASK_27 0x195A +#define CLEARWATER_IRQ2_MASK_28 0x195B +#define CLEARWATER_IRQ2_MASK_30 0x195D +#define CLEARWATER_IRQ2_MASK_31 0x195E +#define CLEARWATER_IRQ2_MASK_32 0x195F +#define CLEARWATER_IRQ2_RAW_STATUS_1 0x1980 +#define CLEARWATER_IRQ2_RAW_STATUS_2 0x1981 +#define CLEARWATER_IRQ2_RAW_STATUS_6 0x1985 +#define CLEARWATER_IRQ2_RAW_STATUS_7 0x1986 +#define CLEARWATER_IRQ2_RAW_STATUS_9 0x1988 +#define CLEARWATER_IRQ2_RAW_STATUS_10 0x1989 +#define CLEARWATER_IRQ2_RAW_STATUS_11 0x198A +#define CLEARWATER_IRQ2_RAW_STATUS_12 0x198B +#define CLEARWATER_IRQ2_RAW_STATUS_13 0x198C +#define CLEARWATER_IRQ2_RAW_STATUS_14 0x198D +#define CLEARWATER_IRQ2_RAW_STATUS_15 0x198E +#define CLEARWATER_IRQ2_RAW_STATUS_17 0x1990 +#define CLEARWATER_IRQ2_RAW_STATUS_18 0x1991 +#define CLEARWATER_IRQ2_RAW_STATUS_19 0x1992 +#define CLEARWATER_IRQ2_RAW_STATUS_21 0x1994 +#define CLEARWATER_IRQ2_RAW_STATUS_22 0x1995 +#define CLEARWATER_IRQ2_RAW_STATUS_23 0x1996 +#define CLEARWATER_IRQ2_RAW_STATUS_24 0x1997 +#define CLEARWATER_IRQ2_RAW_STATUS_25 0x1998 +#define CLEARWATER_IRQ2_RAW_STATUS_30 0x199D +#define CLEARWATER_IRQ2_RAW_STATUS_31 0x199E +#define CLEARWATER_IRQ2_RAW_STATUS_32 0x199F +#define CLEARWATER_INTERRUPT_DEBOUNCE_7 0x1A06 +#define CLEARWATER_INTERRUPT_DEBOUNCE_15 0x1A0E +#define CLEARWATER_IRQ1_CTRL 0x1A80 +#define CLEARWATER_IRQ2_CTRL 0x1A82 +#define CLEARWATER_INTERRUPT_RAW_STATUS_1 0x1AA0 +#define ARIZONA_WSEQ_SEQUENCE_1 0x3000 +#define ARIZONA_WSEQ_SEQUENCE_2 0x3002 +#define ARIZONA_WSEQ_SEQUENCE_3 0x3004 +#define ARIZONA_WSEQ_SEQUENCE_4 0x3006 +#define ARIZONA_WSEQ_SEQUENCE_5 0x3008 +#define ARIZONA_WSEQ_SEQUENCE_6 0x300A +#define ARIZONA_WSEQ_SEQUENCE_7 0x300C +#define ARIZONA_WSEQ_SEQUENCE_8 0x300E +#define ARIZONA_WSEQ_SEQUENCE_9 0x3010 +#define ARIZONA_WSEQ_SEQUENCE_10 0x3012 +#define ARIZONA_WSEQ_SEQUENCE_11 0x3014 +#define ARIZONA_WSEQ_SEQUENCE_12 0x3016 +#define ARIZONA_WSEQ_SEQUENCE_13 0x3018 +#define ARIZONA_WSEQ_SEQUENCE_14 0x301A +#define ARIZONA_WSEQ_SEQUENCE_15 0x301C +#define ARIZONA_WSEQ_SEQUENCE_16 0x301E +#define ARIZONA_WSEQ_SEQUENCE_17 0x3020 +#define ARIZONA_WSEQ_SEQUENCE_18 0x3022 +#define ARIZONA_WSEQ_SEQUENCE_19 0x3024 +#define ARIZONA_WSEQ_SEQUENCE_20 0x3026 +#define ARIZONA_WSEQ_SEQUENCE_21 0x3028 +#define ARIZONA_WSEQ_SEQUENCE_22 0x302A +#define ARIZONA_WSEQ_SEQUENCE_23 0x302C +#define ARIZONA_WSEQ_SEQUENCE_24 0x302E +#define ARIZONA_WSEQ_SEQUENCE_25 0x3030 +#define ARIZONA_WSEQ_SEQUENCE_26 0x3032 +#define ARIZONA_WSEQ_SEQUENCE_27 0x3034 +#define ARIZONA_WSEQ_SEQUENCE_28 0x3036 +#define ARIZONA_WSEQ_SEQUENCE_29 0x3038 +#define ARIZONA_WSEQ_SEQUENCE_30 0x303A +#define ARIZONA_WSEQ_SEQUENCE_31 0x303C +#define ARIZONA_WSEQ_SEQUENCE_32 0x303E +#define ARIZONA_WSEQ_SEQUENCE_33 0x3040 +#define ARIZONA_WSEQ_SEQUENCE_34 0x3042 +#define ARIZONA_WSEQ_SEQUENCE_35 0x3044 +#define ARIZONA_WSEQ_SEQUENCE_36 0x3046 +#define ARIZONA_WSEQ_SEQUENCE_37 0x3048 +#define ARIZONA_WSEQ_SEQUENCE_38 0x304A +#define ARIZONA_WSEQ_SEQUENCE_39 0x304C +#define ARIZONA_WSEQ_SEQUENCE_40 0x304E +#define ARIZONA_WSEQ_SEQUENCE_41 0x3050 +#define ARIZONA_WSEQ_SEQUENCE_42 0x3052 +#define ARIZONA_WSEQ_SEQUENCE_43 0x3054 +#define ARIZONA_WSEQ_SEQUENCE_44 0x3056 +#define ARIZONA_WSEQ_SEQUENCE_45 0x3058 +#define ARIZONA_WSEQ_SEQUENCE_46 0x305A +#define ARIZONA_WSEQ_SEQUENCE_47 0x305C +#define ARIZONA_WSEQ_SEQUENCE_48 0x305E +#define ARIZONA_WSEQ_SEQUENCE_49 0x3060 +#define ARIZONA_WSEQ_SEQUENCE_50 0x3062 +#define ARIZONA_WSEQ_SEQUENCE_51 0x3064 +#define ARIZONA_WSEQ_SEQUENCE_52 0x3066 +#define ARIZONA_WSEQ_SEQUENCE_53 0x3068 +#define ARIZONA_WSEQ_SEQUENCE_54 0x306A +#define ARIZONA_WSEQ_SEQUENCE_55 0x306C +#define ARIZONA_WSEQ_SEQUENCE_56 0x306E +#define ARIZONA_WSEQ_SEQUENCE_57 0x3070 +#define ARIZONA_WSEQ_SEQUENCE_58 0x3072 +#define ARIZONA_WSEQ_SEQUENCE_59 0x3074 +#define ARIZONA_WSEQ_SEQUENCE_60 0x3076 +#define ARIZONA_WSEQ_SEQUENCE_61 0x3078 +#define ARIZONA_WSEQ_SEQUENCE_62 0x307A +#define ARIZONA_WSEQ_SEQUENCE_63 0x307C +#define ARIZONA_WSEQ_SEQUENCE_64 0x307E +#define ARIZONA_WSEQ_SEQUENCE_65 0x3080 +#define ARIZONA_WSEQ_SEQUENCE_66 0x3082 +#define ARIZONA_WSEQ_SEQUENCE_67 0x3084 +#define ARIZONA_WSEQ_SEQUENCE_68 0x3086 +#define ARIZONA_WSEQ_SEQUENCE_69 0x3088 +#define ARIZONA_WSEQ_SEQUENCE_70 0x308A +#define ARIZONA_WSEQ_SEQUENCE_71 0x308C +#define ARIZONA_WSEQ_SEQUENCE_72 0x308E +#define ARIZONA_WSEQ_SEQUENCE_73 0x3090 +#define ARIZONA_WSEQ_SEQUENCE_74 0x3092 +#define ARIZONA_WSEQ_SEQUENCE_75 0x3094 +#define ARIZONA_WSEQ_SEQUENCE_76 0x3096 +#define ARIZONA_WSEQ_SEQUENCE_77 0x3098 +#define ARIZONA_WSEQ_SEQUENCE_78 0x309A +#define ARIZONA_WSEQ_SEQUENCE_79 0x309C +#define ARIZONA_WSEQ_SEQUENCE_80 0x309E +#define ARIZONA_WSEQ_SEQUENCE_81 0x30A0 +#define ARIZONA_WSEQ_SEQUENCE_82 0x30A2 +#define ARIZONA_WSEQ_SEQUENCE_83 0x30A4 +#define ARIZONA_WSEQ_SEQUENCE_84 0x30A6 +#define ARIZONA_WSEQ_SEQUENCE_85 0x30A8 +#define ARIZONA_WSEQ_SEQUENCE_86 0x30AA +#define ARIZONA_WSEQ_SEQUENCE_87 0x30AC +#define ARIZONA_WSEQ_SEQUENCE_88 0x30AE +#define ARIZONA_WSEQ_SEQUENCE_89 0x30B0 +#define ARIZONA_WSEQ_SEQUENCE_90 0x30B2 +#define ARIZONA_WSEQ_SEQUENCE_91 0x30B4 +#define ARIZONA_WSEQ_SEQUENCE_92 0x30B6 +#define ARIZONA_WSEQ_SEQUENCE_93 0x30B8 +#define ARIZONA_WSEQ_SEQUENCE_94 0x30BA +#define ARIZONA_WSEQ_SEQUENCE_95 0x30BC +#define ARIZONA_WSEQ_SEQUENCE_96 0x30BE +#define ARIZONA_WSEQ_SEQUENCE_97 0x30C0 +#define ARIZONA_WSEQ_SEQUENCE_98 0x30C2 +#define ARIZONA_WSEQ_SEQUENCE_99 0x30C4 +#define ARIZONA_WSEQ_SEQUENCE_100 0x30C6 +#define ARIZONA_WSEQ_SEQUENCE_101 0x30C8 +#define ARIZONA_WSEQ_SEQUENCE_102 0x30CA +#define ARIZONA_WSEQ_SEQUENCE_103 0x30CC +#define ARIZONA_WSEQ_SEQUENCE_104 0x30CE +#define ARIZONA_WSEQ_SEQUENCE_105 0x30D0 +#define ARIZONA_WSEQ_SEQUENCE_106 0x30D2 +#define ARIZONA_WSEQ_SEQUENCE_107 0x30D4 +#define ARIZONA_WSEQ_SEQUENCE_108 0x30D6 +#define ARIZONA_WSEQ_SEQUENCE_109 0x30D8 +#define ARIZONA_WSEQ_SEQUENCE_110 0x30DA +#define ARIZONA_WSEQ_SEQUENCE_111 0x30DC +#define ARIZONA_WSEQ_SEQUENCE_112 0x30DE +#define ARIZONA_WSEQ_SEQUENCE_113 0x30E0 +#define ARIZONA_WSEQ_SEQUENCE_114 0x30E2 +#define ARIZONA_WSEQ_SEQUENCE_115 0x30E4 +#define ARIZONA_WSEQ_SEQUENCE_116 0x30E6 +#define ARIZONA_WSEQ_SEQUENCE_117 0x30E8 +#define ARIZONA_WSEQ_SEQUENCE_118 0x30EA +#define ARIZONA_WSEQ_SEQUENCE_119 0x30EC +#define ARIZONA_WSEQ_SEQUENCE_120 0x30EE +#define ARIZONA_WSEQ_SEQUENCE_121 0x30F0 +#define ARIZONA_WSEQ_SEQUENCE_122 0x30F2 +#define ARIZONA_WSEQ_SEQUENCE_123 0x30F4 +#define ARIZONA_WSEQ_SEQUENCE_124 0x30F6 +#define ARIZONA_WSEQ_SEQUENCE_125 0x30F8 +#define ARIZONA_WSEQ_SEQUENCE_126 0x30FA +#define ARIZONA_WSEQ_SEQUENCE_127 0x30FC +#define ARIZONA_WSEQ_SEQUENCE_128 0x30FE +#define ARIZONA_WSEQ_SEQUENCE_129 0x3100 +#define ARIZONA_WSEQ_SEQUENCE_130 0x3102 +#define ARIZONA_WSEQ_SEQUENCE_131 0x3104 +#define ARIZONA_WSEQ_SEQUENCE_132 0x3106 +#define ARIZONA_WSEQ_SEQUENCE_133 0x3108 +#define ARIZONA_WSEQ_SEQUENCE_134 0x310A +#define ARIZONA_WSEQ_SEQUENCE_135 0x310C +#define ARIZONA_WSEQ_SEQUENCE_136 0x310E +#define ARIZONA_WSEQ_SEQUENCE_137 0x3110 +#define ARIZONA_WSEQ_SEQUENCE_138 0x3112 +#define ARIZONA_WSEQ_SEQUENCE_139 0x3114 +#define ARIZONA_WSEQ_SEQUENCE_140 0x3116 +#define ARIZONA_WSEQ_SEQUENCE_141 0x3118 +#define ARIZONA_WSEQ_SEQUENCE_142 0x311A +#define ARIZONA_WSEQ_SEQUENCE_143 0x311C +#define ARIZONA_WSEQ_SEQUENCE_144 0x311E +#define ARIZONA_WSEQ_SEQUENCE_145 0x3120 +#define ARIZONA_WSEQ_SEQUENCE_146 0x3122 +#define ARIZONA_WSEQ_SEQUENCE_147 0x3124 +#define ARIZONA_WSEQ_SEQUENCE_148 0x3126 +#define ARIZONA_WSEQ_SEQUENCE_149 0x3128 +#define ARIZONA_WSEQ_SEQUENCE_150 0x312A +#define ARIZONA_WSEQ_SEQUENCE_151 0x312C +#define ARIZONA_WSEQ_SEQUENCE_152 0x312E +#define ARIZONA_WSEQ_SEQUENCE_153 0x3130 +#define ARIZONA_WSEQ_SEQUENCE_154 0x3132 +#define ARIZONA_WSEQ_SEQUENCE_155 0x3134 +#define ARIZONA_WSEQ_SEQUENCE_156 0x3136 +#define ARIZONA_WSEQ_SEQUENCE_157 0x3138 +#define ARIZONA_WSEQ_SEQUENCE_158 0x313A +#define ARIZONA_WSEQ_SEQUENCE_159 0x313C +#define ARIZONA_WSEQ_SEQUENCE_160 0x313E +#define ARIZONA_WSEQ_SEQUENCE_161 0x3140 +#define ARIZONA_WSEQ_SEQUENCE_162 0x3142 +#define ARIZONA_WSEQ_SEQUENCE_163 0x3144 +#define ARIZONA_WSEQ_SEQUENCE_164 0x3146 +#define ARIZONA_WSEQ_SEQUENCE_165 0x3148 +#define ARIZONA_WSEQ_SEQUENCE_166 0x314A +#define ARIZONA_WSEQ_SEQUENCE_167 0x314C +#define ARIZONA_WSEQ_SEQUENCE_168 0x314E +#define ARIZONA_WSEQ_SEQUENCE_169 0x3150 +#define ARIZONA_WSEQ_SEQUENCE_170 0x3152 +#define ARIZONA_WSEQ_SEQUENCE_171 0x3154 +#define ARIZONA_WSEQ_SEQUENCE_172 0x3156 +#define ARIZONA_WSEQ_SEQUENCE_173 0x3158 +#define ARIZONA_WSEQ_SEQUENCE_174 0x315A +#define ARIZONA_WSEQ_SEQUENCE_175 0x315C +#define ARIZONA_WSEQ_SEQUENCE_176 0x315E +#define ARIZONA_WSEQ_SEQUENCE_177 0x3160 +#define ARIZONA_WSEQ_SEQUENCE_178 0x3162 +#define ARIZONA_WSEQ_SEQUENCE_179 0x3164 +#define ARIZONA_WSEQ_SEQUENCE_180 0x3166 +#define ARIZONA_WSEQ_SEQUENCE_181 0x3168 +#define ARIZONA_WSEQ_SEQUENCE_182 0x316A +#define ARIZONA_WSEQ_SEQUENCE_183 0x316C +#define ARIZONA_WSEQ_SEQUENCE_184 0x316E +#define ARIZONA_WSEQ_SEQUENCE_185 0x3170 +#define ARIZONA_WSEQ_SEQUENCE_186 0x3172 +#define ARIZONA_WSEQ_SEQUENCE_187 0x3174 +#define ARIZONA_WSEQ_SEQUENCE_188 0x3176 +#define ARIZONA_WSEQ_SEQUENCE_189 0x3178 +#define ARIZONA_WSEQ_SEQUENCE_190 0x317A +#define ARIZONA_WSEQ_SEQUENCE_191 0x317C +#define ARIZONA_WSEQ_SEQUENCE_192 0x317E +#define ARIZONA_WSEQ_SEQUENCE_193 0x3180 +#define ARIZONA_WSEQ_SEQUENCE_194 0x3182 +#define ARIZONA_WSEQ_SEQUENCE_195 0x3184 +#define ARIZONA_WSEQ_SEQUENCE_196 0x3186 +#define ARIZONA_WSEQ_SEQUENCE_197 0x3188 +#define ARIZONA_WSEQ_SEQUENCE_198 0x318A +#define ARIZONA_WSEQ_SEQUENCE_199 0x318C +#define ARIZONA_WSEQ_SEQUENCE_200 0x318E +#define ARIZONA_WSEQ_SEQUENCE_201 0x3190 +#define ARIZONA_WSEQ_SEQUENCE_202 0x3192 +#define ARIZONA_WSEQ_SEQUENCE_203 0x3194 +#define ARIZONA_WSEQ_SEQUENCE_204 0x3196 +#define ARIZONA_WSEQ_SEQUENCE_205 0x3198 +#define ARIZONA_WSEQ_SEQUENCE_206 0x319A +#define ARIZONA_WSEQ_SEQUENCE_207 0x319C +#define ARIZONA_WSEQ_SEQUENCE_208 0x319E +#define ARIZONA_WSEQ_SEQUENCE_209 0x31A0 +#define ARIZONA_WSEQ_SEQUENCE_210 0x31A2 +#define ARIZONA_WSEQ_SEQUENCE_211 0x31A4 +#define ARIZONA_WSEQ_SEQUENCE_212 0x31A6 +#define ARIZONA_WSEQ_SEQUENCE_213 0x31A8 +#define ARIZONA_WSEQ_SEQUENCE_214 0x31AA +#define ARIZONA_WSEQ_SEQUENCE_215 0x31AC +#define ARIZONA_WSEQ_SEQUENCE_216 0x31AE +#define ARIZONA_WSEQ_SEQUENCE_217 0x31B0 +#define ARIZONA_WSEQ_SEQUENCE_218 0x31B2 +#define ARIZONA_WSEQ_SEQUENCE_219 0x31B4 +#define ARIZONA_WSEQ_SEQUENCE_220 0x31B6 +#define ARIZONA_WSEQ_SEQUENCE_221 0x31B8 +#define ARIZONA_WSEQ_SEQUENCE_222 0x31BA +#define ARIZONA_WSEQ_SEQUENCE_223 0x31BC +#define ARIZONA_WSEQ_SEQUENCE_224 0x31BE +#define ARIZONA_WSEQ_SEQUENCE_225 0x31C0 +#define ARIZONA_WSEQ_SEQUENCE_226 0x31C2 +#define ARIZONA_WSEQ_SEQUENCE_227 0x31C4 +#define ARIZONA_WSEQ_SEQUENCE_228 0x31C6 +#define ARIZONA_WSEQ_SEQUENCE_229 0x31C8 +#define ARIZONA_WSEQ_SEQUENCE_230 0x31CA +#define ARIZONA_WSEQ_SEQUENCE_231 0x31CC +#define ARIZONA_WSEQ_SEQUENCE_232 0x31CE +#define ARIZONA_WSEQ_SEQUENCE_233 0x31D0 +#define ARIZONA_WSEQ_SEQUENCE_234 0x31D2 +#define ARIZONA_WSEQ_SEQUENCE_235 0x31D4 +#define ARIZONA_WSEQ_SEQUENCE_236 0x31D6 +#define ARIZONA_WSEQ_SEQUENCE_237 0x31D8 +#define ARIZONA_WSEQ_SEQUENCE_238 0x31DA +#define ARIZONA_WSEQ_SEQUENCE_239 0x31DC +#define ARIZONA_WSEQ_SEQUENCE_240 0x31DE +#define ARIZONA_WSEQ_SEQUENCE_241 0x31E0 +#define ARIZONA_WSEQ_SEQUENCE_242 0x31E2 +#define ARIZONA_WSEQ_SEQUENCE_243 0x31E4 +#define ARIZONA_WSEQ_SEQUENCE_244 0x31E6 +#define ARIZONA_WSEQ_SEQUENCE_245 0x31E8 +#define ARIZONA_WSEQ_SEQUENCE_246 0x31EA +#define ARIZONA_WSEQ_SEQUENCE_247 0x31EC +#define ARIZONA_WSEQ_SEQUENCE_248 0x31EE +#define ARIZONA_WSEQ_SEQUENCE_249 0x31F0 +#define ARIZONA_WSEQ_SEQUENCE_250 0x31F2 +#define ARIZONA_WSEQ_SEQUENCE_251 0x31F4 +#define ARIZONA_WSEQ_SEQUENCE_252 0x31F6 +#define ARIZONA_WSEQ_SEQUENCE_253 0x31F8 +#define ARIZONA_WSEQ_SEQUENCE_254 0x31FA +#define ARIZONA_WSEQ_SEQUENCE_255 0x31FC +#define ARIZONA_WSEQ_SEQUENCE_256 0x31FE +#define ARIZONA_WSEQ_SEQUENCE_257 0x3200 +#define ARIZONA_WSEQ_SEQUENCE_258 0x3202 +#define ARIZONA_WSEQ_SEQUENCE_259 0x3204 +#define ARIZONA_WSEQ_SEQUENCE_260 0x3206 +#define ARIZONA_WSEQ_SEQUENCE_261 0x3208 +#define ARIZONA_WSEQ_SEQUENCE_262 0x320A +#define ARIZONA_WSEQ_SEQUENCE_263 0x320C +#define ARIZONA_WSEQ_SEQUENCE_264 0x320E +#define ARIZONA_WSEQ_SEQUENCE_265 0x3210 +#define ARIZONA_WSEQ_SEQUENCE_266 0x3212 +#define ARIZONA_WSEQ_SEQUENCE_267 0x3214 +#define ARIZONA_WSEQ_SEQUENCE_268 0x3216 +#define ARIZONA_WSEQ_SEQUENCE_269 0x3218 +#define ARIZONA_WSEQ_SEQUENCE_270 0x321A +#define ARIZONA_WSEQ_SEQUENCE_271 0x321C +#define ARIZONA_WSEQ_SEQUENCE_272 0x321E +#define ARIZONA_WSEQ_SEQUENCE_273 0x3220 +#define ARIZONA_WSEQ_SEQUENCE_274 0x3222 +#define ARIZONA_WSEQ_SEQUENCE_275 0x3224 +#define ARIZONA_WSEQ_SEQUENCE_276 0x3226 +#define ARIZONA_WSEQ_SEQUENCE_277 0x3228 +#define ARIZONA_WSEQ_SEQUENCE_278 0x322A +#define ARIZONA_WSEQ_SEQUENCE_279 0x322C +#define ARIZONA_WSEQ_SEQUENCE_280 0x322E +#define ARIZONA_WSEQ_SEQUENCE_281 0x3230 +#define ARIZONA_WSEQ_SEQUENCE_282 0x3232 +#define ARIZONA_WSEQ_SEQUENCE_283 0x3234 +#define ARIZONA_WSEQ_SEQUENCE_284 0x3236 +#define ARIZONA_WSEQ_SEQUENCE_285 0x3238 +#define ARIZONA_WSEQ_SEQUENCE_286 0x323A +#define ARIZONA_WSEQ_SEQUENCE_287 0x323C +#define ARIZONA_WSEQ_SEQUENCE_288 0x323E +#define ARIZONA_WSEQ_SEQUENCE_289 0x3240 +#define ARIZONA_WSEQ_SEQUENCE_290 0x3242 +#define ARIZONA_WSEQ_SEQUENCE_291 0x3244 +#define ARIZONA_WSEQ_SEQUENCE_292 0x3246 +#define ARIZONA_WSEQ_SEQUENCE_293 0x3248 +#define ARIZONA_WSEQ_SEQUENCE_294 0x324A +#define ARIZONA_WSEQ_SEQUENCE_295 0x324C +#define ARIZONA_WSEQ_SEQUENCE_296 0x324E +#define ARIZONA_WSEQ_SEQUENCE_297 0x3250 +#define ARIZONA_WSEQ_SEQUENCE_298 0x3252 +#define ARIZONA_WSEQ_SEQUENCE_299 0x3254 +#define ARIZONA_WSEQ_SEQUENCE_300 0x3256 +#define ARIZONA_WSEQ_SEQUENCE_301 0x3258 +#define ARIZONA_WSEQ_SEQUENCE_302 0x325A +#define ARIZONA_WSEQ_SEQUENCE_303 0x325C +#define ARIZONA_WSEQ_SEQUENCE_304 0x325E +#define ARIZONA_WSEQ_SEQUENCE_305 0x3260 +#define ARIZONA_WSEQ_SEQUENCE_306 0x3262 +#define ARIZONA_WSEQ_SEQUENCE_307 0x3264 +#define ARIZONA_WSEQ_SEQUENCE_308 0x3266 +#define ARIZONA_WSEQ_SEQUENCE_309 0x3268 +#define ARIZONA_WSEQ_SEQUENCE_310 0x326A +#define ARIZONA_WSEQ_SEQUENCE_311 0x326C +#define ARIZONA_WSEQ_SEQUENCE_312 0x326E +#define ARIZONA_WSEQ_SEQUENCE_313 0x3270 +#define ARIZONA_WSEQ_SEQUENCE_314 0x3272 +#define ARIZONA_WSEQ_SEQUENCE_315 0x3274 +#define ARIZONA_WSEQ_SEQUENCE_316 0x3276 +#define ARIZONA_WSEQ_SEQUENCE_317 0x3278 +#define ARIZONA_WSEQ_SEQUENCE_318 0x327A +#define ARIZONA_WSEQ_SEQUENCE_319 0x327C +#define ARIZONA_WSEQ_SEQUENCE_320 0x327E +#define ARIZONA_WSEQ_SEQUENCE_321 0x3280 +#define ARIZONA_WSEQ_SEQUENCE_322 0x3282 +#define ARIZONA_WSEQ_SEQUENCE_323 0x3284 +#define ARIZONA_WSEQ_SEQUENCE_324 0x3286 +#define ARIZONA_WSEQ_SEQUENCE_325 0x3288 +#define ARIZONA_WSEQ_SEQUENCE_326 0x328A +#define ARIZONA_WSEQ_SEQUENCE_327 0x328C +#define ARIZONA_WSEQ_SEQUENCE_328 0x328E +#define ARIZONA_WSEQ_SEQUENCE_329 0x3290 +#define ARIZONA_WSEQ_SEQUENCE_330 0x3292 +#define ARIZONA_WSEQ_SEQUENCE_331 0x3294 +#define ARIZONA_WSEQ_SEQUENCE_332 0x3296 +#define ARIZONA_WSEQ_SEQUENCE_333 0x3298 +#define ARIZONA_WSEQ_SEQUENCE_334 0x329A +#define ARIZONA_WSEQ_SEQUENCE_335 0x329C +#define ARIZONA_WSEQ_SEQUENCE_336 0x329E +#define ARIZONA_WSEQ_SEQUENCE_337 0x32A0 +#define ARIZONA_WSEQ_SEQUENCE_338 0x32A2 +#define ARIZONA_WSEQ_SEQUENCE_339 0x32A4 +#define ARIZONA_WSEQ_SEQUENCE_340 0x32A6 +#define ARIZONA_WSEQ_SEQUENCE_341 0x32A8 +#define ARIZONA_WSEQ_SEQUENCE_342 0x32AA +#define ARIZONA_WSEQ_SEQUENCE_343 0x32AC +#define ARIZONA_WSEQ_SEQUENCE_344 0x32AE +#define ARIZONA_WSEQ_SEQUENCE_345 0x32B0 +#define ARIZONA_WSEQ_SEQUENCE_346 0x32B2 +#define ARIZONA_WSEQ_SEQUENCE_347 0x32B4 +#define ARIZONA_WSEQ_SEQUENCE_348 0x32B6 +#define ARIZONA_WSEQ_SEQUENCE_349 0x32B8 +#define ARIZONA_WSEQ_SEQUENCE_350 0x32BA +#define ARIZONA_WSEQ_SEQUENCE_351 0x32BC +#define ARIZONA_WSEQ_SEQUENCE_352 0x32BE +#define ARIZONA_WSEQ_SEQUENCE_353 0x32C0 +#define ARIZONA_WSEQ_SEQUENCE_354 0x32C2 +#define ARIZONA_WSEQ_SEQUENCE_355 0x32C4 +#define ARIZONA_WSEQ_SEQUENCE_356 0x32C6 +#define ARIZONA_WSEQ_SEQUENCE_357 0x32C8 +#define ARIZONA_WSEQ_SEQUENCE_358 0x32CA +#define ARIZONA_WSEQ_SEQUENCE_359 0x32CC +#define ARIZONA_WSEQ_SEQUENCE_360 0x32CE +#define ARIZONA_WSEQ_SEQUENCE_361 0x32D0 +#define ARIZONA_WSEQ_SEQUENCE_362 0x32D2 +#define ARIZONA_WSEQ_SEQUENCE_363 0x32D4 +#define ARIZONA_WSEQ_SEQUENCE_364 0x32D6 +#define ARIZONA_WSEQ_SEQUENCE_365 0x32D8 +#define ARIZONA_WSEQ_SEQUENCE_366 0x32DA +#define ARIZONA_WSEQ_SEQUENCE_367 0x32DC +#define ARIZONA_WSEQ_SEQUENCE_368 0x32DE +#define ARIZONA_WSEQ_SEQUENCE_369 0x32E0 +#define ARIZONA_WSEQ_SEQUENCE_370 0x32E2 +#define ARIZONA_WSEQ_SEQUENCE_371 0x32E4 +#define ARIZONA_WSEQ_SEQUENCE_372 0x32E6 +#define ARIZONA_WSEQ_SEQUENCE_373 0x32E8 +#define ARIZONA_WSEQ_SEQUENCE_374 0x32EA +#define ARIZONA_WSEQ_SEQUENCE_375 0x32EC +#define ARIZONA_WSEQ_SEQUENCE_376 0x32EE +#define ARIZONA_WSEQ_SEQUENCE_377 0x32F0 +#define ARIZONA_WSEQ_SEQUENCE_378 0x32F2 +#define ARIZONA_WSEQ_SEQUENCE_379 0x32F4 +#define ARIZONA_WSEQ_SEQUENCE_380 0x32F6 +#define ARIZONA_WSEQ_SEQUENCE_381 0x32F8 +#define ARIZONA_WSEQ_SEQUENCE_382 0x32FA +#define ARIZONA_WSEQ_SEQUENCE_383 0x32FC +#define ARIZONA_WSEQ_SEQUENCE_384 0x32FE +#define ARIZONA_WSEQ_SEQUENCE_385 0x3300 +#define ARIZONA_WSEQ_SEQUENCE_386 0x3302 +#define ARIZONA_WSEQ_SEQUENCE_387 0x3304 +#define ARIZONA_WSEQ_SEQUENCE_388 0x3306 +#define ARIZONA_WSEQ_SEQUENCE_389 0x3308 +#define ARIZONA_WSEQ_SEQUENCE_390 0x330A +#define ARIZONA_WSEQ_SEQUENCE_391 0x330C +#define ARIZONA_WSEQ_SEQUENCE_392 0x330E +#define ARIZONA_WSEQ_SEQUENCE_393 0x3310 +#define ARIZONA_WSEQ_SEQUENCE_394 0x3312 +#define ARIZONA_WSEQ_SEQUENCE_395 0x3314 +#define ARIZONA_WSEQ_SEQUENCE_396 0x3316 +#define ARIZONA_WSEQ_SEQUENCE_397 0x3318 +#define ARIZONA_WSEQ_SEQUENCE_398 0x331A +#define ARIZONA_WSEQ_SEQUENCE_399 0x331C +#define ARIZONA_WSEQ_SEQUENCE_400 0x331E +#define ARIZONA_WSEQ_SEQUENCE_401 0x3320 +#define ARIZONA_WSEQ_SEQUENCE_402 0x3322 +#define ARIZONA_WSEQ_SEQUENCE_403 0x3324 +#define ARIZONA_WSEQ_SEQUENCE_404 0x3326 +#define ARIZONA_WSEQ_SEQUENCE_405 0x3328 +#define ARIZONA_WSEQ_SEQUENCE_406 0x332A +#define ARIZONA_WSEQ_SEQUENCE_407 0x332C +#define ARIZONA_WSEQ_SEQUENCE_408 0x332E +#define ARIZONA_WSEQ_SEQUENCE_409 0x3330 +#define ARIZONA_WSEQ_SEQUENCE_410 0x3332 +#define ARIZONA_WSEQ_SEQUENCE_411 0x3334 +#define ARIZONA_WSEQ_SEQUENCE_412 0x3336 +#define ARIZONA_WSEQ_SEQUENCE_413 0x3338 +#define ARIZONA_WSEQ_SEQUENCE_414 0x333A +#define ARIZONA_WSEQ_SEQUENCE_415 0x333C +#define ARIZONA_WSEQ_SEQUENCE_416 0x333E +#define ARIZONA_WSEQ_SEQUENCE_417 0x3340 +#define ARIZONA_WSEQ_SEQUENCE_418 0x3342 +#define ARIZONA_WSEQ_SEQUENCE_419 0x3344 +#define ARIZONA_WSEQ_SEQUENCE_420 0x3346 +#define ARIZONA_WSEQ_SEQUENCE_421 0x3348 +#define ARIZONA_WSEQ_SEQUENCE_422 0x334A +#define ARIZONA_WSEQ_SEQUENCE_423 0x334C +#define ARIZONA_WSEQ_SEQUENCE_424 0x334E +#define ARIZONA_WSEQ_SEQUENCE_425 0x3350 +#define ARIZONA_WSEQ_SEQUENCE_426 0x3352 +#define ARIZONA_WSEQ_SEQUENCE_427 0x3354 +#define ARIZONA_WSEQ_SEQUENCE_428 0x3356 +#define ARIZONA_WSEQ_SEQUENCE_429 0x3358 +#define ARIZONA_WSEQ_SEQUENCE_430 0x335A +#define ARIZONA_WSEQ_SEQUENCE_431 0x335C +#define ARIZONA_WSEQ_SEQUENCE_432 0x335E +#define ARIZONA_WSEQ_SEQUENCE_433 0x3360 +#define ARIZONA_WSEQ_SEQUENCE_434 0x3362 +#define ARIZONA_WSEQ_SEQUENCE_435 0x3364 +#define ARIZONA_WSEQ_SEQUENCE_436 0x3366 +#define ARIZONA_WSEQ_SEQUENCE_437 0x3368 +#define ARIZONA_WSEQ_SEQUENCE_438 0x336A +#define ARIZONA_WSEQ_SEQUENCE_439 0x336C +#define ARIZONA_WSEQ_SEQUENCE_440 0x336E +#define ARIZONA_WSEQ_SEQUENCE_441 0x3370 +#define ARIZONA_WSEQ_SEQUENCE_442 0x3372 +#define ARIZONA_WSEQ_SEQUENCE_443 0x3374 +#define ARIZONA_WSEQ_SEQUENCE_444 0x3376 +#define ARIZONA_WSEQ_SEQUENCE_445 0x3378 +#define ARIZONA_WSEQ_SEQUENCE_446 0x337A +#define ARIZONA_WSEQ_SEQUENCE_447 0x337C +#define ARIZONA_WSEQ_SEQUENCE_448 0x337E +#define ARIZONA_WSEQ_SEQUENCE_449 0x3380 +#define ARIZONA_WSEQ_SEQUENCE_450 0x3382 +#define ARIZONA_WSEQ_SEQUENCE_451 0x3384 +#define ARIZONA_WSEQ_SEQUENCE_452 0x3386 +#define ARIZONA_WSEQ_SEQUENCE_453 0x3388 +#define ARIZONA_WSEQ_SEQUENCE_454 0x338A +#define ARIZONA_WSEQ_SEQUENCE_455 0x338C +#define ARIZONA_WSEQ_SEQUENCE_456 0x338E +#define ARIZONA_WSEQ_SEQUENCE_457 0x3390 +#define ARIZONA_WSEQ_SEQUENCE_458 0x3392 +#define ARIZONA_WSEQ_SEQUENCE_459 0x3394 +#define ARIZONA_WSEQ_SEQUENCE_460 0x3396 +#define ARIZONA_WSEQ_SEQUENCE_461 0x3398 +#define ARIZONA_WSEQ_SEQUENCE_462 0x339A +#define ARIZONA_WSEQ_SEQUENCE_463 0x339C +#define ARIZONA_WSEQ_SEQUENCE_464 0x339E +#define ARIZONA_WSEQ_SEQUENCE_465 0x33A0 +#define ARIZONA_WSEQ_SEQUENCE_466 0x33A2 +#define ARIZONA_WSEQ_SEQUENCE_467 0x33A4 +#define ARIZONA_WSEQ_SEQUENCE_468 0x33A6 +#define ARIZONA_WSEQ_SEQUENCE_469 0x33A8 +#define ARIZONA_WSEQ_SEQUENCE_470 0x33AA +#define ARIZONA_WSEQ_SEQUENCE_471 0x33AC +#define ARIZONA_WSEQ_SEQUENCE_472 0x33AE +#define ARIZONA_WSEQ_SEQUENCE_473 0x33B0 +#define ARIZONA_WSEQ_SEQUENCE_474 0x33B2 +#define ARIZONA_WSEQ_SEQUENCE_475 0x33B4 +#define ARIZONA_WSEQ_SEQUENCE_476 0x33B6 +#define ARIZONA_WSEQ_SEQUENCE_477 0x33B8 +#define ARIZONA_WSEQ_SEQUENCE_478 0x33BA +#define ARIZONA_WSEQ_SEQUENCE_479 0x33BC +#define ARIZONA_WSEQ_SEQUENCE_480 0x33BE +#define ARIZONA_WSEQ_SEQUENCE_481 0x33C0 +#define ARIZONA_WSEQ_SEQUENCE_482 0x33C2 +#define ARIZONA_WSEQ_SEQUENCE_483 0x33C4 +#define ARIZONA_WSEQ_SEQUENCE_484 0x33C6 +#define ARIZONA_WSEQ_SEQUENCE_485 0x33C8 +#define ARIZONA_WSEQ_SEQUENCE_486 0x33CA +#define ARIZONA_WSEQ_SEQUENCE_487 0x33CC +#define ARIZONA_WSEQ_SEQUENCE_488 0x33CE +#define ARIZONA_WSEQ_SEQUENCE_489 0x33D0 +#define ARIZONA_WSEQ_SEQUENCE_490 0x33D2 +#define ARIZONA_WSEQ_SEQUENCE_491 0x33D4 +#define ARIZONA_WSEQ_SEQUENCE_492 0x33D6 +#define ARIZONA_WSEQ_SEQUENCE_493 0x33D8 +#define ARIZONA_WSEQ_SEQUENCE_494 0x33DA +#define ARIZONA_WSEQ_SEQUENCE_495 0x33DC +#define ARIZONA_WSEQ_SEQUENCE_496 0x33DE +#define ARIZONA_WSEQ_SEQUENCE_497 0x33E0 +#define ARIZONA_WSEQ_SEQUENCE_498 0x33E2 +#define ARIZONA_WSEQ_SEQUENCE_499 0x33E4 +#define ARIZONA_WSEQ_SEQUENCE_500 0x33E6 +#define ARIZONA_WSEQ_SEQUENCE_501 0x33E8 +#define ARIZONA_WSEQ_SEQUENCE_502 0x33EA +#define ARIZONA_WSEQ_SEQUENCE_503 0x33EC +#define ARIZONA_WSEQ_SEQUENCE_504 0x33EE +#define ARIZONA_WSEQ_SEQUENCE_505 0x33F0 +#define ARIZONA_WSEQ_SEQUENCE_506 0x33F2 +#define ARIZONA_WSEQ_SEQUENCE_507 0x33F4 +#define ARIZONA_WSEQ_SEQUENCE_508 0x33F6 +#define MARLEY_OTP_HPDET_CALIB_1 0x31F8 +#define MARLEY_OTP_HPDET_CALIB_2 0x31FA +#define CLEARWATER_OTP_HPDET_CALIB_1 0x33F8 +#define CLEARWATER_OTP_HPDET_CALIB_2 0x33FA +#define MOON_OTP_HPDET_CALIB_1 0x020004 +#define MOON_OTP_HPDET_CALIB_2 0x020006 +#define CLEARWATER_DSP1_CONFIG 0x0FFE00 +#define CLEARWATER_DSP1_STATUS_1 0x0FFE04 +#define CLEARWATER_DSP1_STATUS_2 0x0FFE06 +#define MOON_DSP1_WATCHDOG 0x0FFE0A +#define CLEARWATER_DSP1_WDMA_CONFIG_1 0x0FFE30 +#define CLEARWATER_DSP1_WDMA_CONFIG_2 0x0FFE32 +#define CLEARWATER_DSP1_RDMA_CONFIG_1 0x0FFE34 +#define CLEARWATER_DSP1_SCRATCH_0_1 0x0FFE40 +#define CLEARWATER_DSP1_SCRATCH_2_3 0x0FFE42 +#define MOON_DSP1_BUS_ERR_ADDR 0x0FFE52 +#define MOON_DSP1_REGION_LOCK_STATUS 0x0FFE64 +#define MOON_DSP1_LOCK_REGION_1_LOCK_REGION_0 0x0FFE66 +#define MOON_DSP1_LOCK_REGION_3_LOCK_REGION_2 0x0FFE68 +#define MOON_DSP1_LOCK_REGION_5_LOCK_REGION_4 0x0FFE6A +#define MOON_DSP1_LOCK_REGION_7_LOCK_REGION_6 0x0FFE6C +#define MOON_DSP1_LOCK_REGION_9_LOCK_REGION_8 0x0FFE6E +#define MOON_DSP1_LOCK_REGION_CTRL 0x0FFE7A +#define MOON_DSP1_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x0FFE7C +#define CLEARWATER_DSP2_CONFIG 0x17FE00 +#define CLEARWATER_DSP2_STATUS_1 0x17FE04 +#define CLEARWATER_DSP2_STATUS_2 0x17FE06 +#define MOON_DSP2_WATCHDOG 0x17FE0A +#define CLEARWATER_DSP2_WDMA_CONFIG_1 0x17FE30 +#define CLEARWATER_DSP2_WDMA_CONFIG_2 0x17FE32 +#define CLEARWATER_DSP2_RDMA_CONFIG_1 0x17FE34 +#define CLEARWATER_DSP2_SCRATCH_0_1 0x17FE40 +#define CLEARWATER_DSP2_SCRATCH_2_3 0x17FE42 +#define MOON_DSP2_BUS_ERR_ADDR 0x17FE52 +#define MOON_DSP2_REGION_LOCK_STATUS 0x17FE64 +#define MOON_DSP2_LOCK_REGION_1_LOCK_REGION_0 0x17FE66 +#define MOON_DSP2_LOCK_REGION_3_LOCK_REGION_2 0x17FE68 +#define MOON_DSP2_LOCK_REGION_5_LOCK_REGION_4 0x17FE6A +#define MOON_DSP2_LOCK_REGION_7_LOCK_REGION_6 0x17FE6C +#define MOON_DSP2_LOCK_REGION_9_LOCK_REGION_8 0x17FE6E +#define MOON_DSP2_LOCK_REGION_CTRL 0x17FE7A +#define MOON_DSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x17FE7C +#define CLEARWATER_DSP3_CONFIG 0x1FFE00 +#define CLEARWATER_DSP3_STATUS_1 0x1FFE04 +#define CLEARWATER_DSP3_STATUS_2 0x1FFE06 +#define MOON_DSP3_WATCHDOG 0x1FFE0A +#define CLEARWATER_DSP3_WDMA_CONFIG_1 0x1FFE30 +#define CLEARWATER_DSP3_WDMA_CONFIG_2 0x1FFE32 +#define CLEARWATER_DSP3_RDMA_CONFIG_1 0x1FFE34 +#define CLEARWATER_DSP3_SCRATCH_0_1 0x1FFE40 +#define CLEARWATER_DSP3_SCRATCH_2_3 0x1FFE42 +#define MOON_DSP3_BUS_ERR_ADDR 0x1FFE52 +#define MOON_DSP3_REGION_LOCK_STATUS 0x1FFE64 +#define MOON_DSP3_LOCK_REGION_1_LOCK_REGION_0 0x1FFE66 +#define MOON_DSP3_LOCK_REGION_3_LOCK_REGION_2 0x1FFE68 +#define MOON_DSP3_LOCK_REGION_5_LOCK_REGION_4 0x1FFE6A +#define MOON_DSP3_LOCK_REGION_7_LOCK_REGION_6 0x1FFE6C +#define MOON_DSP3_LOCK_REGION_9_LOCK_REGION_8 0x1FFE6E +#define MOON_DSP3_LOCK_REGION_CTRL 0x1FFE7A +#define MOON_DSP3_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x1FFE7C +#define CLEARWATER_DSP4_CONFIG 0x27FE00 +#define CLEARWATER_DSP4_STATUS_1 0x27FE04 +#define CLEARWATER_DSP4_STATUS_2 0x27FE06 +#define MOON_DSP4_WATCHDOG 0x27FE0A +#define CLEARWATER_DSP4_WDMA_CONFIG_1 0x27FE30 +#define CLEARWATER_DSP4_WDMA_CONFIG_2 0x27FE32 +#define CLEARWATER_DSP4_RDMA_CONFIG_1 0x27FE34 +#define CLEARWATER_DSP4_SCRATCH_0_1 0x27FE40 +#define CLEARWATER_DSP4_SCRATCH_2_3 0x27FE42 +#define MOON_DSP4_BUS_ERR_ADDR 0x27FE52 +#define MOON_DSP4_REGION_LOCK_STATUS 0x27FE64 +#define MOON_DSP4_LOCK_REGION_1_LOCK_REGION_0 0x27FE66 +#define MOON_DSP4_LOCK_REGION_3_LOCK_REGION_2 0x27FE68 +#define MOON_DSP4_LOCK_REGION_5_LOCK_REGION_4 0x27FE6A +#define MOON_DSP4_LOCK_REGION_7_LOCK_REGION_6 0x27FE6C +#define MOON_DSP4_LOCK_REGION_9_LOCK_REGION_8 0x27FE6E +#define MOON_DSP4_LOCK_REGION_CTRL 0x27FE7A +#define MOON_DSP4_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x27FE7C +#define CLEARWATER_DSP5_CONFIG 0x2FFE00 +#define CLEARWATER_DSP5_STATUS_1 0x2FFE04 +#define CLEARWATER_DSP5_STATUS_2 0x2FFE06 +#define MOON_DSP5_WATCHDOG 0x2FFE0A +#define CLEARWATER_DSP5_WDMA_CONFIG_1 0x2FFE30 +#define CLEARWATER_DSP5_WDMA_CONFIG_2 0x2FFE32 +#define CLEARWATER_DSP5_RDMA_CONFIG_1 0x2FFE34 +#define CLEARWATER_DSP5_SCRATCH_0_1 0x2FFE40 +#define CLEARWATER_DSP5_SCRATCH_2_3 0x2FFE42 +#define MOON_DSP5_BUS_ERR_ADDR 0x2FFE52 +#define MOON_DSP5_REGION_LOCK_STATUS 0x2FFE64 +#define MOON_DSP5_LOCK_REGION_1_LOCK_REGION_0 0x2FFE66 +#define MOON_DSP5_LOCK_REGION_3_LOCK_REGION_2 0x2FFE68 +#define MOON_DSP5_LOCK_REGION_5_LOCK_REGION_4 0x2FFE6A +#define MOON_DSP5_LOCK_REGION_7_LOCK_REGION_6 0x2FFE6C +#define MOON_DSP5_LOCK_REGION_9_LOCK_REGION_8 0x2FFE6E +#define MOON_DSP5_LOCK_REGION_CTRL 0x2FFE7A +#define MOON_DSP5_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x2FFE7C +#define CLEARWATER_DSP6_CONFIG 0x37FE00 +#define CLEARWATER_DSP6_STATUS_1 0x37FE04 +#define CLEARWATER_DSP6_STATUS_2 0x37FE06 +#define MOON_DSP6_WATCHDOG 0x37FE0A +#define CLEARWATER_DSP6_WDMA_CONFIG_1 0x37FE30 +#define CLEARWATER_DSP6_WDMA_CONFIG_2 0x37FE32 +#define CLEARWATER_DSP6_RDMA_CONFIG_1 0x37FE34 +#define CLEARWATER_DSP6_SCRATCH_0_1 0x37FE40 +#define CLEARWATER_DSP6_SCRATCH_2_3 0x37FE42 +#define MOON_DSP6_BUS_ERR_ADDR 0x37FE52 +#define MOON_DSP6_REGION_LOCK_STATUS 0x37FE64 +#define MOON_DSP6_LOCK_REGION_1_LOCK_REGION_0 0x37FE66 +#define MOON_DSP6_LOCK_REGION_3_LOCK_REGION_2 0x37FE68 +#define MOON_DSP6_LOCK_REGION_5_LOCK_REGION_4 0x37FE6A +#define MOON_DSP6_LOCK_REGION_7_LOCK_REGION_6 0x37FE6C +#define MOON_DSP6_LOCK_REGION_9_LOCK_REGION_8 0x37FE6E +#define MOON_DSP6_LOCK_REGION_CTRL 0x37FE7A +#define MOON_DSP6_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x37FE7C +#define CLEARWATER_DSP7_CONFIG 0x3FFE00 +#define CLEARWATER_DSP7_STATUS_1 0x3FFE04 +#define CLEARWATER_DSP7_STATUS_2 0x3FFE06 +#define MOON_DSP7_WATCHDOG 0x3FFE0A +#define CLEARWATER_DSP7_WDMA_CONFIG_1 0x3FFE30 +#define CLEARWATER_DSP7_WDMA_CONFIG_2 0x3FFE32 +#define CLEARWATER_DSP7_RDMA_CONFIG_1 0x3FFE34 +#define CLEARWATER_DSP7_SCRATCH_0_1 0x3FFE40 +#define CLEARWATER_DSP7_SCRATCH_2_3 0x3FFE42 +#define MOON_DSP7_BUS_ERR_ADDR 0x3FFE52 +#define MOON_DSP7_REGION_LOCK_STATUS 0x3FFE64 +#define MOON_DSP7_LOCK_REGION_1_LOCK_REGION_0 0x3FFE66 +#define MOON_DSP7_LOCK_REGION_3_LOCK_REGION_2 0x3FFE68 +#define MOON_DSP7_LOCK_REGION_5_LOCK_REGION_4 0x3FFE6A +#define MOON_DSP7_LOCK_REGION_7_LOCK_REGION_6 0x3FFE6C +#define MOON_DSP7_LOCK_REGION_9_LOCK_REGION_8 0x3FFE6E +#define MOON_DSP7_LOCK_REGION_CTRL 0x3FFE7A +#define MOON_DSP7_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x3FFE7C /* * Field Definitions. @@ -1283,6 +2697,42 @@ #define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */ #define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */ +/* + * R66 (0x42) - Spare Triggers + */ +#define ARIZONA_WS_TRG8 0x0080 /* WS_TRG8 */ +#define ARIZONA_WS_TRG8_MASK 0x0080 /* WS_TRG8 */ +#define ARIZONA_WS_TRG8_SHIFT 7 /* WS_TRG8 */ +#define ARIZONA_WS_TRG8_WIDTH 1 /* WS_TRG8 */ +#define ARIZONA_WS_TRG7 0x0040 /* WS_TRG7 */ +#define ARIZONA_WS_TRG7_MASK 0x0040 /* WS_TRG7 */ +#define ARIZONA_WS_TRG7_SHIFT 6 /* WS_TRG7 */ +#define ARIZONA_WS_TRG7_WIDTH 1 /* WS_TRG7 */ +#define ARIZONA_WS_TRG6 0x0020 /* WS_TRG6 */ +#define ARIZONA_WS_TRG6_MASK 0x0020 /* WS_TRG6 */ +#define ARIZONA_WS_TRG6_SHIFT 5 /* WS_TRG6 */ +#define ARIZONA_WS_TRG6_WIDTH 1 /* WS_TRG6 */ +#define ARIZONA_WS_TRG5 0x0010 /* WS_TRG5 */ +#define ARIZONA_WS_TRG5_MASK 0x0010 /* WS_TRG5 */ +#define ARIZONA_WS_TRG5_SHIFT 4 /* WS_TRG5 */ +#define ARIZONA_WS_TRG5_WIDTH 1 /* WS_TRG5 */ +#define ARIZONA_WS_TRG4 0x0008 /* WS_TRG4 */ +#define ARIZONA_WS_TRG4_MASK 0x0008 /* WS_TRG4 */ +#define ARIZONA_WS_TRG4_SHIFT 3 /* WS_TRG4 */ +#define ARIZONA_WS_TRG4_WIDTH 1 /* WS_TRG4 */ +#define ARIZONA_WS_TRG3 0x0004 /* WS_TRG3 */ +#define ARIZONA_WS_TRG3_MASK 0x0004 /* WS_TRG3 */ +#define ARIZONA_WS_TRG3_SHIFT 2 /* WS_TRG3 */ +#define ARIZONA_WS_TRG3_WIDTH 1 /* WS_TRG3 */ +#define ARIZONA_WS_TRG2 0x0002 /* WS_TRG2 */ +#define ARIZONA_WS_TRG2_MASK 0x0002 /* WS_TRG2 */ +#define ARIZONA_WS_TRG2_SHIFT 1 /* WS_TRG2 */ +#define ARIZONA_WS_TRG2_WIDTH 1 /* WS_TRG2 */ +#define ARIZONA_WS_TRG1 0x0001 /* WS_TRG1 */ +#define ARIZONA_WS_TRG1_MASK 0x0001 /* WS_TRG1 */ +#define ARIZONA_WS_TRG1_SHIFT 0 /* WS_TRG1 */ +#define ARIZONA_WS_TRG1_WIDTH 1 /* WS_TRG1 */ + /* * R97 (0x61) - Sample Rate Sequence Select 1 */ @@ -1442,6 +2892,17 @@ #define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */ #define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */ +/* + * R160 (0xA0) - Clearwater Comfort Noise Generator + */ +#define CLEARWATER_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */ +#define CLEARWATER_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */ +#define CLEARWATER_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */ +#define CLEARWATER_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */ +#define CLEARWATER_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */ +#define CLEARWATER_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */ +#define CLEARWATER_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */ + /* * R256 (0x100) - Clock 32k 1 */ @@ -1530,16 +2991,53 @@ /* * R275 (0x113) - Async sample rate 1 */ -#define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */ -#define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */ -#define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_1_MASK 0x001F /* ASYNC_SAMPLE_RATE_1 - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_1_SHIFT 0 /* ASYNC_SAMPLE_RATE_1 - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_1_WIDTH 5 /* ASYNC_SAMPLE_RATE_1 - [4:0] */ + +/* + * R276 (0x114) - Async sample rate 2 + */ +#define ARIZONA_ASYNC_SAMPLE_RATE_2_MASK 0x001F /* ASYNC_SAMPLE_RATE_2 - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_2_SHIFT 0 /* ASYNC_SAMPLE_RATE_2 - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_2_WIDTH 5 /* ASYNC_SAMPLE_RATE_2 - [4:0] */ /* * R283 (0x11B) - Async sample rate 1 status */ -#define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */ -#define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */ -#define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_1_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_1_STS - [4:0] */ + +/* + * R284 (0x11C) - Async sample rate 2 status + */ +#define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */ +#define ARIZONA_ASYNC_SAMPLE_RATE_2_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_2_STS - [4:0] */ + +/* + * R109 (0x120) - DSP_Clock_1 + */ +#define CLEARWATER_DSP_CLK_FREQ_LEGACY 0x0700 /* DSP_CLK_FREQ_LEGACY - [10:8] */ +#define CLEARWATER_DSP_CLK_FREQ_LEGACY_MASK 0x0700 /* DSP_CLK_FREQ_LEGACY - [10:8] */ +#define CLEARWATER_DSP_CLK_FREQ_LEGACY_SHIFT 8 /* DSP_CLK_FREQ_LEGACY - [10:8] */ +#define CLEARWATER_DSP_CLK_FREQ_LEGACY_WIDTH 3 /* DSP_CLK_FREQ_LEGACY - [10:8] */ +#define CLEARWATER_DSP_CLK_ENA 0x0040 /* DSP_CLK_ENA */ +#define CLEARWATER_DSP_CLK_ENA_MASK 0x0040 /* DSP_CLK_ENA */ +#define CLEARWATER_DSP_CLK_ENA_SHIFT 6 /* DSP_CLK_ENA */ +#define CLEARWATER_DSP_CLK_ENA_WIDTH 1 /* DSP_CLK_ENA */ +#define CLEARWATER_DSP_CLK_SRC 0x000F /* DSP_CLK_SRC - [3:0] */ +#define CLEARWATER_DSP_CLK_SRC_MASK 0x000F /* DSP_CLK_SRC - [3:0] */ +#define CLEARWATER_DSP_CLK_SRC_SHIFT 0 /* DSP_CLK_SRC - [3:0] */ +#define CLEARWATER_DSP_CLK_SRC_WIDTH 4 /* DSP_CLK_SRC - [3:0] */ + +/* + * R110 (0x122) - DSP_Clock_2 + */ +#define CLEARWATER_DSP_CLK_FREQ_MASK 0x03FF /* DSP_CLK_FREQ - [9:0] */ +#define CLEARWATER_DSP_CLK_FREQ_SHIFT 0 /* DSP_CLK_FREQ - [9:0] */ +#define CLEARWATER_DSP_CLK_FREQ_WIDTH 10 /* DSP_CLK_FREQ - [9:0] */ /* * R329 (0x149) - Output system clock @@ -1659,9 +3157,9 @@ /* * R373 (0x175) - FLL1 Control 5 */ -#define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */ -#define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */ -#define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */ +#define ARIZONA_FLL1_FRATIO_MASK 0x0F00 /* FLL1_FRATIO - [11:8] */ +#define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [11:8] */ +#define ARIZONA_FLL1_FRATIO_WIDTH 4 /* FLL1_FRATIO - [11:8] */ #define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */ #define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */ #define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */ @@ -1694,6 +3192,16 @@ #define ARIZONA_FLL1_GAIN_SHIFT 2 /* FLL1_GAIN */ #define ARIZONA_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN */ +/* + * R378 (0x17A) - FLL1 EFS 2 + */ +#define ARIZONA_FLL1_PHASE_GAIN_MASK 0xF000 /* FLL1_PHASE_GAIN */ +#define ARIZONA_FLL1_PHASE_GAIN_SHIFT 12 /* FLL1_PHASE_GAIN */ +#define ARIZONA_FLL1_PHASE_GAIN_WIDTH 4 /* FLL1_PHASE_GAIN */ +#define ARIZONA_FLL1_PHASE_ENA_MASK 0x0800 /* FLL1_PHASE_ENA */ +#define ARIZONA_FLL1_PHASE_ENA_SHIFT 11 /* FLL1_PHASE_ENA */ +#define ARIZONA_FLL1_PHASE_ENA_WIDTH 1 /* FLL1_PHASE_ENA */ + /* * R385 (0x181) - FLL1 Synchroniser 1 */ @@ -1902,7 +3410,7 @@ #define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */ #define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */ #define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */ -#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */ +#define ARIZONA_FLL2_SYNC_BW 0x0001 /* FLL2_SYNC_BW */ #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */ #define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */ #define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */ @@ -1931,6 +3439,317 @@ #define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */ #define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */ +/* + * R433 (0x1B1) - FLL3 Control 1 + */ +#define ARIZONA_FLL3_FREERUN 0x0002 /* FLL3_FREERUN */ +#define ARIZONA_FLL3_FREERUN_MASK 0x0002 /* FLL3_FREERUN */ +#define ARIZONA_FLL3_FREERUN_SHIFT 1 /* FLL3_FREERUN */ +#define ARIZONA_FLL3_FREERUN_WIDTH 1 /* FLL3_FREERUN */ +#define ARIZONA_FLL3_ENA 0x0001 /* FLL3_ENA */ +#define ARIZONA_FLL3_ENA_MASK 0x0001 /* FLL3_ENA */ +#define ARIZONA_FLL3_ENA_SHIFT 0 /* FLL3_ENA */ +#define ARIZONA_FLL3_ENA_WIDTH 1 /* FLL3_ENA */ + +/* + * R434 (0x1B2) - FLL3 Control 2 + */ +#define ARIZONA_FLL3_CTRL_UPD 0x8000 /* FLL3_CTRL_UPD */ +#define ARIZONA_FLL3_CTRL_UPD_MASK 0x8000 /* FLL3_CTRL_UPD */ +#define ARIZONA_FLL3_CTRL_UPD_SHIFT 15 /* FLL3_CTRL_UPD */ +#define ARIZONA_FLL3_CTRL_UPD_WIDTH 1 /* FLL3_CTRL_UPD */ +#define ARIZONA_FLL3_N_MASK 0x03FF /* FLL3_N - [9:0] */ +#define ARIZONA_FLL3_N_SHIFT 0 /* FLL3_N - [9:0] */ +#define ARIZONA_FLL3_N_WIDTH 10 /* FLL3_N - [9:0] */ + +/* + * R435 (0x1B3) - FLL3 Control 3 + */ +#define ARIZONA_FLL3_THETA_MASK 0xFFFF /* FLL3_THETA - [15:0] */ +#define ARIZONA_FLL3_THETA_SHIFT 0 /* FLL3_THETA - [15:0] */ +#define ARIZONA_FLL3_THETA_WIDTH 16 /* FLL3_THETA - [15:0] */ + +/* + * R436 (0x1B4) - FLL3 Control 4 + */ +#define ARIZONA_FLL3_LAMBDA_MASK 0xFFFF /* FLL3_LAMBDA - [15:0] */ +#define ARIZONA_FLL3_LAMBDA_SHIFT 0 /* FLL3_LAMBDA - [15:0] */ +#define ARIZONA_FLL3_LAMBDA_WIDTH 16 /* FLL3_LAMBDA - [15:0] */ + +/* + * R437 (0x1B5) - FLL3 Control 5 + */ +#define ARIZONA_FLL3_FRATIO_MASK 0x0700 /* FLL3_FRATIO - [10:8] */ +#define ARIZONA_FLL3_FRATIO_SHIFT 8 /* FLL3_FRATIO - [10:8] */ +#define ARIZONA_FLL3_FRATIO_WIDTH 3 /* FLL3_FRATIO - [10:8] */ +#define ARIZONA_FLL3_OUTDIV_MASK 0x000E /* FLL3_OUTDIV - [3:1] */ +#define ARIZONA_FLL3_OUTDIV_SHIFT 1 /* FLL3_OUTDIV - [3:1] */ +#define ARIZONA_FLL3_OUTDIV_WIDTH 3 /* FLL3_OUTDIV - [3:1] */ + +/* + * R438 (0x1B6) - FLL3 Control 6 + */ +#define ARIZONA_FLL3_CLK_REF_DIV_MASK 0x00C0 /* FLL3_CLK_REF_DIV - [7:6] */ +#define ARIZONA_FLL3_CLK_REF_DIV_SHIFT 6 /* FLL3_CLK_REF_DIV - [7:6] */ +#define ARIZONA_FLL3_CLK_REF_DIV_WIDTH 2 /* FLL3_CLK_REF_DIV - [7:6] */ +#define ARIZONA_FLL3_CLK_REF_SRC_MASK 0x000F /* FLL3_CLK_REF_SRC - [3:0] */ +#define ARIZONA_FLL3_CLK_REF_SRC_SHIFT 0 /* FLL3_CLK_REF_SRC - [3:0] */ +#define ARIZONA_FLL3_CLK_REF_SRC_WIDTH 4 /* FLL3_CLK_REF_SRC - [3:0] */ + +/* + * R439 (0x1B7) - FLL3 Loop Filter Test 1 + */ +#define ARIZONA_FLL3_FRC_INTEG_UPD 0x8000 /* FLL3_FRC_INTEG_UPD */ +#define ARIZONA_FLL3_FRC_INTEG_UPD_MASK 0x8000 /* FLL3_FRC_INTEG_UPD */ +#define ARIZONA_FLL3_FRC_INTEG_UPD_SHIFT 15 /* FLL3_FRC_INTEG_UPD */ +#define ARIZONA_FLL3_FRC_INTEG_UPD_WIDTH 1 /* FLL3_FRC_INTEG_UPD */ +#define ARIZONA_FLL3_FRC_INTEG_VAL_MASK 0x0FFF /* FLL3_FRC_INTEG_VAL - [11:0] */ +#define ARIZONA_FLL3_FRC_INTEG_VAL_SHIFT 0 /* FLL3_FRC_INTEG_VAL - [11:0] */ +#define ARIZONA_FLL3_FRC_INTEG_VAL_WIDTH 12 /* FLL3_FRC_INTEG_VAL - [11:0] */ + +/* + * R441 (0x1B9) - FLL3 Control 7 + */ +#define ARIZONA_FLL3_GAIN_MASK 0x003c /* FLL3_GAIN */ +#define ARIZONA_FLL3_GAIN_SHIFT 2 /* FLL3_GAIN */ +#define ARIZONA_FLL3_GAIN_WIDTH 4 /* FLL3_GAIN */ + +/* + * R449 (0x1C1) - FLL3 Synchroniser 1 + */ +#define ARIZONA_FLL3_SYNC_ENA 0x0001 /* FLL3_SYNC_ENA */ +#define ARIZONA_FLL3_SYNC_ENA_MASK 0x0001 /* FLL3_SYNC_ENA */ +#define ARIZONA_FLL3_SYNC_ENA_SHIFT 0 /* FLL3_SYNC_ENA */ +#define ARIZONA_FLL3_SYNC_ENA_WIDTH 1 /* FLL3_SYNC_ENA */ + +/* + * R450 (0x1C2) - FLL3 Synchroniser 2 + */ +#define ARIZONA_FLL3_SYNC_N_MASK 0x03FF /* FLL3_SYNC_N - [9:0] */ +#define ARIZONA_FLL3_SYNC_N_SHIFT 0 /* FLL3_SYNC_N - [9:0] */ +#define ARIZONA_FLL3_SYNC_N_WIDTH 10 /* FLL3_SYNC_N - [9:0] */ + +/* + * R451 (0x1C3) - FLL3 Synchroniser 3 + */ +#define ARIZONA_FLL3_SYNC_THETA_MASK 0xFFFF /* FLL3_SYNC_THETA - [15:0] */ +#define ARIZONA_FLL3_SYNC_THETA_SHIFT 0 /* FLL3_SYNC_THETA - [15:0] */ +#define ARIZONA_FLL3_SYNC_THETA_WIDTH 16 /* FLL3_SYNC_THETA - [15:0] */ + +/* + * R452 (0x1C4) - FLL3 Synchroniser 4 + */ +#define ARIZONA_FLL3_SYNC_LAMBDA_MASK 0xFFFF /* FLL3_SYNC_LAMBDA - [15:0] */ +#define ARIZONA_FLL3_SYNC_LAMBDA_SHIFT 0 /* FLL3_SYNC_LAMBDA - [15:0] */ +#define ARIZONA_FLL3_SYNC_LAMBDA_WIDTH 16 /* FLL3_SYNC_LAMBDA - [15:0] */ + +/* + * R453 (0x1C5) - FLL3 Synchroniser 5 + */ +#define ARIZONA_FLL3_SYNC_FRATIO_MASK 0x0700 /* FLL3_SYNC_FRATIO - [10:8] */ +#define ARIZONA_FLL3_SYNC_FRATIO_SHIFT 8 /* FLL3_SYNC_FRATIO - [10:8] */ +#define ARIZONA_FLL3_SYNC_FRATIO_WIDTH 3 /* FLL3_SYNC_FRATIO - [10:8] */ + +/* + * R454 (0x1C6) - FLL3 Synchroniser 6 + */ +#define ARIZONA_FLL3_CLK_SYNC_DIV_MASK 0x00C0 /* FLL3_CLK_SYNC_DIV - [7:6] */ +#define ARIZONA_FLL3_CLK_SYNC_DIV_SHIFT 6 /* FLL3_CLK_SYNC_DIV - [7:6] */ +#define ARIZONA_FLL3_CLK_SYNC_DIV_WIDTH 2 /* FLL3_CLK_SYNC_DIV - [7:6] */ +#define ARIZONA_FLL3_CLK_SYNC_SRC_MASK 0x000F /* FLL3_CLK_SYNC_SRC - [3:0] */ +#define ARIZONA_FLL3_CLK_SYNC_SRC_SHIFT 0 /* FLL3_CLK_SYNC_SRC - [3:0] */ +#define ARIZONA_FLL3_CLK_SYNC_SRC_WIDTH 4 /* FLL3_CLK_SYNC_SRC - [3:0] */ + +/* + * R455 (0x1C7) - FLL3 Synchroniser 7 + */ +#define ARIZONA_FLL3_SYNC_GAIN_MASK 0x003c /* FLL3_SYNC_GAIN */ +#define ARIZONA_FLL3_SYNC_GAIN_SHIFT 2 /* FLL3_SYNC_GAIN */ +#define ARIZONA_FLL3_SYNC_GAIN_WIDTH 4 /* FLL3_SYNC_GAIN */ +#define ARIZONA_FLL3_SYNC_BW 0x0001 /* FLL3_SYNC_BW */ +#define ARIZONA_FLL3_SYNC_BW_MASK 0x0001 /* FLL3_SYNC_BW */ +#define ARIZONA_FLL3_SYNC_BW_SHIFT 0 /* FLL3_SYNC_BW */ +#define ARIZONA_FLL3_SYNC_BW_WIDTH 1 /* FLL3_SYNC_BW */ + +/* + * R457 (0x1C9) - FLL3 Spread Spectrum + */ +#define ARIZONA_FLL3_SS_AMPL_MASK 0x0030 /* FLL3_SS_AMPL - [5:4] */ +#define ARIZONA_FLL3_SS_AMPL_SHIFT 4 /* FLL3_SS_AMPL - [5:4] */ +#define ARIZONA_FLL3_SS_AMPL_WIDTH 2 /* FLL3_SS_AMPL - [5:4] */ +#define ARIZONA_FLL3_SS_FREQ_MASK 0x000C /* FLL3_SS_FREQ - [3:2] */ +#define ARIZONA_FLL3_SS_FREQ_SHIFT 2 /* FLL3_SS_FREQ - [3:2] */ +#define ARIZONA_FLL3_SS_FREQ_WIDTH 2 /* FLL3_SS_FREQ - [3:2] */ +#define ARIZONA_FLL3_SS_SEL_MASK 0x0003 /* FLL3_SS_SEL - [1:0] */ +#define ARIZONA_FLL3_SS_SEL_SHIFT 0 /* FLL3_SS_SEL - [1:0] */ +#define ARIZONA_FLL3_SS_SEL_WIDTH 2 /* FLL3_SS_SEL - [1:0] */ + +/* + * R458 (0x1CA) - FLL3 GPIO Clock + */ +#define ARIZONA_FLL3_GPDIV_MASK 0x00FE /* FLL3_GPDIV - [7:1] */ +#define ARIZONA_FLL3_GPDIV_SHIFT 1 /* FLL3_GPDIV - [7:1] */ +#define ARIZONA_FLL3_GPDIV_WIDTH 7 /* FLL3_GPDIV - [7:1] */ +#define ARIZONA_FLL3_GPDIV_ENA 0x0001 /* FLL3_GPDIV_ENA */ +#define ARIZONA_FLL3_GPDIV_ENA_MASK 0x0001 /* FLL3_GPDIV_ENA */ +#define ARIZONA_FLL3_GPDIV_ENA_SHIFT 0 /* FLL3_GPDIV_ENA */ +#define ARIZONA_FLL3_GPDIV_ENA_WIDTH 1 /* FLL3_GPDIV_ENA */ + +/* + * R465 (0x1D1) - MOON_FLLAO_CONTROL_1 + */ +#define MOON_FLL_AO_HOLD 0x0004 /* FLL_AO_HOLD */ +#define MOON_FLL_AO_HOLD_MASK 0x0004 /* FLL_AO_HOLD */ +#define MOON_FLL_AO_HOLD_SHIFT 2 /* FLL_AO_HOLD */ +#define MOON_FLL_AO_HOLD_WIDTH 1 /* FLL_AO_HOLD */ +#define MOON_FLL_AO_FREERUN 0x0002 /* FLL_AO_FREERUN */ +#define MOON_FLL_AO_FREERUN_MASK 0x0002 /* FLL_AO_FREERUN */ +#define MOON_FLL_AO_FREERUN_SHIFT 1 /* FLL_AO_FREERUN */ +#define MOON_FLL_AO_FREERUN_WIDTH 1 /* FLL_AO_FREERUN */ +#define MOON_FLL_AO_ENA 0x0001 /* FLL_AO_ENA */ +#define MOON_FLL_AO_ENA_MASK 0x0001 /* FLL_AO_ENA */ +#define MOON_FLL_AO_ENA_SHIFT 0 /* FLL_AO_ENA */ +#define MOON_FLL_AO_ENA_WIDTH 1 /* FLL_AO_ENA */ + +/* + * R466 (0x1D2) - MOON_FLLAO_CONTROL_2 + */ +#define MOON_FLL_AO_CTRL_UPD 0x8000 /* FLL_AO_CTRL_UPD */ +#define MOON_FLL_AO_CTRL_UPD_MASK 0x8000 /* FLL_AO_CTRL_UPD */ +#define MOON_FLL_AO_CTRL_UPD_SHIFT 15 /* FLL_AO_CTRL_UPD */ +#define MOON_FLL_AO_CTRL_UPD_WIDTH 1 /* FLL_AO_CTRL_UPD */ +#define MOON_FLL_AO_N 0x03FF /* FLL_AO_N - [9:0] */ +#define MOON_FLL_AO_N_MASK 0x03FF /* FLL_AO_N - [9:0] */ +#define MOON_FLL_AO_N_SHIFT 0 /* FLL_AO_N - [9:0] */ +#define MOON_FLL_AO_N_WIDTH 10 /* FLL_AO_N - [9:0] */ + +/* + * R467 (0x1D3) - MOON_FLLAO_CONTROL_3 + */ +#define MOON_FLL_AO_THETA_MASK 0x00FF /* FLL_AO_THETA - [7:0] */ +#define MOON_FLL_AO_THETA_SHIFT 0 /* FLL_AO_THETA - [7:0] */ +#define MOON_FLL_AO_THETA_WIDTH 8 /* FLL_AO_THETA - [7:0] */ + +/* + * R468 (0x1D4) - MOON_FLLAO_CONTROL_4 + */ +#define MOON_FLL_AO_LAMBDA_MASK 0x00FF /* FLL_AO_LAMBDA - [7:0] */ +#define MOON_FLL_AO_LAMBDA_SHIFT 0 /* FLL_AO_LAMBDA - [7:0] */ +#define MOON_FLL_AO_LAMBDA_WIDTH 8 /* FLL_AO_LAMBDA - [7:0] */ + +/* + * R469 (0x1D5) - MOON_FLLAO_CONTROL_5 + */ +#define MOON_FLL_AO_FB_DIV_MASK 0x00FF /* FLL_AO_FB_DIV - [7:0] */ +#define MOON_FLL_AO_FB_DIV_SHIFT 0 /* FLL_AO_FB_DIV - [7:0] */ +#define MOON_FLL_AO_FB_DIV_WIDTH 8 /* FLL_AO_FB_DIV - [7:0] */ + +/* + * R470 (0x1D6) - MOON_FLLAO_CONTROL_6 + */ +#define MOON_FLL_AO_REFDET_ENA 0x8000 /* FLL_AO_REFDET_ENA */ +#define MOON_FLL_AO_REFDET_ENA_MASK 0x8000 /* FLL_AO_REFDET_ENA */ +#define MOON_FLL_AO_REFDET_ENA_SHIFT 15 /* FLL_AO_REFDET_ENA */ +#define MOON_FLL_AO_REFDET_ENA_WIDTH 1 /* FLL_AO_REFDET_ENA */ +#define MOON_FLL_AO_REFCLK_DIV 0x00C0 /* FLL_AO_REFCLK_DIV - [7:6] */ +#define MOON_FLL_AO_REFCLK_DIV_MASK 0x00C0 /* FLL_AO_REFCLK_DIV - [7:6] */ +#define MOON_FLL_AO_REFCLK_DIV_SHIFT 6 /* FLL_AO_REFCLK_DIV - [7:6] */ +#define MOON_FLL_AO_REFCLK_DIV_WIDTH 2 /* FLL_AO_REFCLK_DIV - [7:6] */ +#define MOON_FLL_AO_REFCLK_SRC 0x000F /* FLL_AO_REFCLK_SRC - [3:0] */ +#define MOON_FLL_AO_REFCLK_SRC_MASK 0x000F /* FLL_AO_REFCLK_SRC - [3:0] */ +#define MOON_FLL_AO_REFCLK_SRC_SHIFT 0 /* FLL_AO_REFCLK_SRC - [3:0] */ +#define MOON_FLL_AO_REFCLK_SRC_WIDTH 4 /* FLL_AO_REFCLK_SRC - [3:0] */ + +/* + * R472 (0x1D8) - MOON_FLLAO_CONTROL_7 + */ +#define MOON_FLL_AO_GAIN_MASK 0x000F /* FLL_AO_GAIN - [3:0] */ +#define MOON_FLL_AO_GAIN_SHIFT 0 /* FLL_AO_GAIN - [3:0] */ +#define MOON_FLL_AO_GAIN_WIDTH 4 /* FLL_AO_GAIN - [3:0] */ + +/* + * R474 (0x1DA) - MOON_FLLAO_CONTROL_8 + */ +#define MOON_FLL_AO_HS_DITH_TUNE 0xF000 /* FLL_AO_HS_DITH_TUNE - [15:12] */ +#define MOON_FLL_AO_HS_DITH_TUNE_MASK 0xF000 /* FLL_AO_HS_DITH_TUNE - [15:12] */ +#define MOON_FLL_AO_HS_DITH_TUNE_SHIFT 12 /* FLL_AO_HS_DITH_TUNE - [15:12] */ +#define MOON_FLL_AO_HS_DITH_TUNE_WIDTH 4 /* FLL_AO_HS_DITH_TUNE - [15:12] */ +#define MOON_FLL_AO_LS_DITH_TUNE_SHAPED 0x00F0 /* FLL_AO_LS_DITH_TUNE_SHAPED - [7:4] */ +#define MOON_FLL_AO_LS_DITH_TUNE_SHAPED_MASK 0x00F0 /* FLL_AO_LS_DITH_TUNE_SHAPED - [7:4] */ +#define MOON_FLL_AO_LS_DITH_TUNE_SHAPED_SHIFT 4 /* FLL_AO_LS_DITH_TUNE_SHAPED - [7:4] */ +#define MOON_FLL_AO_LS_DITH_TUNE_SHAPED_WIDTH 4 /* FLL_AO_LS_DITH_TUNE_SHAPED - [7:4] */ +#define MOON_FLL_AO_LS_DITH_TUNE_NONSHAPED 0x000F /* FLL_AO_LS_DITH_TUNE_NONSHAPED - [3:0] */ +#define MOON_FLL_AO_LS_DITH_TUNE_NONSHAPED_MASK 0x000F /* FLL_AO_LS_DITH_TUNE_NONSHAPED - [3:0] */ +#define MOON_FLL_AO_LS_DITH_TUNE_NONSHAPED_SHIFT 0 /* FLL_AO_LS_DITH_TUNE_NONSHAPED - [3:0] */ +#define MOON_FLL_AO_LS_DITH_TUNE_NONSHAPED_WIDTH 4 /* FLL_AO_LS_DITH_TUNE_NONSHAPED - [3:0] */ + +/* + * R475 (0x1DB) - MOON_FLLAO_CONTROL_9 + */ +#define MOON_FLL_AO_TR_RATE_MASK 0x000F /* FLL_AO_TR_RATE - [3:0] */ +#define MOON_FLL_AO_TR_RATE_SHIFT 0 /* FLL_AO_TR_RATE - [3:0] */ +#define MOON_FLL_AO_TR_RATE_WIDTH 4 /* FLL_AO_TR_RATE - [3:0] */ + +/* + * R476 (0x1DC) - MOON_FLLAO_CONTROL_10 + */ +#define MOON_FLL_AO_PHASEDET_ENA 0x1000 /* FLL_AO_PHASEDET_ENA */ +#define MOON_FLL_AO_PHASEDET_ENA_MASK 0x1000 /* FLL_AO_PHASEDET_ENA */ +#define MOON_FLL_AO_PHASEDET_ENA_SHIFT 12 /* FLL_AO_PHASEDET_ENA */ +#define MOON_FLL_AO_PHASEDET_ENA_WIDTH 1 /* FLL_AO_PHASEDET_ENA */ +#define MOON_FLL_AO_WLR_SDM_FRC_ENA 0x0800 /* FLL_AO_WLR_SDM_FRC_ENA */ +#define MOON_FLL_AO_WLR_SDM_FRC_ENA_MASK 0x0800 /* FLL_AO_WLR_SDM_FRC_ENA */ +#define MOON_FLL_AO_WLR_SDM_FRC_ENA_SHIFT 11 /* FLL_AO_WLR_SDM_FRC_ENA */ +#define MOON_FLL_AO_WLR_SDM_FRC_ENA_WIDTH 1 /* FLL_AO_WLR_SDM_FRC_ENA */ +#define MOON_FLL_AO_WLR_SDM_ENA 0x0400 /* FLL_AO_WLR_SDM_ENA */ +#define MOON_FLL_AO_WLR_SDM_ENA_MASK 0x0400 /* FLL_AO_WLR_SDM_ENA */ +#define MOON_FLL_AO_WLR_SDM_ENA_SHIFT 10 /* FLL_AO_WLR_SDM_ENA */ +#define MOON_FLL_AO_WLR_SDM_ENA_WIDTH 1 /* FLL_AO_WLR_SDM_ENA */ +#define MOON_FLL_AO_SYNC_EFS_ENA 0x0200 /* FLL_AO_SYNC_EFS_ENA */ +#define MOON_FLL_AO_SYNC_EFS_ENA_MASK 0x0200 /* FLL_AO_SYNC_EFS_ENA */ +#define MOON_FLL_AO_SYNC_EFS_ENA_SHIFT 9 /* FLL_AO_SYNC_EFS_ENA */ +#define MOON_FLL_AO_SYNC_EFS_ENA_WIDTH 1 /* FLL_AO_SYNC_EFS_ENA */ +#define MOON_FLL_AO_LS_DITH_ENA 0x0080 /* FLL_AO_LS_DITH_ENA */ +#define MOON_FLL_AO_LS_DITH_ENA_MASK 0x0080 /* FLL_AO_LS_DITH_ENA */ +#define MOON_FLL_AO_LS_DITH_ENA_SHIFT 7 /* FLL_AO_LS_DITH_ENA */ +#define MOON_FLL_AO_LS_DITH_ENA_WIDTH 1 /* FLL_AO_LS_DITH_ENA */ +#define MOON_FLL_AO_HS_DITH_ENA 0x0040 /* FLL_AO_HS_DITH_ENA */ +#define MOON_FLL_AO_HS_DITH_ENA_MASK 0x0040 /* FLL_AO_HS_DITH_ENA */ +#define MOON_FLL_AO_HS_DITH_ENA_SHIFT 6 /* FLL_AO_HS_DITH_ENA */ +#define MOON_FLL_AO_HS_DITH_ENA_WIDTH 1 /* FLL_AO_HS_DITH_ENA */ +#define MOON_FLL_AO_OSF_FRC_ENA 0x0010 /* FLL_AO_OSF_FRC_ENA */ +#define MOON_FLL_AO_OSF_FRC_ENA_MASK 0x0010 /* FLL_AO_OSF_FRC_ENA */ +#define MOON_FLL_AO_OSF_FRC_ENA_SHIFT 4 /* FLL_AO_OSF_FRC_ENA */ +#define MOON_FLL_AO_OSF_FRC_ENA_WIDTH 1 /* FLL_AO_OSF_FRC_ENA */ +#define MOON_FLL_AO_OSF_ENA 0x0008 /* FLL_AO_OSF_ENA */ +#define MOON_FLL_AO_OSF_ENA_MASK 0x0008 /* FLL_AO_OSF_ENA */ +#define MOON_FLL_AO_OSF_ENA_SHIFT 3 /* FLL_AO_OSF_ENA */ +#define MOON_FLL_AO_OSF_ENA_WIDTH 1 /* FLL_AO_OSF_ENA */ +#define MOON_FLL_AO_AUTO_DFSAT_ENA 0x0002 /* FLL_AO_AUTO_DFSAT_ENA */ +#define MOON_FLL_AO_AUTO_DFSAT_ENA_MASK 0x0002 /* FLL_AO_AUTO_DFSAT_ENA */ +#define MOON_FLL_AO_AUTO_DFSAT_ENA_SHIFT 1 /* FLL_AO_AUTO_DFSAT_ENA */ +#define MOON_FLL_AO_AUTO_DFSAT_ENA_WIDTH 1 /* FLL_AO_AUTO_DFSAT_ENA */ +#define MOON_FLL_AO_DFSAT_ENA 0x0001 /* FLL_AO_DFSAT_ENA */ +#define MOON_FLL_AO_DFSAT_ENA_MASK 0x0001 /* FLL_AO_DFSAT_ENA */ +#define MOON_FLL_AO_DFSAT_ENA_SHIFT 0 /* FLL_AO_DFSAT_ENA */ +#define MOON_FLL_AO_DFSAT_ENA_WIDTH 1 /* FLL_AO_DFSAT_ENA */ + +/* + * R477 (0x1DD) - MOON_FLLAO_CONTROL_11 + */ +#define MOON_FLL_AO_LOCKDET_PHASE_MASK 0x0080 /* FLL_AO_LOCKDET_PHASE_MASK */ +#define MOON_FLL_AO_LOCKDET_PHASE_MASK_MASK 0x0080 /* FLL_AO_LOCKDET_PHASE_MASK */ +#define MOON_FLL_AO_LOCKDET_PHASE_MASK_SHIFT 7 /* FLL_AO_LOCKDET_PHASE_MASK */ +#define MOON_FLL_AO_LOCKDET_PHASE_MASK_WIDTH 1 /* FLL_AO_LOCKDET_PHASE_MASK */ +#define MOON_FLL_AO_LOCKDET_THR 0x001E /* FLL_AO_LOCKDET_THR - [4:1] */ +#define MOON_FLL_AO_LOCKDET_THR_MASK 0x001E /* FLL_AO_LOCKDET_THR - [4:1] */ +#define MOON_FLL_AO_LOCKDET_THR_SHIFT 1 /* FLL_AO_LOCKDET_THR - [4:1] */ +#define MOON_FLL_AO_LOCKDET_THR_WIDTH 4 /* FLL_AO_LOCKDET_THR - [4:1] */ +#define MOON_FLL_AO_LOCKDET_ENA 0x0001 /* FLL_AO_LOCKDET_ENA */ +#define MOON_FLL_AO_LOCKDET_ENA_MASK 0x0001 /* FLL_AO_LOCKDET_ENA */ +#define MOON_FLL_AO_LOCKDET_ENA_SHIFT 0 /* FLL_AO_LOCKDET_ENA */ +#define MOON_FLL_AO_LOCKDET_ENA_WIDTH 1 /* FLL_AO_LOCKDET_ENA */ + /* * R512 (0x200) - Mic Charge Pump 1 */ @@ -2093,6 +3912,197 @@ #define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */ #define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */ +/* + * R539 (0x21B) - Mic Bias Ctrl 4 + */ +#define ARIZONA_MICB4_EXT_CAP 0x8000 /* MICB4_EXT_CAP */ +#define ARIZONA_MICB4_EXT_CAP_MASK 0x8000 /* MICB4_EXT_CAP */ +#define ARIZONA_MICB4_EXT_CAP_SHIFT 15 /* MICB4_EXT_CAP */ +#define ARIZONA_MICB4_EXT_CAP_WIDTH 1 /* MICB4_EXT_CAP */ +#define ARIZONA_MICB4_LVL_MASK 0x01E0 /* MICB4_LVL - [8:5] */ +#define ARIZONA_MICB4_LVL_SHIFT 5 /* MICB4_LVL - [8:5] */ +#define ARIZONA_MICB4_LVL_WIDTH 4 /* MICB4_LVL - [8:5] */ +#define ARIZONA_MICB4_FAST 0x0010 /* MICB4_FAST */ +#define ARIZONA_MICB4_FAST_MASK 0x0010 /* MICB4_FAST */ +#define ARIZONA_MICB4_FAST_SHIFT 4 /* MICB4_FAST */ +#define ARIZONA_MICB4_FAST_WIDTH 1 /* MICB4_FAST */ +#define ARIZONA_MICB4_RATE 0x0008 /* MICB4_RATE */ +#define ARIZONA_MICB4_RATE_MASK 0x0008 /* MICB4_RATE */ +#define ARIZONA_MICB4_RATE_SHIFT 3 /* MICB4_RATE */ +#define ARIZONA_MICB4_RATE_WIDTH 1 /* MICB4_RATE */ +#define ARIZONA_MICB4_DISCH 0x0004 /* MICB4_DISCH */ +#define ARIZONA_MICB4_DISCH_MASK 0x0004 /* MICB4_DISCH */ +#define ARIZONA_MICB4_DISCH_SHIFT 2 /* MICB4_DISCH */ +#define ARIZONA_MICB4_DISCH_WIDTH 1 /* MICB4_DISCH */ +#define ARIZONA_MICB4_BYPASS 0x0002 /* MICB4_BYPASS */ +#define ARIZONA_MICB4_BYPASS_MASK 0x0002 /* MICB4_BYPASS */ +#define ARIZONA_MICB4_BYPASS_SHIFT 1 /* MICB4_BYPASS */ +#define ARIZONA_MICB4_BYPASS_WIDTH 1 /* MICB4_BYPASS */ +#define ARIZONA_MICB4_ENA 0x0001 /* MICB4_ENA */ +#define ARIZONA_MICB4_ENA_MASK 0x0001 /* MICB4_ENA */ +#define ARIZONA_MICB4_ENA_SHIFT 0 /* MICB4_ENA */ +#define ARIZONA_MICB4_ENA_WIDTH 1 /* MICB4_ENA */ + +/* + * R540 (0x21C) - Mic Bias Ctrl 5 + */ +#define ARIZONA_MICB1D_BYP 0x4000 /* MICB1D_BYP */ +#define ARIZONA_MICB1D_BYP_MASK 0x4000 /* MICB1D_BYP */ +#define ARIZONA_MICB1D_BYP_SHIFT 14 /* MICB1D_BYP */ +#define ARIZONA_MICB1D_BYP_WIDTH 1 /* MICB1D_BYP */ +#define ARIZONA_MICB1D_DISCH 0x2000 /* MICB1D_DISCH */ +#define ARIZONA_MICB1D_DISCH_MASK 0x2000 /* MICB1D_DISCH */ +#define ARIZONA_MICB1D_DISCH_SHIFT 13 /* MICB1D_DISCH */ +#define ARIZONA_MICB1D_DISCH_WIDTH 1 /* MICB1D_DISCH */ +#define ARIZONA_MICB1D_ENA 0x1000 /* MICB1D_ENA */ +#define ARIZONA_MICB1D_ENA_MASK 0x1000 /* MICB1D_ENA */ +#define ARIZONA_MICB1D_ENA_SHIFT 12 /* MICB1D_ENA */ +#define ARIZONA_MICB1D_ENA_WIDTH 1 /* MICB1D_ENA */ +#define ARIZONA_MICB1C_BYP 0x0400 /* MICB1C_BYP */ +#define ARIZONA_MICB1C_BYP_MASK 0x0400 /* MICB1C_BYP */ +#define ARIZONA_MICB1C_BYP_SHIFT 10 /* MICB1C_BYP */ +#define ARIZONA_MICB1C_BYP_WIDTH 1 /* MICB1C_BYP */ +#define ARIZONA_MICB1C_DISCH 0x0200 /* MICB1C_DISCH */ +#define ARIZONA_MICB1C_DISCH_MASK 0x0200 /* MICB1C_DISCH */ +#define ARIZONA_MICB1C_DISCH_SHIFT 9 /* MICB1C_DISCH */ +#define ARIZONA_MICB1C_DISCH_WIDTH 1 /* MICB1C_DISCH */ +#define ARIZONA_MICB1C_ENA 0x0100 /* MICB1C_ENA */ +#define ARIZONA_MICB1C_ENA_MASK 0x0100 /* MICB1C_ENA */ +#define ARIZONA_MICB1C_ENA_SHIFT 8 /* MICB1C_ENA */ +#define ARIZONA_MICB1C_ENA_WIDTH 1 /* MICB1C_ENA */ +#define ARIZONA_MICB1B_BYP 0x0040 /* MICB1B_BYP */ +#define ARIZONA_MICB1B_BYP_MASK 0x0040 /* MICB1B_BYP */ +#define ARIZONA_MICB1B_BYP_SHIFT 6 /* MICB1B_BYP */ +#define ARIZONA_MICB1B_BYP_WIDTH 1 /* MICB1B_BYP */ +#define ARIZONA_MICB1B_DISCH 0x0020 /* MICB1B_DISCH */ +#define ARIZONA_MICB1B_DISCH_MASK 0x0020 /* MICB1B_DISCH */ +#define ARIZONA_MICB1B_DISCH_SHIFT 5 /* MICB1B_DISCH */ +#define ARIZONA_MICB1B_DISCH_WIDTH 1 /* MICB1B_DISCH */ +#define ARIZONA_MICB1B_ENA 0x0010 /* MICB1B_ENA */ +#define ARIZONA_MICB1B_ENA_MASK 0x0010 /* MICB1B_ENA */ +#define ARIZONA_MICB1B_ENA_SHIFT 4 /* MICB1B_ENA */ +#define ARIZONA_MICB1B_ENA_WIDTH 1 /* MICB1B_ENA */ +#define ARIZONA_MICB1A_BYP 0x0004 /* MICB1A_BYP */ +#define ARIZONA_MICB1A_BYP_MASK 0x0004 /* MICB1A_BYP */ +#define ARIZONA_MICB1A_BYP_SHIFT 2 /* MICB1A_BYP */ +#define ARIZONA_MICB1A_BYP_WIDTH 1 /* MICB1A_BYP */ +#define ARIZONA_MICB1A_DISCH 0x0002 /* MICB1A_DISCH */ +#define ARIZONA_MICB1A_DISCH_MASK 0x0002 /* MICB1A_DISCH */ +#define ARIZONA_MICB1A_DISCH_SHIFT 1 /* MICB1A_DISCH */ +#define ARIZONA_MICB1A_DISCH_WIDTH 1 /* MICB1A_DISCH */ +#define ARIZONA_MICB1A_ENA 0x0001 /* MICB1A_ENA */ +#define ARIZONA_MICB1A_ENA_MASK 0x0001 /* MICB1A_ENA */ +#define ARIZONA_MICB1A_ENA_SHIFT 0 /* MICB1A_ENA */ +#define ARIZONA_MICB1A_ENA_WIDTH 1 /* MICB1A_ENA */ + +/* + * R542 (0x21E) - Mic Bias Ctrl 6 + */ +#define ARIZONA_MICB2D_BYP 0x4000 /* MICB2D_BYP */ +#define ARIZONA_MICB2D_BYP_MASK 0x4000 /* MICB2D_BYP */ +#define ARIZONA_MICB2D_BYP_SHIFT 14 /* MICB2D_BYP */ +#define ARIZONA_MICB2D_BYP_WIDTH 1 /* MICB2D_BYP */ +#define ARIZONA_MICB2D_DISCH 0x2000 /* MICB2D_DISCH */ +#define ARIZONA_MICB2D_DISCH_MASK 0x2000 /* MICB2D_DISCH */ +#define ARIZONA_MICB2D_DISCH_SHIFT 13 /* MICB2D_DISCH */ +#define ARIZONA_MICB2D_DISCH_WIDTH 1 /* MICB2D_DISCH */ +#define ARIZONA_MICB2D_ENA 0x1000 /* MICB2D_ENA */ +#define ARIZONA_MICB2D_ENA_MASK 0x1000 /* MICB2D_ENA */ +#define ARIZONA_MICB2D_ENA_SHIFT 12 /* MICB2D_ENA */ +#define ARIZONA_MICB2D_ENA_WIDTH 1 /* MICB2D_ENA */ +#define ARIZONA_MICB2C_BYP 0x0400 /* MICB2C_BYP */ +#define ARIZONA_MICB2C_BYP_MASK 0x0400 /* MICB2C_BYP */ +#define ARIZONA_MICB2C_BYP_SHIFT 10 /* MICB2C_BYP */ +#define ARIZONA_MICB2C_BYP_WIDTH 1 /* MICB2C_BYP */ +#define ARIZONA_MICB2C_DISCH 0x0200 /* MICB2C_DISCH */ +#define ARIZONA_MICB2C_DISCH_MASK 0x0200 /* MICB2C_DISCH */ +#define ARIZONA_MICB2C_DISCH_SHIFT 9 /* MICB2C_DISCH */ +#define ARIZONA_MICB2C_DISCH_WIDTH 1 /* MICB2C_DISCH */ +#define ARIZONA_MICB2C_ENA 0x0100 /* MICB2C_ENA */ +#define ARIZONA_MICB2C_ENA_MASK 0x0100 /* MICB2C_ENA */ +#define ARIZONA_MICB2C_ENA_SHIFT 8 /* MICB2C_ENA */ +#define ARIZONA_MICB2C_ENA_WIDTH 1 /* MICB2C_ENA */ +#define ARIZONA_MICB2B_BYP 0x0040 /* MICB2B_BYP */ +#define ARIZONA_MICB2B_BYP_MASK 0x0040 /* MICB2B_BYP */ +#define ARIZONA_MICB2B_BYP_SHIFT 6 /* MICB2B_BYP */ +#define ARIZONA_MICB2B_BYP_WIDTH 1 /* MICB2B_BYP */ +#define ARIZONA_MICB2B_DISCH 0x0020 /* MICB2B_DISCH */ +#define ARIZONA_MICB2B_DISCH_MASK 0x0020 /* MICB2B_DISCH */ +#define ARIZONA_MICB2B_DISCH_SHIFT 5 /* MICB2B_DISCH */ +#define ARIZONA_MICB2B_DISCH_WIDTH 1 /* MICB2B_DISCH */ +#define ARIZONA_MICB2B_ENA 0x0010 /* MICB2B_ENA */ +#define ARIZONA_MICB2B_ENA_MASK 0x0010 /* MICB2B_ENA */ +#define ARIZONA_MICB2B_ENA_SHIFT 4 /* MICB2B_ENA */ +#define ARIZONA_MICB2B_ENA_WIDTH 1 /* MICB2B_ENA */ +#define ARIZONA_MICB2A_BYP 0x0004 /* MICB2A_BYP */ +#define ARIZONA_MICB2A_BYP_MASK 0x0004 /* MICB2A_BYP */ +#define ARIZONA_MICB2A_BYP_SHIFT 2 /* MICB2A_BYP */ +#define ARIZONA_MICB2A_BYP_WIDTH 1 /* MICB2A_BYP */ +#define ARIZONA_MICB2A_DISCH 0x0002 /* MICB2A_DISCH */ +#define ARIZONA_MICB2A_DISCH_MASK 0x0002 /* MICB2A_DISCH */ +#define ARIZONA_MICB2A_DISCH_SHIFT 1 /* MICB2A_DISCH */ +#define ARIZONA_MICB2A_DISCH_WIDTH 1 /* MICB2A_DISCH */ +#define ARIZONA_MICB2A_ENA 0x0001 /* MICB2A_ENA */ +#define ARIZONA_MICB2A_ENA_MASK 0x0001 /* MICB2A_ENA */ +#define ARIZONA_MICB2A_ENA_SHIFT 0 /* MICB2A_ENA */ +#define ARIZONA_MICB2A_ENA_WIDTH 1 /* MICB2A_ENA */ + +/* + * R549 (0x225) - HP Ctrl 1L + */ +#define ARIZONA_RMV_SHRT_HP1L 0x4000 /* RMV_SHRT_HP1L */ +#define ARIZONA_RMV_SHRT_HP1L_MASK 0x4000 /* RMV_SHRT_HP1L */ +#define ARIZONA_RMV_SHRT_HP1L_SHIFT 14 /* RMV_SHRT_HP1L */ +#define ARIZONA_RMV_SHRT_HP1L_WIDTH 1 /* RMV_SHRT_HP1L */ +#define ARIZONA_HP1L_FLWR 0x0004 /* HP1L_FLWR */ +#define ARIZONA_HP1L_FLWR_MASK 0x0004 /* HP1L_FLWR */ +#define ARIZONA_HP1L_FLWR_SHIFT 2 /* HP1L_FLWR */ +#define ARIZONA_HP1L_FLWR_WIDTH 1 /* HP1L_FLWR */ +#define ARIZONA_HP1L_SHRTI 0x0002 /* HP1L_SHRTI */ +#define ARIZONA_HP1L_SHRTI_MASK 0x0002 /* HP1L_SHRTI */ +#define ARIZONA_HP1L_SHRTI_SHIFT 1 /* HP1L_SHRTI */ +#define ARIZONA_HP1L_SHRTI_WIDTH 1 /* HP1L_SHRTI */ +#define ARIZONA_HP1L_SHRTO 0x0001 /* HP1L_SHRTO */ +#define ARIZONA_HP1L_SHRTO_MASK 0x0001 /* HP1L_SHRTO */ +#define ARIZONA_HP1L_SHRTO_SHIFT 0 /* HP1L_SHRTO */ +#define ARIZONA_HP1L_SHRTO_WIDTH 1 /* HP1L_SHRTO */ + +/* + * R550 (0x226) - HP Ctrl 1R + */ +#define ARIZONA_RMV_SHRT_HP1R 0x4000 /* RMV_SHRT_HP1R */ +#define ARIZONA_RMV_SHRT_HP1R_MASK 0x4000 /* RMV_SHRT_HP1R */ +#define ARIZONA_RMV_SHRT_HP1R_SHIFT 14 /* RMV_SHRT_HP1R */ +#define ARIZONA_RMV_SHRT_HP1R_WIDTH 1 /* RMV_SHRT_HP1R */ +#define ARIZONA_HP1R_FLWR 0x0004 /* HP1R_FLWR */ +#define ARIZONA_HP1R_FLWR_MASK 0x0004 /* HP1R_FLWR */ +#define ARIZONA_HP1R_FLWR_SHIFT 2 /* HP1R_FLWR */ +#define ARIZONA_HP1R_FLWR_WIDTH 1 /* HP1R_FLWR */ +#define ARIZONA_HP1R_SHRTI 0x0002 /* HP1R_SHRTI */ +#define ARIZONA_HP1R_SHRTI_MASK 0x0002 /* HP1R_SHRTI */ +#define ARIZONA_HP1R_SHRTI_SHIFT 1 /* HP1R_SHRTI */ +#define ARIZONA_HP1R_SHRTI_WIDTH 1 /* HP1R_SHRTI */ +#define ARIZONA_HP1R_SHRTO 0x0001 /* HP1R_SHRTO */ +#define ARIZONA_HP1R_SHRTO_MASK 0x0001 /* HP1R_SHRTO */ +#define ARIZONA_HP1R_SHRTO_SHIFT 0 /* HP1R_SHRTO */ +#define ARIZONA_HP1R_SHRTO_WIDTH 1 /* HP1R_SHRTO */ + +/* + * R638 (0x27E) - Clearwater EDRE HP stereo control + */ +#define ARIZONA_HP3_EDRE_STEREO 0x0004 /* HP3_EDRE_STEREO */ +#define ARIZONA_HP3_EDRE_STEREO_MASK 0x0004 /* HP3_EDRE_STEREO */ +#define ARIZONA_HP3_EDRE_STEREO_SHIFT 2 /* HP3_EDRE_STEREO */ +#define ARIZONA_HP3_EDRE_STEREO_WIDTH 1 /* HP3_EDRE_STEREO */ +#define ARIZONA_HP2_EDRE_STEREO 0x0002 /* HP2_EDRE_STEREO */ +#define ARIZONA_HP2_EDRE_STEREO_MASK 0x0002 /* HP2_EDRE_STEREO */ +#define ARIZONA_HP2_EDRE_STEREO_SHIFT 1 /* HP2_EDRE_STEREO */ +#define ARIZONA_HP2_EDRE_STEREO_WIDTH 1 /* HP2_EDRE_STEREO */ +#define ARIZONA_HP1_EDRE_STEREO 0x0001 /* HP1_EDRE_STEREO */ +#define ARIZONA_HP1_EDRE_STEREO_MASK 0x0001 /* HP1_EDRE_STEREO */ +#define ARIZONA_HP1_EDRE_STEREO_SHIFT 0 /* HP1_EDRE_STEREO */ +#define ARIZONA_HP1_EDRE_STEREO_WIDTH 1 /* HP1_EDRE_STEREO */ + /* * R659 (0x293) - Accessory Detect Mode 1 */ @@ -2100,13 +4110,49 @@ #define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */ #define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */ #define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */ -#define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */ -#define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */ -#define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */ +#define ARIZONA_ACCDET_POLARITY_INV_ENA 0x0080 /* ACCDET_POLARITY_INV_ENA */ +#define ARIZONA_ACCDET_POLARITY_INV_ENA_MASK 0x0080 /* ACCDET_POLARITY_INV_ENA */ +#define ARIZONA_ACCDET_POLARITY_INV_ENA_SHIFT 7 /* ACCDET_POLARITY_INV_ENA */ +#define ARIZONA_ACCDET_POLARITY_INV_ENA_WIDTH 1 /* ACCDET_POLARITY_INV_ENA */ +#define ARIZONA_ACCDET_MODE_MASK 0x0007 /* ACCDET_MODE - [2:0] */ +#define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [2:0] */ +#define ARIZONA_ACCDET_MODE_WIDTH 3 /* ACCDET_MODE - [2:0] */ + +/* + * R665 (0x299) - MOON_HEADPHONE_DETECT_0 + */ +#define MOON_HPD_GND_SEL 0x0007 /*HPD_GND_SEL[2:0]*/ +#define MOON_HPD_GND_SEL_MASK 0x0007 /*HPD_GND_SEL[2:0]*/ +#define MOON_HPD_GND_SEL_SHIFT 0 /*HPD_GND_SEL[2:0]*/ +#define MOON_HPD_GND_SEL_WIDTH 3 /*HPD_GND_SEL[2:0]*/ +#define MOON_HPD_SENSE_SEL 0x00F0 /*HPD_SENSE_SEL[4:7]*/ +#define MOON_HPD_SENSE_SEL_MASK 0x00F0 /*HPD_SENSE_SEL[4:7]*/ +#define MOON_HPD_SENSE_SEL_SHIFT 4 /*HPD_SENSE_SEL[4:7]*/ +#define MOON_HPD_SENSE_SEL_WIDTH 4 /*HPD_SENSE_SEL[4:7]*/ +#define MOON_HPD_FRC_SEL 0x0F00 /*HPD_FRC_SEL[8:11]*/ +#define MOON_HPD_FRC_SEL_MASK 0x0F00 /*HPD_FRC_SEL[8:11]*/ +#define MOON_HPD_FRC_SEL_SHIFT 8 /*HPD_FRC_SEL[8:11]*/ +#define MOON_HPD_FRC_SEL_WIDTH 4 /*HPD_FRC_SEL[8:11]*/ +#define MOON_HPD_OUT_SEL 0x7000 /*HPD_OUT_SEL[12:14]*/ +#define MOON_HPD_OUT_SEL_MASK 0x7000 /*HPD_OUT_SEL[12:14]*/ +#define MOON_HPD_OUT_SEL_SHIFT 12 /*HPD_OUT_SEL[12:14]*/ +#define MOON_HPD_OUT_SEL_WIDTH 3 /*HPD_OUT_SEL[12:14]*/ +#define MOON_HPD_OVD_ENA_SEL 0x8000 /*HPD_OVD_ENA[15]]*/ +#define MOON_HPD_OVD_ENA_SEL_MASK 0x8000 /*HPD_OVD_ENA[15]]*/ +#define MOON_HPD_OVD_ENA_SEL_SHIFT 15 /*HPD_OVD_ENA[15]]*/ +#define MOON_HPD_OVD_ENA_SEL_WIDTH 1 /*HPD_OVD_ENA[15]]*/ /* * R667 (0x29B) - Headphone Detect 1 */ +#define VEGAS_HP_FAST_MODE 0x8000 /* HP_FAST_MODE [15] */ +#define VEGAS_HP_FAST_MODE_MASK 0x8000 /* HP_FAST_MODE [15] */ +#define VEGAS_HP_FAST_MODE_SHIFT 15 /* HP_FAST_MODE [15] */ +#define VEGAS_HP_FAST_MODE_WIDTH 1 /* HP_FAST_MODE [15] */ +#define ARIZONA_HP_FAST_MODE 0x0800 /* HP_FAST_MODE [11] */ +#define ARIZONA_HP_FAST_MODE_MASK 0x0800 /* HP_FAST_MODE [11] */ +#define ARIZONA_HP_FAST_MODE_SHIFT 11 /* HP_FAST_MODE [11] */ +#define ARIZONA_HP_FAST_MODE_WIDTH 1 /* HP_FAST_MODE [11] */ #define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */ #define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */ #define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */ @@ -2124,6 +4170,12 @@ #define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */ #define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */ #define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */ +#define CLEARWATER_HP_RATE_MASK 0x0006 /* HP_RATE - [2:1] */ +#define CLEARWATER_HP_RATE_SHIFT 1 /* HP_RATE - [2:1] */ +#define CLEARWATER_HP_RATE_WIDTH 2 /* HP_RATE - [2:1] */ +#define VEGAS_HP_RATE_MASK 0x0006 /* HP_RATE - [2:1] */ +#define VEGAS_HP_RATE_SHIFT 1 /* HP_RATE - [2:1] */ +#define VEGAS_HP_RATE_WIDTH 2 /* HP_RATE - [2:1] */ #define ARIZONA_HP_RATE 0x0002 /* HP_RATE */ #define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */ #define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */ @@ -2143,7 +4195,6 @@ #define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ #define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ #define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ - #define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */ #define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */ #define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */ @@ -2152,6 +4203,20 @@ #define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */ #define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */ +/* + * R669 (0x29D) - Headphone Detect 3 + */ +#define ARIZONA_HP_DACVAL_MASK 0x03FF /* HP_DACVAL [9:0] */ +#define ARIZONA_HP_DACVAL_SHIFT 0 /* HP_DACVAL [9:0] */ +#define ARIZONA_HP_DACVAL_WIDTH 10 /* HP_DACVAL [9:0] */ + +/* + * R669 (0x29F) - Headphone Detect 5 + */ +#define ARIZONA_HP_DACVAL_DOWN_MASK 0x03FF /* HP_DACVAL_DOWN [9:0] */ +#define ARIZONA_HP_DACVAL_DOWN_SHIFT 0 /* HP_DACVAL_DOWN [9:0] */ +#define ARIZONA_HP_DACVAL_DOWN_WIDTH 10 /* HP_DACVAL_DOWN [9:0] */ + /* * R674 (0x2A2) - MICD clamp control */ @@ -2159,6 +4224,19 @@ #define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */ #define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */ +/* + * R674 (0x2A2) - MOON_MIC_DETECT_0 + */ +#define MOON_MICD1_GND_MASK 0x0007 /* MICD1_GND_SEL - [2:0] */ +#define MOON_MICD1_GND_SHIFT 0 /* MICD1_GND_SEL - [2:0] */ +#define MOON_MICD1_GND_WIDTH 3 /* MICD1_GND_SEL - [2:0] */ +#define MOON_MICD1_SENSE_MASK 0x0070 /* MICD1_SENSE_SEL - [2:0] */ +#define MOON_MICD1_SENSE_SHIFT 4 /* MICD1_SENSE_SEL - [2:0] */ +#define MOON_MICD1_SENSE_WIDTH 3 /* MICD1_SENSE_SEL - [2:0] */ +#define MOON_MICD1_ADC_MODE_MASK 0x8000 /* MICD1_ADC_MODE - [2:0] */ +#define MOON_MICD1_ADC_MODE_SHIFT 15 /* MICD1_ADC_MODE - [2:0] */ +#define MOON_MICD1_ADC_MODE_WIDTH 1 /* MICD1_ADC_MODE - [2:0] */ + /* * R675 (0x2A3) - Mic Detect 1 */ @@ -2171,6 +4249,9 @@ #define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */ #define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */ #define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */ +#define MOON_MICD_BIAS_SRC_MASK 0x00F0 /* MICD_BIAS_SRC - [7:4] */ +#define MOON_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [7:4] */ +#define MOON_MICD_BIAS_SRC_WIDTH 4 /* MICD_BIAS_SRC - [7:4] */ #define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */ #define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ #define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ @@ -2190,6 +4271,15 @@ /* * R677 (0x2A5) - Mic Detect 3 */ +#define ARIZONA_MICD_LVL_0 0x0004 /* MICD_LVL - [2] */ +#define ARIZONA_MICD_LVL_1 0x0008 /* MICD_LVL - [3] */ +#define ARIZONA_MICD_LVL_2 0x0010 /* MICD_LVL - [4] */ +#define ARIZONA_MICD_LVL_3 0x0020 /* MICD_LVL - [5] */ +#define ARIZONA_MICD_LVL_4 0x0040 /* MICD_LVL - [6] */ +#define ARIZONA_MICD_LVL_5 0x0080 /* MICD_LVL - [7] */ +#define ARIZONA_MICD_LVL_6 0x0100 /* MICD_LVL - [8] */ +#define ARIZONA_MICD_LVL_7 0x0200 /* MICD_LVL - [9] */ +#define ARIZONA_MICD_LVL_8 0x0400 /* MICD_LVL - [10] */ #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ @@ -2202,6 +4292,91 @@ #define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */ #define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */ +/* + * R683 (0x2AB) - Mic Detect 4 + */ +#define ARIZONA_MICDET_ADCVAL_DIFF_MASK 0xFF00 /* MICDET_ADCVAL_DIFF - [15:8] */ +#define ARIZONA_MICDET_ADCVAL_DIFF_SHIFT 8 /* MICDET_ADCVAL_DIFF - [15:8] */ +#define ARIZONA_MICDET_ADCVAL_DIFF_WIDTH 8 /* MICDET_ADCVAL_DIFF - [15:8] */ +#define ARIZONA_MICDET_ADCVAL_MASK 0x007F /* MICDET_ADCVAL - [15:8] */ +#define ARIZONA_MICDET_ADCVAL_SHIFT 0 /* MICDET_ADCVAL - [15:8] */ +#define ARIZONA_MICDET_ADCVAL_WIDTH 7 /* MICDET_ADCVAL - [15:8] */ + +/* + * R690 (0x2B2) - MICDET2_CONTROL_0 + */ +#define MOON_MICD2_ADC_MODE 0x8000 /* MICD2_ADC_MODE */ +#define MOON_MICD2_ADC_MODE_MASK 0x8000 /* MICD2_ADC_MODE */ +#define MOON_MICD2_ADC_MODE_SHIFT 15 /* MICD2_ADC_MODE */ +#define MOON_MICD2_ADC_MODE_WIDTH 1 /* MICD2_ADC_MODE */ +#define MOON_MICD2_SENSE_SEL 0x0070 /* MICD2_SENSE_SEL - [6:4] */ +#define MOON_MICD2_SENSE_SEL_MASK 0x0070 /* MICD2_SENSE_SEL - [6:4] */ +#define MOON_MICD2_SENSE_SEL_SHIFT 4 /* MICD2_SENSE_SEL - [6:4] */ +#define MOON_MICD2_SENSE_SEL_WIDTH 3 /* MICD2_SENSE_SEL - [6:4] */ +#define MOON_MICD2_GND_SEL 0x0007 /* MICD2_GND_SEL - [2:0] */ +#define MOON_MICD2_GND_SEL_MASK 0x0007 /* MICD2_GND_SEL - [2:0] */ +#define MOON_MICD2_GND_SEL_SHIFT 0 /* MICD2_GND_SEL - [2:0] */ +#define MOON_MICD2_GND_SEL_WIDTH 3 /* MICD2_GND_SEL - [2:0] */ + +/* + * R691 (0x2B3) - MICDET2_CONTROL_1 + */ +#define MOON_MICD2_BIAS_STARTTIME 0xF000 /* MICD2_BIAS_STARTTIME - [15:12] */ +#define MOON_MICD2_BIAS_STARTTIME_MASK 0xF000 /* MICD2_BIAS_STARTTIME - [15:12] */ +#define MOON_MICD2_BIAS_STARTTIME_SHIFT 12 /* MICD2_BIAS_STARTTIME - [15:12] */ +#define MOON_MICD2_BIAS_STARTTIME_WIDTH 4 /* MICD2_BIAS_STARTTIME - [15:12] */ +#define MOON_MICD2_RATE 0x0F00 /* MICD2_RATE - [11:8] */ +#define MOON_MICD2_RATE_MASK 0x0F00 /* MICD2_RATE - [11:8] */ +#define MOON_MICD2_RATE_SHIFT 8 /* MICD2_RATE - [11:8] */ +#define MOON_MICD2_RATE_WIDTH 4 /* MICD2_RATE - [11:8] */ +#define MOON_MICD2_BIAS_SRC 0x00F0 /* MICD2_BIAS_SRC - [7:4] */ +#define MOON_MICD2_BIAS_SRC_MASK 0x00F0 /* MICD2_BIAS_SRC - [7:4] */ +#define MOON_MICD2_BIAS_SRC_SHIFT 4 /* MICD2_BIAS_SRC - [7:4] */ +#define MOON_MICD2_BIAS_SRC_WIDTH 4 /* MICD2_BIAS_SRC - [7:4] */ +#define MOON_MICD2_DBTIME 0x0002 /* MICD2_DBTIME */ +#define MOON_MICD2_DBTIME_MASK 0x0002 /* MICD2_DBTIME */ +#define MOON_MICD2_DBTIME_SHIFT 1 /* MICD2_DBTIME */ +#define MOON_MICD2_DBTIME_WIDTH 1 /* MICD2_DBTIME */ +#define MOON_MICD2_ENA 0x0001 /* MICD2_ENA */ +#define MOON_MICD2_ENA_MASK 0x0001 /* MICD2_ENA */ +#define MOON_MICD2_ENA_SHIFT 0 /* MICD2_ENA */ +#define MOON_MICD2_ENA_WIDTH 1 /* MICD2_ENA */ + +/* + * R692 (0x2B4) - MICDET2_CONTROL_2 + */ +#define MOON_MICD2_LVL_SEL_MASK 0x00FF /* MICD2_LVL_SEL - [7:0] */ +#define MOON_MICD2_LVL_SEL_SHIFT 0 /* MICD2_LVL_SEL - [7:0] */ +#define MOON_MICD2_LVL_SEL_WIDTH 8 /* MICD2_LVL_SEL - [7:0] */ + +/* + * R693 (0x2B5) - MICDET2_CONTROL_3 + */ +#define MOON_MICD2_LVL 0x07FC /* MICD2_LVL - [10:2] */ +#define MOON_MICD2_LVL_MASK 0x07FC /* MICD2_LVL - [10:2] */ +#define MOON_MICD2_LVL_SHIFT 2 /* MICD2_LVL - [10:2] */ +#define MOON_MICD2_LVL_WIDTH 9 /* MICD2_LVL - [10:2] */ +#define MOON_MICD2_VALID 0x0002 /* MICD2_VALID */ +#define MOON_MICD2_VALID_MASK 0x0002 /* MICD2_VALID */ +#define MOON_MICD2_VALID_SHIFT 1 /* MICD2_VALID */ +#define MOON_MICD2_VALID_WIDTH 1 /* MICD2_VALID */ +#define MOON_MICD2_STS 0x0001 /* MICD2_STS */ +#define MOON_MICD2_STS_MASK 0x0001 /* MICD2_STS */ +#define MOON_MICD2_STS_SHIFT 0 /* MICD2_STS */ +#define MOON_MICD2_STS_WIDTH 1 /* MICD2_STS */ + +/* + * R699 (0x2BB) - MICDET2_CONTROL_4 + */ +#define MOON_MICD2_ADCVAL_DIFF 0xFF00 /* MICD2_ADCVAL_DIFF - [15:8] */ +#define MOON_MICD2_ADCVAL_DIFF_MASK 0xFF00 /* MICD2_ADCVAL_DIFF - [15:8] */ +#define MOON_MICD2_ADCVAL_DIFF_SHIFT 8 /* MICD2_ADCVAL_DIFF - [15:8] */ +#define MOON_MICD2_ADCVAL_DIFF_WIDTH 8 /* MICD2_ADCVAL_DIFF - [15:8] */ +#define MOON_MICD2_ADCVAL 0x007F /* MICD2_ADCVAL - [6:0] */ +#define MOON_MICD2_ADCVAL_MASK 0x007F /* MICD2_ADCVAL - [6:0] */ +#define MOON_MICD2_ADCVAL_SHIFT 0 /* MICD2_ADCVAL - [6:0] */ +#define MOON_MICD2_ADCVAL_WIDTH 7 /* MICD2_ADCVAL - [6:0] */ + /* * R707 (0x2C3) - Mic noise mix control 1 */ @@ -2213,6 +4388,14 @@ #define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */ #define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */ +/* + * R710 (0x2C6) - Micd Clamp control + */ +#define CLEARWATER_MICD_CLAMP_OVD_MASK 0x0010 /* MICD_CLAMP_OVD */ +#define CLEARWATER_MICD_CLAMP_OVD_SHIFT 4 /* MICD_CLAMP_OVD */ +#define CLEARWATER_MICD_CLAMP_OVD_WIDTH 1 /* MICD_CLAMP_OVD */ +#define CLEARWATER_MICD_CLAMP_OVD 0x0010 /* MICD_CLAMP_OVD */ + /* * R715 (0x2CB) - Isolation control */ @@ -2236,6 +4419,22 @@ /* * R768 (0x300) - Input Enables */ +#define ARIZONA_IN6L_ENA 0x0800 /* IN6L_ENA */ +#define ARIZONA_IN6L_ENA_MASK 0x0800 /* IN6L_ENA */ +#define ARIZONA_IN6L_ENA_SHIFT 11 /* IN6L_ENA */ +#define ARIZONA_IN6L_ENA_WIDTH 1 /* IN6L_ENA */ +#define ARIZONA_IN6R_ENA 0x0400 /* IN6R_ENA */ +#define ARIZONA_IN6R_ENA_MASK 0x0400 /* IN6R_ENA */ +#define ARIZONA_IN6R_ENA_SHIFT 10 /* IN6R_ENA */ +#define ARIZONA_IN6R_ENA_WIDTH 1 /* IN6R_ENA */ +#define ARIZONA_IN5L_ENA 0x0200 /* IN5L_ENA */ +#define ARIZONA_IN5L_ENA_MASK 0x0200 /* IN5L_ENA */ +#define ARIZONA_IN5L_ENA_SHIFT 9 /* IN5L_ENA */ +#define ARIZONA_IN5L_ENA_WIDTH 1 /* IN5L_ENA */ +#define ARIZONA_IN5R_ENA 0x0100 /* IN5R_ENA */ +#define ARIZONA_IN5R_ENA_MASK 0x0100 /* IN5R_ENA */ +#define ARIZONA_IN5R_ENA_SHIFT 8 /* IN5R_ENA */ +#define ARIZONA_IN5R_ENA_WIDTH 1 /* IN5R_ENA */ #define ARIZONA_IN4L_ENA 0x0080 /* IN4L_ENA */ #define ARIZONA_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */ #define ARIZONA_IN4L_ENA_SHIFT 7 /* IN4L_ENA */ @@ -2275,6 +4474,9 @@ #define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */ #define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */ #define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */ +#define MOON_IN_MODE_MASK 0x0400 /* IN_RATE_MODE */ +#define MOON_IN_MODE_SHIFT 10 /* IN_RATE_MODE */ +#define MOON_IN_MODE_WIDTH 1 /* IN_RATE_MODE */ /* * R777 (0x309) - Input Volume Ramp @@ -2286,18 +4488,31 @@ #define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ +/* + * R780 (0x30C) - HPF Control + */ +#define ARIZONA_IN_HPF_CUT_MASK 0x0007 /* IN_HPF_CUT [2:0] */ +#define ARIZONA_IN_HPF_CUT_SHIFT 0 /* IN_HPF_CUT [2:0] */ +#define ARIZONA_IN_HPF_CUT_WIDTH 3 /* IN_HPF_CUT [2:0] */ + /* * R784 (0x310) - IN1L Control */ +#define ARIZONA_IN1L_HPF_MASK 0x8000 /* IN1L_HPF - [15] */ +#define ARIZONA_IN1L_HPF_SHIFT 15 /* IN1L_HPF - [15] */ +#define ARIZONA_IN1L_HPF_WIDTH 1 /* IN1L_HPF - [15] */ #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */ #define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ #define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ #define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ -#define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ -#define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ -#define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ +#define ARIZONA_IN1_MODE_MASK 0x0400 /* IN1_MODE - [10] */ +#define ARIZONA_IN1_MODE_SHIFT 10 /* IN1_MODE - [10] */ +#define ARIZONA_IN1_MODE_WIDTH 1 /* IN1_MODE - [10] */ +#define ARIZONA_IN1_SINGLE_ENDED_MASK 0x0200 /* IN1_MODE - [9] */ +#define ARIZONA_IN1_SINGLE_ENDED_SHIFT 9 /* IN1_MODE - [9] */ +#define ARIZONA_IN1_SINGLE_ENDED_WIDTH 1 /* IN1_MODE - [9] */ #define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ #define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ #define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ @@ -2305,6 +4520,16 @@ /* * R785 (0x311) - ADC Digital Volume 1L */ +#define ARIZONA_IN1L_SRC_MASK 0x4000 /* IN1L_SRC - [14] */ +#define ARIZONA_IN1L_SRC_SHIFT 14 /* IN1L_SRC - [14] */ +#define ARIZONA_IN1L_SRC_WIDTH 1 /* IN1L_SRC - [14] */ +#define ARIZONA_IN1L_SRC_SE_MASK 0x2000 /* IN1L_SRC - [13] */ +#define ARIZONA_IN1L_SRC_SE_SHIFT 13 /* IN1L_SRC - [13] */ +#define ARIZONA_IN1L_SRC_SE_WIDTH 1 /* IN1L_SRC - [13] */ +#define MOON_IN1L_LP_MODE 0x0800 /* LP_MODE - [9] */ +#define MOON_IN1L_LP_MODE_MASK 0x0800 /* LP_MODE - [9] */ +#define MOON_IN1L_LP_MODE_SHIFT 11 /* LP_MODE - [9] */ +#define MOON_IN1L_LP_MODE_WIDTH 1 /* LP_MODE - [9] */ #define ARIZONA_IN_VU 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ @@ -2323,17 +4548,39 @@ #define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */ #define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */ #define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */ +#define CLEARWATER_IN1_OSR_MASK 0x0700 /* IN1_OSR - [8:10] */ +#define CLEARWATER_IN1_OSR_SHIFT 8 /* IN1_OSR - [8:10] */ +#define CLEARWATER_IN1_OSR_WIDTH 3 /* IN1_OSR - [8:10] */ + +/* +* R787 (0x313) - IN1L Rate Control +*/ +#define MOON_IN1L_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN1L_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN1L_RATE_WIDTH 4 /* IN_RATE - [3:0] */ /* * R788 (0x314) - IN1R Control */ +#define ARIZONA_IN1R_HPF_MASK 0x8000 /* IN1R_HPF - [15] */ +#define ARIZONA_IN1R_HPF_SHIFT 15 /* IN1R_HPF - [15] */ +#define ARIZONA_IN1R_HPF_WIDTH 1 /* IN1R_HPF - [15] */ #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ +#define MOON_IN1_DMICCLK_SRC_MASK 0x1800 /* DMICCLK_SRC[1:0] */ +#define MOON_IN1_DMICCLK_SRC_SHIFT 11 /* DMICCLK_SRC[1:0] */ +#define MOON_IN1_DMICCLK_SRC_WIDTH 2 /* DMICCLK_SRC[1:0] */ /* * R789 (0x315) - ADC Digital Volume 1R */ +#define ARIZONA_IN1R_SRC_MASK 0x4000 /* IN1R_SRC - [14] */ +#define ARIZONA_IN1R_SRC_SHIFT 14 /* IN1R_SRC - [14] */ +#define ARIZONA_IN1R_SRC_WIDTH 1 /* IN1R_SRC - [14] */ +#define ARIZONA_IN1R_SRC_SE_MASK 0x2000 /* IN1R_SRC - [13] */ +#define ARIZONA_IN1R_SRC_SE_SHIFT 13 /* IN1R_SRC - [13] */ +#define ARIZONA_IN1R_SRC_SE_WIDTH 1 /* IN1R_SRC - [13] */ #define ARIZONA_IN_VU 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ @@ -2353,18 +4600,31 @@ #define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */ #define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */ +/* +* R791 (0x317) - IN1R Rate Control +*/ +#define MOON_IN1R_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN1R_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN1R_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + /* * R792 (0x318) - IN2L Control */ +#define ARIZONA_IN2L_HPF_MASK 0x8000 /* IN2L_HPF - [15] */ +#define ARIZONA_IN2L_HPF_SHIFT 15 /* IN2L_HPF - [15] */ +#define ARIZONA_IN2L_HPF_WIDTH 1 /* IN2L_HPF - [15] */ #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */ #define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ #define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ #define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ -#define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ -#define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ -#define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ +#define ARIZONA_IN2_MODE_MASK 0x0400 /* IN2_MODE - [10] */ +#define ARIZONA_IN2_MODE_SHIFT 10 /* IN2_MODE - [10] */ +#define ARIZONA_IN2_MODE_WIDTH 1 /* IN2_MODE - [10] */ +#define ARIZONA_IN2_SINGLE_ENDED_MASK 0x0200 /* IN2_MODE - [9] */ +#define ARIZONA_IN2_SINGLE_ENDED_SHIFT 9 /* IN2_MODE - [9] */ +#define ARIZONA_IN2_SINGLE_ENDED_WIDTH 1 /* IN2_MODE - [9] */ #define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ #define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ #define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ @@ -2372,6 +4632,12 @@ /* * R793 (0x319) - ADC Digital Volume 2L */ +#define ARIZONA_IN2L_SRC_MASK 0x4000 /* IN2L_SRC - [14] */ +#define ARIZONA_IN2L_SRC_SHIFT 14 /* IN2L_SRC - [14] */ +#define ARIZONA_IN2L_SRC_WIDTH 1 /* IN2L_SRC - [14] */ +#define ARIZONA_IN2L_SRC_SE_MASK 0x2000 /* IN2L_SRC - [13] */ +#define ARIZONA_IN2L_SRC_SE_SHIFT 13 /* IN2L_SRC - [13] */ +#define ARIZONA_IN2L_SRC_SE_WIDTH 1 /* IN2L_SRC - [13] */ #define ARIZONA_IN_VU 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ @@ -2390,17 +4656,39 @@ #define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */ #define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */ #define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */ +#define CLEARWATER_IN2_OSR_MASK 0x0700 /* IN2_OSR - [8:10] */ +#define CLEARWATER_IN2_OSR_SHIFT 8 /* IN2_OSR - [8:10] */ +#define CLEARWATER_IN2_OSR_WIDTH 3 /* IN2_OSR - [8:10] */ + +/* +* R795 (0x31B) - IN2L Rate Control +*/ +#define MOON_IN2L_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN2L_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN2L_RATE_WIDTH 4 /* IN_RATE - [3:0] */ /* * R796 (0x31C) - IN2R Control */ +#define ARIZONA_IN2R_HPF_MASK 0x8000 /* IN2R_HPF - [15] */ +#define ARIZONA_IN2R_HPF_SHIFT 15 /* IN2R_HPF - [15] */ +#define ARIZONA_IN2R_HPF_WIDTH 1 /* IN2R_HPF - [15] */ #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ +#define MOON_IN2_DMICCLK_SRC_MASK 0x1800 /* DMICCLK_SRC[1:0] */ +#define MOON_IN2_DMICCLK_SRC_SHIFT 11 /* DMICCLK_SRC[1:0] */ +#define MOON_IN2_DMICCLK_SRC_WIDTH 2 /* DMICCLK_SRC[1:0] */ /* * R797 (0x31D) - ADC Digital Volume 2R */ +#define ARIZONA_IN2R_SRC_MASK 0x4000 /* IN2R_SRC - [14] */ +#define ARIZONA_IN2R_SRC_SHIFT 14 /* IN2R_SRC - [14] */ +#define ARIZONA_IN2R_SRC_WIDTH 1 /* IN2R_SRC - [14] */ +#define ARIZONA_IN2R_SRC_SE_MASK 0x2000 /* IN2R_SRC - [13] */ +#define ARIZONA_IN2R_SRC_SE_SHIFT 13 /* IN2R_SRC - [13] */ +#define ARIZONA_IN2R_SRC_SE_WIDTH 1 /* IN2R_SRC - [13] */ #define ARIZONA_IN_VU 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ @@ -2420,18 +4708,31 @@ #define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */ #define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */ +/* +* R799 (0x31F) - IN2R Rate Control +*/ +#define MOON_IN2R_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN2R_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN2R_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + /* * R800 (0x320) - IN3L Control */ +#define ARIZONA_IN3L_HPF_MASK 0x8000 /* IN3L_HPF - [15] */ +#define ARIZONA_IN3L_HPF_SHIFT 15 /* IN3L_HPF - [15] */ +#define ARIZONA_IN3L_HPF_WIDTH 1 /* IN3L_HPF - [15] */ #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */ #define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ #define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ #define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ -#define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ -#define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ -#define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ +#define ARIZONA_IN3_MODE_MASK 0x0400 /* IN3_MODE - [10] */ +#define ARIZONA_IN3_MODE_SHIFT 10 /* IN3_MODE - [10] */ +#define ARIZONA_IN3_MODE_WIDTH 1 /* IN3_MODE - [10] */ +#define ARIZONA_IN3_SINGLE_ENDED_MASK 0x0200 /* IN3_MODE - [9] */ +#define ARIZONA_IN3_SINGLE_ENDED_SHIFT 9 /* IN3_MODE - [9] */ +#define ARIZONA_IN3_SINGLE_ENDED_WIDTH 1 /* IN3_MODE - [9] */ #define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ #define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ #define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ @@ -2457,13 +4758,29 @@ #define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */ #define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */ #define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */ +#define CLEARWATER_IN3_OSR_MASK 0x0700 /* IN3_OSR - [8:10] */ +#define CLEARWATER_IN3_OSR_SHIFT 8 /* IN3_OSR - [8:10] */ +#define CLEARWATER_IN3_OSR_WIDTH 3 /* IN3_OSR - [8:10] */ + +/* +* R803 (0x323) - IN3L Rate Control +*/ +#define MOON_IN3L_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN3L_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN3L_RATE_WIDTH 4 /* IN_RATE - [3:0] */ /* * R804 (0x324) - IN3R Control */ +#define ARIZONA_IN3R_HPF_MASK 0x8000 /* IN3R_HPF - [15] */ +#define ARIZONA_IN3R_HPF_SHIFT 15 /* IN3R_HPF - [15] */ +#define ARIZONA_IN3R_HPF_WIDTH 1 /* IN3R_HPF - [15] */ #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ +#define MOON_IN3_DMICCLK_SRC_MASK 0x1800 /* DMICCLK_SRC[1:0] */ +#define MOON_IN3_DMICCLK_SRC_SHIFT 11 /* DMICCLK_SRC[1:0] */ +#define MOON_IN3_DMICCLK_SRC_WIDTH 2 /* DMICCLK_SRC[1:0] */ /* * R805 (0x325) - ADC Digital Volume 3R @@ -2487,9 +4804,19 @@ #define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */ #define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */ +/* +* R807 (0x327) - IN3R Rate Control +*/ +#define MOON_IN3R_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN3R_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN3R_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + /* * R808 (0x328) - IN4 Control */ +#define ARIZONA_IN4L_HPF_MASK 0x8000 /* IN4L_HPF - [15] */ +#define ARIZONA_IN4L_HPF_SHIFT 15 /* IN4L_HPF - [15] */ +#define ARIZONA_IN4L_HPF_WIDTH 1 /* IN4L_HPF - [15] */ #define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */ #define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */ #define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */ @@ -2518,6 +4845,26 @@ #define ARIZONA_IN4L_DMIC_DLY_MASK 0x003F /* IN4L_DMIC_DLY - [5:0] */ #define ARIZONA_IN4L_DMIC_DLY_SHIFT 0 /* IN4L_DMIC_DLY - [5:0] */ #define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */ +#define CLEARWATER_IN4_OSR_MASK 0x0700 /* IN4_OSR - [8:10] */ +#define CLEARWATER_IN4_OSR_SHIFT 8 /* IN4_OSR - [8:10] */ +#define CLEARWATER_IN4_OSR_WIDTH 3 /* IN4_OSR - [8:10] */ + +/* +* R811 (0x32B) - IN4L Rate Control +*/ +#define MOON_IN4L_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN4L_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN4L_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + +/* + * R812 (0x32C) - IN4R Control + */ +#define ARIZONA_IN4R_HPF_MASK 0x8000 /* IN4R_HPF - [15] */ +#define ARIZONA_IN4R_HPF_SHIFT 15 /* IN4R_HPF - [15] */ +#define ARIZONA_IN4R_HPF_WIDTH 1 /* IN4R_HPF - [15] */ +#define MOON_IN4_DMICCLK_SRC_MASK 0x1800 /* DMICCLK_SRC[1:0] */ +#define MOON_IN4_DMICCLK_SRC_SHIFT 11 /* DMICCLK_SRC[1:0] */ +#define MOON_IN4_DMICCLK_SRC_WIDTH 2 /* DMICCLK_SRC[1:0] */ /* * R813 (0x32D) - ADC Digital Volume 4R @@ -2541,9 +4888,213 @@ #define ARIZONA_IN4R_DMIC_DLY_SHIFT 0 /* IN4R_DMIC_DLY - [5:0] */ #define ARIZONA_IN4R_DMIC_DLY_WIDTH 6 /* IN4R_DMIC_DLY - [5:0] */ +/* +* R815 (0x32F) - IN4R Rate Control +*/ +#define MOON_IN4R_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN4R_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN4R_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + +/* + * R816 (0x330) - IN5L Control + */ +#define ARIZONA_IN5L_HPF_MASK 0x8000 /* IN5L_HPF - [15] */ +#define ARIZONA_IN5L_HPF_SHIFT 15 /* IN5L_HPF - [15] */ +#define ARIZONA_IN5L_HPF_WIDTH 1 /* IN5L_HPF - [15] */ +#define ARIZONA_IN5_OSR_MASK 0x6000 /* IN5_OSR - [14:13] */ +#define ARIZONA_IN5_OSR_SHIFT 13 /* IN5_OSR - [14:13] */ +#define ARIZONA_IN5_OSR_WIDTH 2 /* IN5_OSR - [14:13] */ +#define ARIZONA_IN5_DMIC_SUP_MASK 0x1800 /* IN5_DMIC_SUP - [12:11] */ +#define ARIZONA_IN5_DMIC_SUP_SHIFT 11 /* IN5_DMIC_SUP - [12:11] */ +#define ARIZONA_IN5_DMIC_SUP_WIDTH 2 /* IN5_DMIC_SUP - [12:11] */ + +/* + * R817 (0x331) - ADC Digital Volume 5L + */ +#define ARIZONA_IN_VU 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ +#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ +#define ARIZONA_IN5L_MUTE 0x0100 /* IN5L_MUTE */ +#define ARIZONA_IN5L_MUTE_MASK 0x0100 /* IN5L_MUTE */ +#define ARIZONA_IN5L_MUTE_SHIFT 8 /* IN5L_MUTE */ +#define ARIZONA_IN5L_MUTE_WIDTH 1 /* IN5L_MUTE */ +#define ARIZONA_IN5L_DIG_VOL_MASK 0x00FF /* IN5L_DIG_VOL - [7:0] */ +#define ARIZONA_IN5L_DIG_VOL_SHIFT 0 /* IN5L_DIG_VOL - [7:0] */ +#define ARIZONA_IN5L_DIG_VOL_WIDTH 8 /* IN5L_DIG_VOL - [7:0] */ + +/* + * R818 (0x332) - DMIC5L Control + */ +#define ARIZONA_IN5L_DMIC_DLY_MASK 0x003F /* IN5L_DMIC_DLY - [5:0] */ +#define ARIZONA_IN5L_DMIC_DLY_SHIFT 0 /* IN5L_DMIC_DLY - [5:0] */ +#define ARIZONA_IN5L_DMIC_DLY_WIDTH 6 /* IN5L_DMIC_DLY - [5:0] */ +#define CLEARWATER_IN5_OSR_MASK 0x0700 /* IN5_OSR - [8:10] */ +#define CLEARWATER_IN5_OSR_SHIFT 8 /* IN5_OSR - [8:10] */ +#define CLEARWATER_IN5_OSR_WIDTH 3 /* IN5_OSR - [8:10] */ + +/* +* R819 (0x333) - IN5L Rate Control +*/ +#define MOON_IN5L_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN5L_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN5L_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + +/* + * R820 (0x334) - IN5R Control + */ +#define ARIZONA_IN5R_HPF_MASK 0x8000 /* IN5R_HPF - [15] */ +#define ARIZONA_IN5R_HPF_SHIFT 15 /* IN5R_HPF - [15] */ +#define ARIZONA_IN5R_HPF_WIDTH 1 /* IN5R_HPF - [15] */ +#define MOON_IN5_DMICCLK_SRC_MASK 0x1800 /* DMICCLK_SRC[1:0] */ +#define MOON_IN5_DMICCLK_SRC_SHIFT 11 /* DMICCLK_SRC[1:0] */ +#define MOON_IN5_DMICCLK_SRC_WIDTH 2 /* DMICCLK_SRC[1:0] */ + +/* + * R821 (0x335) - ADC Digital Volume 5R + */ +#define ARIZONA_IN_VU 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ +#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ +#define ARIZONA_IN5R_MUTE 0x0100 /* IN5R_MUTE */ +#define ARIZONA_IN5R_MUTE_MASK 0x0100 /* IN5R_MUTE */ +#define ARIZONA_IN5R_MUTE_SHIFT 8 /* IN5R_MUTE */ +#define ARIZONA_IN5R_MUTE_WIDTH 1 /* IN5R_MUTE */ +#define ARIZONA_IN5R_DIG_VOL_MASK 0x00FF /* IN5R_DIG_VOL - [7:0] */ +#define ARIZONA_IN5R_DIG_VOL_SHIFT 0 /* IN5R_DIG_VOL - [7:0] */ +#define ARIZONA_IN5R_DIG_VOL_WIDTH 8 /* IN5R_DIG_VOL - [7:0] */ + +/* + * R822 (0x336) - DMIC5R Control + */ +#define ARIZONA_IN5R_DMIC_DLY_MASK 0x003F /* IN5R_DMIC_DLY - [5:0] */ +#define ARIZONA_IN5R_DMIC_DLY_SHIFT 0 /* IN5R_DMIC_DLY - [5:0] */ +#define ARIZONA_IN5R_DMIC_DLY_WIDTH 6 /* IN5R_DMIC_DLY - [5:0] */ + +/* +* R823 (0x337) - IN5R Rate Control +*/ +#define MOON_IN5R_RATE_MASK 0x7800 /* IN_RATE - [3:0] */ +#define MOON_IN5R_RATE_SHIFT 11 /* IN_RATE - [3:0] */ +#define MOON_IN5R_RATE_WIDTH 4 /* IN_RATE - [3:0] */ + +/* + * R824 (0x338) - IN6L Control + */ +#define ARIZONA_IN6L_HPF_MASK 0x8000 /* IN6L_HPF - [15] */ +#define ARIZONA_IN6L_HPF_SHIFT 15 /* IN6L_HPF - [15] */ +#define ARIZONA_IN6L_HPF_WIDTH 1 /* IN6L_HPF - [15] */ +#define ARIZONA_IN6_OSR_MASK 0x6000 /* IN6_OSR - [14:13] */ +#define ARIZONA_IN6_OSR_SHIFT 13 /* IN6_OSR - [14:13] */ +#define ARIZONA_IN6_OSR_WIDTH 2 /* IN6_OSR - [14:13] */ +#define ARIZONA_IN6_DMIC_SUP_MASK 0x1800 /* IN6_DMIC_SUP - [12:11] */ +#define ARIZONA_IN6_DMIC_SUP_SHIFT 11 /* IN6_DMIC_SUP - [12:11] */ +#define ARIZONA_IN6_DMIC_SUP_WIDTH 2 /* IN6_DMIC_SUP - [12:11] */ + +/* + * R825 (0x339) - ADC Digital Volume 6L + */ +#define ARIZONA_IN_VU 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ +#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ +#define ARIZONA_IN6L_MUTE 0x0100 /* IN6L_MUTE */ +#define ARIZONA_IN6L_MUTE_MASK 0x0100 /* IN6L_MUTE */ +#define ARIZONA_IN6L_MUTE_SHIFT 8 /* IN6L_MUTE */ +#define ARIZONA_IN6L_MUTE_WIDTH 1 /* IN6L_MUTE */ +#define ARIZONA_IN6L_DIG_VOL_MASK 0x00FF /* IN6L_DIG_VOL - [7:0] */ +#define ARIZONA_IN6L_DIG_VOL_SHIFT 0 /* IN6L_DIG_VOL - [7:0] */ +#define ARIZONA_IN6L_DIG_VOL_WIDTH 8 /* IN6L_DIG_VOL - [7:0] */ + +/* + * R826 (0x33A) - DMIC6L Control + */ +#define ARIZONA_IN6L_DMIC_DLY_MASK 0x003F /* IN6L_DMIC_DLY - [5:0] */ +#define ARIZONA_IN6L_DMIC_DLY_SHIFT 0 /* IN6L_DMIC_DLY - [5:0] */ +#define ARIZONA_IN6L_DMIC_DLY_WIDTH 6 /* IN6L_DMIC_DLY - [5:0] */ +#define CLEARWATER_IN6_OSR_MASK 0x0700 /* IN6_OSR - [8:10] */ +#define CLEARWATER_IN6_OSR_SHIFT 8 /* IN6_OSR - [8:10] */ +#define CLEARWATER_IN6_OSR_WIDTH 3 /* IN6_OSR - [8:10] */ + +/* + * R828 (0x33C) - IN6R Control + */ +#define ARIZONA_IN6R_HPF_MASK 0x8000 /* IN6R_HPF - [15] */ +#define ARIZONA_IN6R_HPF_SHIFT 15 /* IN6R_HPF - [15] */ +#define ARIZONA_IN6R_HPF_WIDTH 1 /* IN6R_HPF - [15] */ + +/* + * R829 (0x33D) - ADC Digital Volume 6R + */ +#define ARIZONA_IN_VU 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */ +#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */ +#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */ +#define ARIZONA_IN6R_MUTE 0x0100 /* IN6R_MUTE */ +#define ARIZONA_IN6R_MUTE_MASK 0x0100 /* IN6R_MUTE */ +#define ARIZONA_IN6R_MUTE_SHIFT 8 /* IN6R_MUTE */ +#define ARIZONA_IN6R_MUTE_WIDTH 1 /* IN6R_MUTE */ +#define ARIZONA_IN6R_DIG_VOL_MASK 0x00FF /* IN6R_DIG_VOL - [7:0] */ +#define ARIZONA_IN6R_DIG_VOL_SHIFT 0 /* IN6R_DIG_VOL - [7:0] */ +#define ARIZONA_IN6R_DIG_VOL_WIDTH 8 /* IN6R_DIG_VOL - [7:0] */ + +/* + * R830 (0x33E) - DMIC6R Control + */ +#define ARIZONA_IN6R_DMIC_DLY_MASK 0x003F /* IN6R_DMIC_DLY - [5:0] */ +#define ARIZONA_IN6R_DMIC_DLY_SHIFT 0 /* IN6R_DMIC_DLY - [5:0] */ +#define ARIZONA_IN6R_DMIC_DLY_WIDTH 6 /* IN6R_DMIC_DLY - [5:0] */ + +/* + * R915 (0x393) - ADC VCO Cal 4 + */ +#define ARIZONA_ADC1L_COUNT_RD_MASK 0x1FC0 /* ADC1L_COUNT_RD - [12:6] */ +#define ARIZONA_ADC1L_COUNT_RD_SHIFT 6 /* ADC1L_COUNT_RD - [12:6] */ +#define ARIZONA_ADC1L_COUNT_RD_WIDTH 7 /* ADC1L_COUNT_RD - [12:6] */ + +/* + * R916 (0x394) - ADC VCO Cal 5 + */ +#define ARIZONA_ADC1R_COUNT_RD_MASK 0x1FC0 /* ADC1R_COUNT_RD - [12:6] */ +#define ARIZONA_ADC1R_COUNT_RD_SHIFT 6 /* ADC1R_COUNT_RD - [12:6] */ +#define ARIZONA_ADC1R_COUNT_RD_WIDTH 7 /* ADC1R_COUNT_RD - [12:6] */ + +/* + * R917 (0x395) - ADC VCO Cal 6 + */ +#define ARIZONA_ADC2L_COUNT_RD_MASK 0x1FC0 /* ADC2L_COUNT_RD - [12:6] */ +#define ARIZONA_ADC2L_COUNT_RD_SHIFT 6 /* ADC2L_COUNT_RD - [12:6] */ +#define ARIZONA_ADC2L_COUNT_RD_WIDTH 7 /* ADC2L_COUNT_RD - [12:6] */ + +/* + * R918 (0x396) - ADC VCO Cal 7 + */ +#define ARIZONA_ADC2R_COUNT_RD_MASK 0x1FC0 /* ADC2R_COUNT_RD - [12:6] */ +#define ARIZONA_ADC2R_COUNT_RD_SHIFT 6 /* ADC2R_COUNT_RD - [12:6] */ +#define ARIZONA_ADC2R_COUNT_RD_WIDTH 7 /* ADC2R_COUNT_RD - [12:6] */ + +/* + * R919 (0x397) - ADC VCO Cal 8 + */ +#define ARIZONA_ADC3L_COUNT_RD_MASK 0x1FC0 /* ADC3L_COUNT_RD - [12:6] */ +#define ARIZONA_ADC3L_COUNT_RD_SHIFT 6 /* ADC3L_COUNT_RD - [12:6] */ +#define ARIZONA_ADC3L_COUNT_RD_WIDTH 7 /* ADC3L_COUNT_RD - [12:6] */ + +/* + * R920 (0x398) - ADC VCO Cal 9 + */ +#define ARIZONA_ADC3R_COUNT_RD_MASK 0x1FC0 /* ADC3R_COUNT_RD - [12:6] */ +#define ARIZONA_ADC3R_COUNT_RD_SHIFT 6 /* ADC3R_COUNT_RD - [12:6] */ +#define ARIZONA_ADC3R_COUNT_RD_WIDTH 7 /* ADC3R_COUNT_RD - [12:6] */ + /* * R1024 (0x400) - Output Enables 1 */ +#define ARIZONA_EP_SEL 0x8000 /* EP_SEL */ +#define ARIZONA_EP_SEL_MASK 0x8000 /* EP_SEL */ +#define ARIZONA_EP_SEL_SHIFT 15 /* EP_SEL */ +#define ARIZONA_EP_SEL_WIDTH 1 /* EP_SEL */ #define ARIZONA_OUT6L_ENA 0x0800 /* OUT6L_ENA */ #define ARIZONA_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */ #define ARIZONA_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */ @@ -2682,6 +5233,13 @@ #define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */ #define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */ +/* + * R1042 (0x412) - MOON_OUT1_CONFIG + */ +#define MOON_HP1_GND_SEL_MASK 0x0007 /* HP1_GND_SEL[2:0] */ +#define MOON_HP1_GND_SEL_SHIFT 0 /* HP1_GND_SEL[2:0] */ +#define MOON_HP1_GND_SEL_WIDTH 3 /* HP1_GND_SEL[2:0] */ + /* * R1043 (0x413) - Noise Gate Select 1L */ @@ -2772,6 +5330,13 @@ #define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */ #define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */ +/* + * R1050 (0x41A) - MOON_OUT2_CONFIG + */ +#define MOON_HP2_GND_SEL_MASK 0x0007 /* HP2_GND_SEL[2:0] */ +#define MOON_HP2_GND_SEL_SHIFT 0 /* HP2_GND_SEL[2:0] */ +#define MOON_HP2_GND_SEL_WIDTH 3 /* HP2_GND_SEL[2:0] */ + /* * R1051 (0x41B) - Noise Gate Select 2L */ @@ -3129,6 +5694,140 @@ #define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */ #define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */ +/* + * R1088 (0x440) - DRE Enable + */ +#define ARIZONA_DRE3R_ENA 0x0020 /* DRE3L_ENA */ +#define ARIZONA_DRE3R_ENA_MASK 0x0020 /* DRE3L_ENA */ +#define ARIZONA_DRE3R_ENA_SHIFT 5 /* DRE3L_ENA */ +#define ARIZONA_DRE3R_ENA_WIDTH 1 /* DRE3L_ENA */ +#define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */ +#define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */ +#define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */ +#define ARIZONA_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */ +#define ARIZONA_DRE2R_ENA 0x0008 /* DRE2R_ENA */ +#define ARIZONA_DRE2R_ENA_MASK 0x0008 /* DRE2R_ENA */ +#define ARIZONA_DRE2R_ENA_SHIFT 3 /* DRE2R_ENA */ +#define ARIZONA_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */ +#define ARIZONA_DRE2L_ENA 0x0004 /* DRE2L_ENA */ +#define ARIZONA_DRE2L_ENA_MASK 0x0004 /* DRE2L_ENA */ +#define ARIZONA_DRE2L_ENA_SHIFT 2 /* DRE2L_ENA */ +#define ARIZONA_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */ +#define ARIZONA_DRE1R_ENA 0x0002 /* DRE1R_ENA */ +#define ARIZONA_DRE1R_ENA_MASK 0x0002 /* DRE1R_ENA */ +#define ARIZONA_DRE1R_ENA_SHIFT 1 /* DRE1R_ENA */ +#define ARIZONA_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */ +#define ARIZONA_DRE1L_ENA 0x0001 /* DRE1L_ENA */ +#define ARIZONA_DRE1L_ENA_MASK 0x0001 /* DRE1L_ENA */ +#define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */ +#define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */ + +/* + * R1088 (0x440) - DRE Enable (Vegas) + */ +#define VEGAS_DRE3L_ENA 0x0020 /* DRE3L_ENA */ +#define VEGAS_DRE3L_ENA_MASK 0x0020 /* DRE3L_ENA */ +#define VEGAS_DRE3L_ENA_SHIFT 5 /* DRE3L_ENA */ +#define VEGAS_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */ +#define VEGAS_DRE3R_ENA 0x0010 /* DRE3R_ENA */ +#define VEGAS_DRE3R_ENA_MASK 0x0010 /* DRE3R_ENA */ +#define VEGAS_DRE3R_ENA_SHIFT 4 /* DRE3R_ENA */ +#define VEGAS_DRE3R_ENA_WIDTH 1 /* DRE3R_ENA */ +#define VEGAS_DRE2L_ENA 0x0008 /* DRE2L_ENA */ +#define VEGAS_DRE2L_ENA_MASK 0x0008 /* DRE2L_ENA */ +#define VEGAS_DRE2L_ENA_SHIFT 3 /* DRE2L_ENA */ +#define VEGAS_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */ +#define VEGAS_DRE2R_ENA 0x0004 /* DRE2R_ENA */ +#define VEGAS_DRE2R_ENA_MASK 0x0004 /* DRE2R_ENA */ +#define VEGAS_DRE2R_ENA_SHIFT 2 /* DRE2R_ENA */ +#define VEGAS_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */ +#define VEGAS_DRE1L_ENA 0x0002 /* DRE1L_ENA */ +#define VEGAS_DRE1L_ENA_MASK 0x0002 /* DRE1L_ENA */ +#define VEGAS_DRE1L_ENA_SHIFT 1 /* DRE1L_ENA */ +#define VEGAS_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */ +#define VEGAS_DRE1R_ENA 0x0001 /* DRE1R_ENA */ +#define VEGAS_DRE1R_ENA_MASK 0x0001 /* DRE1R_ENA */ +#define VEGAS_DRE1R_ENA_SHIFT 0 /* DRE1R_ENA */ +#define VEGAS_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */ + +/* + * R1089 (0x441) - DRE Control 1 + */ +#define ARIZONA_DRE_ENV_TC_FAST_MASK 0x0F00 /* DRE_ENV_TC_FAST - [11:8] */ +#define ARIZONA_DRE_ENV_TC_FAST_SHIFT 8 /* DRE_ENV_TC_FAST - [11:8] */ +#define ARIZONA_DRE_ENV_TC_FAST_WIDTH 4 /* DRE_ENV_TC_FAST - [11:8] */ + +/* + * R1090 (0x442) - DRE Control 2 + */ +#define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */ +#define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */ +#define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */ +#define ARIZONA_DRE_ALOG_VOL_DELAY_MASK 0x000F /* DRE_ALOG_VOL_DELAY - [3:0] */ +#define ARIZONA_DRE_ALOG_VOL_DELAY_SHIFT 0 /* DRE_ALOG_VOL_DELAY - [3:0] */ +#define ARIZONA_DRE_ALOG_VOL_DELAY_WIDTH 4 /* DRE_ALOG_VOL_DELAY - [3:0] */ + +/* + * R1091 (0x443) - DRE Control 3 + */ +#define ARIZONA_DRE_GAIN_SHIFT_MASK 0xC000 /* DRE_GAIN_SHIFT - [15:14] */ +#define ARIZONA_DRE_GAIN_SHIFT_SHIFT 14 /* DRE_GAIN_SHIFT - [15:14] */ +#define ARIZONA_DRE_GAIN_SHIFT_WIDTH 2 /* DRE_GAIN_SHIFT - [15:14] */ +#define ARIZONA_DRE_LOW_LEVEL_ABS_MASK 0x000F /* LOW_LEVEL_ABS - [3:0] */ +#define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */ +#define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */ + +/* R486 (0x448) - EDRE_Enable + */ +#define CLEARWATER_EDRE_OUT4L_THR3_ENA 0x0800 /* EDRE_OUT4L_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR3_ENA_MASK 0x0800 /* EDRE_OUT4L_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR3_ENA_SHIFT 11 /* EDRE_OUT4L_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR3_ENA_WIDTH 1 /* EDRE_OUT4L_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR3_ENA 0x0400 /* EDRE_OUT4R_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR3_ENA_MASK 0x0400 /* EDRE_OUT4R_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR3_ENA_SHIFT 10 /* EDRE_OUT4R_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR3_ENA_WIDTH 1 /* EDRE_OUT4R_THR3_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR2_ENA 0x0200 /* EDRE_OUT4L_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR2_ENA_MASK 0x0200 /* EDRE_OUT4L_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR2_ENA_SHIFT 9 /* EDRE_OUT4L_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR2_ENA_WIDTH 1 /* EDRE_OUT4L_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR2_ENA 0x0100 /* EDRE_OUT4R_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR2_ENA_MASK 0x0100 /* EDRE_OUT4R_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR2_ENA_SHIFT 8 /* EDRE_OUT4R_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR2_ENA_WIDTH 1 /* EDRE_OUT4R_THR2_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR1_ENA 0x0080 /* EDRE_OUT4L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR1_ENA_MASK 0x0080 /* EDRE_OUT4L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR1_ENA_SHIFT 7 /* EDRE_OUT4L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4L_THR1_ENA_WIDTH 1 /* EDRE_OUT4L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR1_ENA 0x0040 /* EDRE_OUT4R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR1_ENA_MASK 0x0040 /* EDRE_OUT4R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR1_ENA_SHIFT 6 /* EDRE_OUT4R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT4R_THR1_ENA_WIDTH 1 /* EDRE_OUT4R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3L_THR1_ENA 0x0020 /* EDRE_OUT3L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3L_THR1_ENA_MASK 0x0020 /* EDRE_OUT3L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3L_THR1_ENA_SHIFT 5 /* EDRE_OUT3L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3L_THR1_ENA_WIDTH 1 /* EDRE_OUT3L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3R_THR1_ENA 0x0010 /* EDRE_OUT3R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3R_THR1_ENA_MASK 0x0010 /* EDRE_OUT3R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3R_THR1_ENA_SHIFT 4 /* EDRE_OUT3R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT3R_THR1_ENA_WIDTH 1 /* EDRE_OUT3R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2L_THR1_ENA 0x0008 /* EDRE_OUT2L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2L_THR1_ENA_MASK 0x0008 /* EDRE_OUT2L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2L_THR1_ENA_SHIFT 3 /* EDRE_OUT2L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2L_THR1_ENA_WIDTH 1 /* EDRE_OUT2L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2R_THR1_ENA 0x0004 /* EDRE_OUT2R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2R_THR1_ENA_MASK 0x0004 /* EDRE_OUT2R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2R_THR1_ENA_SHIFT 2 /* EDRE_OUT2R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT2R_THR1_ENA_WIDTH 1 /* EDRE_OUT2R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1L_THR1_ENA 0x0002 /* EDRE_OUT1L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1L_THR1_ENA_MASK 0x0002 /* EDRE_OUT1L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1L_THR1_ENA_SHIFT 1 /* EDRE_OUT1L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1L_THR1_ENA_WIDTH 1 /* EDRE_OUT1L_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1R_THR1_ENA 0x0001 /* EDRE_OUT1R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1R_THR1_ENA_MASK 0x0001 /* EDRE_OUT1R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1R_THR1_ENA_SHIFT 0 /* EDRE_OUT1R_THR1_ENA */ +#define CLEARWATER_EDRE_OUT1R_THR1_ENA_WIDTH 1 /* EDRE_OUT1R_THR1_ENA */ + /* * R1104 (0x450) - DAC AEC Control 1 */ @@ -3212,6 +5911,139 @@ #define ARIZONA_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ +/* + * R1184 (0x4A0) - HP1 Short Circuit Ctrl + */ +#define ARIZONA_HP1_SC_ENA 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_MASK 0x1000 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_SHIFT 12 /* HP1_SC_ENA */ +#define ARIZONA_HP1_SC_ENA_WIDTH 1 /* HP1_SC_ENA */ + +/* + * R1185 (0x4A1) - HP2 Short Circuit Ctrl + */ +#define ARIZONA_HP2_SC_ENA 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_MASK 0x1000 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_SHIFT 12 /* HP2_SC_ENA */ +#define ARIZONA_HP2_SC_ENA_WIDTH 1 /* HP2_SC_ENA */ + +/* + * R1186 (0x4A2) - HP3 Short Circuit Ctrl + */ +#define ARIZONA_HP3_SC_ENA 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_MASK 0x1000 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_SHIFT 12 /* HP3_SC_ENA */ +#define ARIZONA_HP3_SC_ENA_WIDTH 1 /* HP3_SC_ENA */ + +/* + * R1188 (0x4A4) HP Test Ctrl 1 + */ +#define ARIZONA_HP1_TST_CAP_SEL_MASK 0x0003 /* HP1_TST_CAP_SEL - [1:0] */ +#define ARIZONA_HP1_TST_CAP_SEL_SHIFT 0 /* HP1_TST_CAP_SEL - [1:0] */ +#define ARIZONA_HP1_TST_CAP_SEL_WIDTH 2 /* HP1_TST_CAP_SEL - [1:0] */ + +/* + * R539 (0x4A8) - HP_Test_Ctrl_5 + */ +#define ARIZONA_HP1L_TST_CINT 0x4000 /* HP1L_TST_CINT */ +#define ARIZONA_HP1L_TST_CINT_MASK 0x4000 /* HP1L_TST_CINT */ +#define ARIZONA_HP1L_TST_CINT_SHIFT 14 /* HP1L_TST_CINT */ +#define ARIZONA_HP1L_TST_CINT_WIDTH 1 /* HP1L_TST_CINT */ +#define ARIZONA_HP1L_TST_GBW 0x3000 /* HP1L_TST_GBW - [13:12] */ +#define ARIZONA_HP1L_TST_GBW_MASK 0x3000 /* HP1L_TST_GBW - [13:12] */ +#define ARIZONA_HP1L_TST_GBW_SHIFT 12 /* HP1L_TST_GBW - [13:12] */ +#define ARIZONA_HP1L_TST_GBW_WIDTH 2 /* HP1L_TST_GBW - [13:12] */ +#define ARIZONA_HP1L_TST_PGAS 0x0800 /* HP1L_TST_PGAS */ +#define ARIZONA_HP1L_TST_PGAS_MASK 0x0800 /* HP1L_TST_PGAS */ +#define ARIZONA_HP1L_TST_PGAS_SHIFT 11 /* HP1L_TST_PGAS */ +#define ARIZONA_HP1L_TST_PGAS_WIDTH 1 /* HP1L_TST_PGAS */ +#define ARIZONA_HP1L_TST_DUMP 0x0400 /* HP1L_TST_DUMP */ +#define ARIZONA_HP1L_TST_DUMP_MASK 0x0400 /* HP1L_TST_DUMP */ +#define ARIZONA_HP1L_TST_DUMP_SHIFT 10 /* HP1L_TST_DUMP */ +#define ARIZONA_HP1L_TST_DUMP_WIDTH 1 /* HP1L_TST_DUMP */ +#define ARIZONA_HP1L_TST_RST 0x0200 /* HP1L_TST_RST */ +#define ARIZONA_HP1L_TST_RST_MASK 0x0200 /* HP1L_TST_RST */ +#define ARIZONA_HP1L_TST_RST_SHIFT 9 /* HP1L_TST_RST */ +#define ARIZONA_HP1L_TST_RST_WIDTH 1 /* HP1L_TST_RST */ +#define ARIZONA_HP1L_ONEFLT 0x0100 /* HP1L_ONEFLT */ +#define ARIZONA_HP1L_ONEFLT_MASK 0x0100 /* HP1L_ONEFLT */ +#define ARIZONA_HP1L_ONEFLT_SHIFT 8 /* HP1L_ONEFLT */ +#define ARIZONA_HP1L_ONEFLT_WIDTH 1 /* HP1L_ONEFLT */ +#define ARIZONA_HP1L_TST_THDOFF 0x00C0 /* HP1L_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1L_TST_THDOFF_MASK 0x00C0 /* HP1L_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1L_TST_THDOFF_SHIFT 6 /* HP1L_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1L_TST_THDOFF_WIDTH 2 /* HP1L_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1L_CTRL_IOUT 0x0030 /* HP1L_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1L_CTRL_IOUT_MASK 0x0030 /* HP1L_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1L_CTRL_IOUT_SHIFT 4 /* HP1L_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1L_CTRL_IOUT_WIDTH 2 /* HP1L_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1L_TST_ILG 0x0008 /* HP1L_TST_ILG */ +#define ARIZONA_HP1L_TST_ILG_MASK 0x0008 /* HP1L_TST_ILG */ +#define ARIZONA_HP1L_TST_ILG_SHIFT 3 /* HP1L_TST_ILG */ +#define ARIZONA_HP1L_TST_ILG_WIDTH 1 /* HP1L_TST_ILG */ +#define ARIZONA_HP1L_TST_IBIAS 0x0003 /* HP1L_TST_IBIAS - [1:0] */ +#define ARIZONA_HP1L_TST_IBIAS_MASK 0x0003 /* HP1L_TST_IBIAS - [1:0] */ +#define ARIZONA_HP1L_TST_IBIAS_SHIFT 0 /* HP1L_TST_IBIAS - [1:0] */ +#define ARIZONA_HP1L_TST_IBIAS_WIDTH 2 /* HP1L_TST_IBIAS - [1:0] */ + +/* + * R540 (0x4A9) - HP_Test_Ctrl_6 + */ +#define ARIZONA_HP1R_TST_CINT 0x4000 /* HP1R_TST_CINT */ +#define ARIZONA_HP1R_TST_CINT_MASK 0x4000 /* HP1R_TST_CINT */ +#define ARIZONA_HP1R_TST_CINT_SHIFT 14 /* HP1R_TST_CINT */ +#define ARIZONA_HP1R_TST_CINT_WIDTH 1 /* HP1R_TST_CINT */ +#define ARIZONA_HP1R_TST_GBW 0x3000 /* HP1R_TST_GBW - [13:12] */ +#define ARIZONA_HP1R_TST_GBW_MASK 0x3000 /* HP1R_TST_GBW - [13:12] */ +#define ARIZONA_HP1R_TST_GBW_SHIFT 12 /* HP1R_TST_GBW - [13:12] */ +#define ARIZONA_HP1R_TST_GBW_WIDTH 2 /* HP1R_TST_GBW - [13:12] */ +#define ARIZONA_HP1R_TST_PGAS 0x0800 /* HP1R_TST_PGAS */ +#define ARIZONA_HP1R_TST_PGAS_MASK 0x0800 /* HP1R_TST_PGAS */ +#define ARIZONA_HP1R_TST_PGAS_SHIFT 11 /* HP1R_TST_PGAS */ +#define ARIZONA_HP1R_TST_PGAS_WIDTH 1 /* HP1R_TST_PGAS */ +#define ARIZONA_HP1R_TST_DUMP 0x0400 /* HP1R_TST_DUMP */ +#define ARIZONA_HP1R_TST_DUMP_MASK 0x0400 /* HP1R_TST_DUMP */ +#define ARIZONA_HP1R_TST_DUMP_SHIFT 10 /* HP1R_TST_DUMP */ +#define ARIZONA_HP1R_TST_DUMP_WIDTH 1 /* HP1R_TST_DUMP */ +#define ARIZONA_HP1R_TST_RST 0x0200 /* HP1R_TST_RST */ +#define ARIZONA_HP1R_TST_RST_MASK 0x0200 /* HP1R_TST_RST */ +#define ARIZONA_HP1R_TST_RST_SHIFT 9 /* HP1R_TST_RST */ +#define ARIZONA_HP1R_TST_RST_WIDTH 1 /* HP1R_TST_RST */ +#define ARIZONA_HP1R_ONEFLT 0x0100 /* HP1R_ONEFLT */ +#define ARIZONA_HP1R_ONEFLT_MASK 0x0100 /* HP1R_ONEFLT */ +#define ARIZONA_HP1R_ONEFLT_SHIFT 8 /* HP1R_ONEFLT */ +#define ARIZONA_HP1R_ONEFLT_WIDTH 1 /* HP1R_ONEFLT */ +#define ARIZONA_HP1R_TST_THDOFF 0x00C0 /* HP1R_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1R_TST_THDOFF_MASK 0x00C0 /* HP1R_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1R_TST_THDOFF_SHIFT 6 /* HP1R_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1R_TST_THDOFF_WIDTH 2 /* HP1R_TST_THDOFF - [7:6] */ +#define ARIZONA_HP1R_CTRL_IOUT 0x0030 /* HP1R_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1R_CTRL_IOUT_MASK 0x0030 /* HP1R_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1R_CTRL_IOUT_SHIFT 4 /* HP1R_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1R_CTRL_IOUT_WIDTH 2 /* HP1R_CTRL_IOUT - [5:4] */ +#define ARIZONA_HP1R_TST_ILG 0x0008 /* HP1R_TST_ILG */ +#define ARIZONA_HP1R_TST_ILG_MASK 0x0008 /* HP1R_TST_ILG */ +#define ARIZONA_HP1R_TST_ILG_SHIFT 3 /* HP1R_TST_ILG */ +#define ARIZONA_HP1R_TST_ILG_WIDTH 1 /* HP1R_TST_ILG */ +#define ARIZONA_HP1R_TST_IBIAS 0x0003 /* HP1R_TST_IBIAS - [1:0] */ +#define ARIZONA_HP1R_TST_IBIAS_MASK 0x0003 /* HP1R_TST_IBIAS - [1:0] */ +#define ARIZONA_HP1R_TST_IBIAS_SHIFT 0 /* HP1R_TST_IBIAS - [1:0] */ +#define ARIZONA_HP1R_TST_IBIAS_WIDTH 2 /* HP1R_TST_IBIAS - [1:0] */ + +/* + * R1208 (0x4B8) - Speaker control 5 + */ +#define ARIZONA_SPK_THERM_ENA 0x1000 /* SPK_THERM_ENA */ +#define ARIZONA_SPK_THERM_ENA_MASK 0x1000 /* SPK_THERM_ENA */ +#define ARIZONA_SPK_THERM_ENA_SHIFT 12 /* SPK_THERM_ENA */ +#define ARIZONA_SPK_THERM_ENA_WIDTH 1 /* SPK_THERM_ENA */ +#define FLORIDA_SPK_THERM_ENA 0x0800 /* SPK_THERM_ENA */ +#define FLORIDA_SPK_THERM_ENA_MASK 0x0800 /* SPK_THERM_ENA */ +#define FLORIDA_SPK_THERM_ENA_SHIFT 11 /* SPK_THERM_ENA */ +#define FLORIDA_SPK_THERM_ENA_WIDTH 1 /* SPK_THERM_ENA */ + + + /* * R1244 (0x4DC) - DAC comp 1 */ @@ -3296,6 +6128,10 @@ /* * R1282 (0x502) - AIF1 Rx Pin Ctrl */ +#define ARIZONA_AIF1RX_LRCLK_ADV 0x0008 /* AIF1RX_LRCLK_ADV */ +#define ARIZONA_AIF1RX_LRCLK_ADV_MASK 0x0008 /* AIF1RX_LRCLK_ADV */ +#define ARIZONA_AIF1RX_LRCLK_ADV_SHIFT 3 /* AIF1RX_LRCLK_ADV */ +#define ARIZONA_AIF1RX_LRCLK_ADV_WIDTH 1 /* AIF1RX_LRCLK_ADV */ #define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ #define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ #define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ @@ -3678,6 +6514,48 @@ #define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */ #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ +/* + * R1355 (0x54B) - AIF2 Frame Ctrl 5 + */ +#define ARIZONA_AIF2TX3_SLOT_MASK 0x003F /* AIF2TX3_SLOT - [5:0] */ +#define ARIZONA_AIF2TX3_SLOT_SHIFT 0 /* AIF2TX3_SLOT - [5:0] */ +#define ARIZONA_AIF2TX3_SLOT_WIDTH 6 /* AIF2TX3_SLOT - [5:0] */ + +/* + * R1356 (0x54C) - AIF2 Frame Ctrl 6 + */ +#define ARIZONA_AIF2TX4_SLOT_MASK 0x003F /* AIF2TX4_SLOT - [5:0] */ +#define ARIZONA_AIF2TX4_SLOT_SHIFT 0 /* AIF2TX4_SLOT - [5:0] */ +#define ARIZONA_AIF2TX4_SLOT_WIDTH 6 /* AIF2TX4_SLOT - [5:0] */ + + +/* + * R1357 (0x54D) - AIF2 Frame Ctrl 7 + */ +#define ARIZONA_AIF2TX5_SLOT_MASK 0x003F /* AIF2TX5_SLOT - [5:0] */ +#define ARIZONA_AIF2TX5_SLOT_SHIFT 0 /* AIF2TX5_SLOT - [5:0] */ +#define ARIZONA_AIF2TX5_SLOT_WIDTH 6 /* AIF2TX5_SLOT - [5:0] */ + +/* + * R1358 (0x54E) - AIF2 Frame Ctrl 8 + */ +#define ARIZONA_AIF2TX6_SLOT_MASK 0x003F /* AIF2TX6_SLOT - [5:0] */ +#define ARIZONA_AIF2TX6_SLOT_SHIFT 0 /* AIF2TX6_SLOT - [5:0] */ +#define ARIZONA_AIF2TX6_SLOT_WIDTH 6 /* AIF2TX6_SLOT - [5:0] */ + +/* + * R1359 (0x54F) - AIF2 Frame Ctrl 9 + */ +#define ARIZONA_AIF2TX7_SLOT_MASK 0x003F /* AIF2TX7_SLOT - [5:0] */ +#define ARIZONA_AIF2TX7_SLOT_SHIFT 0 /* AIF2TX7_SLOT - [5:0] */ +#define ARIZONA_AIF2TX7_SLOT_WIDTH 6 /* AIF2TX7_SLOT - [5:0] */ +/* + * R1360 (0x550) - AIF2 Frame Ctrl 10 + */ +#define ARIZONA_AIF2TX8_SLOT_MASK 0x003F /* AIF2TX8_SLOT - [5:0] */ +#define ARIZONA_AIF2TX8_SLOT_SHIFT 0 /* AIF2TX8_SLOT - [5:0] */ +#define ARIZONA_AIF2TX8_SLOT_WIDTH 6 /* AIF2TX8_SLOT - [5:0] */ + /* * R1361 (0x551) - AIF2 Frame Ctrl 11 */ @@ -3692,9 +6570,75 @@ #define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */ #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ +/* + * R1363 (0x553) - AIF2 Frame Ctrl 13 + */ +#define ARIZONA_AIF2RX3_SLOT_MASK 0x003F /* AIF2RX3_SLOT - [5:0] */ +#define ARIZONA_AIF2RX3_SLOT_SHIFT 0 /* AIF2RX3_SLOT - [5:0] */ +#define ARIZONA_AIF2RX3_SLOT_WIDTH 6 /* AIF2RX3_SLOT - [5:0] */ + +/* + * R1364 (0x554) - AIF2 Frame Ctrl 14 + */ +#define ARIZONA_AIF2RX4_SLOT_MASK 0x003F /* AIF2RX4_SLOT - [5:0] */ +#define ARIZONA_AIF2RX4_SLOT_SHIFT 0 /* AIF2RX4_SLOT - [5:0] */ +#define ARIZONA_AIF2RX4_SLOT_WIDTH 6 /* AIF2RX4_SLOT - [5:0] */ + +/* + * R1365 (0x555) - AIF2 Frame Ctrl 15 + */ +#define ARIZONA_AIF2RX5_SLOT_MASK 0x003F /* AIF2RX5_SLOT - [5:0] */ +#define ARIZONA_AIF2RX5_SLOT_SHIFT 0 /* AIF2RX5_SLOT - [5:0] */ +#define ARIZONA_AIF2RX5_SLOT_WIDTH 6 /* AIF2RX5_SLOT - [5:0] */ + +/* + * R1366 (0x556) - AIF2 Frame Ctrl 16 + */ +#define ARIZONA_AIF2RX6_SLOT_MASK 0x003F /* AIF2RX6_SLOT - [5:0] */ +#define ARIZONA_AIF2RX6_SLOT_SHIFT 0 /* AIF2RX6_SLOT - [5:0] */ +#define ARIZONA_AIF2RX6_SLOT_WIDTH 6 /* AIF2RX6_SLOT - [5:0] */ + +/* + * R1367 (0x557) - AIF2 Frame Ctrl 17 + */ +#define ARIZONA_AIF2RX7_SLOT_MASK 0x003F /* AIF2RX7_SLOT - [5:0] */ +#define ARIZONA_AIF2RX7_SLOT_SHIFT 0 /* AIF2RX7_SLOT - [5:0] */ +#define ARIZONA_AIF2RX7_SLOT_WIDTH 6 /* AIF2RX7_SLOT - [5:0] */ + +/* + * R1368 (0x558) - AIF2 Frame Ctrl 18 + */ +#define ARIZONA_AIF2RX8_SLOT_MASK 0x003F /* AIF2RX8_SLOT - [5:0] */ +#define ARIZONA_AIF2RX8_SLOT_SHIFT 0 /* AIF2RX8_SLOT - [5:0] */ +#define ARIZONA_AIF2RX8_SLOT_WIDTH 6 /* AIF2RX8_SLOT - [5:0] */ + /* * R1369 (0x559) - AIF2 Tx Enables */ +#define ARIZONA_AIF2TX8_ENA 0x0080 /* AIF2TX8_ENA */ +#define ARIZONA_AIF2TX8_ENA_MASK 0x0080 /* AIF2TX8_ENA */ +#define ARIZONA_AIF2TX8_ENA_SHIFT 7 /* AIF2TX8_ENA */ +#define ARIZONA_AIF2TX8_ENA_WIDTH 1 /* AIF2TX8_ENA */ +#define ARIZONA_AIF2TX7_ENA 0x0040 /* AIF2TX7_ENA */ +#define ARIZONA_AIF2TX7_ENA_MASK 0x0040 /* AIF2TX7_ENA */ +#define ARIZONA_AIF2TX7_ENA_SHIFT 6 /* AIF2TX7_ENA */ +#define ARIZONA_AIF2TX7_ENA_WIDTH 1 /* AIF2TX7_ENA */ +#define ARIZONA_AIF2TX6_ENA 0x0020 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_MASK 0x0020 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_SHIFT 5 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX6_ENA_WIDTH 1 /* AIF2TX6_ENA */ +#define ARIZONA_AIF2TX5_ENA 0x0010 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_MASK 0x0010 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_SHIFT 4 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX5_ENA_WIDTH 1 /* AIF2TX5_ENA */ +#define ARIZONA_AIF2TX4_ENA 0x0008 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_MASK 0x0008 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_SHIFT 3 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX4_ENA_WIDTH 1 /* AIF2TX4_ENA */ +#define ARIZONA_AIF2TX3_ENA 0x0004 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_MASK 0x0004 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_SHIFT 2 /* AIF2TX3_ENA */ +#define ARIZONA_AIF2TX3_ENA_WIDTH 1 /* AIF2TX3_ENA */ #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ @@ -3707,6 +6651,30 @@ /* * R1370 (0x55A) - AIF2 Rx Enables */ +#define ARIZONA_AIF2RX8_ENA 0x0080 /* AIF2RX8_ENA */ +#define ARIZONA_AIF2RX8_ENA_MASK 0x0080 /* AIF2RX8_ENA */ +#define ARIZONA_AIF2RX8_ENA_SHIFT 7 /* AIF2RX8_ENA */ +#define ARIZONA_AIF2RX8_ENA_WIDTH 1 /* AIF2RX8_ENA */ +#define ARIZONA_AIF2RX7_ENA 0x0040 /* AIF2RX7_ENA */ +#define ARIZONA_AIF2RX7_ENA_MASK 0x0040 /* AIF2RX7_ENA */ +#define ARIZONA_AIF2RX7_ENA_SHIFT 6 /* AIF2RX7_ENA */ +#define ARIZONA_AIF2RX7_ENA_WIDTH 1 /* AIF2RX7_ENA */ +#define ARIZONA_AIF2RX6_ENA 0x0020 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_MASK 0x0020 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_SHIFT 5 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX6_ENA_WIDTH 1 /* AIF2RX6_ENA */ +#define ARIZONA_AIF2RX5_ENA 0x0010 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_MASK 0x0010 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_SHIFT 4 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX5_ENA_WIDTH 1 /* AIF2RX5_ENA */ +#define ARIZONA_AIF2RX4_ENA 0x0008 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_MASK 0x0008 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_SHIFT 3 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX4_ENA_WIDTH 1 /* AIF2RX4_ENA */ +#define ARIZONA_AIF2RX3_ENA 0x0004 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_MASK 0x0004 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_SHIFT 2 /* AIF2RX3_ENA */ +#define ARIZONA_AIF2RX3_ENA_WIDTH 1 /* AIF2RX3_ENA */ #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ @@ -3896,13 +6864,264 @@ #define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */ /* - * R1507 (0x5E3) - SLIMbus Framer Ref Gear + * R1440 (0x5A0) - AIF4 BCLK Ctrl */ -#define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */ -#define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */ -#define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */ -#define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */ -#define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */ +#define ARIZONA_AIF4_BCLK_INV 0x0080 /* AIF4_BCLK_INV */ +#define ARIZONA_AIF4_BCLK_INV_MASK 0x0080 /* AIF4_BCLK_INV */ +#define ARIZONA_AIF4_BCLK_INV_SHIFT 7 /* AIF4_BCLK_INV */ +#define ARIZONA_AIF4_BCLK_INV_WIDTH 1 /* AIF4_BCLK_INV */ +#define ARIZONA_AIF4_BCLK_FRC 0x0040 /* AIF4_BCLK_FRC */ +#define ARIZONA_AIF4_BCLK_FRC_MASK 0x0040 /* AIF4_BCLK_FRC */ +#define ARIZONA_AIF4_BCLK_FRC_SHIFT 6 /* AIF4_BCLK_FRC */ +#define ARIZONA_AIF4_BCLK_FRC_WIDTH 1 /* AIF4_BCLK_FRC */ +#define ARIZONA_AIF4_BCLK_MSTR 0x0020 /* AIF4_BCLK_MSTR */ +#define ARIZONA_AIF4_BCLK_MSTR_MASK 0x0020 /* AIF4_BCLK_MSTR */ +#define ARIZONA_AIF4_BCLK_MSTR_SHIFT 5 /* AIF4_BCLK_MSTR */ +#define ARIZONA_AIF4_BCLK_MSTR_WIDTH 1 /* AIF4_BCLK_MSTR */ +#define ARIZONA_AIF4_BCLK_FREQ_MASK 0x001F /* AIF4_BCLK_FREQ - [4:0] */ +#define ARIZONA_AIF4_BCLK_FREQ_SHIFT 0 /* AIF4_BCLK_FREQ - [4:0] */ +#define ARIZONA_AIF4_BCLK_FREQ_WIDTH 5 /* AIF4_BCLK_FREQ - [4:0] */ + +/* + * R1441 (0x5A1) - AIF4 Tx Pin Ctrl + */ +#define ARIZONA_AIF4TX_DAT_TRI 0x0020 /* AIF4TX_DAT_TRI */ +#define ARIZONA_AIF4TX_DAT_TRI_MASK 0x0020 /* AIF4TX_DAT_TRI */ +#define ARIZONA_AIF4TX_DAT_TRI_SHIFT 5 /* AIF4TX_DAT_TRI */ +#define ARIZONA_AIF4TX_DAT_TRI_WIDTH 1 /* AIF4TX_DAT_TRI */ +#define ARIZONA_AIF4TX_LRCLK_SRC 0x0008 /* AIF4TX_LRCLK_SRC */ +#define ARIZONA_AIF4TX_LRCLK_SRC_MASK 0x0008 /* AIF4TX_LRCLK_SRC */ +#define ARIZONA_AIF4TX_LRCLK_SRC_SHIFT 3 /* AIF4TX_LRCLK_SRC */ +#define ARIZONA_AIF4TX_LRCLK_SRC_WIDTH 1 /* AIF4TX_LRCLK_SRC */ +#define ARIZONA_AIF4TX_LRCLK_INV 0x0004 /* AIF4TX_LRCLK_INV */ +#define ARIZONA_AIF4TX_LRCLK_INV_MASK 0x0004 /* AIF4TX_LRCLK_INV */ +#define ARIZONA_AIF4TX_LRCLK_INV_SHIFT 2 /* AIF4TX_LRCLK_INV */ +#define ARIZONA_AIF4TX_LRCLK_INV_WIDTH 1 /* AIF4TX_LRCLK_INV */ +#define ARIZONA_AIF4TX_LRCLK_FRC 0x0002 /* AIF4TX_LRCLK_FRC */ +#define ARIZONA_AIF4TX_LRCLK_FRC_MASK 0x0002 /* AIF4TX_LRCLK_FRC */ +#define ARIZONA_AIF4TX_LRCLK_FRC_SHIFT 1 /* AIF4TX_LRCLK_FRC */ +#define ARIZONA_AIF4TX_LRCLK_FRC_WIDTH 1 /* AIF4TX_LRCLK_FRC */ +#define ARIZONA_AIF4TX_LRCLK_MSTR 0x0001 /* AIF4TX_LRCLK_MSTR */ +#define ARIZONA_AIF4TX_LRCLK_MSTR_MASK 0x0001 /* AIF4TX_LRCLK_MSTR */ +#define ARIZONA_AIF4TX_LRCLK_MSTR_SHIFT 0 /* AIF4TX_LRCLK_MSTR */ +#define ARIZONA_AIF4TX_LRCLK_MSTR_WIDTH 1 /* AIF4TX_LRCLK_MSTR */ + +/* + * R1442 (0x5A2) - AIF4 Rx Pin Ctrl + */ +#define ARIZONA_AIF4RX_LRCLK_INV 0x0004 /* AIF4RX_LRCLK_INV */ +#define ARIZONA_AIF4RX_LRCLK_INV_MASK 0x0004 /* AIF4RX_LRCLK_INV */ +#define ARIZONA_AIF4RX_LRCLK_INV_SHIFT 2 /* AIF4RX_LRCLK_INV */ +#define ARIZONA_AIF4RX_LRCLK_INV_WIDTH 1 /* AIF4RX_LRCLK_INV */ +#define ARIZONA_AIF4RX_LRCLK_FRC 0x0002 /* AIF4RX_LRCLK_FRC */ +#define ARIZONA_AIF4RX_LRCLK_FRC_MASK 0x0002 /* AIF4RX_LRCLK_FRC */ +#define ARIZONA_AIF4RX_LRCLK_FRC_SHIFT 1 /* AIF4RX_LRCLK_FRC */ +#define ARIZONA_AIF4RX_LRCLK_FRC_WIDTH 1 /* AIF4RX_LRCLK_FRC */ +#define ARIZONA_AIF4RX_LRCLK_MSTR 0x0001 /* AIF4RX_LRCLK_MSTR */ +#define ARIZONA_AIF4RX_LRCLK_MSTR_MASK 0x0001 /* AIF4RX_LRCLK_MSTR */ +#define ARIZONA_AIF4RX_LRCLK_MSTR_SHIFT 0 /* AIF4RX_LRCLK_MSTR */ +#define ARIZONA_AIF4RX_LRCLK_MSTR_WIDTH 1 /* AIF4RX_LRCLK_MSTR */ + +/* + * R1443 (0x5A3) - AIF4 Rate Ctrl + */ +#define ARIZONA_AIF4_RATE_MASK 0x7800 /* AIF4_RATE - [14:11] */ +#define ARIZONA_AIF4_RATE_SHIFT 11 /* AIF4_RATE - [14:11] */ +#define ARIZONA_AIF4_RATE_WIDTH 4 /* AIF4_RATE - [14:11] */ +#define ARIZONA_AIF4_TRI 0x0040 /* AIF4_TRI */ +#define ARIZONA_AIF4_TRI_MASK 0x0040 /* AIF4_TRI */ +#define ARIZONA_AIF4_TRI_SHIFT 6 /* AIF4_TRI */ +#define ARIZONA_AIF4_TRI_WIDTH 1 /* AIF4_TRI */ + +/* + * R1444 (0x5A4) - AIF4 Format + */ +#define ARIZONA_AIF4_FMT_MASK 0x0007 /* AIF4_FMT - [2:0] */ +#define ARIZONA_AIF4_FMT_SHIFT 0 /* AIF4_FMT - [2:0] */ +#define ARIZONA_AIF4_FMT_WIDTH 3 /* AIF4_FMT - [2:0] */ + +/* + * R1445 (0x5A5) - AIF4 Tx BCLK Rate + */ +#define ARIZONA_AIF4TX_BCPF_MASK 0x1FFF /* AIF4TX_BCPF - [12:0] */ +#define ARIZONA_AIF4TX_BCPF_SHIFT 0 /* AIF4TX_BCPF - [12:0] */ +#define ARIZONA_AIF4TX_BCPF_WIDTH 13 /* AIF4TX_BCPF - [12:0] */ + +/* + * R1446 (0x5A6) - AIF4 Rx BCLK Rate + */ +#define ARIZONA_AIF4RX_BCPF_MASK 0x1FFF /* AIF4RX_BCPF - [12:0] */ +#define ARIZONA_AIF4RX_BCPF_SHIFT 0 /* AIF4RX_BCPF - [12:0] */ +#define ARIZONA_AIF4RX_BCPF_WIDTH 13 /* AIF4RX_BCPF - [12:0] */ + +/* + * R1447 (0x5A7) - AIF4 Frame Ctrl 1 + */ +#define ARIZONA_AIF4TX_WL_MASK 0x3F00 /* AIF4TX_WL - [13:8] */ +#define ARIZONA_AIF4TX_WL_SHIFT 8 /* AIF4TX_WL - [13:8] */ +#define ARIZONA_AIF4TX_WL_WIDTH 6 /* AIF4TX_WL - [13:8] */ +#define ARIZONA_AIF4TX_SLOT_LEN_MASK 0x00FF /* AIF4TX_SLOT_LEN - [7:0] */ +#define ARIZONA_AIF4TX_SLOT_LEN_SHIFT 0 /* AIF4TX_SLOT_LEN - [7:0] */ +#define ARIZONA_AIF4TX_SLOT_LEN_WIDTH 8 /* AIF4TX_SLOT_LEN - [7:0] */ + +/* + * R1448 (0x5A8) - AIF4 Frame Ctrl 2 + */ +#define ARIZONA_AIF4RX_WL_MASK 0x3F00 /* AIF4RX_WL - [13:8] */ +#define ARIZONA_AIF4RX_WL_SHIFT 8 /* AIF4RX_WL - [13:8] */ +#define ARIZONA_AIF4RX_WL_WIDTH 6 /* AIF4RX_WL - [13:8] */ +#define ARIZONA_AIF4RX_SLOT_LEN_MASK 0x00FF /* AIF4RX_SLOT_LEN - [7:0] */ +#define ARIZONA_AIF4RX_SLOT_LEN_SHIFT 0 /* AIF4RX_SLOT_LEN - [7:0] */ +#define ARIZONA_AIF4RX_SLOT_LEN_WIDTH 8 /* AIF4RX_SLOT_LEN - [7:0] */ + +/* + * R1449 (0x5A9) - AIF4 Frame Ctrl 3 + */ +#define ARIZONA_AIF4TX1_SLOT_MASK 0x003F /* AIF4TX1_SLOT - [5:0] */ +#define ARIZONA_AIF4TX1_SLOT_SHIFT 0 /* AIF4TX1_SLOT - [5:0] */ +#define ARIZONA_AIF4TX1_SLOT_WIDTH 6 /* AIF4TX1_SLOT - [5:0] */ + +/* + * R1450 (0x5AA) - AIF4 Frame Ctrl 4 + */ +#define ARIZONA_AIF4TX2_SLOT_MASK 0x003F /* AIF4TX2_SLOT - [5:0] */ +#define ARIZONA_AIF4TX2_SLOT_SHIFT 0 /* AIF4TX2_SLOT - [5:0] */ +#define ARIZONA_AIF4TX2_SLOT_WIDTH 6 /* AIF4TX2_SLOT - [5:0] */ + +/* + * R1457 (0x5B1) - AIF4 Frame Ctrl 11 + */ +#define ARIZONA_AIF4RX1_SLOT_MASK 0x003F /* AIF4RX1_SLOT - [5:0] */ +#define ARIZONA_AIF4RX1_SLOT_SHIFT 0 /* AIF4RX1_SLOT - [5:0] */ +#define ARIZONA_AIF4RX1_SLOT_WIDTH 6 /* AIF4RX1_SLOT - [5:0] */ + +/* + * R1458 (0x5B2) - AIF4 Frame Ctrl 12 + */ +#define ARIZONA_AIF4RX2_SLOT_MASK 0x003F /* AIF4RX2_SLOT - [5:0] */ +#define ARIZONA_AIF4RX2_SLOT_SHIFT 0 /* AIF4RX2_SLOT - [5:0] */ +#define ARIZONA_AIF4RX2_SLOT_WIDTH 6 /* AIF4RX2_SLOT - [5:0] */ + +/* + * R1465 (0x5B9) - AIF4 Tx Enables + */ +#define ARIZONA_AIF4TX2_ENA 0x0002 /* AIF4TX2_ENA */ +#define ARIZONA_AIF4TX2_ENA_MASK 0x0002 /* AIF4TX2_ENA */ +#define ARIZONA_AIF4TX2_ENA_SHIFT 1 /* AIF4TX2_ENA */ +#define ARIZONA_AIF4TX2_ENA_WIDTH 1 /* AIF4TX2_ENA */ +#define ARIZONA_AIF4TX1_ENA 0x0001 /* AIF4TX1_ENA */ +#define ARIZONA_AIF4TX1_ENA_MASK 0x0001 /* AIF4TX1_ENA */ +#define ARIZONA_AIF4TX1_ENA_SHIFT 0 /* AIF4TX1_ENA */ +#define ARIZONA_AIF4TX1_ENA_WIDTH 1 /* AIF4TX1_ENA */ + +/* + * R1466 (0x5BA) - AIF4 Rx Enables + */ +#define ARIZONA_AIF4RX2_ENA 0x0002 /* AIF4RX2_ENA */ +#define ARIZONA_AIF4RX2_ENA_MASK 0x0002 /* AIF4RX2_ENA */ +#define ARIZONA_AIF4RX2_ENA_SHIFT 1 /* AIF4RX2_ENA */ +#define ARIZONA_AIF4RX2_ENA_WIDTH 1 /* AIF4RX2_ENA */ +#define ARIZONA_AIF4RX1_ENA 0x0001 /* AIF4RX1_ENA */ +#define ARIZONA_AIF4RX1_ENA_MASK 0x0001 /* AIF4RX1_ENA */ +#define ARIZONA_AIF4RX1_ENA_SHIFT 0 /* AIF4RX1_ENA */ +#define ARIZONA_AIF4RX1_ENA_WIDTH 1 /* AIF4RX1_ENA */ + +/* + * R1467 (0x5BB) - AIF4 Force Write + */ +#define ARIZONA_AIF4_FRC_WR 0x0001 /* AIF4_FRC_WR */ +#define ARIZONA_AIF4_FRC_WR_MASK 0x0001 /* AIF4_FRC_WR */ +#define ARIZONA_AIF4_FRC_WR_SHIFT 0 /* AIF4_FRC_WR */ +#define ARIZONA_AIF4_FRC_WR_WIDTH 1 /* AIF4_FRC_WR */ + +/* + * R1474 (0x5C2) - SPD1 TX Control + */ +#define ARIZONA_SPD1_VAL2 0x2000 /* SPD1_VAL2 */ +#define ARIZONA_SPD1_VAL2_MASK 0x2000 /* SPD1_VAL2 */ +#define ARIZONA_SPD1_VAL2_SHIFT 13 /* SPD1_VAL2 */ +#define ARIZONA_SPD1_VAL2_WIDTH 1 /* SPD1_VAL2 */ +#define ARIZONA_SPD1_VAL1 0x1000 /* SPD1_VAL1 */ +#define ARIZONA_SPD1_VAL1_MASK 0x1000 /* SPD1_VAL1 */ +#define ARIZONA_SPD1_VAL1_SHIFT 12 /* SPD1_VAL1 */ +#define ARIZONA_SPD1_VAL1_WIDTH 1 /* SPD1_VAL1 */ +#define ARIZONA_SPD1_RATE_MASK 0x00F0 /* SPD1_RATE */ +#define ARIZONA_SPD1_RATE_SHIFT 4 /* SPD1_RATE */ +#define ARIZONA_SPD1_RATE_WIDTH 4 /* SPD1_RATE */ +#define ARIZONA_SPD1_ENA 0x0001 /* SPD1_ENA */ +#define ARIZONA_SPD1_ENA_MASK 0x0001 /* SPD1_ENA */ +#define ARIZONA_SPD1_ENA_SHIFT 0 /* SPD1_ENA */ +#define ARIZONA_SPD1_ENA_WIDTH 1 /* SPD1_ENA */ + +/* + * R1475 (0x5C3) - SPD1 TX Channel Status 1 + */ +#define ARIZONA_SPD1_CATCODE_MASK 0xFF00 /* SPD1_CATCODE */ +#define ARIZONA_SPD1_CATCODE_SHIFT 8 /* SPD1_CATCODE */ +#define ARIZONA_SPD1_CATCODE_WIDTH 8 /* SPD1_CATCODE */ +#define ARIZONA_SPD1_CHSTMODE_MASK 0x00C0 /* SPD1_CHSTMODE */ +#define ARIZONA_SPD1_CHSTMODE_SHIFT 6 /* SPD1_CHSTMODE */ +#define ARIZONA_SPD1_CHSTMODE_WIDTH 2 /* SPD1_CHSTMODE */ +#define ARIZONA_SPD1_PREEMPH_MASK 0x0038 /* SPD1_PREEMPH */ +#define ARIZONA_SPD1_PREEMPH_SHIFT 3 /* SPD1_PREEMPH */ +#define ARIZONA_SPD1_PREEMPH_WIDTH 3 /* SPD1_PREEMPH */ +#define ARIZONA_SPD1_NOCOPY 0x0004 /* SPD1_NOCOPY */ +#define ARIZONA_SPD1_NOCOPY_MASK 0x0004 /* SPD1_NOCOPY */ +#define ARIZONA_SPD1_NOCOPY_SHIFT 2 /* SPD1_NOCOPY */ +#define ARIZONA_SPD1_NOCOPY_WIDTH 1 /* SPD1_NOCOPY */ +#define ARIZONA_SPD1_NOAUDIO 0x0002 /* SPD1_NOAUDIO */ +#define ARIZONA_SPD1_NOAUDIO_MASK 0x0002 /* SPD1_NOAUDIO */ +#define ARIZONA_SPD1_NOAUDIO_SHIFT 1 /* SPD1_NOAUDIO */ +#define ARIZONA_SPD1_NOAUDIO_WIDTH 1 /* SPD1_NOAUDIO */ +#define ARIZONA_SPD1_PRO 0x0001 /* SPD1_PRO */ +#define ARIZONA_SPD1_PRO_MASK 0x0001 /* SPD1_PRO */ +#define ARIZONA_SPD1_PRO_SHIFT 0 /* SPD1_PRO */ +#define ARIZONA_SPD1_PRO_WIDTH 1 /* SPD1_PRO */ + +/* + * R1475 (0x5C4) - SPD1 TX Channel Status 2 + */ +#define ARIZONA_SPD1_FREQ_MASK 0xF000 /* SPD1_FREQ */ +#define ARIZONA_SPD1_FREQ_SHIFT 12 /* SPD1_FREQ */ +#define ARIZONA_SPD1_FREQ_WIDTH 4 /* SPD1_FREQ */ +#define ARIZONA_SPD1_CHNUM2_MASK 0x0F00 /* SPD1_CHNUM2 */ +#define ARIZONA_SPD1_CHNUM2_SHIFT 8 /* SPD1_CHNUM2 */ +#define ARIZONA_SPD1_CHNUM2_WIDTH 4 /* SPD1_CHNUM2 */ +#define ARIZONA_SPD1_CHNUM1_MASK 0x00F0 /* SPD1_CHNUM1 */ +#define ARIZONA_SPD1_CHNUM1_SHIFT 4 /* SPD1_CHNUM1 */ +#define ARIZONA_SPD1_CHNUM1_WIDTH 4 /* SPD1_CHNUM1 */ +#define ARIZONA_SPD1_SRCNUM_MASK 0x000F /* SPD1_SRCNUM */ +#define ARIZONA_SPD1_SRCNUM_SHIFT 0 /* SPD1_SRCNUM */ +#define ARIZONA_SPD1_SRCNUM_WIDTH 4 /* SPD1_SRCNUM */ + +/* + * R1475 (0x5C5) - SPD1 TX Channel Status 3 + */ +#define ARIZONA_SPD1_ORGSAMP_MASK 0x0F00 /* SPD1_ORGSAMP */ +#define ARIZONA_SPD1_ORGSAMP_SHIFT 8 /* SPD1_ORGSAMP */ +#define ARIZONA_SPD1_ORGSAMP_WIDTH 4 /* SPD1_ORGSAMP */ +#define ARIZONA_SPD1_TXWL_MASK 0x00E0 /* SPD1_TXWL */ +#define ARIZONA_SPD1_TXWL_SHIFT 5 /* SPD1_TXWL */ +#define ARIZONA_SPD1_TXWL_WIDTH 3 /* SPD1_TXWL */ +#define ARIZONA_SPD1_MAXWL 0x0010 /* SPD1_MAXWL */ +#define ARIZONA_SPD1_MAXWL_MASK 0x0010 /* SPD1_MAXWL */ +#define ARIZONA_SPD1_MAXWL_SHIFT 4 /* SPD1_MAXWL */ +#define ARIZONA_SPD1_MAXWL_WIDTH 1 /* SPD1_MAXWL */ +#define ARIZONA_SPD1_CS31_30_MASK 0x000C /* SPD1_CS31_30 */ +#define ARIZONA_SPD1_CS31_30_SHIFT 2 /* SPD1_CS31_30 */ +#define ARIZONA_SPD1_CS31_30_WIDTH 2 /* SPD1_CS31_30 */ +#define ARIZONA_SPD1_CLKACU_MASK 0x0003 /* SPD1_CLKACU */ +#define ARIZONA_SPD1_CLKACU_SHIFT 2 /* SPD1_CLKACU */ +#define ARIZONA_SPD1_CLKACU_WIDTH 0 /* SPD1_CLKACU */ + +/* + * R1507 (0x5E3) - SLIMbus Framer Ref Gear + */ +#define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */ +#define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */ +#define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */ +#define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */ +#define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */ #define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */ #define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */ @@ -4149,6 +7368,13 @@ #define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */ #define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */ +/* + * R3096 (0xC18) - GP Switch 1 + */ +#define ARIZONA_SW1_MODE_MASK 0x0003 /* SW1_MODE - [1:0] */ +#define ARIZONA_SW1_MODE_SHIFT 0 /* SW1_MODE - [1:0] */ +#define ARIZONA_SW1_MODE_WIDTH 2 /* SW1_MODE - [1:0] */ + /* * R3104 (0xC20) - Misc Pad Ctrl 1 */ @@ -4360,14 +7586,14 @@ /* * R3330 (0xD02) - Interrupt Status 3 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */ -#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT1 0x8000 /* SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT1_MASK 0x8000 /* SPK_OVERHEAD_WARN_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT1_SHIFT 15 /* SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_EINT1 0x4000 /* SPK_OVERHEAT_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_EINT1_MASK 0x4000 /* SPK_OVERHEAT_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_EINT1_SHIFT 14 /* SPK_OVERHEAT_EINT1 */ +#define ARIZONA_SPK_OVERHEAT_EINT1_WIDTH 1 /* SPK_OVERHEAT_EINT1 */ #define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */ #define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */ #define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */ @@ -4464,6 +7690,77 @@ #define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */ #define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */ #define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_HP3R_DONE_EINT1 0x0020 /* HP3R_DONE_EINT1 */ +#define ARIZONA_HP3R_DONE_EINT1_MASK 0x0020 /* HP3R_DONE_EINT1 */ +#define ARIZONA_HP3R_DONE_EINT1_SHIFT 5 /* HP3R_DONE_EINT1 */ +#define ARIZONA_HP3R_DONE_EINT1_WIDTH 1 /* HP3R_DONE_EINT1 */ +#define ARIZONA_HP3L_DONE_EINT1 0x0010 /* HP3L_DONE_EINT1 */ +#define ARIZONA_HP3L_DONE_EINT1_MASK 0x0010 /* HP3L_DONE_EINT1 */ +#define ARIZONA_HP3L_DONE_EINT1_SHIFT 4 /* HP3L_DONE_EINT1 */ +#define ARIZONA_HP3L_DONE_EINT1_WIDTH 1 /* HP3L_DONE_EINT1 */ +#define ARIZONA_HP2R_DONE_EINT1 0x0008 /* HP2R_DONE_EINT1 */ +#define ARIZONA_HP2R_DONE_EINT1_MASK 0x0008 /* HP2R_DONE_EINT1 */ +#define ARIZONA_HP2R_DONE_EINT1_SHIFT 3 /* HP2R_DONE_EINT1 */ +#define ARIZONA_HP2R_DONE_EINT1_WIDTH 1 /* HP2R_DONE_EINT1 */ +#define ARIZONA_HP2L_DONE_EINT1 0x0004 /* HP2L_DONE_EINT1 */ +#define ARIZONA_HP2L_DONE_EINT1_MASK 0x0004 /* HP2L_DONE_EINT1 */ +#define ARIZONA_HP2L_DONE_EINT1_SHIFT 2 /* HP2L_DONE_EINT1 */ +#define ARIZONA_HP2L_DONE_EINT1_WIDTH 1 /* HP2L_DONE_EINT1 */ +#define ARIZONA_HP1R_DONE_EINT1 0x0002 /* HP1R_DONE_EINT1 */ +#define ARIZONA_HP1R_DONE_EINT1_MASK 0x0002 /* HP1R_DONE_EINT1 */ +#define ARIZONA_HP1R_DONE_EINT1_SHIFT 1 /* HP1R_DONE_EINT1 */ +#define ARIZONA_HP1R_DONE_EINT1_WIDTH 1 /* HP1R_DONE_EINT1 */ +#define ARIZONA_HP1L_DONE_EINT1 0x0001 /* HP1L_DONE_EINT1 */ +#define ARIZONA_HP1L_DONE_EINT1_MASK 0x0001 /* HP1L_DONE_EINT1 */ +#define ARIZONA_HP1L_DONE_EINT1_SHIFT 0 /* HP1L_DONE_EINT1 */ +#define ARIZONA_HP1L_DONE_EINT1_WIDTH 1 /* HP1L_DONE_EINT1 */ + +/* + * R3331 (0xD03) - Interrupt Status 4 (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_AIF3_ERR_EINT1 0x8000 /* AIF3_ERR_EINT1 */ +#define ARIZONA_V2_AIF3_ERR_EINT1_MASK 0x8000 /* AIF3_ERR_EINT1 */ +#define ARIZONA_V2_AIF3_ERR_EINT1_SHIFT 15 /* AIF3_ERR_EINT1 */ +#define ARIZONA_V2_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */ +#define ARIZONA_V2_AIF2_ERR_EINT1 0x4000 /* AIF2_ERR_EINT1 */ +#define ARIZONA_V2_AIF2_ERR_EINT1_MASK 0x4000 /* AIF2_ERR_EINT1 */ +#define ARIZONA_V2_AIF2_ERR_EINT1_SHIFT 14 /* AIF2_ERR_EINT1 */ +#define ARIZONA_V2_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */ +#define ARIZONA_V2_AIF1_ERR_EINT1 0x2000 /* AIF1_ERR_EINT1 */ +#define ARIZONA_V2_AIF1_ERR_EINT1_MASK 0x2000 /* AIF1_ERR_EINT1 */ +#define ARIZONA_V2_AIF1_ERR_EINT1_SHIFT 13 /* AIF1_ERR_EINT1 */ +#define ARIZONA_V2_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT1 0x1000 /* CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT1_MASK 0x1000 /* CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT1_SHIFT 12 /* CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 0x0800 /* MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0800 /* MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 11 /* MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 0x0400 /* ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0400 /* ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 10 /* ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 0x0200 /* SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_MASK 0x0200 /* SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_SHIFT 9 /* SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1 0x0100 /* ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_MASK 0x0100 /* ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_SHIFT 8 /* ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1 0x0080 /* ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_MASK 0x0080 /* ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_SHIFT 7 /* ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1 0x0040 /* ISRC3_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_MASK 0x0040 /* ISRC3_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_SHIFT 6 /* ISRC3_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_WIDTH 1 /* ISRC3_CFG_ERR_EINT1 */ /* * R3332 (0xD04) - Interrupt Status 5 @@ -4489,6 +7786,85 @@ #define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */ #define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */ +/* + * R3332 (0xD05) - Interrupt Status 5 (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT1 0x0008 /* ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT1_MASK 0x0008 /* ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT1_SHIFT 3 /* ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */ + +/* + * R3333 (0xD05) - Interrupt Status 6 + */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT1 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_SPK1R_SHORT_EINT1 0x2000 /* SPK1R_SHORT_EINT1 */ +#define ARIZONA_SPK1R_SHORT_EINT1_MASK 0x2000 /* SPK1R_SHORT_EINT1 */ +#define ARIZONA_SPK1R_SHORT_EINT1_SHIFT 13 /* SPK1R_SHORT_EINT1 */ +#define ARIZONA_SPK1R_SHORT_EINT1_WIDTH 1 /* SPK1R_SHORT_EINT1 */ +#define ARIZONA_SPK1L_SHORT_EINT1 0x1000 /* SPK1L_SHORT_EINT1 */ +#define ARIZONA_SPK1L_SHORT_EINT1_MASK 0x1000 /* SPK1L_SHORT_EINT1 */ +#define ARIZONA_SPK1L_SHORT_EINT1_SHIFT 12 /* SPK1L_SHORT_EINT1 */ +#define ARIZONA_SPK1L_SHORT_EINT1_WIDTH 1 /* SPK1L_SHORT_EINT1 */ +#define ARIZONA_HP3R_SC_NEG_EINT1 0x0800 /* HP3R_SC_NEG_EINT1 */ +#define ARIZONA_HP3R_SC_NEG_EINT1_MASK 0x0800 /* HP3R_SC_NEG_EINT1 */ +#define ARIZONA_HP3R_SC_NEG_EINT1_SHIFT 11 /* HP3R_SC_NEG_EINT1 */ +#define ARIZONA_HP3R_SC_NEG_EINT1_WIDTH 1 /* HP3R_SC_NEG_EINT1 */ +#define ARIZONA_HP3R_SC_POS_EINT1 0x0400 /* HP3R_SC_POS_EINT1 */ +#define ARIZONA_HP3R_SC_POS_EINT1_MASK 0x0400 /* HP3R_SC_POS_EINT1 */ +#define ARIZONA_HP3R_SC_POS_EINT1_SHIFT 10 /* HP3R_SC_POS_EINT1 */ +#define ARIZONA_HP3R_SC_POS_EINT1_WIDTH 1 /* HP3R_SC_POS_EINT1 */ +#define ARIZONA_HP3L_SC_NEG_EINT1 0x0200 /* HP3L_SC_NEG_EINT1 */ +#define ARIZONA_HP3L_SC_NEG_EINT1_MASK 0x0200 /* HP3L_SC_NEG_EINT1 */ +#define ARIZONA_HP3L_SC_NEG_EINT1_SHIFT 9 /* HP3L_SC_NEG_EINT1 */ +#define ARIZONA_HP3L_SC_NEG_EINT1_WIDTH 1 /* HP3L_SC_NEG_EINT1 */ +#define ARIZONA_HP3L_SC_POS_EINT1 0x0100 /* HP3L_SC_POS_EINT1 */ +#define ARIZONA_HP3L_SC_POS_EINT1_MASK 0x0100 /* HP3L_SC_POS_EINT1 */ +#define ARIZONA_HP3L_SC_POS_EINT1_SHIFT 8 /* HP3L_SC_POS_EINT1 */ +#define ARIZONA_HP3L_SC_POS_EINT1_WIDTH 1 /* HP3L_SC_POS_EINT1 */ +#define ARIZONA_HP2R_SC_NEG_EINT1 0x0080 /* HP2R_SC_NEG_EINT1 */ +#define ARIZONA_HP2R_SC_NEG_EINT1_MASK 0x0080 /* HP2R_SC_NEG_EINT1 */ +#define ARIZONA_HP2R_SC_NEG_EINT1_SHIFT 7 /* HP2R_SC_NEG_EINT1 */ +#define ARIZONA_HP2R_SC_NEG_EINT1_WIDTH 1 /* HP2R_SC_NEG_EINT1 */ +#define ARIZONA_HP2R_SC_POS_EINT1 0x0040 /* HP2R_SC_POS_EINT1 */ +#define ARIZONA_HP2R_SC_POS_EINT1_MASK 0x0040 /* HP2R_SC_POS_EINT1 */ +#define ARIZONA_HP2R_SC_POS_EINT1_SHIFT 6 /* HP2R_SC_POS_EINT1 */ +#define ARIZONA_HP2R_SC_POS_EINT1_WIDTH 1 /* HP2R_SC_POS_EINT1 */ +#define ARIZONA_HP2L_SC_NEG_EINT1 0x0020 /* HP2L_SC_NEG_EINT1 */ +#define ARIZONA_HP2L_SC_NEG_EINT1_MASK 0x0020 /* HP2L_SC_NEG_EINT1 */ +#define ARIZONA_HP2L_SC_NEG_EINT1_SHIFT 5 /* HP2L_SC_NEG_EINT1 */ +#define ARIZONA_HP2L_SC_NEG_EINT1_WIDTH 1 /* HP2L_SC_NEG_EINT1 */ +#define ARIZONA_HP2L_SC_POS_EINT1 0x0010 /* HP2L_SC_POS_EINT1 */ +#define ARIZONA_HP2L_SC_POS_EINT1_MASK 0x0010 /* HP2L_SC_POS_EINT1 */ +#define ARIZONA_HP2L_SC_POS_EINT1_SHIFT 4 /* HP2L_SC_POS_EINT1 */ +#define ARIZONA_HP2L_SC_POS_EINT1_WIDTH 1 /* HP2L_SC_POS_EINT1 */ +#define ARIZONA_HP1R_SC_NEG_EINT1 0x0008 /* HP1R_SC_NEG_EINT1 */ +#define ARIZONA_HP1R_SC_NEG_EINT1_MASK 0x0008 /* HP1R_SC_NEG_EINT1 */ +#define ARIZONA_HP1R_SC_NEG_EINT1_SHIFT 3 /* HP1R_SC_NEG_EINT1 */ +#define ARIZONA_HP1R_SC_NEG_EINT1_WIDTH 1 /* HP1R_SC_NEG_EINT1 */ +#define ARIZONA_HP1R_SC_POS_EINT1 0x0004 /* HP1R_SC_POS_EINT1 */ +#define ARIZONA_HP1R_SC_POS_EINT1_MASK 0x0004 /* HP1R_SC_POS_EINT1 */ +#define ARIZONA_HP1R_SC_POS_EINT1_SHIFT 2 /* HP1R_SC_POS_EINT1 */ +#define ARIZONA_HP1R_SC_POS_EINT1_WIDTH 1 /* HP1R_SC_POS_EINT1 */ +#define ARIZONA_HP1L_SC_NEG_EINT1 0x0002 /* HP1L_SC_NEG_EINT1 */ +#define ARIZONA_HP1L_SC_NEG_EINT1_MASK 0x0002 /* HP1L_SC_NEG_EINT1 */ +#define ARIZONA_HP1L_SC_NEG_EINT1_SHIFT 1 /* HP1L_SC_NEG_EINT1 */ +#define ARIZONA_HP1L_SC_NEG_EINT1_WIDTH 1 /* HP1L_SC_NEG_EINT1 */ +#define ARIZONA_HP1L_SC_POS_EINT1 0x0001 /* HP1L_SC_POS_EINT1 */ +#define ARIZONA_HP1L_SC_POS_EINT1_MASK 0x0001 /* HP1L_SC_POS_EINT1 */ +#define ARIZONA_HP1L_SC_POS_EINT1_SHIFT 0 /* HP1L_SC_POS_EINT1 */ +#define ARIZONA_HP1L_SC_POS_EINT1_WIDTH 1 /* HP1L_SC_POS_EINT1 */ + /* * R3336 (0xD08) - Interrupt Status 1 Mask */ @@ -4528,14 +7904,14 @@ /* * R3338 (0xD0A) - Interrupt Status 3 Mask */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_MASK 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_SHIFT 15 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT1 0x4000 /* IM_SPK_OVERHEAT_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT1_MASK 0x4000 /* IM_SPK_OVERHEAT_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT1_SHIFT 14 /* IM_SPK_OVERHEAT_EINT1 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_EINT1 */ #define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */ #define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */ #define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */ @@ -4592,46 +7968,117 @@ /* * R3339 (0xD0B) - Interrupt Status 4 Mask */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */ -#define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */ -#define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */ -#define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */ -#define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */ -#define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */ -#define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */ -#define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */ -#define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */ -#define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */ -#define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */ -#define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */ -#define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_IM_HP3R_DONE_EINT1 0x0020 /* IM_HP3R_DONE_EINT1 */ +#define ARIZONA_IM_HP3R_DONE_EINT1_MASK 0x0020 /* IM_HP3R_DONE_EINT1 */ +#define ARIZONA_IM_HP3R_DONE_EINT1_SHIFT 5 /* IM_HP3R_DONE_EINT1 */ +#define ARIZONA_IM_HP3R_DONE_EINT1_WIDTH 1 /* IM_HP3R_DONE_EINT1 */ +#define ARIZONA_IM_HP3L_DONE_EINT1 0x0010 /* IM_HP3L_DONE_EINT1 */ +#define ARIZONA_IM_HP3L_DONE_EINT1_MASK 0x0010 /* IM_HP3L_DONE_EINT1 */ +#define ARIZONA_IM_HP3L_DONE_EINT1_SHIFT 4 /* IM_HP3L_DONE_EINT1 */ +#define ARIZONA_IM_HP3L_DONE_EINT1_WIDTH 1 /* IM_HP3L_DONE_EINT1 */ +#define ARIZONA_IM_HP2R_DONE_EINT1 0x0008 /* IM_HP2R_DONE_EINT1 */ +#define ARIZONA_IM_HP2R_DONE_EINT1_MASK 0x0008 /* IM_HP2R_DONE_EINT1 */ +#define ARIZONA_IM_HP2R_DONE_EINT1_SHIFT 3 /* IM_HP2R_DONE_EINT1 */ +#define ARIZONA_IM_HP2R_DONE_EINT1_WIDTH 1 /* IM_HP2R_DONE_EINT1 */ +#define ARIZONA_IM_HP2L_DONE_EINT1 0x0004 /* IM_HP2L_DONE_EINT1 */ +#define ARIZONA_IM_HP2L_DONE_EINT1_MASK 0x0004 /* IM_HP2L_DONE_EINT1 */ +#define ARIZONA_IM_HP2L_DONE_EINT1_SHIFT 2 /* IM_HP2L_DONE_EINT1 */ +#define ARIZONA_IM_HP2L_DONE_EINT1_WIDTH 1 /* IM_HP2L_DONE_EINT1 */ +#define ARIZONA_IM_HP1R_DONE_EINT1 0x0002 /* IM_HP1R_DONE_EINT1 */ +#define ARIZONA_IM_HP1R_DONE_EINT1_MASK 0x0002 /* IM_HP1R_DONE_EINT1 */ +#define ARIZONA_IM_HP1R_DONE_EINT1_SHIFT 1 /* IM_HP1R_DONE_EINT1 */ +#define ARIZONA_IM_HP1R_DONE_EINT1_WIDTH 1 /* IM_HP1R_DONE_EINT1 */ +#define ARIZONA_IM_HP1L_DONE_EINT1 0x0001 /* IM_HP1L_DONE_EINT1 */ +#define ARIZONA_IM_HP1L_DONE_EINT1_MASK 0x0001 /* IM_HP1L_DONE_EINT1 */ +#define ARIZONA_IM_HP1L_DONE_EINT1_SHIFT 0 /* IM_HP1L_DONE_EINT1 */ +#define ARIZONA_IM_HP1L_DONE_EINT1_WIDTH 1 /* IM_HP1L_DONE_EINT1 */ + +/* + * R3339 (0xD0B) - Interrupt Status 4 Mask (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT1 0x8000 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT1_MASK 0x8000 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT1_SHIFT 15 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT1 0x4000 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT1_MASK 0x4000 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT1_SHIFT 14 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT1 0x2000 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT1_MASK 0x2000 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT1_SHIFT 13 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1 0x1000 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_MASK 0x1000 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_SHIFT 12 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 11 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 10 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1 0x0200 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 9 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1 0x0100 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0100 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_SHIFT 8 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1 0x0080 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1 0x0040 /* IM_ISRC3_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC3_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC3_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC3_CFG_ERR_EINT1 */ /* * R3340 (0xD0C) - Interrupt Status 5 Mask @@ -4657,6 +8104,85 @@ #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */ #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */ +/* + * R3340 (0xD0C) - Interrupt Status 5 Mask (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1 0x0008 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_MASK 0x0008 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_SHIFT 3 /* IM_ASRC_CFG_ERR_EINT1 */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */ + +/* + * R3341 (0xD0D) - Interrupt Status 6 Mask + */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT1 0x2000 /* IM_SPK1R_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT1_MASK 0x2000 /* IM_SPK1R_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT1_SHIFT 13 /* IM_SPK1R_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT1_WIDTH 1 /* IM_SPK1R_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT1 0x1000 /* IM_SPK1L_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT1_MASK 0x1000 /* IM_SPK1L_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT1_SHIFT 12 /* IM_SPK1L_SHORT_EINT1 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT1_WIDTH 1 /* IM_SPK1L_SHORT_EINT1 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT1 0x0800 /* IM_HP3R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT1_MASK 0x0800 /* IM_HP3R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT1_SHIFT 11 /* IM_HP3R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT1_WIDTH 1 /* IM_HP3R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT1 0x0400 /* IM_HP3R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT1_MASK 0x0400 /* IM_HP3R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT1_SHIFT 10 /* IM_HP3R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT1_WIDTH 1 /* IM_HP3R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT1 0x0200 /* IM_HP3L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT1_MASK 0x0200 /* IM_HP3L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT1_SHIFT 9 /* IM_HP3L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT1_WIDTH 1 /* IM_HP3L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT1 0x0100 /* IM_HP3L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT1_MASK 0x0100 /* IM_HP3L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT1_SHIFT 8 /* IM_HP3L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT1_WIDTH 1 /* IM_HP3L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT1 0x0080 /* IM_HP2R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT1_MASK 0x0080 /* IM_HP2R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT1_SHIFT 7 /* IM_HP2R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT1_WIDTH 1 /* IM_HP2R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT1 0x0040 /* IM_HP2R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT1_MASK 0x0040 /* IM_HP2R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT1_SHIFT 6 /* IM_HP2R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT1_WIDTH 1 /* IM_HP2R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT1 0x0020 /* IM_HP2L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT1_MASK 0x0020 /* IM_HP2L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT1_SHIFT 5 /* IM_HP2L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT1_WIDTH 1 /* IM_HP2L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT1 0x0010 /* IM_HP2L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT1_MASK 0x0010 /* IM_HP2L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT1_SHIFT 4 /* IM_HP2L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT1_WIDTH 1 /* IM_HP2L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT1 0x0008 /* IM_HP1R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT1_MASK 0x0008 /* IM_HP1R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT1_SHIFT 3 /* IM_HP1R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT1_WIDTH 1 /* IM_HP1R_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT1 0x0004 /* IM_HP1R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT1_MASK 0x0004 /* IM_HP1R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT1_SHIFT 2 /* IM_HP1R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT1_WIDTH 1 /* IM_HP1R_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT1 0x0002 /* IM_HP1L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT1_MASK 0x0002 /* IM_HP1L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT1_SHIFT 1 /* IM_HP1L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT1_WIDTH 1 /* IM_HP1L_SC_NEG_EINT1 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT1 0x0001 /* IM_HP1L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT1_MASK 0x0001 /* IM_HP1L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT1_SHIFT 0 /* IM_HP1L_SC_POS_EINT1 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT1_WIDTH 1 /* IM_HP1L_SC_POS_EINT1 */ + /* * R3343 (0xD0F) - Interrupt Control */ @@ -4704,14 +8230,14 @@ /* * R3346 (0xD12) - IRQ2 Status 3 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */ -#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT2 0x8000 /* SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT2_MASK 0x8000 /* SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT2_SHIFT 15 /* SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_EINT2 0x4000 /* SPK_OVERHEAT_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_EINT2_MASK 0x4000 /* SPK_OVERHEAT_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_EINT2_SHIFT 14 /* SPK_OVERHEAT_EINT2 */ +#define ARIZONA_SPK_OVERHEAT_EINT2_WIDTH 1 /* SPK_OVERHEAT_EINT2 */ #define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */ #define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */ #define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */ @@ -4808,6 +8334,77 @@ #define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */ #define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */ #define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_HP3R_DONE_EINT2 0x0020 /* HP3R_DONE_EINT2 */ +#define ARIZONA_HP3R_DONE_EINT2_MASK 0x0020 /* HP3R_DONE_EINT2 */ +#define ARIZONA_HP3R_DONE_EINT2_SHIFT 5 /* HP3R_DONE_EINT2 */ +#define ARIZONA_HP3R_DONE_EINT2_WIDTH 1 /* HP3R_DONE_EINT2 */ +#define ARIZONA_HP3L_DONE_EINT2 0x0010 /* HP3L_DONE_EINT2 */ +#define ARIZONA_HP3L_DONE_EINT2_MASK 0x0010 /* HP3L_DONE_EINT2 */ +#define ARIZONA_HP3L_DONE_EINT2_SHIFT 4 /* HP3L_DONE_EINT2 */ +#define ARIZONA_HP3L_DONE_EINT2_WIDTH 1 /* HP3L_DONE_EINT2 */ +#define ARIZONA_HP2R_DONE_EINT2 0x0008 /* HP2R_DONE_EINT2 */ +#define ARIZONA_HP2R_DONE_EINT2_MASK 0x0008 /* HP2R_DONE_EINT2 */ +#define ARIZONA_HP2R_DONE_EINT2_SHIFT 3 /* HP2R_DONE_EINT2 */ +#define ARIZONA_HP2R_DONE_EINT2_WIDTH 1 /* HP2R_DONE_EINT2 */ +#define ARIZONA_HP2L_DONE_EINT2 0x0004 /* HP2L_DONE_EINT2 */ +#define ARIZONA_HP2L_DONE_EINT2_MASK 0x0004 /* HP2L_DONE_EINT2 */ +#define ARIZONA_HP2L_DONE_EINT2_SHIFT 2 /* HP2L_DONE_EINT2 */ +#define ARIZONA_HP2L_DONE_EINT2_WIDTH 1 /* HP2L_DONE_EINT2 */ +#define ARIZONA_HP1R_DONE_EINT2 0x0002 /* HP1R_DONE_EINT2 */ +#define ARIZONA_HP1R_DONE_EINT2_MASK 0x0002 /* HP1R_DONE_EINT2 */ +#define ARIZONA_HP1R_DONE_EINT2_SHIFT 1 /* HP1R_DONE_EINT2 */ +#define ARIZONA_HP1R_DONE_EINT2_WIDTH 1 /* HP1R_DONE_EINT2 */ +#define ARIZONA_HP1L_DONE_EINT2 0x0001 /* HP1L_DONE_EINT2 */ +#define ARIZONA_HP1L_DONE_EINT2_MASK 0x0001 /* HP1L_DONE_EINT2 */ +#define ARIZONA_HP1L_DONE_EINT2_SHIFT 0 /* HP1L_DONE_EINT2 */ +#define ARIZONA_HP1L_DONE_EINT2_WIDTH 1 /* HP1L_DONE_EINT2 */ + +/* + * R3347 (0xD13) - IRQ2 Status 4 (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_AIF3_ERR_EINT2 0x8000 /* AIF3_ERR_EINT2 */ +#define ARIZONA_V2_AIF3_ERR_EINT2_MASK 0x8000 /* AIF3_ERR_EINT2 */ +#define ARIZONA_V2_AIF3_ERR_EINT2_SHIFT 15 /* AIF3_ERR_EINT2 */ +#define ARIZONA_V2_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */ +#define ARIZONA_V2_AIF2_ERR_EINT2 0x4000 /* AIF2_ERR_EINT2 */ +#define ARIZONA_V2_AIF2_ERR_EINT2_MASK 0x4000 /* AIF2_ERR_EINT2 */ +#define ARIZONA_V2_AIF2_ERR_EINT2_SHIFT 14 /* AIF2_ERR_EINT2 */ +#define ARIZONA_V2_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */ +#define ARIZONA_V2_AIF1_ERR_EINT2 0x2000 /* AIF1_ERR_EINT2 */ +#define ARIZONA_V2_AIF1_ERR_EINT2_MASK 0x2000 /* AIF1_ERR_EINT2 */ +#define ARIZONA_V2_AIF1_ERR_EINT2_SHIFT 13 /* AIF1_ERR_EINT2 */ +#define ARIZONA_V2_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT2 0x1000 /* CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT2_MASK 0x1000 /* CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT2_SHIFT 12 /* CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2 0x0800 /* MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0800 /* MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 11 /* MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2 0x0400 /* ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0400 /* ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 10 /* ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2 0x0200 /* SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_MASK 0x0200 /* SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_SHIFT 9 /* SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2 0x0100 /* ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_MASK 0x0100 /* ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_SHIFT 8 /* ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2 0x0080 /* ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_MASK 0x0080 /* ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_SHIFT 7 /* ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2 0x0040 /* ISRC3_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_MASK 0x0040 /* ISRC3_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_SHIFT 6 /* ISRC3_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_WIDTH 1 /* ISRC3_CFG_ERR_EINT2 */ /* * R3348 (0xD14) - IRQ2 Status 5 @@ -4833,6 +8430,85 @@ #define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */ #define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */ +/* + * R3348 (0xD14) - IRQ2 Status 5 (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT2 0x0008 /* ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT2_MASK 0x0008 /* ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT2_SHIFT 3 /* ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_V2_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */ + +/* + * R3349 (0xD15) - IRQ2 Status 6 + */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT2 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_SPK1R_SHORT_EINT2 0x2000 /* SPK1R_SHORT_EINT2 */ +#define ARIZONA_SPK1R_SHORT_EINT2_MASK 0x2000 /* SPK1R_SHORT_EINT2 */ +#define ARIZONA_SPK1R_SHORT_EINT2_SHIFT 13 /* SPK1R_SHORT_EINT2 */ +#define ARIZONA_SPK1R_SHORT_EINT2_WIDTH 1 /* SPK1R_SHORT_EINT2 */ +#define ARIZONA_SPK1L_SHORT_EINT2 0x1000 /* SPK1L_SHORT_EINT2 */ +#define ARIZONA_SPK1L_SHORT_EINT2_MASK 0x1000 /* SPK1L_SHORT_EINT2 */ +#define ARIZONA_SPK1L_SHORT_EINT2_SHIFT 12 /* SPK1L_SHORT_EINT2 */ +#define ARIZONA_SPK1L_SHORT_EINT2_WIDTH 1 /* SPK1L_SHORT_EINT2 */ +#define ARIZONA_HP3R_SC_NEG_EINT2 0x0800 /* HP3R_SC_NEG_EINT2 */ +#define ARIZONA_HP3R_SC_NEG_EINT2_MASK 0x0800 /* HP3R_SC_NEG_EINT2 */ +#define ARIZONA_HP3R_SC_NEG_EINT2_SHIFT 11 /* HP3R_SC_NEG_EINT2 */ +#define ARIZONA_HP3R_SC_NEG_EINT2_WIDTH 1 /* HP3R_SC_NEG_EINT2 */ +#define ARIZONA_HP3R_SC_POS_EINT2 0x0400 /* HP3R_SC_POS_EINT2 */ +#define ARIZONA_HP3R_SC_POS_EINT2_MASK 0x0400 /* HP3R_SC_POS_EINT2 */ +#define ARIZONA_HP3R_SC_POS_EINT2_SHIFT 10 /* HP3R_SC_POS_EINT2 */ +#define ARIZONA_HP3R_SC_POS_EINT2_WIDTH 1 /* HP3R_SC_POS_EINT2 */ +#define ARIZONA_HP3L_SC_NEG_EINT2 0x0200 /* HP3L_SC_NEG_EINT2 */ +#define ARIZONA_HP3L_SC_NEG_EINT2_MASK 0x0200 /* HP3L_SC_NEG_EINT2 */ +#define ARIZONA_HP3L_SC_NEG_EINT2_SHIFT 9 /* HP3L_SC_NEG_EINT2 */ +#define ARIZONA_HP3L_SC_NEG_EINT2_WIDTH 1 /* HP3L_SC_NEG_EINT2 */ +#define ARIZONA_HP3L_SC_POS_EINT2 0x0100 /* HP3L_SC_POS_EINT2 */ +#define ARIZONA_HP3L_SC_POS_EINT2_MASK 0x0100 /* HP3L_SC_POS_EINT2 */ +#define ARIZONA_HP3L_SC_POS_EINT2_SHIFT 8 /* HP3L_SC_POS_EINT2 */ +#define ARIZONA_HP3L_SC_POS_EINT2_WIDTH 1 /* HP3L_SC_POS_EINT2 */ +#define ARIZONA_HP2R_SC_NEG_EINT2 0x0080 /* HP2R_SC_NEG_EINT2 */ +#define ARIZONA_HP2R_SC_NEG_EINT2_MASK 0x0080 /* HP2R_SC_NEG_EINT2 */ +#define ARIZONA_HP2R_SC_NEG_EINT2_SHIFT 7 /* HP2R_SC_NEG_EINT2 */ +#define ARIZONA_HP2R_SC_NEG_EINT2_WIDTH 1 /* HP2R_SC_NEG_EINT2 */ +#define ARIZONA_HP2R_SC_POS_EINT2 0x0040 /* HP2R_SC_POS_EINT2 */ +#define ARIZONA_HP2R_SC_POS_EINT2_MASK 0x0040 /* HP2R_SC_POS_EINT2 */ +#define ARIZONA_HP2R_SC_POS_EINT2_SHIFT 6 /* HP2R_SC_POS_EINT2 */ +#define ARIZONA_HP2R_SC_POS_EINT2_WIDTH 1 /* HP2R_SC_POS_EINT2 */ +#define ARIZONA_HP2L_SC_NEG_EINT2 0x0020 /* HP2L_SC_NEG_EINT2 */ +#define ARIZONA_HP2L_SC_NEG_EINT2_MASK 0x0020 /* HP2L_SC_NEG_EINT2 */ +#define ARIZONA_HP2L_SC_NEG_EINT2_SHIFT 5 /* HP2L_SC_NEG_EINT2 */ +#define ARIZONA_HP2L_SC_NEG_EINT2_WIDTH 1 /* HP2L_SC_NEG_EINT2 */ +#define ARIZONA_HP2L_SC_POS_EINT2 0x0010 /* HP2L_SC_POS_EINT2 */ +#define ARIZONA_HP2L_SC_POS_EINT2_MASK 0x0010 /* HP2L_SC_POS_EINT2 */ +#define ARIZONA_HP2L_SC_POS_EINT2_SHIFT 4 /* HP2L_SC_POS_EINT2 */ +#define ARIZONA_HP2L_SC_POS_EINT2_WIDTH 1 /* HP2L_SC_POS_EINT2 */ +#define ARIZONA_HP1R_SC_NEG_EINT2 0x0008 /* HP1R_SC_NEG_EINT2 */ +#define ARIZONA_HP1R_SC_NEG_EINT2_MASK 0x0008 /* HP1R_SC_NEG_EINT2 */ +#define ARIZONA_HP1R_SC_NEG_EINT2_SHIFT 3 /* HP1R_SC_NEG_EINT2 */ +#define ARIZONA_HP1R_SC_NEG_EINT2_WIDTH 1 /* HP1R_SC_NEG_EINT2 */ +#define ARIZONA_HP1R_SC_POS_EINT2 0x0004 /* HP1R_SC_POS_EINT2 */ +#define ARIZONA_HP1R_SC_POS_EINT2_MASK 0x0004 /* HP1R_SC_POS_EINT2 */ +#define ARIZONA_HP1R_SC_POS_EINT2_SHIFT 2 /* HP1R_SC_POS_EINT2 */ +#define ARIZONA_HP1R_SC_POS_EINT2_WIDTH 1 /* HP1R_SC_POS_EINT2 */ +#define ARIZONA_HP1L_SC_NEG_EINT2 0x0002 /* HP1L_SC_NEG_EINT2 */ +#define ARIZONA_HP1L_SC_NEG_EINT2_MASK 0x0002 /* HP1L_SC_NEG_EINT2 */ +#define ARIZONA_HP1L_SC_NEG_EINT2_SHIFT 1 /* HP1L_SC_NEG_EINT2 */ +#define ARIZONA_HP1L_SC_NEG_EINT2_WIDTH 1 /* HP1L_SC_NEG_EINT2 */ +#define ARIZONA_HP1L_SC_POS_EINT2 0x0001 /* HP1L_SC_POS_EINT2 */ +#define ARIZONA_HP1L_SC_POS_EINT2_MASK 0x0001 /* HP1L_SC_POS_EINT2 */ +#define ARIZONA_HP1L_SC_POS_EINT2_SHIFT 0 /* HP1L_SC_POS_EINT2 */ +#define ARIZONA_HP1L_SC_POS_EINT2_WIDTH 1 /* HP1L_SC_POS_EINT2 */ + /* * R3352 (0xD18) - IRQ2 Status 1 Mask */ @@ -4872,14 +8548,14 @@ /* * R3354 (0xD1A) - IRQ2 Status 3 Mask */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */ -#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_MASK 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_SHIFT 15 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT2 0x4000 /* IM_SPK_OVERHEAT_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT2_MASK 0x4000 /* IM_SPK_OVERHEAT_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT2_SHIFT 14 /* IM_SPK_OVERHEAT_EINT2 */ +#define ARIZONA_IM_SPK_OVERHEAT_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_EINT2 */ #define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */ #define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */ #define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */ @@ -4936,46 +8612,117 @@ /* * R3355 (0xD1B) - IRQ2 Status 4 Mask */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */ -#define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */ -#define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */ -#define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */ -#define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */ -#define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */ -#define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */ -#define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */ -#define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */ -#define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */ -#define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */ -#define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */ -#define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */ -#define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ -#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */ -#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_IM_HP3R_DONE_EINT2 0x0020 /* IM_HP3R_DONE_EINT2 */ +#define ARIZONA_IM_HP3R_DONE_EINT2_MASK 0x0020 /* IM_HP3R_DONE_EINT2 */ +#define ARIZONA_IM_HP3R_DONE_EINT2_SHIFT 5 /* IM_HP3R_DONE_EINT2 */ +#define ARIZONA_IM_HP3R_DONE_EINT2_WIDTH 1 /* IM_HP3R_DONE_EINT2 */ +#define ARIZONA_IM_HP3L_DONE_EINT2 0x0010 /* IM_HP3L_DONE_EINT2 */ +#define ARIZONA_IM_HP3L_DONE_EINT2_MASK 0x0010 /* IM_HP3L_DONE_EINT2 */ +#define ARIZONA_IM_HP3L_DONE_EINT2_SHIFT 4 /* IM_HP3L_DONE_EINT2 */ +#define ARIZONA_IM_HP3L_DONE_EINT2_WIDTH 1 /* IM_HP3L_DONE_EINT2 */ +#define ARIZONA_IM_HP2R_DONE_EINT2 0x0008 /* IM_HP2R_DONE_EINT2 */ +#define ARIZONA_IM_HP2R_DONE_EINT2_MASK 0x0008 /* IM_HP2R_DONE_EINT2 */ +#define ARIZONA_IM_HP2R_DONE_EINT2_SHIFT 3 /* IM_HP2R_DONE_EINT2 */ +#define ARIZONA_IM_HP2R_DONE_EINT2_WIDTH 1 /* IM_HP2R_DONE_EINT2 */ +#define ARIZONA_IM_HP2L_DONE_EINT2 0x0004 /* IM_HP2L_DONE_EINT2 */ +#define ARIZONA_IM_HP2L_DONE_EINT2_MASK 0x0004 /* IM_HP2L_DONE_EINT2 */ +#define ARIZONA_IM_HP2L_DONE_EINT2_SHIFT 2 /* IM_HP2L_DONE_EINT2 */ +#define ARIZONA_IM_HP2L_DONE_EINT2_WIDTH 1 /* IM_HP2L_DONE_EINT2 */ +#define ARIZONA_IM_HP1R_DONE_EINT2 0x0002 /* IM_HP1R_DONE_EINT2 */ +#define ARIZONA_IM_HP1R_DONE_EINT2_MASK 0x0002 /* IM_HP1R_DONE_EINT2 */ +#define ARIZONA_IM_HP1R_DONE_EINT2_SHIFT 1 /* IM_HP1R_DONE_EINT2 */ +#define ARIZONA_IM_HP1R_DONE_EINT2_WIDTH 1 /* IM_HP1R_DONE_EINT2 */ +#define ARIZONA_IM_HP1L_DONE_EINT2 0x0001 /* IM_HP1L_DONE_EINT2 */ +#define ARIZONA_IM_HP1L_DONE_EINT2_MASK 0x0001 /* IM_HP1L_DONE_EINT2 */ +#define ARIZONA_IM_HP1L_DONE_EINT2_SHIFT 0 /* IM_HP1L_DONE_EINT2 */ +#define ARIZONA_IM_HP1L_DONE_EINT2_WIDTH 1 /* IM_HP1L_DONE_EINT2 */ + +/* + * R3355 (0xD1B) - IRQ2 Status 4 Mask (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT2 0x8000 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT2_MASK 0x8000 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT2_SHIFT 15 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT2 0x4000 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT2_MASK 0x4000 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT2_SHIFT 14 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT2 0x2000 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT2_MASK 0x2000 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT2_SHIFT 13 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_V2_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2 0x1000 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_MASK 0x1000 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_SHIFT 12 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 11 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 10 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2 0x0200 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 9 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2 0x0100 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0100 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_SHIFT 8 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2 0x0080 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2 0x0040 /* IM_ISRC3_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC3_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC3_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC3_CFG_ERR_EINT2 */ /* * R3356 (0xD1C) - IRQ2 Status 5 Mask @@ -5002,6 +8749,85 @@ #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */ #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */ +/* + * R3340 (0xD0C) - Interrupt Status 5 Mask (Alternate layout) + * + * Alternate layout used on later devices, note only fields that have moved + * are specified + */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2 0x0008 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_MASK 0x0008 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_SHIFT 3 /* IM_ASRC_CFG_ERR_EINT2 */ +#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */ + +/* + * R3357 (0xD1D) - IRQ2 Status 6 Mask + */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT2 0x2000 /* IM_SPK1R_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT2_MASK 0x2000 /* IM_SPK1R_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT2_SHIFT 13 /* IM_SPK1R_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1R_SHORT_EINT2_WIDTH 1 /* IM_SPK1R_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT2 0x1000 /* IM_SPK1L_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT2_MASK 0x1000 /* IM_SPK1L_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT2_SHIFT 12 /* IM_SPK1L_SHORT_EINT2 */ +#define ARIZONA_IM_SPK1L_SHORT_EINT2_WIDTH 1 /* IM_SPK1L_SHORT_EINT2 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT2 0x0800 /* IM_HP3R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT2_MASK 0x0800 /* IM_HP3R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT2_SHIFT 11 /* IM_HP3R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3R_SC_NEG_EINT2_WIDTH 1 /* IM_HP3R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT2 0x0400 /* IM_HP3R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT2_MASK 0x0400 /* IM_HP3R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT2_SHIFT 10 /* IM_HP3R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3R_SC_POS_EINT2_WIDTH 1 /* IM_HP3R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT2 0x0200 /* IM_HP3L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT2_MASK 0x0200 /* IM_HP3L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT2_SHIFT 9 /* IM_HP3L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3L_SC_NEG_EINT2_WIDTH 1 /* IM_HP3L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT2 0x0100 /* IM_HP3L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT2_MASK 0x0100 /* IM_HP3L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT2_SHIFT 8 /* IM_HP3L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP3L_SC_POS_EINT2_WIDTH 1 /* IM_HP3L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT2 0x0080 /* IM_HP2R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT2_MASK 0x0080 /* IM_HP2R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT2_SHIFT 7 /* IM_HP2R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2R_SC_NEG_EINT2_WIDTH 1 /* IM_HP2R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT2 0x0040 /* IM_HP2R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT2_MASK 0x0040 /* IM_HP2R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT2_SHIFT 6 /* IM_HP2R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2R_SC_POS_EINT2_WIDTH 1 /* IM_HP2R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT2 0x0020 /* IM_HP2L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT2_MASK 0x0020 /* IM_HP2L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT2_SHIFT 5 /* IM_HP2L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2L_SC_NEG_EINT2_WIDTH 1 /* IM_HP2L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT2 0x0010 /* IM_HP2L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT2_MASK 0x0010 /* IM_HP2L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT2_SHIFT 4 /* IM_HP2L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP2L_SC_POS_EINT2_WIDTH 1 /* IM_HP2L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT2 0x0008 /* IM_HP1R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT2_MASK 0x0008 /* IM_HP1R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT2_SHIFT 3 /* IM_HP1R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1R_SC_NEG_EINT2_WIDTH 1 /* IM_HP1R_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT2 0x0004 /* IM_HP1R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT2_MASK 0x0004 /* IM_HP1R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT2_SHIFT 2 /* IM_HP1R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1R_SC_POS_EINT2_WIDTH 1 /* IM_HP1R_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT2 0x0002 /* IM_HP1L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT2_MASK 0x0002 /* IM_HP1L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT2_SHIFT 1 /* IM_HP1L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1L_SC_NEG_EINT2_WIDTH 1 /* IM_HP1L_SC_NEG_EINT2 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT2 0x0001 /* IM_HP1L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT2_MASK 0x0001 /* IM_HP1L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT2_SHIFT 0 /* IM_HP1L_SC_POS_EINT2 */ +#define ARIZONA_IM_HP1L_SC_POS_EINT2_WIDTH 1 /* IM_HP1L_SC_POS_EINT2 */ + /* * R3359 (0xD1F) - IRQ2 Control */ @@ -5029,14 +8855,14 @@ /* * R3361 (0xD21) - Interrupt Raw Status 3 */ -#define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */ -#define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */ -#define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */ -#define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */ -#define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ -#define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ -#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ -#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ +#define ARIZONA_SPK_OVERHEAT_WARN_STS 0x8000 /* SPK_OVERHEAT_WARN_STS */ +#define ARIZONA_SPK_OVERHEAT_WARN_STS_MASK 0x8000 /* SPK_OVERHEAT_WARN_STS */ +#define ARIZONA_SPK_OVERHEAT_WARN_STS_SHIFT 15 /* SPK_OVERHEAT_WARN_STS */ +#define ARIZONA_SPK_OVERHEAT_WARN_STS_WIDTH 1 /* SPK_OVERHEAT_WARN_STS */ +#define ARIZONA_SPK_OVERHEAT_STS 0x4000 /* SPK_OVERHEAT_STS */ +#define ARIZONA_SPK_OVERHEAT_STS_MASK 0x4000 /* SPK_OVERHEAT_STS */ +#define ARIZONA_SPK_OVERHEAT_STS_SHIFT 14 /* SPK_OVERHEAT_STS */ +#define ARIZONA_SPK_OVERHEAT_STS_WIDTH 1 /* SPK_OVERHEAT_STS */ #define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */ #define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */ #define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */ @@ -5133,6 +8959,30 @@ #define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */ #define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */ #define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */ +#define ARIZONA_HP3R_DONE_STS 0x0020 /* HP3R_DONE_STS */ +#define ARIZONA_HP3R_DONE_STS_MASK 0x0020 /* HP3R_DONE_STS */ +#define ARIZONA_HP3R_DONE_STS_SHIFT 5 /* HP3R_DONE_STS */ +#define ARIZONA_HP3R_DONE_STS_WIDTH 1 /* HP3R_DONE_STS */ +#define ARIZONA_HP3L_DONE_STS 0x0010 /* HP3L_DONE_STS */ +#define ARIZONA_HP3L_DONE_STS_MASK 0x0010 /* HP3L_DONE_STS */ +#define ARIZONA_HP3L_DONE_STS_SHIFT 4 /* HP3L_DONE_STS */ +#define ARIZONA_HP3L_DONE_STS_WIDTH 1 /* HP3L_DONE_STS */ +#define ARIZONA_HP2R_DONE_STS 0x0008 /* HP2R_DONE_STS */ +#define ARIZONA_HP2R_DONE_STS_MASK 0x0008 /* HP2R_DONE_STS */ +#define ARIZONA_HP2R_DONE_STS_SHIFT 3 /* HP2R_DONE_STS */ +#define ARIZONA_HP2R_DONE_STS_WIDTH 1 /* HP2R_DONE_STS */ +#define ARIZONA_HP2L_DONE_STS 0x0004 /* HP2L_DONE_STS */ +#define ARIZONA_HP2L_DONE_STS_MASK 0x0004 /* HP2L_DONE_STS */ +#define ARIZONA_HP2L_DONE_STS_SHIFT 2 /* HP2L_DONE_STS */ +#define ARIZONA_HP2L_DONE_STS_WIDTH 1 /* HP2L_DONE_STS */ +#define ARIZONA_HP1R_DONE_STS 0x0002 /* HP1R_DONE_STS */ +#define ARIZONA_HP1R_DONE_STS_MASK 0x0002 /* HP1R_DONE_STS */ +#define ARIZONA_HP1R_DONE_STS_SHIFT 1 /* HP1R_DONE_STS */ +#define ARIZONA_HP1R_DONE_STS_WIDTH 1 /* HP1R_DONE_STS */ +#define ARIZONA_HP1L_DONE_STS 0x0001 /* HP1L_DONE_STS */ +#define ARIZONA_HP1L_DONE_STS_MASK 0x0001 /* HP1L_DONE_STS */ +#define ARIZONA_HP1L_DONE_STS_SHIFT 0 /* HP1L_DONE_STS */ +#define ARIZONA_HP1L_DONE_STS_WIDTH 1 /* HP1L_DONE_STS */ /* * R3363 (0xD23) - Interrupt Raw Status 5 @@ -5217,50 +9067,58 @@ /* * R3365 (0xD25) - Interrupt Raw Status 7 */ -#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ -#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ +#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ -#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ +#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */ -#define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */ -#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */ -#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */ -#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */ -#define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */ -#define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */ -#define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */ -#define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */ -#define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */ -#define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */ -#define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */ -#define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */ +#define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */ +#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */ +#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */ +#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */ +#define ARIZONA_ISRC3_OVERCLOCKED_STS 0x0004 /* ISRC3_OVERCLOCKED_STS */ +#define ARIZONA_ISRC3_OVERCLOCKED_STS_MASK 0x0004 /* ISRC3_OVERCLOCKED_STS */ +#define ARIZONA_ISRC3_OVERCLOCKED_STS_SHIFT 2 /* ISRC3_OVERCLOCKED_STS */ +#define ARIZONA_ISRC3_OVERCLOCKED_STS_WIDTH 1 /* ISRC3_OVERCLOCKED_STS */ +#define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */ +#define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */ +#define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */ +#define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */ +#define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */ +#define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */ +#define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */ +#define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */ /* * R3366 (0xD26) - Interrupt Raw Status 8 */ +#define ARIZONA_SPDIF_OVERCLOCKED_STS 0x8000 /* SPDIF_OVERCLOCKED_STS */ +#define ARIZONA_SPDIF_OVERCLOCKED_STS_MASK 0x8000 /* SPDIF_OVERCLOCKED_STS */ +#define ARIZONA_SPDIF_OVERCLOCKED_STS_SHIFT 15 /* SPDIF_OVERCLOCKED_STS */ +#define ARIZONA_SPDIF_OVERCLOCKED_STS_WIDTH 1 /* SPDIF_OVERCLOCKED_STS */ #define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */ #define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */ #define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */ @@ -5273,6 +9131,10 @@ #define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */ #define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */ #define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */ +#define ARIZONA_ISRC3_UNDERCLOCKED_STS 0x0080 /* ISRC3_UNDERCLOCKED_STS */ +#define ARIZONA_ISRC3_UNDERCLOCKED_STS_MASK 0x0080 /* ISRC3_UNDERCLOCKED_STS */ +#define ARIZONA_ISRC3_UNDERCLOCKED_STS_SHIFT 7 /* ISRC3_UNDERCLOCKED_STS */ +#define ARIZONA_ISRC3_UNDERCLOCKED_STS_WIDTH 1 /* ISRC3_UNDERCLOCKED_STS */ #define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */ #define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */ #define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */ @@ -5302,6 +9164,74 @@ #define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */ #define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */ +/* + * R3368 (0xD28) - Interrupt Raw Status 9 + */ +#define ARIZONA_DSP_SHARED_WR_COLL_STS 0x8000 /* DSP_SHARED_WR_COLL_STS */ +#define ARIZONA_DSP_SHARED_WR_COLL_STS_MASK 0x8000 /* DSP_SHARED_WR_COLL_STS */ +#define ARIZONA_DSP_SHARED_WR_COLL_STS_SHIFT 15 /* DSP_SHARED_WR_COLL_STS */ +#define ARIZONA_DSP_SHARED_WR_COLL_STS_WIDTH 1 /* DSP_SHARED_WR_COLL_STS */ +#define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ +#define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ +#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ +#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ +#define ARIZONA_SPK1R_SHORT_STS 0x2000 /* SPK1R_SHORT_STS */ +#define ARIZONA_SPK1R_SHORT_STS_MASK 0x2000 /* SPK1R_SHORT_STS */ +#define ARIZONA_SPK1R_SHORT_STS_SHIFT 13 /* SPK1R_SHORT_STS */ +#define ARIZONA_SPK1R_SHORT_STS_WIDTH 1 /* SPK1R_SHORT_STS */ +#define ARIZONA_SPK1L_SHORT_STS 0x1000 /* SPK1L_SHORT_STS */ +#define ARIZONA_SPK1L_SHORT_STS_MASK 0x1000 /* SPK1L_SHORT_STS */ +#define ARIZONA_SPK1L_SHORT_STS_SHIFT 12 /* SPK1L_SHORT_STS */ +#define ARIZONA_SPK1L_SHORT_STS_WIDTH 1 /* SPK1L_SHORT_STS */ +#define ARIZONA_HP3R_SC_NEG_STS 0x0800 /* HP3R_SC_NEG_STS */ +#define ARIZONA_HP3R_SC_NEG_STS_MASK 0x0800 /* HP3R_SC_NEG_STS */ +#define ARIZONA_HP3R_SC_NEG_STS_SHIFT 11 /* HP3R_SC_NEG_STS */ +#define ARIZONA_HP3R_SC_NEG_STS_WIDTH 1 /* HP3R_SC_NEG_STS */ +#define ARIZONA_HP3R_SC_POS_STS 0x0400 /* HP3R_SC_POS_STS */ +#define ARIZONA_HP3R_SC_POS_STS_MASK 0x0400 /* HP3R_SC_POS_STS */ +#define ARIZONA_HP3R_SC_POS_STS_SHIFT 10 /* HP3R_SC_POS_STS */ +#define ARIZONA_HP3R_SC_POS_STS_WIDTH 1 /* HP3R_SC_POS_STS */ +#define ARIZONA_HP3L_SC_NEG_STS 0x0200 /* HP3L_SC_NEG_STS */ +#define ARIZONA_HP3L_SC_NEG_STS_MASK 0x0200 /* HP3L_SC_NEG_STS */ +#define ARIZONA_HP3L_SC_NEG_STS_SHIFT 9 /* HP3L_SC_NEG_STS */ +#define ARIZONA_HP3L_SC_NEG_STS_WIDTH 1 /* HP3L_SC_NEG_STS */ +#define ARIZONA_HP3L_SC_POS_STS 0x0100 /* HP3L_SC_POS_STS */ +#define ARIZONA_HP3L_SC_POS_STS_MASK 0x0100 /* HP3L_SC_POS_STS */ +#define ARIZONA_HP3L_SC_POS_STS_SHIFT 8 /* HP3L_SC_POS_STS */ +#define ARIZONA_HP3L_SC_POS_STS_WIDTH 1 /* HP3L_SC_POS_STS */ +#define ARIZONA_HP2R_SC_NEG_STS 0x0080 /* HP2R_SC_NEG_STS */ +#define ARIZONA_HP2R_SC_NEG_STS_MASK 0x0080 /* HP2R_SC_NEG_STS */ +#define ARIZONA_HP2R_SC_NEG_STS_SHIFT 7 /* HP2R_SC_NEG_STS */ +#define ARIZONA_HP2R_SC_NEG_STS_WIDTH 1 /* HP2R_SC_NEG_STS */ +#define ARIZONA_HP2R_SC_POS_STS 0x0040 /* HP2R_SC_POS_STS */ +#define ARIZONA_HP2R_SC_POS_STS_MASK 0x0040 /* HP2R_SC_POS_STS */ +#define ARIZONA_HP2R_SC_POS_STS_SHIFT 6 /* HP2R_SC_POS_STS */ +#define ARIZONA_HP2R_SC_POS_STS_WIDTH 1 /* HP2R_SC_POS_STS */ +#define ARIZONA_HP2L_SC_NEG_STS 0x0020 /* HP2L_SC_NEG_STS */ +#define ARIZONA_HP2L_SC_NEG_STS_MASK 0x0020 /* HP2L_SC_NEG_STS */ +#define ARIZONA_HP2L_SC_NEG_STS_SHIFT 5 /* HP2L_SC_NEG_STS */ +#define ARIZONA_HP2L_SC_NEG_STS_WIDTH 1 /* HP2L_SC_NEG_STS */ +#define ARIZONA_HP2L_SC_POS_STS 0x0010 /* HP2L_SC_POS_STS */ +#define ARIZONA_HP2L_SC_POS_STS_MASK 0x0010 /* HP2L_SC_POS_STS */ +#define ARIZONA_HP2L_SC_POS_STS_SHIFT 4 /* HP2L_SC_POS_STS */ +#define ARIZONA_HP2L_SC_POS_STS_WIDTH 1 /* HP2L_SC_POS_STS */ +#define ARIZONA_HP1R_SC_NEG_STS 0x0008 /* HP1R_SC_NEG_STS */ +#define ARIZONA_HP1R_SC_NEG_STS_MASK 0x0008 /* HP1R_SC_NEG_STS */ +#define ARIZONA_HP1R_SC_NEG_STS_SHIFT 3 /* HP1R_SC_NEG_STS */ +#define ARIZONA_HP1R_SC_NEG_STS_WIDTH 1 /* HP1R_SC_NEG_STS */ +#define ARIZONA_HP1R_SC_POS_STS 0x0004 /* HP1R_SC_POS_STS */ +#define ARIZONA_HP1R_SC_POS_STS_MASK 0x0004 /* HP1R_SC_POS_STS */ +#define ARIZONA_HP1R_SC_POS_STS_SHIFT 2 /* HP1R_SC_POS_STS */ +#define ARIZONA_HP1R_SC_POS_STS_WIDTH 1 /* HP1R_SC_POS_STS */ +#define ARIZONA_HP1L_SC_NEG_STS 0x0002 /* HP1L_SC_NEG_STS */ +#define ARIZONA_HP1L_SC_NEG_STS_MASK 0x0002 /* HP1L_SC_NEG_STS */ +#define ARIZONA_HP1L_SC_NEG_STS_SHIFT 1 /* HP1L_SC_NEG_STS */ +#define ARIZONA_HP1L_SC_NEG_STS_WIDTH 1 /* HP1L_SC_NEG_STS */ +#define ARIZONA_HP1L_SC_POS_STS 0x0001 /* HP1L_SC_POS_STS */ +#define ARIZONA_HP1L_SC_POS_STS_MASK 0x0001 /* HP1L_SC_POS_STS */ +#define ARIZONA_HP1L_SC_POS_STS_SHIFT 0 /* HP1L_SC_POS_STS */ +#define ARIZONA_HP1L_SC_POS_STS_WIDTH 1 /* HP1L_SC_POS_STS */ + /* * R3392 (0xD40) - IRQ Pin Status */ @@ -6468,6 +10398,74 @@ #define ARIZONA_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */ #define ARIZONA_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ +/* + * R3808 (0xED0) - ASRC2_ENABLE + */ +#define CLEARWATER_ASRC2_IN2L_ENA 0x0008 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC2_IN2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC2_IN2L_ENA_SHIFT 3 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC2_IN2L_ENA_WIDTH 1 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC2_IN2R_ENA 0x0004 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC2_IN2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC2_IN2R_ENA_SHIFT 2 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC2_IN2R_ENA_WIDTH 1 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC2_IN1L_ENA 0x0002 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC2_IN1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC2_IN1L_ENA_SHIFT 1 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC2_IN1L_ENA_WIDTH 1 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC2_IN1R_ENA 0x0001 /* ASRC1R_ENA */ +#define CLEARWATER_ASRC2_IN1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ +#define CLEARWATER_ASRC2_IN1R_ENA_SHIFT 0 /* ASRC1R_ENA */ +#define CLEARWATER_ASRC2_IN1R_ENA_WIDTH 1 /* ASRC1R_ENA */ + +/* + * R3810 (0xED2) - ASRC2_RATE1 + */ +#define CLEARWATER_ASRC2_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */ +#define CLEARWATER_ASRC2_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */ +#define CLEARWATER_ASRC2_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */ + +/* + * R3811 (0xED3) - ASRC2_RATE2 + */ +#define CLEARWATER_ASRC2_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */ +#define CLEARWATER_ASRC2_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */ +#define CLEARWATER_ASRC2_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */ + +/* + * R3808 (0xEE0) - ASRC1_ENABLE + */ +#define CLEARWATER_ASRC1_IN2L_ENA 0x0008 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC1_IN2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC1_IN2L_ENA_SHIFT 3 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC1_IN2L_ENA_WIDTH 1 /* ASRC2L_ENA */ +#define CLEARWATER_ASRC1_IN2R_ENA 0x0004 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC1_IN2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC1_IN2R_ENA_SHIFT 2 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC1_IN2R_ENA_WIDTH 1 /* ASRC2R_ENA */ +#define CLEARWATER_ASRC1_IN1L_ENA 0x0002 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC1_IN1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC1_IN1L_ENA_SHIFT 1 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC1_IN1L_ENA_WIDTH 1 /* ASRC1L_ENA */ +#define CLEARWATER_ASRC1_IN1R_ENA 0x0001 /* ASRC1R_ENA */ +#define CLEARWATER_ASRC1_IN1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ +#define CLEARWATER_ASRC1_IN1R_ENA_SHIFT 0 /* ASRC1R_ENA */ +#define CLEARWATER_ASRC1_IN1R_ENA_WIDTH 1 /* ASRC1R_ENA */ + +/* + * R3810 (0xEE2) - ASRC1_RATE1 + */ +#define CLEARWATER_ASRC1_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */ +#define CLEARWATER_ASRC1_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */ +#define CLEARWATER_ASRC1_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */ + +/* + * R3811 (0xEE3) - ASRC1_RATE2 + */ +#define CLEARWATER_ASRC1_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */ +#define CLEARWATER_ASRC1_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */ +#define CLEARWATER_ASRC1_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */ + /* * R3808 (0xEE0) - ASRC_ENABLE */ @@ -6673,6 +10671,123 @@ #define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */ #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */ +/* + * R3833 (0xEF9) - ISRC 4 CTRL 1 + */ +#define ARIZONA_ISRC4_FSH_MASK 0x7800 /* ISRC4_FSH - [14:11] */ +#define ARIZONA_ISRC4_FSH_SHIFT 11 /* ISRC4_FSH - [14:11] */ +#define ARIZONA_ISRC4_FSH_WIDTH 4 /* ISRC4_FSH - [14:11] */ +#define ARIZONA_ISRC4_CLK_SEL_MASK 0x0700 /* ISRC4_CLK_SEL - [10:8] */ +#define ARIZONA_ISRC4_CLK_SEL_SHIFT 8 /* ISRC4_CLK_SEL - [10:8] */ +#define ARIZONA_ISRC4_CLK_SEL_WIDTH 3 /* ISRC4_CLK_SEL - [10:8] */ + +/* + * R3834 (0xEFA) - ISRC 4 CTRL 2 + */ +#define ARIZONA_ISRC4_FSL_MASK 0x7800 /* ISRC4_FSL - [14:11] */ +#define ARIZONA_ISRC4_FSL_SHIFT 11 /* ISRC4_FSL - [14:11] */ +#define ARIZONA_ISRC4_FSL_WIDTH 4 /* ISRC4_FSL - [14:11] */ + +/* + * R3835 (0xEFB) - ISRC 4 CTRL 3 + */ +#define ARIZONA_ISRC4_INT0_ENA 0x8000 /* ISRC4_INT0_ENA */ +#define ARIZONA_ISRC4_INT0_ENA_MASK 0x8000 /* ISRC4_INT0_ENA */ +#define ARIZONA_ISRC4_INT0_ENA_SHIFT 15 /* ISRC4_INT0_ENA */ +#define ARIZONA_ISRC4_INT0_ENA_WIDTH 1 /* ISRC4_INT0_ENA */ +#define ARIZONA_ISRC4_INT1_ENA 0x4000 /* ISRC4_INT1_ENA */ +#define ARIZONA_ISRC4_INT1_ENA_MASK 0x4000 /* ISRC4_INT1_ENA */ +#define ARIZONA_ISRC4_INT1_ENA_SHIFT 14 /* ISRC4_INT1_ENA */ +#define ARIZONA_ISRC4_INT1_ENA_WIDTH 1 /* ISRC4_INT1_ENA */ +#define ARIZONA_ISRC4_INT2_ENA 0x2000 /* ISRC4_INT2_ENA */ +#define ARIZONA_ISRC4_INT2_ENA_MASK 0x2000 /* ISRC4_INT2_ENA */ +#define ARIZONA_ISRC4_INT2_ENA_SHIFT 13 /* ISRC4_INT2_ENA */ +#define ARIZONA_ISRC4_INT2_ENA_WIDTH 1 /* ISRC4_INT2_ENA */ +#define ARIZONA_ISRC4_INT3_ENA 0x1000 /* ISRC4_INT3_ENA */ +#define ARIZONA_ISRC4_INT3_ENA_MASK 0x1000 /* ISRC4_INT3_ENA */ +#define ARIZONA_ISRC4_INT3_ENA_SHIFT 12 /* ISRC4_INT3_ENA */ +#define ARIZONA_ISRC4_INT3_ENA_WIDTH 1 /* ISRC4_INT3_ENA */ +#define ARIZONA_ISRC4_DEC0_ENA 0x0200 /* ISRC4_DEC0_ENA */ +#define ARIZONA_ISRC4_DEC0_ENA_MASK 0x0200 /* ISRC4_DEC0_ENA */ +#define ARIZONA_ISRC4_DEC0_ENA_SHIFT 9 /* ISRC4_DEC0_ENA */ +#define ARIZONA_ISRC4_DEC0_ENA_WIDTH 1 /* ISRC4_DEC0_ENA */ +#define ARIZONA_ISRC4_DEC1_ENA 0x0100 /* ISRC4_DEC1_ENA */ +#define ARIZONA_ISRC4_DEC1_ENA_MASK 0x0100 /* ISRC4_DEC1_ENA */ +#define ARIZONA_ISRC4_DEC1_ENA_SHIFT 8 /* ISRC4_DEC1_ENA */ +#define ARIZONA_ISRC4_DEC1_ENA_WIDTH 1 /* ISRC4_DEC1_ENA */ +#define ARIZONA_ISRC4_DEC2_ENA 0x0080 /* ISRC4_DEC2_ENA */ +#define ARIZONA_ISRC4_DEC2_ENA_MASK 0x0080 /* ISRC4_DEC2_ENA */ +#define ARIZONA_ISRC4_DEC2_ENA_SHIFT 7 /* ISRC4_DEC2_ENA */ +#define ARIZONA_ISRC4_DEC2_ENA_WIDTH 1 /* ISRC4_DEC2_ENA */ +#define ARIZONA_ISRC4_DEC3_ENA 0x0040 /* ISRC4_DEC3_ENA */ +#define ARIZONA_ISRC4_DEC3_ENA_MASK 0x0040 /* ISRC4_DEC3_ENA */ +#define ARIZONA_ISRC4_DEC3_ENA_SHIFT 6 /* ISRC4_DEC3_ENA */ +#define ARIZONA_ISRC4_DEC3_ENA_WIDTH 1 /* ISRC4_DEC3_ENA */ +#define ARIZONA_ISRC4_NOTCH_ENA 0x0001 /* ISRC4_NOTCH_ENA */ +#define ARIZONA_ISRC4_NOTCH_ENA_MASK 0x0001 /* ISRC4_NOTCH_ENA */ +#define ARIZONA_ISRC4_NOTCH_ENA_SHIFT 0 /* ISRC4_NOTCH_ENA */ +#define ARIZONA_ISRC4_NOTCH_ENA_WIDTH 1 /* ISRC4_NOTCH_ENA */ + +/* + * R3840 (0xF00) - Clock Control + */ +#define ARIZONA_EXT_NG_SEL_CLR 0x0080 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_CLR_MASK 0x0080 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_CLR_SHIFT 7 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_CLR_WIDTH 1 /* EXT_NG_SEL_CLR */ +#define ARIZONA_EXT_NG_SEL_SET 0x0040 /* EXT_NG_SEL_SET */ +#define ARIZONA_EXT_NG_SEL_SET_MASK 0x0040 /* EXT_NG_SEL_SET */ +#define ARIZONA_EXT_NG_SEL_SET_SHIFT 6 /* EXT_NG_SEL_SET */ +#define ARIZONA_EXT_NG_SEL_SET_WIDTH 1 /* EXT_NG_SEL_SET */ +#define ARIZONA_CLK_R_ENA_CLR 0x0020 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_CLR_MASK 0x0020 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_CLR_SHIFT 5 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_CLR_WIDTH 1 /* CLK_R_ENA_CLR */ +#define ARIZONA_CLK_R_ENA_SET 0x0010 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_R_ENA_SET_MASK 0x0010 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_R_ENA_SET_SHIFT 4 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_R_ENA_SET_WIDTH 1 /* CLK_R_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_CLR 0x0008 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_CLR_MASK 0x0008 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_CLR_SHIFT 3 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_CLR_WIDTH 1 /* CLK_NG_ENA_CLR */ +#define ARIZONA_CLK_NG_ENA_SET 0x0004 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_SET_MASK 0x0004 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_SET_SHIFT 2 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_NG_ENA_SET_WIDTH 1 /* CLK_NG_ENA_SET */ +#define ARIZONA_CLK_L_ENA_CLR 0x0002 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_CLR_MASK 0x0002 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_CLR_SHIFT 1 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_CLR_WIDTH 1 /* CLK_L_ENA_CLR */ +#define ARIZONA_CLK_L_ENA_SET 0x0001 /* CLK_L_ENA_SET */ +#define ARIZONA_CLK_L_ENA_SET_MASK 0x0001 /* CLK_L_ENA_SET */ +#define ARIZONA_CLK_L_ENA_SET_SHIFT 0 /* CLK_L_ENA_SET */ +#define ARIZONA_CLK_L_ENA_SET_WIDTH 1 /* CLK_L_ENA_SET */ + +/* + * R3841 (0xF01) - ANC SRC + */ +#define ARIZONA_IN_RXANCR_SEL_MASK 0x0070 /* IN_RXANCR_SEL - [4:6] */ +#define ARIZONA_IN_RXANCR_SEL_SHIFT 4 /* IN_RXANCR_SEL - [4:6] */ +#define ARIZONA_IN_RXANCR_SEL_WIDTH 3 /* IN_RXANCR_SEL - [4:6] */ +#define ARIZONA_IN_RXANCL_SEL_MASK 0x0007 /* IN_RXANCL_SEL - [0:2] */ +#define ARIZONA_IN_RXANCL_SEL_SHIFT 0 /* IN_RXANCL_SEL - [0:2] */ +#define ARIZONA_IN_RXANCL_SEL_WIDTH 3 /* IN_RXANCL_SEL - [0:2] */ + +/* + * R3863 (0xF17) - FCL ADC Reformatter Control + */ +#define ARIZONA_FCL_MIC_MODE_SEL 0x000C /* FCL_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCL_MIC_MODE_SEL_SHIFT 2 /* FCL_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCL_MIC_MODE_SEL_WIDTH 2 /* FCL_MIC_MODE_SEL - [2:3] */ + +/* + * R3954 (0xF72) - FCR ADC Reformatter Control + */ +#define ARIZONA_FCR_MIC_MODE_SEL 0x000C /* FCR_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCR_MIC_MODE_SEL_SHIFT 2 /* FCR_MIC_MODE_SEL - [2:3] */ +#define ARIZONA_FCR_MIC_MODE_SEL_WIDTH 2 /* FCR_MIC_MODE_SEL - [2:3] */ + /* * R4352 (0x1100) - DSP1 Control 1 */ @@ -6726,4 +10841,2329 @@ #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */ +/* +* R1718 (0x1380) - FRF_Coefficient_1L_1 +*/ +#define CLEARWATER_FRF_COEFF_1L_1_MASK 0xFFFF /* FRF_COEFF_1L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_1_SHIFT 0 /* FRF_COEFF_1L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_1_WIDTH 16 /* FRF_COEFF_1L_1 - [15:0] */ + +/* + * R1719 (0x1381) - FRF_Coefficient_1L_2 + */ +#define CLEARWATER_FRF_COEFF_1L_2_MASK 0xFFFF /* FRF_COEFF_1L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_2_SHIFT 0 /* FRF_COEFF_1L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_2_WIDTH 16 /* FRF_COEFF_1L_2 - [15:0] */ + +/* + * R1720 (0x1382) - FRF_Coefficient_1L_3 + */ +#define CLEARWATER_FRF_COEFF_1L_3_MASK 0xFFFF /* FRF_COEFF_1L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_3_SHIFT 0 /* FRF_COEFF_1L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_3_WIDTH 16 /* FRF_COEFF_1L_3 - [15:0] */ + +/* + * R1721 (0x1383) - FRF_Coefficient_1L_4 + */ +#define CLEARWATER_FRF_COEFF_1L_4_MASK 0xFFFF /* FRF_COEFF_1L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_4_SHIFT 0 /* FRF_COEFF_1L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1L_4_WIDTH 16 /* FRF_COEFF_1L_4 - [15:0] */ + +/* + * R1722 (0x1390) - FRF_Coefficient_1R_1 + */ +#define CLEARWATER_FRF_COEFF_1R_1_MASK 0xFFFF /* FRF_COEFF_1R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_1_SHIFT 0 /* FRF_COEFF_1R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_1_WIDTH 16 /* FRF_COEFF_1R_1 - [15:0] */ + +/* + * R1723 (0x1391) - FRF_Coefficient_1R_2 + */ +#define CLEARWATER_FRF_COEFF_1R_2_MASK 0xFFFF /* FRF_COEFF_1R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_2_SHIFT 0 /* FRF_COEFF_1R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_2_WIDTH 16 /* FRF_COEFF_1R_2 - [15:0] */ + +/* + * R1724 (0x1392) - FRF_Coefficient_1R_3 + */ +#define CLEARWATER_FRF_COEFF_1R_3_MASK 0xFFFF /* FRF_COEFF_1R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_3_SHIFT 0 /* FRF_COEFF_1R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_3_WIDTH 16 /* FRF_COEFF_1R_3 - [15:0] */ + +/* + * R1725 (0x1393) - FRF_Coefficient_1R_4 + */ +#define CLEARWATER_FRF_COEFF_1R_4_MASK 0xFFFF /* FRF_COEFF_1R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_4_SHIFT 0 /* FRF_COEFF_1R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_1R_4_WIDTH 16 /* FRF_COEFF_1R_4 - [15:0] */ + +/* + * R1726 (0x13A0) - FRF_Coefficient_2L_1 + */ +#define CLEARWATER_FRF_COEFF_2L_1_MASK 0xFFFF /* FRF_COEFF_2L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_1_SHIFT 0 /* FRF_COEFF_2L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_1_WIDTH 16 /* FRF_COEFF_2L_1 - [15:0] */ + +/* + * R1727 (0x13A1) - FRF_Coefficient_2L_2 + */ +#define CLEARWATER_FRF_COEFF_2L_2_MASK 0xFFFF /* FRF_COEFF_2L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_2_SHIFT 0 /* FRF_COEFF_2L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_2_WIDTH 16 /* FRF_COEFF_2L_2 - [15:0] */ + +/* + * R1728 (0x13A2) - FRF_Coefficient_2L_3 + */ +#define CLEARWATER_FRF_COEFF_2L_3_MASK 0xFFFF /* FRF_COEFF_2L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_3_SHIFT 0 /* FRF_COEFF_2L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_3_WIDTH 16 /* FRF_COEFF_2L_3 - [15:0] */ + +/* + * R1729 (0x13A3) - FRF_Coefficient_2L_4 + */ +#define CLEARWATER_FRF_COEFF_2L_4_MASK 0xFFFF /* FRF_COEFF_2L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_4_SHIFT 0 /* FRF_COEFF_2L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2L_4_WIDTH 16 /* FRF_COEFF_2L_4 - [15:0] */ + +/* + * R1730 (0x13B0) - FRF_Coefficient_2R_1 + */ +#define CLEARWATER_FRF_COEFF_2R_1_MASK 0xFFFF /* FRF_COEFF_2R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_1_SHIFT 0 /* FRF_COEFF_2R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_1_WIDTH 16 /* FRF_COEFF_2R_1 - [15:0] */ + +/* + * R1731 (0x13B1) - FRF_Coefficient_2R_2 + */ +#define CLEARWATER_FRF_COEFF_2R_2_MASK 0xFFFF /* FRF_COEFF_2R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_2_SHIFT 0 /* FRF_COEFF_2R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_2_WIDTH 16 /* FRF_COEFF_2R_2 - [15:0] */ + +/* + * R1732 (0x13B2) - FRF_Coefficient_2R_3 + */ +#define CLEARWATER_FRF_COEFF_2R_3_MASK 0xFFFF /* FRF_COEFF_2R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_3_SHIFT 0 /* FRF_COEFF_2R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_3_WIDTH 16 /* FRF_COEFF_2R_3 - [15:0] */ + +/* + * R1733 (0x13B3) - FRF_Coefficient_2R_4 + */ +#define CLEARWATER_FRF_COEFF_2R_4_MASK 0xFFFF /* FRF_COEFF_2R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_4_SHIFT 0 /* FRF_COEFF_2R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_2R_4_WIDTH 16 /* FRF_COEFF_2R_4 - [15:0] */ + +/* + * R1734 (0x13C0) - FRF_Coefficient_3L_1 + */ +#define CLEARWATER_FRF_COEFF_3L_1_MASK 0xFFFF /* FRF_COEFF_3L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_1_SHIFT 0 /* FRF_COEFF_3L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_1_WIDTH 16 /* FRF_COEFF_3L_1 - [15:0] */ + +/* + * R1735 (0x13C1) - FRF_Coefficient_3L_2 + */ +#define CLEARWATER_FRF_COEFF_3L_2_MASK 0xFFFF /* FRF_COEFF_3L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_2_SHIFT 0 /* FRF_COEFF_3L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_2_WIDTH 16 /* FRF_COEFF_3L_2 - [15:0] */ + +/* + * R1736 (0x13C2) - FRF_Coefficient_3L_3 + */ +#define CLEARWATER_FRF_COEFF_3L_3_MASK 0xFFFF /* FRF_COEFF_3L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_3_SHIFT 0 /* FRF_COEFF_3L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_3_WIDTH 16 /* FRF_COEFF_3L_3 - [15:0] */ + +/* + * R1737 (0x13C3) - FRF_Coefficient_3L_4 + */ +#define CLEARWATER_FRF_COEFF_3L_4_MASK 0xFFFF /* FRF_COEFF_3L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_4_SHIFT 0 /* FRF_COEFF_3L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3L_4_WIDTH 16 /* FRF_COEFF_3L_4 - [15:0] */ + +/* + * R1738 (0x13D0) - FRF_Coefficient_3R_1 + */ +#define CLEARWATER_FRF_COEFF_3R_1_MASK 0xFFFF /* FRF_COEFF_3R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_1_SHIFT 0 /* FRF_COEFF_3R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_1_WIDTH 16 /* FRF_COEFF_3R_1 - [15:0] */ + +/* + * R1739 (0x13D1) - FRF_Coefficient_3R_2 + */ +#define CLEARWATER_FRF_COEFF_3R_2_MASK 0xFFFF /* FRF_COEFF_3R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_2_SHIFT 0 /* FRF_COEFF_3R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_2_WIDTH 16 /* FRF_COEFF_3R_2 - [15:0] */ + +/* + * R1740 (0x13D2) - FRF_Coefficient_3R_3 + */ +#define CLEARWATER_FRF_COEFF_3R_3_MASK 0xFFFF /* FRF_COEFF_3R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_3_SHIFT 0 /* FRF_COEFF_3R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_3_WIDTH 16 /* FRF_COEFF_3R_3 - [15:0] */ + +/* + * R1741 (0x13D3) - FRF_Coefficient_3R_4 + */ +#define CLEARWATER_FRF_COEFF_3R_4_MASK 0xFFFF /* FRF_COEFF_3R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_4_SHIFT 0 /* FRF_COEFF_3R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_3R_4_WIDTH 16 /* FRF_COEFF_3R_4 - [15:0] */ + +/* + * R1742 (0x13E0) - FRF_Coefficient_4L_1 + */ +#define CLEARWATER_FRF_COEFF_4L_1_MASK 0xFFFF /* FRF_COEFF_4L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_1_SHIFT 0 /* FRF_COEFF_4L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_1_WIDTH 16 /* FRF_COEFF_4L_1 - [15:0] */ + +/* + * R1743 (0x13E1) - FRF_Coefficient_4L_2 + */ +#define CLEARWATER_FRF_COEFF_4L_2_MASK 0xFFFF /* FRF_COEFF_4L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_2_SHIFT 0 /* FRF_COEFF_4L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_2_WIDTH 16 /* FRF_COEFF_4L_2 - [15:0] */ + +/* + * R1744 (0x13E2) - FRF_Coefficient_4L_3 + */ +#define CLEARWATER_FRF_COEFF_4L_3_MASK 0xFFFF /* FRF_COEFF_4L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_3_SHIFT 0 /* FRF_COEFF_4L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_3_WIDTH 16 /* FRF_COEFF_4L_3 - [15:0] */ + +/* + * R1745 (0x13E3) - FRF_Coefficient_4L_4 + */ +#define CLEARWATER_FRF_COEFF_4L_4_MASK 0xFFFF /* FRF_COEFF_4L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_4_SHIFT 0 /* FRF_COEFF_4L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4L_4_WIDTH 16 /* FRF_COEFF_4L_4 - [15:0] */ + +/* + * R1746 (0x13F0) - FRF_Coefficient_4R_1 + */ +#define CLEARWATER_FRF_COEFF_4R_1_MASK 0xFFFF /* FRF_COEFF_4R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_1_SHIFT 0 /* FRF_COEFF_4R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_1_WIDTH 16 /* FRF_COEFF_4R_1 - [15:0] */ + +/* + * R1747 (0x13F1) - FRF_Coefficient_4R_2 + */ +#define CLEARWATER_FRF_COEFF_4R_2_MASK 0xFFFF /* FRF_COEFF_4R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_2_SHIFT 0 /* FRF_COEFF_4R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_2_WIDTH 16 /* FRF_COEFF_4R_2 - [15:0] */ + +/* + * R1748 (0x13F2) - FRF_Coefficient_4R_3 + */ +#define CLEARWATER_FRF_COEFF_4R_3_MASK 0xFFFF /* FRF_COEFF_4R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_3_SHIFT 0 /* FRF_COEFF_4R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_3_WIDTH 16 /* FRF_COEFF_4R_3 - [15:0] */ + +/* + * R1749 (0x13F3) - FRF_Coefficient_4R_4 + */ +#define CLEARWATER_FRF_COEFF_4R_4_MASK 0xFFFF /* FRF_COEFF_4R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_4_SHIFT 0 /* FRF_COEFF_4R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_4R_4_WIDTH 16 /* FRF_COEFF_4R_4 - [15:0] */ + +/* + * R1750 (0x1400) - FRF_Coefficient_5L_1 + */ +#define CLEARWATER_FRF_COEFF_5L_1_MASK 0xFFFF /* FRF_COEFF_5L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_1_SHIFT 0 /* FRF_COEFF_5L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_1_WIDTH 16 /* FRF_COEFF_5L_1 - [15:0] */ + +/* + * R1751 (0x1401) - FRF_Coefficient_5L_2 + */ +#define CLEARWATER_FRF_COEFF_5L_2_MASK 0xFFFF /* FRF_COEFF_5L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_2_SHIFT 0 /* FRF_COEFF_5L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_2_WIDTH 16 /* FRF_COEFF_5L_2 - [15:0] */ + +/* + * R1752 (0x1402) - FRF_Coefficient_5L_3 + */ +#define CLEARWATER_FRF_COEFF_5L_3_MASK 0xFFFF /* FRF_COEFF_5L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_3_SHIFT 0 /* FRF_COEFF_5L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_3_WIDTH 16 /* FRF_COEFF_5L_3 - [15:0] */ + +/* + * R1753 (0x1403) - FRF_Coefficient_5L_4 + */ +#define CLEARWATER_FRF_COEFF_5L_4_MASK 0xFFFF /* FRF_COEFF_5L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_4_SHIFT 0 /* FRF_COEFF_5L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5L_4_WIDTH 16 /* FRF_COEFF_5L_4 - [15:0] */ + +/* + * R1754 (0x1410) - FRF_Coefficient_5R_1 + */ +#define CLEARWATER_FRF_COEFF_5R_1_MASK 0xFFFF /* FRF_COEFF_5R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_1_SHIFT 0 /* FRF_COEFF_5R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_1_WIDTH 16 /* FRF_COEFF_5R_1 - [15:0] */ + +/* + * R1755 (0x1411) - FRF_Coefficient_5R_2 + */ +#define CLEARWATER_FRF_COEFF_5R_2_MASK 0xFFFF /* FRF_COEFF_5R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_2_SHIFT 0 /* FRF_COEFF_5R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_2_WIDTH 16 /* FRF_COEFF_5R_2 - [15:0] */ + +/* + * R1756 (0x1412) - FRF_Coefficient_5R_3 + */ +#define CLEARWATER_FRF_COEFF_5R_3_MASK 0xFFFF /* FRF_COEFF_5R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_3_SHIFT 0 /* FRF_COEFF_5R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_3_WIDTH 16 /* FRF_COEFF_5R_3 - [15:0] */ + +/* + * R1757 (0x1413) - FRF_Coefficient_5R_4 + */ +#define CLEARWATER_FRF_COEFF_5R_4_MASK 0xFFFF /* FRF_COEFF_5R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_4_SHIFT 0 /* FRF_COEFF_5R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_5R_4_WIDTH 16 /* FRF_COEFF_5R_4 - [15:0] */ + +/* + * R1758 (0x1420) - FRF_Coefficient_6L_1 + */ +#define CLEARWATER_FRF_COEFF_6L_1_MASK 0xFFFF /* FRF_COEFF_6L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_1_SHIFT 0 /* FRF_COEFF_6L_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_1_WIDTH 16 /* FRF_COEFF_6L_1 - [15:0] */ + +/* + * R1759 (0x1421) - FRF_Coefficient_6L_2 + */ +#define CLEARWATER_FRF_COEFF_6L_2_MASK 0xFFFF /* FRF_COEFF_6L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_2_SHIFT 0 /* FRF_COEFF_6L_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_2_WIDTH 16 /* FRF_COEFF_6L_2 - [15:0] */ + +/* + * R1760 (0x1422) - FRF_Coefficient_6L_3 + */ +#define CLEARWATER_FRF_COEFF_6L_3_MASK 0xFFFF /* FRF_COEFF_6L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_3_SHIFT 0 /* FRF_COEFF_6L_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_3_WIDTH 16 /* FRF_COEFF_6L_3 - [15:0] */ + +/* + * R1761 (0x1423) - FRF_Coefficient_6L_4 + */ +#define CLEARWATER_FRF_COEFF_6L_4_MASK 0xFFFF /* FRF_COEFF_6L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_4_SHIFT 0 /* FRF_COEFF_6L_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6L_4_WIDTH 16 /* FRF_COEFF_6L_4 - [15:0] */ + +/* + * R1762 (0x1430) - FRF_Coefficient_6R_1 + */ +#define CLEARWATER_FRF_COEFF_6R_1_MASK 0xFFFF /* FRF_COEFF_6R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_1_SHIFT 0 /* FRF_COEFF_6R_1 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_1_WIDTH 16 /* FRF_COEFF_6R_1 - [15:0] */ + +/* + * R1763 (0x1431) - FRF_Coefficient_6R_2 + */ +#define CLEARWATER_FRF_COEFF_6R_2_MASK 0xFFFF /* FRF_COEFF_6R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_2_SHIFT 0 /* FRF_COEFF_6R_2 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_2_WIDTH 16 /* FRF_COEFF_6R_2 - [15:0] */ + +/* + * R1764 (0x1432) - FRF_Coefficient_6R_3 + */ +#define CLEARWATER_FRF_COEFF_6R_3_MASK 0xFFFF /* FRF_COEFF_6R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_3_SHIFT 0 /* FRF_COEFF_6R_3 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_3_WIDTH 16 /* FRF_COEFF_6R_3 - [15:0] */ + +/* + * R1765 (0x1433) - FRF_Coefficient_6R_4 + */ +#define CLEARWATER_FRF_COEFF_6R_4_MASK 0xFFFF /* FRF_COEFF_6R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_4_SHIFT 0 /* FRF_COEFF_6R_4 - [15:0] */ +#define CLEARWATER_FRF_COEFF_6R_4_WIDTH 16 /* FRF_COEFF_6R_4 - [15:0] */ + +/* + * R1675 (0x1480) - DFC1_CTRL + */ +#define MOON_DFC1_RATE 0x003C /* DFC1_RATE - [5:2] */ +#define MOON_DFC1_RATE_MASK 0x003C /* DFC1_RATE - [5:2] */ +#define MOON_DFC1_RATE_SHIFT 2 /* DFC1_RATE - [5:2] */ +#define MOON_DFC1_RATE_WIDTH 4 /* DFC1_RATE - [5:2] */ +#define MOON_DFC1_DITH_ENA 0x0002 /* DFC1_DITH_ENA */ +#define MOON_DFC1_DITH_ENA_MASK 0x0002 /* DFC1_DITH_ENA */ +#define MOON_DFC1_DITH_ENA_SHIFT 1 /* DFC1_DITH_ENA */ +#define MOON_DFC1_DITH_ENA_WIDTH 1 /* DFC1_DITH_ENA */ +#define MOON_DFC1_ENA 0x0001 /* DFC1_ENA */ +#define MOON_DFC1_ENA_MASK 0x0001 /* DFC1_ENA */ +#define MOON_DFC1_ENA_SHIFT 0 /* DFC1_ENA */ +#define MOON_DFC1_ENA_WIDTH 1 /* DFC1_ENA */ + +/* + * R1677 (0x1482) - DFC1_RX + */ +#define MOON_DFC1_RX_DATA_WIDTH 0x1F00 /* DFC1_RX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_RX_DATA_WIDTH_MASK 0x1F00 /* DFC1_RX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_RX_DATA_WIDTH_SHIFT 8 /* DFC1_RX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_RX_DATA_WIDTH_WIDTH 5 /* DFC1_RX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_RX_DATA_TYPE 0x0007 /* DFC1_RX_DATA_TYPE - [2:0] */ +#define MOON_DFC1_RX_DATA_TYPE_MASK 0x0007 /* DFC1_RX_DATA_TYPE - [2:0] */ +#define MOON_DFC1_RX_DATA_TYPE_SHIFT 0 /* DFC1_RX_DATA_TYPE - [2:0] */ +#define MOON_DFC1_RX_DATA_TYPE_WIDTH 3 /* DFC1_RX_DATA_TYPE - [2:0] */ + +/* + * R1679 (0x1484) - DFC1_TX + */ +#define MOON_DFC1_TX_DATA_WIDTH 0x1F00 /* DFC1_TX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_TX_DATA_WIDTH_MASK 0x1F00 /* DFC1_TX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_TX_DATA_WIDTH_SHIFT 8 /* DFC1_TX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_TX_DATA_WIDTH_WIDTH 5 /* DFC1_TX_DATA_WIDTH - [12:8] */ +#define MOON_DFC1_TX_DATA_TYPE 0x0007 /* DFC1_TX_DATA_TYPE - [2:0] */ +#define MOON_DFC1_TX_DATA_TYPE_MASK 0x0007 /* DFC1_TX_DATA_TYPE - [2:0] */ +#define MOON_DFC1_TX_DATA_TYPE_SHIFT 0 /* DFC1_TX_DATA_TYPE - [2:0] */ +#define MOON_DFC1_TX_DATA_TYPE_WIDTH 3 /* DFC1_TX_DATA_TYPE - [2:0] */ + +/* + * R6144 (0x1800) - IRQ1 Status 1 + */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT1 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_CTRLIF_ERR_EINT1 0x1000 /* CTRLIF_ERR_EINT1 */ +#define CLEARWATER_CTRLIF_ERR_EINT1_MASK 0x1000 /* CTRLIF_ERR_EINT1 */ +#define CLEARWATER_CTRLIF_ERR_EINT1_SHIFT 12 /* CTRLIF_ERR_EINT1 */ +#define CLEARWATER_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT1 0x0200 /* IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT1_MASK 0x0200 /* IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT1_SHIFT 9 /* IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT1_WIDTH 1 /* IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_CLOCK_DETECT_EINT1 0x0100 /* CLOCK_DETECT_EINT1 */ +#define CLEARWATER_CLOCK_DETECT_EINT1_MASK 0x0100 /* CLOCK_DETECT_EINT1 */ +#define CLEARWATER_CLOCK_DETECT_EINT1_SHIFT 8 /* CLOCK_DETECT_EINT1 */ +#define CLEARWATER_CLOCK_DETECT_EINT1_WIDTH 1 /* CLOCK_DETECT_EINT1 */ +#define CLEARWATER_BOOT_DONE_EINT1 0x0080 /* BOOT_DONE_EINT1 */ +#define CLEARWATER_BOOT_DONE_EINT1_MASK 0x0080 /* BOOT_DONE_EINT1 */ +#define CLEARWATER_BOOT_DONE_EINT1_SHIFT 7 /* BOOT_DONE_EINT1 */ +#define CLEARWATER_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */ + +/* + * R6145 (0x1801) - IRQ1 Status 2 + */ +#define MOON_FLLAO_LOCK_EINT1 0x0800 /* FLLAO_LOCK_EINT1 */ +#define MOON_FLLAO_LOCK_EINT1_MASK 0x0800 /* FLLAO_LOCK_EINT1 */ +#define MOON_FLLAO_LOCK_EINT1_SHIFT 11 /* FLLAO_LOCK_EINT1 */ +#define MOON_FLLAO_LOCK_EINT1_WIDTH 1 /* FLLAO_LOCK_EINT1 */ +#define CLEARWATER_FLL3_LOCK_EINT1 0x0400 /* FLL3_LOCK_EINT1 */ +#define CLEARWATER_FLL3_LOCK_EINT1_MASK 0x0400 /* FLL3_LOCK_EINT1 */ +#define CLEARWATER_FLL3_LOCK_EINT1_SHIFT 10 /* FLL3_LOCK_EINT1 */ +#define CLEARWATER_FLL3_LOCK_EINT1_WIDTH 1 /* FLL3_LOCK_EINT1 */ +#define CLEARWATER_FLL2_LOCK_EINT1 0x0200 /* FLL2_LOCK_EINT1 */ +#define CLEARWATER_FLL2_LOCK_EINT1_MASK 0x0200 /* FLL2_LOCK_EINT1 */ +#define CLEARWATER_FLL2_LOCK_EINT1_SHIFT 9 /* FLL2_LOCK_EINT1 */ +#define CLEARWATER_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */ +#define CLEARWATER_FLL1_LOCK_EINT1 0x0100 /* FLL1_LOCK_EINT1 */ +#define CLEARWATER_FLL1_LOCK_EINT1_MASK 0x0100 /* FLL1_LOCK_EINT1 */ +#define CLEARWATER_FLL1_LOCK_EINT1_SHIFT 8 /* FLL1_LOCK_EINT1 */ +#define CLEARWATER_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */ + +/* + * R6149 (0x1805) - IRQ1 Status 6 + */ +#define CLEARWATER_MICDET_EINT1 0x0100 /* MICDET_EINT1 */ +#define CLEARWATER_MICDET_EINT1_MASK 0x0100 /* MICDET_EINT1 */ +#define CLEARWATER_MICDET_EINT1_SHIFT 8 /* MICDET_EINT1 */ +#define CLEARWATER_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */ +#define MOON_MICDET2_EINT1 0x0200 /* MICDET2_EINT1 */ +#define MOON_MICDET2_EINT1_MASK 0x0200 /* MICDET2_EINT1 */ +#define MOON_MICDET2_EINT1_SHIFT 9 /* MICDET2_EINT1 */ +#define MOON_MICDET2_EINT1_WIDTH 1 /* MICDET2_EINT1 */ +#define CLEARWATER_HPDET_EINT1 0x0001 /* HPDET_EINT1 */ +#define CLEARWATER_HPDET_EINT1_MASK 0x0001 /* HPDET_EINT1 */ +#define CLEARWATER_HPDET_EINT1_SHIFT 0 /* HPDET_EINT1 */ +#define CLEARWATER_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */ + +/* + * R6150 (0x1806) - IRQ1 Status 7 + */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT1 0x0020 /* MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT1_MASK 0x0020 /* MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT1_SHIFT 5 /* MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT1_WIDTH 1 /* MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT1 0x0010 /* MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT1_MASK 0x0010 /* MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT1_SHIFT 4 /* MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT1_WIDTH 1 /* MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_JD2_FALL_EINT1 0x0008 /* JD2_FALL_EINT1 */ +#define CLEARWATER_JD2_FALL_EINT1_MASK 0x0008 /* JD2_FALL_EINT1 */ +#define CLEARWATER_JD2_FALL_EINT1_SHIFT 3 /* JD2_FALL_EINT1 */ +#define CLEARWATER_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */ +#define CLEARWATER_JD2_RISE_EINT1 0x0004 /* JD2_RISE_EINT1 */ +#define CLEARWATER_JD2_RISE_EINT1_MASK 0x0004 /* JD2_RISE_EINT1 */ +#define CLEARWATER_JD2_RISE_EINT1_SHIFT 2 /* JD2_RISE_EINT1 */ +#define CLEARWATER_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */ +#define CLEARWATER_JD1_FALL_EINT1 0x0002 /* JD1_FALL_EINT1 */ +#define CLEARWATER_JD1_FALL_EINT1_MASK 0x0002 /* JD1_FALL_EINT1 */ +#define CLEARWATER_JD1_FALL_EINT1_SHIFT 1 /* JD1_FALL_EINT1 */ +#define CLEARWATER_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */ +#define CLEARWATER_JD1_RISE_EINT1 0x0001 /* JD1_RISE_EINT1 */ +#define CLEARWATER_JD1_RISE_EINT1_MASK 0x0001 /* JD1_RISE_EINT1 */ +#define CLEARWATER_JD1_RISE_EINT1_SHIFT 0 /* JD1_RISE_EINT1 */ +#define CLEARWATER_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */ + +/* + * R6152 (0x1808) - IRQ1 Status 9 + */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT1 0x0800 /* ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT1_MASK 0x0800 /* ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT1_SHIFT 11 /* ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT1_WIDTH 1 /* ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT1 0x0400 /* ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT1_MASK 0x0400 /* ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT1_SHIFT 10 /* ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT1_WIDTH 1 /* ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT1 0x0200 /* ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT1_MASK 0x0200 /* ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT1_SHIFT 9 /* ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT1_WIDTH 1 /* ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT1 0x0100 /* ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT1_MASK 0x0100 /* ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT1_SHIFT 8 /* ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT1_WIDTH 1 /* ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_DRC2_SIG_DET_EINT1 0x0002 /* DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_DRC2_SIG_DET_EINT1_MASK 0x0002 /* DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_DRC2_SIG_DET_EINT1_SHIFT 1 /* DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_DRC1_SIG_DET_EINT1 0x0001 /* DRC1_SIG_DET_EINT1 */ +#define CLEARWATER_DRC1_SIG_DET_EINT1_MASK 0x0001 /* DRC1_SIG_DET_EINT1 */ +#define CLEARWATER_DRC1_SIG_DET_EINT1_SHIFT 0 /* DRC1_SIG_DET_EINT1 */ +#define CLEARWATER_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */ + +/* + * R6154 (0x180A) - IRQ1 Status 11 + */ +#define CLEARWATER_DSP_IRQ16_EINT1 0x8000 /* DSP_IRQ16_EINT1 */ +#define CLEARWATER_DSP_IRQ16_EINT1_MASK 0x8000 /* DSP_IRQ16_EINT1 */ +#define CLEARWATER_DSP_IRQ16_EINT1_SHIFT 15 /* DSP_IRQ16_EINT1 */ +#define CLEARWATER_DSP_IRQ16_EINT1_WIDTH 1 /* DSP_IRQ16_EINT1 */ +#define CLEARWATER_DSP_IRQ15_EINT1 0x4000 /* DSP_IRQ15_EINT1 */ +#define CLEARWATER_DSP_IRQ15_EINT1_MASK 0x4000 /* DSP_IRQ15_EINT1 */ +#define CLEARWATER_DSP_IRQ15_EINT1_SHIFT 14 /* DSP_IRQ15_EINT1 */ +#define CLEARWATER_DSP_IRQ15_EINT1_WIDTH 1 /* DSP_IRQ15_EINT1 */ +#define CLEARWATER_DSP_IRQ14_EINT1 0x2000 /* DSP_IRQ14_EINT1 */ +#define CLEARWATER_DSP_IRQ14_EINT1_MASK 0x2000 /* DSP_IRQ14_EINT1 */ +#define CLEARWATER_DSP_IRQ14_EINT1_SHIFT 13 /* DSP_IRQ14_EINT1 */ +#define CLEARWATER_DSP_IRQ14_EINT1_WIDTH 1 /* DSP_IRQ14_EINT1 */ +#define CLEARWATER_DSP_IRQ13_EINT1 0x1000 /* DSP_IRQ13_EINT1 */ +#define CLEARWATER_DSP_IRQ13_EINT1_MASK 0x1000 /* DSP_IRQ13_EINT1 */ +#define CLEARWATER_DSP_IRQ13_EINT1_SHIFT 12 /* DSP_IRQ13_EINT1 */ +#define CLEARWATER_DSP_IRQ13_EINT1_WIDTH 1 /* DSP_IRQ13_EINT1 */ +#define CLEARWATER_DSP_IRQ12_EINT1 0x0800 /* DSP_IRQ12_EINT1 */ +#define CLEARWATER_DSP_IRQ12_EINT1_MASK 0x0800 /* DSP_IRQ12_EINT1 */ +#define CLEARWATER_DSP_IRQ12_EINT1_SHIFT 11 /* DSP_IRQ12_EINT1 */ +#define CLEARWATER_DSP_IRQ12_EINT1_WIDTH 1 /* DSP_IRQ12_EINT1 */ +#define CLEARWATER_DSP_IRQ11_EINT1 0x0400 /* DSP_IRQ11_EINT1 */ +#define CLEARWATER_DSP_IRQ11_EINT1_MASK 0x0400 /* DSP_IRQ11_EINT1 */ +#define CLEARWATER_DSP_IRQ11_EINT1_SHIFT 10 /* DSP_IRQ11_EINT1 */ +#define CLEARWATER_DSP_IRQ11_EINT1_WIDTH 1 /* DSP_IRQ11_EINT1 */ +#define CLEARWATER_DSP_IRQ10_EINT1 0x0200 /* DSP_IRQ10_EINT1 */ +#define CLEARWATER_DSP_IRQ10_EINT1_MASK 0x0200 /* DSP_IRQ10_EINT1 */ +#define CLEARWATER_DSP_IRQ10_EINT1_SHIFT 9 /* DSP_IRQ10_EINT1 */ +#define CLEARWATER_DSP_IRQ10_EINT1_WIDTH 1 /* DSP_IRQ10_EINT1 */ +#define CLEARWATER_DSP_IRQ9_EINT1 0x0100 /* DSP_IRQ9_EINT1 */ +#define CLEARWATER_DSP_IRQ9_EINT1_MASK 0x0100 /* DSP_IRQ9_EINT1 */ +#define CLEARWATER_DSP_IRQ9_EINT1_SHIFT 8 /* DSP_IRQ9_EINT1 */ +#define CLEARWATER_DSP_IRQ9_EINT1_WIDTH 1 /* DSP_IRQ9_EINT1 */ +#define CLEARWATER_DSP_IRQ8_EINT1 0x0080 /* DSP_IRQ8_EINT1 */ +#define CLEARWATER_DSP_IRQ8_EINT1_MASK 0x0080 /* DSP_IRQ8_EINT1 */ +#define CLEARWATER_DSP_IRQ8_EINT1_SHIFT 7 /* DSP_IRQ8_EINT1 */ +#define CLEARWATER_DSP_IRQ8_EINT1_WIDTH 1 /* DSP_IRQ8_EINT1 */ +#define CLEARWATER_DSP_IRQ7_EINT1 0x0040 /* DSP_IRQ7_EINT1 */ +#define CLEARWATER_DSP_IRQ7_EINT1_MASK 0x0040 /* DSP_IRQ7_EINT1 */ +#define CLEARWATER_DSP_IRQ7_EINT1_SHIFT 6 /* DSP_IRQ7_EINT1 */ +#define CLEARWATER_DSP_IRQ7_EINT1_WIDTH 1 /* DSP_IRQ7_EINT1 */ +#define CLEARWATER_DSP_IRQ6_EINT1 0x0020 /* DSP_IRQ6_EINT1 */ +#define CLEARWATER_DSP_IRQ6_EINT1_MASK 0x0020 /* DSP_IRQ6_EINT1 */ +#define CLEARWATER_DSP_IRQ6_EINT1_SHIFT 5 /* DSP_IRQ6_EINT1 */ +#define CLEARWATER_DSP_IRQ6_EINT1_WIDTH 1 /* DSP_IRQ6_EINT1 */ +#define CLEARWATER_DSP_IRQ5_EINT1 0x0010 /* DSP_IRQ5_EINT1 */ +#define CLEARWATER_DSP_IRQ5_EINT1_MASK 0x0010 /* DSP_IRQ5_EINT1 */ +#define CLEARWATER_DSP_IRQ5_EINT1_SHIFT 4 /* DSP_IRQ5_EINT1 */ +#define CLEARWATER_DSP_IRQ5_EINT1_WIDTH 1 /* DSP_IRQ5_EINT1 */ +#define CLEARWATER_DSP_IRQ4_EINT1 0x0008 /* DSP_IRQ4_EINT1 */ +#define CLEARWATER_DSP_IRQ4_EINT1_MASK 0x0008 /* DSP_IRQ4_EINT1 */ +#define CLEARWATER_DSP_IRQ4_EINT1_SHIFT 3 /* DSP_IRQ4_EINT1 */ +#define CLEARWATER_DSP_IRQ4_EINT1_WIDTH 1 /* DSP_IRQ4_EINT1 */ +#define CLEARWATER_DSP_IRQ3_EINT1 0x0004 /* DSP_IRQ3_EINT1 */ +#define CLEARWATER_DSP_IRQ3_EINT1_MASK 0x0004 /* DSP_IRQ3_EINT1 */ +#define CLEARWATER_DSP_IRQ3_EINT1_SHIFT 2 /* DSP_IRQ3_EINT1 */ +#define CLEARWATER_DSP_IRQ3_EINT1_WIDTH 1 /* DSP_IRQ3_EINT1 */ +#define CLEARWATER_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */ +#define CLEARWATER_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */ +#define CLEARWATER_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */ +#define CLEARWATER_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */ +#define CLEARWATER_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */ +#define CLEARWATER_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */ +#define CLEARWATER_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */ +#define CLEARWATER_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */ + +/* + * R6155 (0x180B) - IRQ1 Status 12 + */ +#define CLEARWATER_SPKOUTR_SC_EINT1 0x0080 /* SPKOUTR_SC_EINT1 */ +#define CLEARWATER_SPKOUTR_SC_EINT1_MASK 0x0080 /* SPKOUTR_SC_EINT1 */ +#define CLEARWATER_SPKOUTR_SC_EINT1_SHIFT 7 /* SPKOUTR_SC_EINT1 */ +#define CLEARWATER_SPKOUTR_SC_EINT1_WIDTH 1 /* SPKOUTR_SC_EINT1 */ +#define CLEARWATER_SPKOUTL_SC_EINT1 0x0040 /* SPKOUTL_SC_EINT1 */ +#define CLEARWATER_SPKOUTL_SC_EINT1_MASK 0x0040 /* SPKOUTL_SC_EINT1 */ +#define CLEARWATER_SPKOUTL_SC_EINT1_SHIFT 6 /* SPKOUTL_SC_EINT1 */ +#define CLEARWATER_SPKOUTL_SC_EINT1_WIDTH 1 /* SPKOUTL_SC_EINT1 */ +#define CLEARWATER_HP3R_SC_EINT1 0x0020 /* HP3R_SC_EINT1 */ +#define CLEARWATER_HP3R_SC_EINT1_MASK 0x0020 /* HP3R_SC_EINT1 */ +#define CLEARWATER_HP3R_SC_EINT1_SHIFT 5 /* HP3R_SC_EINT1 */ +#define CLEARWATER_HP3R_SC_EINT1_WIDTH 1 /* HP3R_SC_EINT1 */ +#define CLEARWATER_HP3L_SC_EINT1 0x0010 /* HP3L_SC_EINT1 */ +#define CLEARWATER_HP3L_SC_EINT1_MASK 0x0010 /* HP3L_SC_EINT1 */ +#define CLEARWATER_HP3L_SC_EINT1_SHIFT 4 /* HP3L_SC_EINT1 */ +#define CLEARWATER_HP3L_SC_EINT1_WIDTH 1 /* HP3L_SC_EINT1 */ +#define CLEARWATER_HP2R_SC_EINT1 0x0008 /* HP2R_SC_EINT1 */ +#define CLEARWATER_HP2R_SC_EINT1_MASK 0x0008 /* HP2R_SC_EINT1 */ +#define CLEARWATER_HP2R_SC_EINT1_SHIFT 3 /* HP2R_SC_EINT1 */ +#define CLEARWATER_HP2R_SC_EINT1_WIDTH 1 /* HP2R_SC_EINT1 */ +#define CLEARWATER_HP2L_SC_EINT1 0x0004 /* HP2L_SC_EINT1 */ +#define CLEARWATER_HP2L_SC_EINT1_MASK 0x0004 /* HP2L_SC_EINT1 */ +#define CLEARWATER_HP2L_SC_EINT1_SHIFT 2 /* HP2L_SC_EINT1 */ +#define CLEARWATER_HP2L_SC_EINT1_WIDTH 1 /* HP2L_SC_EINT1 */ +#define CLEARWATER_HP1R_SC_EINT1 0x0002 /* HP1R_SC_EINT1 */ +#define CLEARWATER_HP1R_SC_EINT1_MASK 0x0002 /* HP1R_SC_EINT1 */ +#define CLEARWATER_HP1R_SC_EINT1_SHIFT 1 /* HP1R_SC_EINT1 */ +#define CLEARWATER_HP1R_SC_EINT1_WIDTH 1 /* HP1R_SC_EINT1 */ +#define CLEARWATER_HP1L_SC_EINT1 0x0001 /* HP1L_SC_EINT1 */ +#define CLEARWATER_HP1L_SC_EINT1_MASK 0x0001 /* HP1L_SC_EINT1 */ +#define CLEARWATER_HP1L_SC_EINT1_SHIFT 0 /* HP1L_SC_EINT1 */ +#define CLEARWATER_HP1L_SC_EINT1_WIDTH 1 /* HP1L_SC_EINT1 */ + +/* + * R6156 (0x180C) - IRQ1 Status 13 + */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT1 0x0080 /* SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT1_MASK 0x0080 /* SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT1_SHIFT 7 /* SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT1_WIDTH 1 /* SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT1 0x0040 /* SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT1_MASK 0x0040 /* SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT1_SHIFT 6 /* SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT1_WIDTH 1 /* SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT1 0x0020 /* HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT1_MASK 0x0020 /* HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT1_SHIFT 5 /* HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT1_WIDTH 1 /* HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT1 0x0010 /* HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT1_MASK 0x0010 /* HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT1_SHIFT 4 /* HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT1_WIDTH 1 /* HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT1 0x0008 /* HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT1_MASK 0x0008 /* HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT1_SHIFT 3 /* HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT1_WIDTH 1 /* HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT1 0x0004 /* HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT1_MASK 0x0004 /* HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT1_SHIFT 2 /* HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT1_WIDTH 1 /* HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT1 0x0002 /* HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT1_MASK 0x0002 /* HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT1_SHIFT 1 /* HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT1_WIDTH 1 /* HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT1 0x0001 /* HP1L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT1_MASK 0x0001 /* HP1L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT1_SHIFT 0 /* HP1L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT1_WIDTH 1 /* HP1L_ENABLE_DONE_EINT1 */ + +/* + * R6157 (0x180D) - IRQ1 Status 14 + */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT1 0x0080 /* SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT1_MASK 0x0080 /* SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT1_SHIFT 7 /* SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT1_WIDTH 1 /* SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT1 0x0040 /* SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT1_MASK 0x0040 /* SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT1_SHIFT 6 /* SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT1_WIDTH 1 /* SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT1 0x0020 /* HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT1_MASK 0x0020 /* HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT1_SHIFT 5 /* HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT1_WIDTH 1 /* HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT1 0x0010 /* HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT1_MASK 0x0010 /* HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT1_SHIFT 4 /* HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT1_WIDTH 1 /* HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT1 0x0008 /* HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT1_MASK 0x0008 /* HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT1_SHIFT 3 /* HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT1_WIDTH 1 /* HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT1 0x0004 /* HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT1_MASK 0x0004 /* HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT1_SHIFT 2 /* HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT1_WIDTH 1 /* HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT1 0x0002 /* HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT1_MASK 0x0002 /* HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT1_SHIFT 1 /* HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT1_WIDTH 1 /* HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT1 0x0001 /* HP1L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT1_MASK 0x0001 /* HP1L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT1_SHIFT 0 /* HP1L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT1_WIDTH 1 /* HP1L_DISABLE_DONE_EINT1 */ + +/* + * R6158 (0x180E) - IRQ1 Status 15 + */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT1 0x0004 /* SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT1_MASK 0x0004 /* SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT1_SHIFT 2 /* SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_EINT1 0x0002 /* SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_EINT1_MASK 0x0002 /* SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_EINT1_SHIFT 1 /* SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_SPK_OVERHEAT_EINT1_WIDTH 1 /* SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT1 0x0001 /* SPK_SHUTDOWN_EINT1 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT1_MASK 0x0001 /* SPK_SHUTDOWN_EINT1 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT1_SHIFT 0 /* SPK_SHUTDOWN_EINT1 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */ + +/* + * R6160 (0x1810) - IRQ1 Status 17 + */ +#define CLEARWATER_GP1_EINT1 0x0001 /* GP1_EINT1 */ +#define CLEARWATER_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */ +#define CLEARWATER_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */ +#define CLEARWATER_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */ +#define CLEARWATER_GP2_EINT1 0x0002 /* GP2_EINT1 */ +#define CLEARWATER_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */ +#define CLEARWATER_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */ +#define CLEARWATER_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */ +#define CLEARWATER_GP3_EINT1 0x0004 /* GP3_EINT1 */ +#define CLEARWATER_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */ +#define CLEARWATER_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */ +#define CLEARWATER_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */ +#define CLEARWATER_GP4_EINT1 0x0008 /* GP4_EINT1 */ +#define CLEARWATER_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */ +#define CLEARWATER_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */ +#define CLEARWATER_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */ +#define CLEARWATER_GP5_EINT1 0x0010 /* GP5_EINT1 */ +#define CLEARWATER_GP5_EINT1_MASK 0x0010 /* GP5_EINT1 */ +#define CLEARWATER_GP5_EINT1_SHIFT 4 /* GP5_EINT1 */ +#define CLEARWATER_GP5_EINT1_WIDTH 1 /* GP5_EINT1 */ +#define CLEARWATER_GP6_EINT1 0x0020 /* GP6_EINT1 */ +#define CLEARWATER_GP6_EINT1_MASK 0x0020 /* GP6_EINT1 */ +#define CLEARWATER_GP6_EINT1_SHIFT 5 /* GP6_EINT1 */ +#define CLEARWATER_GP6_EINT1_WIDTH 1 /* GP6_EINT1 */ +#define CLEARWATER_GP7_EINT1 0x0040 /* GP7_EINT1 */ +#define CLEARWATER_GP7_EINT1_MASK 0x0040 /* GP7_EINT1 */ +#define CLEARWATER_GP7_EINT1_SHIFT 6 /* GP7_EINT1 */ +#define CLEARWATER_GP7_EINT1_WIDTH 1 /* GP7_EINT1 */ +#define CLEARWATER_GP8_EINT1 0x0080 /* GP8_EINT1 */ +#define CLEARWATER_GP8_EINT1_MASK 0x0080 /* GP8_EINT1 */ +#define CLEARWATER_GP8_EINT1_SHIFT 7 /* GP8_EINT1 */ +#define CLEARWATER_GP8_EINT1_WIDTH 1 /* GP8_EINT1 */ + +/* + * R6176 (0x1820) - IRQ1 Status 33 + */ +#define MOON_ADSP_ERROR_STATUS_DSP7 0x0040 /* IRQ_DSP7_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP7_MASK 0x0040 /* IRQ_DSP7_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP7_SHIFT 6 /* IRQ_DSP7_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP7_WIDTH 1 /* IRQ_DSP7_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP6 0x0020 /* IRQ_DSP6_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP6_MASK 0x0020 /* IRQ_DSP6_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP6_SHIFT 5 /* IRQ_DSP6_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP6_WIDTH 1 /* IRQ_DSP6_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP5 0x0010 /* IRQ_DSP5_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP5_MASK 0x0010 /* IRQ_DSP5_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP5_SHIFT 4 /* IRQ_DSP5_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP5_WIDTH 1 /* IRQ_DSP5_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP4 0x0008 /* IRQ_DSP4_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP4_MASK 0x0008 /* IRQ_DSP4_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP4_SHIFT 3 /* IRQ_DSP4_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP4_WIDTH 1 /* IRQ_DSP4_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP3 0x0004 /* IRQ_DSP3_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP3_MASK 0x0004 /* IRQ_DSP3_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP3_SHIFT 2 /* IRQ_DSP3_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP3_WIDTH 1 /* IRQ_DSP3_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP2 0x0002 /* IRQ_DSP2_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP2_MASK 0x0002 /* IRQ_DSP2_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP2_SHIFT 1 /* IRQ_DSP2_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP2_WIDTH 1 /* IRQ_DSP2_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP1 0x0001 /* IRQ_DSP1_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP1_MASK 0x0001 /* IRQ_DSP1_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP1_SHIFT 0 /* IRQ_DSP1_BUS_ERR_EINT1 */ +#define MOON_ADSP_ERROR_STATUS_DSP1_WIDTH 1 /* IRQ_DSP1_BUS_ERR_EINT1 */ + +/* + * R6208 (0x1840) - IRQ1 Mask 1 + */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT1 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT1 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT1 0x1000 /* IM_CTRLIF_ERR_EINT1 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT1_MASK 0x1000 /* IM_CTRLIF_ERR_EINT1 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT1_SHIFT 12 /* IM_CTRLIF_ERR_EINT1 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT1 0x0200 /* IM_IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT1_MASK 0x0200 /* IM_IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT1_SHIFT 9 /* IM_IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT1_WIDTH 1 /* IM_IRQ_NO_CLOCK_EINT1 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT1 0x0100 /* IM_CLOCK_DETECT_EINT1 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT1_MASK 0x0100 /* IM_CLOCK_DETECT_EINT1 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT1_SHIFT 8 /* IM_CLOCK_DETECT_EINT1 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT1_WIDTH 1 /* IM_CLOCK_DETECT_EINT1 */ +#define CLEARWATER_IM_BOOT_DONE_EINT1 0x0080 /* IM_BOOT_DONE_EINT1 */ +#define CLEARWATER_IM_BOOT_DONE_EINT1_MASK 0x0080 /* IM_BOOT_DONE_EINT1 */ +#define CLEARWATER_IM_BOOT_DONE_EINT1_SHIFT 7 /* IM_BOOT_DONE_EINT1 */ +#define CLEARWATER_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */ + +/* + * R6209 (0x1841) - IRQ1 Mask 2 + */ +#define CLEARWATER_IM_FLL3_LOCK_EINT1 0x0400 /* IM_FLL3_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL3_LOCK_EINT1_MASK 0x0400 /* IM_FLL3_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL3_LOCK_EINT1_SHIFT 10 /* IM_FLL3_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL3_LOCK_EINT1_WIDTH 1 /* IM_FLL3_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT1 0x0200 /* IM_FLL2_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT1_MASK 0x0200 /* IM_FLL2_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT1_SHIFT 9 /* IM_FLL2_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT1 0x0100 /* IM_FLL1_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT1_MASK 0x0100 /* IM_FLL1_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT1_SHIFT 8 /* IM_FLL1_LOCK_EINT1 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */ + +/* + * R6213 (0x1845) - IRQ1 Mask 6 + */ +#define CLEARWATER_IM_MICDET_EINT1 0x0100 /* IM_MICDET_EINT1 */ +#define CLEARWATER_IM_MICDET_EINT1_MASK 0x0100 /* IM_MICDET_EINT1 */ +#define CLEARWATER_IM_MICDET_EINT1_SHIFT 8 /* IM_MICDET_EINT1 */ +#define CLEARWATER_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */ +#define CLEARWATER_IM_HPDET_EINT1 0x0001 /* IM_HPDET_EINT1 */ +#define CLEARWATER_IM_HPDET_EINT1_MASK 0x0001 /* IM_HPDET_EINT1 */ +#define CLEARWATER_IM_HPDET_EINT1_SHIFT 0 /* IM_HPDET_EINT1 */ +#define CLEARWATER_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */ + +/* + * R6214 (0x1846) - IRQ1 Mask 7 + */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT1 0x0020 /* IM_MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT1_MASK 0x0020 /* IM_MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT1_SHIFT 5 /* IM_MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT1_WIDTH 1 /* IM_MICD_CLAMP_FALL_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT1 0x0010 /* IM_MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT1_MASK 0x0010 /* IM_MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT1_SHIFT 4 /* IM_MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT1_WIDTH 1 /* IM_MICD_CLAMP_RISE_EINT1 */ +#define CLEARWATER_IM_JD2_FALL_EINT1 0x0008 /* IM_JD2_FALL_EINT1 */ +#define CLEARWATER_IM_JD2_FALL_EINT1_MASK 0x0008 /* IM_JD2_FALL_EINT1 */ +#define CLEARWATER_IM_JD2_FALL_EINT1_SHIFT 3 /* IM_JD2_FALL_EINT1 */ +#define CLEARWATER_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */ +#define CLEARWATER_IM_JD2_RISE_EINT1 0x0004 /* IM_JD2_RISE_EINT1 */ +#define CLEARWATER_IM_JD2_RISE_EINT1_MASK 0x0004 /* IM_JD2_RISE_EINT1 */ +#define CLEARWATER_IM_JD2_RISE_EINT1_SHIFT 2 /* IM_JD2_RISE_EINT1 */ +#define CLEARWATER_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */ +#define CLEARWATER_IM_JD1_FALL_EINT1 0x0002 /* IM_JD1_FALL_EINT1 */ +#define CLEARWATER_IM_JD1_FALL_EINT1_MASK 0x0002 /* IM_JD1_FALL_EINT1 */ +#define CLEARWATER_IM_JD1_FALL_EINT1_SHIFT 1 /* IM_JD1_FALL_EINT1 */ +#define CLEARWATER_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */ +#define CLEARWATER_IM_JD1_RISE_EINT1 0x0001 /* IM_JD1_RISE_EINT1 */ +#define CLEARWATER_IM_JD1_RISE_EINT1_MASK 0x0001 /* IM_JD1_RISE_EINT1 */ +#define CLEARWATER_IM_JD1_RISE_EINT1_SHIFT 0 /* IM_JD1_RISE_EINT1 */ +#define CLEARWATER_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */ + +/* + * R6216 (0x1848) - IRQ1 Mask 9 + */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT1 0x0800 /* IM_ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT1_MASK 0x0800 /* IM_ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT1_SHIFT 11 /* IM_ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT1 0x0400 /* IM_ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT1_MASK 0x0400 /* IM_ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT1_SHIFT 10 /* IM_ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT1 0x0200 /* IM_ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT1_MASK 0x0200 /* IM_ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT1_SHIFT 9 /* IM_ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_IN2_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT1 0x0100 /* IM_ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT1_MASK 0x0100 /* IM_ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT1_SHIFT 8 /* IM_ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_IN1_LOCK_EINT1 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT1 0x0002 /* IM_DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT1_MASK 0x0002 /* IM_DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT1_SHIFT 1 /* IM_DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT1 0x0001 /* IM_DRC1_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT1_MASK 0x0001 /* IM_DRC1_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT1_SHIFT 0 /* IM_DRC1_SIG_DET_EINT1 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */ + +/* + * R6218 (0x184A) - IRQ1 Mask 11 + */ +#define CLEARWATER_IM_DSP_IRQ16_EINT1 0x8000 /* IM_DSP_IRQ16_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ16_EINT1_MASK 0x8000 /* IM_DSP_IRQ16_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ16_EINT1_SHIFT 15 /* IM_DSP_IRQ16_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ16_EINT1_WIDTH 1 /* IM_DSP_IRQ16_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT1 0x4000 /* IM_DSP_IRQ15_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT1_MASK 0x4000 /* IM_DSP_IRQ15_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT1_SHIFT 14 /* IM_DSP_IRQ15_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT1_WIDTH 1 /* IM_DSP_IRQ15_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT1 0x2000 /* IM_DSP_IRQ14_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT1_MASK 0x2000 /* IM_DSP_IRQ14_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT1_SHIFT 13 /* IM_DSP_IRQ14_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT1_WIDTH 1 /* IM_DSP_IRQ14_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT1 0x1000 /* IM_DSP_IRQ13_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT1_MASK 0x1000 /* IM_DSP_IRQ13_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT1_SHIFT 12 /* IM_DSP_IRQ13_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT1_WIDTH 1 /* IM_DSP_IRQ13_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT1 0x0800 /* IM_DSP_IRQ12_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT1_MASK 0x0800 /* IM_DSP_IRQ12_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT1_SHIFT 11 /* IM_DSP_IRQ12_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT1_WIDTH 1 /* IM_DSP_IRQ12_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT1 0x0400 /* IM_DSP_IRQ11_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT1_MASK 0x0400 /* IM_DSP_IRQ11_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT1_SHIFT 10 /* IM_DSP_IRQ11_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT1_WIDTH 1 /* IM_DSP_IRQ11_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT1 0x0200 /* IM_DSP_IRQ10_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT1_MASK 0x0200 /* IM_DSP_IRQ10_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT1_SHIFT 9 /* IM_DSP_IRQ10_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT1_WIDTH 1 /* IM_DSP_IRQ10_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT1 0x0100 /* IM_DSP_IRQ9_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT1_MASK 0x0100 /* IM_DSP_IRQ9_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT1_SHIFT 8 /* IM_DSP_IRQ9_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT1_WIDTH 1 /* IM_DSP_IRQ9_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT1 0x0080 /* IM_DSP_IRQ8_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT1_MASK 0x0080 /* IM_DSP_IRQ8_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT1_SHIFT 7 /* IM_DSP_IRQ8_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT1_WIDTH 1 /* IM_DSP_IRQ8_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT1 0x0040 /* IM_DSP_IRQ7_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT1_MASK 0x0040 /* IM_DSP_IRQ7_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT1_SHIFT 6 /* IM_DSP_IRQ7_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT1_WIDTH 1 /* IM_DSP_IRQ7_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT1 0x0020 /* IM_DSP_IRQ6_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT1_MASK 0x0020 /* IM_DSP_IRQ6_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT1_SHIFT 5 /* IM_DSP_IRQ6_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT1_WIDTH 1 /* IM_DSP_IRQ6_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT1 0x0010 /* IM_DSP_IRQ5_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT1_MASK 0x0010 /* IM_DSP_IRQ5_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT1_SHIFT 4 /* IM_DSP_IRQ5_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT1_WIDTH 1 /* IM_DSP_IRQ5_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT1 0x0008 /* IM_DSP_IRQ4_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT1_MASK 0x0008 /* IM_DSP_IRQ4_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT1_SHIFT 3 /* IM_DSP_IRQ4_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT1_WIDTH 1 /* IM_DSP_IRQ4_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT1 0x0004 /* IM_DSP_IRQ3_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT1_MASK 0x0004 /* IM_DSP_IRQ3_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT1_SHIFT 2 /* IM_DSP_IRQ3_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT1_WIDTH 1 /* IM_DSP_IRQ3_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */ + +/* + * R6219 (0x184B) - IRQ1 Mask 12 + */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT1 0x0080 /* IM_SPKOUTR_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT1_MASK 0x0080 /* IM_SPKOUTR_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT1_SHIFT 7 /* IM_SPKOUTR_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT1_WIDTH 1 /* IM_SPKOUTR_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT1 0x0040 /* IM_SPKOUTL_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT1_MASK 0x0040 /* IM_SPKOUTL_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT1_SHIFT 6 /* IM_SPKOUTL_SC_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT1_WIDTH 1 /* IM_SPKOUTL_SC_EINT1 */ +#define CLEARWATER_IM_HP3R_SC_EINT1 0x0020 /* IM_HP3R_SC_EINT1 */ +#define CLEARWATER_IM_HP3R_SC_EINT1_MASK 0x0020 /* IM_HP3R_SC_EINT1 */ +#define CLEARWATER_IM_HP3R_SC_EINT1_SHIFT 5 /* IM_HP3R_SC_EINT1 */ +#define CLEARWATER_IM_HP3R_SC_EINT1_WIDTH 1 /* IM_HP3R_SC_EINT1 */ +#define CLEARWATER_IM_HP3L_SC_EINT1 0x0010 /* IM_HP3L_SC_EINT1 */ +#define CLEARWATER_IM_HP3L_SC_EINT1_MASK 0x0010 /* IM_HP3L_SC_EINT1 */ +#define CLEARWATER_IM_HP3L_SC_EINT1_SHIFT 4 /* IM_HP3L_SC_EINT1 */ +#define CLEARWATER_IM_HP3L_SC_EINT1_WIDTH 1 /* IM_HP3L_SC_EINT1 */ +#define CLEARWATER_IM_HP2R_SC_EINT1 0x0008 /* IM_HP2R_SC_EINT1 */ +#define CLEARWATER_IM_HP2R_SC_EINT1_MASK 0x0008 /* IM_HP2R_SC_EINT1 */ +#define CLEARWATER_IM_HP2R_SC_EINT1_SHIFT 3 /* IM_HP2R_SC_EINT1 */ +#define CLEARWATER_IM_HP2R_SC_EINT1_WIDTH 1 /* IM_HP2R_SC_EINT1 */ +#define CLEARWATER_IM_HP2L_SC_EINT1 0x0004 /* IM_HP2L_SC_EINT1 */ +#define CLEARWATER_IM_HP2L_SC_EINT1_MASK 0x0004 /* IM_HP2L_SC_EINT1 */ +#define CLEARWATER_IM_HP2L_SC_EINT1_SHIFT 2 /* IM_HP2L_SC_EINT1 */ +#define CLEARWATER_IM_HP2L_SC_EINT1_WIDTH 1 /* IM_HP2L_SC_EINT1 */ +#define CLEARWATER_IM_HP1R_SC_EINT1 0x0002 /* IM_HP1R_SC_EINT1 */ +#define CLEARWATER_IM_HP1R_SC_EINT1_MASK 0x0002 /* IM_HP1R_SC_EINT1 */ +#define CLEARWATER_IM_HP1R_SC_EINT1_SHIFT 1 /* IM_HP1R_SC_EINT1 */ +#define CLEARWATER_IM_HP1R_SC_EINT1_WIDTH 1 /* IM_HP1R_SC_EINT1 */ +#define CLEARWATER_IM_HP1L_SC_EINT1 0x0001 /* IM_HP1L_SC_EINT1 */ +#define CLEARWATER_IM_HP1L_SC_EINT1_MASK 0x0001 /* IM_HP1L_SC_EINT1 */ +#define CLEARWATER_IM_HP1L_SC_EINT1_SHIFT 0 /* IM_HP1L_SC_EINT1 */ +#define CLEARWATER_IM_HP1L_SC_EINT1_WIDTH 1 /* IM_HP1L_SC_EINT1 */ + +/* + * R6220 (0x184C) - IRQ1 Mask 13 + */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT1 0x0080 /* IM_SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT1_MASK 0x0080 /* IM_SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT1_SHIFT 7 /* IM_SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT1_WIDTH 1 /* IM_SPKOUTR_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT1 0x0040 /* IM_SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT1_MASK 0x0040 /* IM_SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT1_SHIFT 6 /* IM_SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT1_WIDTH 1 /* IM_SPKOUTL_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT1 0x0020 /* IM_HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT1_MASK 0x0020 /* IM_HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT1_SHIFT 5 /* IM_HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT1_WIDTH 1 /* IM_HP3R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT1 0x0010 /* IM_HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT1_MASK 0x0010 /* IM_HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT1_SHIFT 4 /* IM_HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT1_WIDTH 1 /* IM_HP3L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT1 0x0008 /* IM_HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT1_MASK 0x0008 /* IM_HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT1_SHIFT 3 /* IM_HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT1_WIDTH 1 /* IM_HP2R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT1 0x0004 /* IM_HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT1_MASK 0x0004 /* IM_HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT1_SHIFT 2 /* IM_HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT1_WIDTH 1 /* IM_HP2L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT1 0x0002 /* IM_HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT1_MASK 0x0002 /* IM_HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT1_SHIFT 1 /* IM_HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT1_WIDTH 1 /* IM_HP1R_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT1 0x0001 /* IM_HP1L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT1_MASK 0x0001 /* IM_HP1L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT1_SHIFT 0 /* IM_HP1L_ENABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT1_WIDTH 1 /* IM_HP1L_ENABLE_DONE_EINT1 */ + +/* + * R6221 (0x184D) - IRQ1 Mask 14 + */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT1 0x0080 /* IM_SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT1_MASK 0x0080 /* IM_SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT1_SHIFT 7 /* IM_SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT1_WIDTH 1 /* IM_SPKOUTR_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT1 0x0040 /* IM_SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT1_MASK 0x0040 /* IM_SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT1_SHIFT 6 /* IM_SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT1_WIDTH 1 /* IM_SPKOUTL_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT1 0x0020 /* IM_HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT1_MASK 0x0020 /* IM_HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT1_SHIFT 5 /* IM_HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT1_WIDTH 1 /* IM_HP3R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT1 0x0010 /* IM_HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT1_MASK 0x0010 /* IM_HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT1_SHIFT 4 /* IM_HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT1_WIDTH 1 /* IM_HP3L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT1 0x0008 /* IM_HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT1_MASK 0x0008 /* IM_HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT1_SHIFT 3 /* IM_HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT1_WIDTH 1 /* IM_HP2R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT1 0x0004 /* IM_HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT1_MASK 0x0004 /* IM_HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT1_SHIFT 2 /* IM_HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT1_WIDTH 1 /* IM_HP2L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT1 0x0002 /* IM_HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT1_MASK 0x0002 /* IM_HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT1_SHIFT 1 /* IM_HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT1_WIDTH 1 /* IM_HP1R_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT1 0x0001 /* IM_HP1L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT1_MASK 0x0001 /* IM_HP1L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT1_SHIFT 0 /* IM_HP1L_DISABLE_DONE_EINT1 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT1_WIDTH 1 /* IM_HP1L_DISABLE_DONE_EINT1 */ + +/* + * R6222 (0x184E) - IRQ1 Mask 15 + */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT1 0x0004 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT1_MASK 0x0004 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT1_SHIFT 2 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT1 0x0002 /* IM_SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT1_MASK 0x0002 /* IM_SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT1_SHIFT 1 /* IM_SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_EINT1 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT1 0x0001 /* IM_SPK_SHUTDOWN_EINT1 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT1_MASK 0x0001 /* IM_SPK_SHUTDOWN_EINT1 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT1_SHIFT 0 /* IM_SPK_SHUTDOWN_EINT1 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */ + +/* + * R6400 (0x1900) - IRQ2 Status 1 + */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT2 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_CTRLIF_ERR_EINT2 0x1000 /* CTRLIF_ERR_EINT2 */ +#define CLEARWATER_CTRLIF_ERR_EINT2_MASK 0x1000 /* CTRLIF_ERR_EINT2 */ +#define CLEARWATER_CTRLIF_ERR_EINT2_SHIFT 12 /* CTRLIF_ERR_EINT2 */ +#define CLEARWATER_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT2 0x0200 /* IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT2_MASK 0x0200 /* IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT2_SHIFT 9 /* IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IRQ_NO_CLOCK_EINT2_WIDTH 1 /* IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_CLOCK_DETECT_EINT2 0x0100 /* CLOCK_DETECT_EINT2 */ +#define CLEARWATER_CLOCK_DETECT_EINT2_MASK 0x0100 /* CLOCK_DETECT_EINT2 */ +#define CLEARWATER_CLOCK_DETECT_EINT2_SHIFT 8 /* CLOCK_DETECT_EINT2 */ +#define CLEARWATER_CLOCK_DETECT_EINT2_WIDTH 1 /* CLOCK_DETECT_EINT2 */ +#define CLEARWATER_BOOT_DONE_EINT2 0x0080 /* BOOT_DONE_EINT2 */ +#define CLEARWATER_BOOT_DONE_EINT2_MASK 0x0080 /* BOOT_DONE_EINT2 */ +#define CLEARWATER_BOOT_DONE_EINT2_SHIFT 7 /* BOOT_DONE_EINT2 */ +#define CLEARWATER_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */ + +/* + * R6401 (0x1901) - IRQ2 Status 2 + */ +#define CLEARWATER_FLL3_LOCK_EINT2 0x0400 /* FLL3_LOCK_EINT2 */ +#define CLEARWATER_FLL3_LOCK_EINT2_MASK 0x0400 /* FLL3_LOCK_EINT2 */ +#define CLEARWATER_FLL3_LOCK_EINT2_SHIFT 10 /* FLL3_LOCK_EINT2 */ +#define CLEARWATER_FLL3_LOCK_EINT2_WIDTH 1 /* FLL3_LOCK_EINT2 */ +#define CLEARWATER_FLL2_LOCK_EINT2 0x0200 /* FLL2_LOCK_EINT2 */ +#define CLEARWATER_FLL2_LOCK_EINT2_MASK 0x0200 /* FLL2_LOCK_EINT2 */ +#define CLEARWATER_FLL2_LOCK_EINT2_SHIFT 9 /* FLL2_LOCK_EINT2 */ +#define CLEARWATER_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */ +#define CLEARWATER_FLL1_LOCK_EINT2 0x0100 /* FLL1_LOCK_EINT2 */ +#define CLEARWATER_FLL1_LOCK_EINT2_MASK 0x0100 /* FLL1_LOCK_EINT2 */ +#define CLEARWATER_FLL1_LOCK_EINT2_SHIFT 8 /* FLL1_LOCK_EINT2 */ +#define CLEARWATER_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */ + +/* + * R6405 (0x1905) - IRQ2 Status 6 + */ +#define CLEARWATER_MICDET_EINT2 0x0100 /* MICDET_EINT2 */ +#define CLEARWATER_MICDET_EINT2_MASK 0x0100 /* MICDET_EINT2 */ +#define CLEARWATER_MICDET_EINT2_SHIFT 8 /* MICDET_EINT2 */ +#define CLEARWATER_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */ +#define CLEARWATER_HPDET_EINT2 0x0001 /* HPDET_EINT2 */ +#define CLEARWATER_HPDET_EINT2_MASK 0x0001 /* HPDET_EINT2 */ +#define CLEARWATER_HPDET_EINT2_SHIFT 0 /* HPDET_EINT2 */ +#define CLEARWATER_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */ + +/* + * R6406 (0x1906) - IRQ2 Status 7 + */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT2 0x0020 /* MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT2_MASK 0x0020 /* MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT2_SHIFT 5 /* MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_MICD_CLAMP_FALL_EINT2_WIDTH 1 /* MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT2 0x0010 /* MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT2_MASK 0x0010 /* MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT2_SHIFT 4 /* MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_MICD_CLAMP_RISE_EINT2_WIDTH 1 /* MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_JD2_FALL_EINT2 0x0008 /* JD2_FALL_EINT2 */ +#define CLEARWATER_JD2_FALL_EINT2_MASK 0x0008 /* JD2_FALL_EINT2 */ +#define CLEARWATER_JD2_FALL_EINT2_SHIFT 3 /* JD2_FALL_EINT2 */ +#define CLEARWATER_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */ +#define CLEARWATER_JD2_RISE_EINT2 0x0004 /* JD2_RISE_EINT2 */ +#define CLEARWATER_JD2_RISE_EINT2_MASK 0x0004 /* JD2_RISE_EINT2 */ +#define CLEARWATER_JD2_RISE_EINT2_SHIFT 2 /* JD2_RISE_EINT2 */ +#define CLEARWATER_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */ +#define CLEARWATER_JD1_FALL_EINT2 0x0002 /* JD1_FALL_EINT2 */ +#define CLEARWATER_JD1_FALL_EINT2_MASK 0x0002 /* JD1_FALL_EINT2 */ +#define CLEARWATER_JD1_FALL_EINT2_SHIFT 1 /* JD1_FALL_EINT2 */ +#define CLEARWATER_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */ +#define CLEARWATER_JD1_RISE_EINT2 0x0001 /* JD1_RISE_EINT2 */ +#define CLEARWATER_JD1_RISE_EINT2_MASK 0x0001 /* JD1_RISE_EINT2 */ +#define CLEARWATER_JD1_RISE_EINT2_SHIFT 0 /* JD1_RISE_EINT2 */ +#define CLEARWATER_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */ + +/* + * R6408 (0x1908) - IRQ2 Status 9 + */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT2 0x0800 /* ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT2_MASK 0x0800 /* ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT2_SHIFT 11 /* ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN2_LOCK_EINT2_WIDTH 1 /* ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT2 0x0400 /* ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT2_MASK 0x0400 /* ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT2_SHIFT 10 /* ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_EINT2_WIDTH 1 /* ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT2 0x0200 /* ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT2_MASK 0x0200 /* ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT2_SHIFT 9 /* ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_EINT2_WIDTH 1 /* ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT2 0x0100 /* ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT2_MASK 0x0100 /* ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT2_SHIFT 8 /* ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_EINT2_WIDTH 1 /* ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_DRC2_SIG_DET_EINT2 0x0002 /* DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_DRC2_SIG_DET_EINT2_MASK 0x0002 /* DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_DRC2_SIG_DET_EINT2_SHIFT 1 /* DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_DRC1_SIG_DET_EINT2 0x0001 /* DRC1_SIG_DET_EINT2 */ +#define CLEARWATER_DRC1_SIG_DET_EINT2_MASK 0x0001 /* DRC1_SIG_DET_EINT2 */ +#define CLEARWATER_DRC1_SIG_DET_EINT2_SHIFT 0 /* DRC1_SIG_DET_EINT2 */ +#define CLEARWATER_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */ + +/* + * R6410 (0x190A) - IRQ2 Status 11 + */ +#define CLEARWATER_DSP_IRQ16_EINT2 0x8000 /* DSP_IRQ16_EINT2 */ +#define CLEARWATER_DSP_IRQ16_EINT2_MASK 0x8000 /* DSP_IRQ16_EINT2 */ +#define CLEARWATER_DSP_IRQ16_EINT2_SHIFT 15 /* DSP_IRQ16_EINT2 */ +#define CLEARWATER_DSP_IRQ16_EINT2_WIDTH 1 /* DSP_IRQ16_EINT2 */ +#define CLEARWATER_DSP_IRQ15_EINT2 0x4000 /* DSP_IRQ15_EINT2 */ +#define CLEARWATER_DSP_IRQ15_EINT2_MASK 0x4000 /* DSP_IRQ15_EINT2 */ +#define CLEARWATER_DSP_IRQ15_EINT2_SHIFT 14 /* DSP_IRQ15_EINT2 */ +#define CLEARWATER_DSP_IRQ15_EINT2_WIDTH 1 /* DSP_IRQ15_EINT2 */ +#define CLEARWATER_DSP_IRQ14_EINT2 0x2000 /* DSP_IRQ14_EINT2 */ +#define CLEARWATER_DSP_IRQ14_EINT2_MASK 0x2000 /* DSP_IRQ14_EINT2 */ +#define CLEARWATER_DSP_IRQ14_EINT2_SHIFT 13 /* DSP_IRQ14_EINT2 */ +#define CLEARWATER_DSP_IRQ14_EINT2_WIDTH 1 /* DSP_IRQ14_EINT2 */ +#define CLEARWATER_DSP_IRQ13_EINT2 0x1000 /* DSP_IRQ13_EINT2 */ +#define CLEARWATER_DSP_IRQ13_EINT2_MASK 0x1000 /* DSP_IRQ13_EINT2 */ +#define CLEARWATER_DSP_IRQ13_EINT2_SHIFT 12 /* DSP_IRQ13_EINT2 */ +#define CLEARWATER_DSP_IRQ13_EINT2_WIDTH 1 /* DSP_IRQ13_EINT2 */ +#define CLEARWATER_DSP_IRQ12_EINT2 0x0800 /* DSP_IRQ12_EINT2 */ +#define CLEARWATER_DSP_IRQ12_EINT2_MASK 0x0800 /* DSP_IRQ12_EINT2 */ +#define CLEARWATER_DSP_IRQ12_EINT2_SHIFT 11 /* DSP_IRQ12_EINT2 */ +#define CLEARWATER_DSP_IRQ12_EINT2_WIDTH 1 /* DSP_IRQ12_EINT2 */ +#define CLEARWATER_DSP_IRQ11_EINT2 0x0400 /* DSP_IRQ11_EINT2 */ +#define CLEARWATER_DSP_IRQ11_EINT2_MASK 0x0400 /* DSP_IRQ11_EINT2 */ +#define CLEARWATER_DSP_IRQ11_EINT2_SHIFT 10 /* DSP_IRQ11_EINT2 */ +#define CLEARWATER_DSP_IRQ11_EINT2_WIDTH 1 /* DSP_IRQ11_EINT2 */ +#define CLEARWATER_DSP_IRQ10_EINT2 0x0200 /* DSP_IRQ10_EINT2 */ +#define CLEARWATER_DSP_IRQ10_EINT2_MASK 0x0200 /* DSP_IRQ10_EINT2 */ +#define CLEARWATER_DSP_IRQ10_EINT2_SHIFT 9 /* DSP_IRQ10_EINT2 */ +#define CLEARWATER_DSP_IRQ10_EINT2_WIDTH 1 /* DSP_IRQ10_EINT2 */ +#define CLEARWATER_DSP_IRQ9_EINT2 0x0100 /* DSP_IRQ9_EINT2 */ +#define CLEARWATER_DSP_IRQ9_EINT2_MASK 0x0100 /* DSP_IRQ9_EINT2 */ +#define CLEARWATER_DSP_IRQ9_EINT2_SHIFT 8 /* DSP_IRQ9_EINT2 */ +#define CLEARWATER_DSP_IRQ9_EINT2_WIDTH 1 /* DSP_IRQ9_EINT2 */ +#define CLEARWATER_DSP_IRQ8_EINT2 0x0080 /* DSP_IRQ8_EINT2 */ +#define CLEARWATER_DSP_IRQ8_EINT2_MASK 0x0080 /* DSP_IRQ8_EINT2 */ +#define CLEARWATER_DSP_IRQ8_EINT2_SHIFT 7 /* DSP_IRQ8_EINT2 */ +#define CLEARWATER_DSP_IRQ8_EINT2_WIDTH 1 /* DSP_IRQ8_EINT2 */ +#define CLEARWATER_DSP_IRQ7_EINT2 0x0040 /* DSP_IRQ7_EINT2 */ +#define CLEARWATER_DSP_IRQ7_EINT2_MASK 0x0040 /* DSP_IRQ7_EINT2 */ +#define CLEARWATER_DSP_IRQ7_EINT2_SHIFT 6 /* DSP_IRQ7_EINT2 */ +#define CLEARWATER_DSP_IRQ7_EINT2_WIDTH 1 /* DSP_IRQ7_EINT2 */ +#define CLEARWATER_DSP_IRQ6_EINT2 0x0020 /* DSP_IRQ6_EINT2 */ +#define CLEARWATER_DSP_IRQ6_EINT2_MASK 0x0020 /* DSP_IRQ6_EINT2 */ +#define CLEARWATER_DSP_IRQ6_EINT2_SHIFT 5 /* DSP_IRQ6_EINT2 */ +#define CLEARWATER_DSP_IRQ6_EINT2_WIDTH 1 /* DSP_IRQ6_EINT2 */ +#define CLEARWATER_DSP_IRQ5_EINT2 0x0010 /* DSP_IRQ5_EINT2 */ +#define CLEARWATER_DSP_IRQ5_EINT2_MASK 0x0010 /* DSP_IRQ5_EINT2 */ +#define CLEARWATER_DSP_IRQ5_EINT2_SHIFT 4 /* DSP_IRQ5_EINT2 */ +#define CLEARWATER_DSP_IRQ5_EINT2_WIDTH 1 /* DSP_IRQ5_EINT2 */ +#define CLEARWATER_DSP_IRQ4_EINT2 0x0008 /* DSP_IRQ4_EINT2 */ +#define CLEARWATER_DSP_IRQ4_EINT2_MASK 0x0008 /* DSP_IRQ4_EINT2 */ +#define CLEARWATER_DSP_IRQ4_EINT2_SHIFT 3 /* DSP_IRQ4_EINT2 */ +#define CLEARWATER_DSP_IRQ4_EINT2_WIDTH 1 /* DSP_IRQ4_EINT2 */ +#define CLEARWATER_DSP_IRQ3_EINT2 0x0004 /* DSP_IRQ3_EINT2 */ +#define CLEARWATER_DSP_IRQ3_EINT2_MASK 0x0004 /* DSP_IRQ3_EINT2 */ +#define CLEARWATER_DSP_IRQ3_EINT2_SHIFT 2 /* DSP_IRQ3_EINT2 */ +#define CLEARWATER_DSP_IRQ3_EINT2_WIDTH 1 /* DSP_IRQ3_EINT2 */ +#define CLEARWATER_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */ +#define CLEARWATER_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */ +#define CLEARWATER_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */ +#define CLEARWATER_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */ +#define CLEARWATER_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */ +#define CLEARWATER_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */ +#define CLEARWATER_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */ +#define CLEARWATER_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */ + +/* + * R6411 (0x190B) - IRQ2 Status 12 + */ +#define CLEARWATER_SPKOUTR_SC_EINT2 0x0080 /* SPKOUTR_SC_EINT2 */ +#define CLEARWATER_SPKOUTR_SC_EINT2_MASK 0x0080 /* SPKOUTR_SC_EINT2 */ +#define CLEARWATER_SPKOUTR_SC_EINT2_SHIFT 7 /* SPKOUTR_SC_EINT2 */ +#define CLEARWATER_SPKOUTR_SC_EINT2_WIDTH 1 /* SPKOUTR_SC_EINT2 */ +#define CLEARWATER_SPKOUTL_SC_EINT2 0x0040 /* SPKOUTL_SC_EINT2 */ +#define CLEARWATER_SPKOUTL_SC_EINT2_MASK 0x0040 /* SPKOUTL_SC_EINT2 */ +#define CLEARWATER_SPKOUTL_SC_EINT2_SHIFT 6 /* SPKOUTL_SC_EINT2 */ +#define CLEARWATER_SPKOUTL_SC_EINT2_WIDTH 1 /* SPKOUTL_SC_EINT2 */ +#define CLEARWATER_HP3R_SC_EINT2 0x0020 /* HP3R_SC_EINT2 */ +#define CLEARWATER_HP3R_SC_EINT2_MASK 0x0020 /* HP3R_SC_EINT2 */ +#define CLEARWATER_HP3R_SC_EINT2_SHIFT 5 /* HP3R_SC_EINT2 */ +#define CLEARWATER_HP3R_SC_EINT2_WIDTH 1 /* HP3R_SC_EINT2 */ +#define CLEARWATER_HP3L_SC_EINT2 0x0010 /* HP3L_SC_EINT2 */ +#define CLEARWATER_HP3L_SC_EINT2_MASK 0x0010 /* HP3L_SC_EINT2 */ +#define CLEARWATER_HP3L_SC_EINT2_SHIFT 4 /* HP3L_SC_EINT2 */ +#define CLEARWATER_HP3L_SC_EINT2_WIDTH 1 /* HP3L_SC_EINT2 */ +#define CLEARWATER_HP2R_SC_EINT2 0x0008 /* HP2R_SC_EINT2 */ +#define CLEARWATER_HP2R_SC_EINT2_MASK 0x0008 /* HP2R_SC_EINT2 */ +#define CLEARWATER_HP2R_SC_EINT2_SHIFT 3 /* HP2R_SC_EINT2 */ +#define CLEARWATER_HP2R_SC_EINT2_WIDTH 1 /* HP2R_SC_EINT2 */ +#define CLEARWATER_HP2L_SC_EINT2 0x0004 /* HP2L_SC_EINT2 */ +#define CLEARWATER_HP2L_SC_EINT2_MASK 0x0004 /* HP2L_SC_EINT2 */ +#define CLEARWATER_HP2L_SC_EINT2_SHIFT 2 /* HP2L_SC_EINT2 */ +#define CLEARWATER_HP2L_SC_EINT2_WIDTH 1 /* HP2L_SC_EINT2 */ +#define CLEARWATER_HP1R_SC_EINT2 0x0002 /* HP1R_SC_EINT2 */ +#define CLEARWATER_HP1R_SC_EINT2_MASK 0x0002 /* HP1R_SC_EINT2 */ +#define CLEARWATER_HP1R_SC_EINT2_SHIFT 1 /* HP1R_SC_EINT2 */ +#define CLEARWATER_HP1R_SC_EINT2_WIDTH 1 /* HP1R_SC_EINT2 */ +#define CLEARWATER_HP1L_SC_EINT2 0x0001 /* HP1L_SC_EINT2 */ +#define CLEARWATER_HP1L_SC_EINT2_MASK 0x0001 /* HP1L_SC_EINT2 */ +#define CLEARWATER_HP1L_SC_EINT2_SHIFT 0 /* HP1L_SC_EINT2 */ +#define CLEARWATER_HP1L_SC_EINT2_WIDTH 1 /* HP1L_SC_EINT2 */ + +/* + * R6412 (0x190C) - IRQ2 Status 13 + */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT2 0x0080 /* SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT2_MASK 0x0080 /* SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT2_SHIFT 7 /* SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_EINT2_WIDTH 1 /* SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT2 0x0040 /* SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT2_MASK 0x0040 /* SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT2_SHIFT 6 /* SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_EINT2_WIDTH 1 /* SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT2 0x0020 /* HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT2_MASK 0x0020 /* HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT2_SHIFT 5 /* HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_EINT2_WIDTH 1 /* HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT2 0x0010 /* HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT2_MASK 0x0010 /* HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT2_SHIFT 4 /* HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_EINT2_WIDTH 1 /* HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT2 0x0008 /* HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT2_MASK 0x0008 /* HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT2_SHIFT 3 /* HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_EINT2_WIDTH 1 /* HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT2 0x0004 /* HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT2_MASK 0x0004 /* HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT2_SHIFT 2 /* HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_EINT2_WIDTH 1 /* HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT2 0x0002 /* HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT2_MASK 0x0002 /* HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT2_SHIFT 1 /* HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_EINT2_WIDTH 1 /* HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT2 0x0001 /* HP1L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT2_MASK 0x0001 /* HP1L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT2_SHIFT 0 /* HP1L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_EINT2_WIDTH 1 /* HP1L_ENABLE_DONE_EINT2 */ + +/* + * R6413 (0x190D) - IRQ2 Status 14 + */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT2 0x0080 /* SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT2_MASK 0x0080 /* SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT2_SHIFT 7 /* SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_EINT2_WIDTH 1 /* SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT2 0x0040 /* SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT2_MASK 0x0040 /* SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT2_SHIFT 6 /* SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_EINT2_WIDTH 1 /* SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT2 0x0020 /* HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT2_MASK 0x0020 /* HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT2_SHIFT 5 /* HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_EINT2_WIDTH 1 /* HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT2 0x0010 /* HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT2_MASK 0x0010 /* HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT2_SHIFT 4 /* HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_EINT2_WIDTH 1 /* HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT2 0x0008 /* HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT2_MASK 0x0008 /* HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT2_SHIFT 3 /* HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_EINT2_WIDTH 1 /* HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT2 0x0004 /* HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT2_MASK 0x0004 /* HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT2_SHIFT 2 /* HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_EINT2_WIDTH 1 /* HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT2 0x0002 /* HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT2_MASK 0x0002 /* HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT2_SHIFT 1 /* HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_EINT2_WIDTH 1 /* HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT2 0x0001 /* HP1L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT2_MASK 0x0001 /* HP1L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT2_SHIFT 0 /* HP1L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_EINT2_WIDTH 1 /* HP1L_DISABLE_DONE_EINT2 */ + +/* + * R6414 (0x190E) - IRQ2 Status 15 + */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT2 0x0004 /* SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT2_MASK 0x0004 /* SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT2_SHIFT 2 /* SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_EINT2 0x0002 /* SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_EINT2_MASK 0x0002 /* SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_EINT2_SHIFT 1 /* SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_SPK_OVERHEAT_EINT2_WIDTH 1 /* SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT2 0x0001 /* SPK_SHUTDOWN_EINT2 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT2_MASK 0x0001 /* SPK_SHUTDOWN_EINT2 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT2_SHIFT 0 /* SPK_SHUTDOWN_EINT2 */ +#define CLEARWATER_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */ + +/* + * R6464 (0x1940) - IRQ2 Mask 1 + */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT2 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_IM_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT2 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT2 0x1000 /* IM_CTRLIF_ERR_EINT2 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT2_MASK 0x1000 /* IM_CTRLIF_ERR_EINT2 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT2_SHIFT 12 /* IM_CTRLIF_ERR_EINT2 */ +#define CLEARWATER_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT2 0x0200 /* IM_IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT2_MASK 0x0200 /* IM_IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT2_SHIFT 9 /* IM_IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IM_IRQ_NO_CLOCK_EINT2_WIDTH 1 /* IM_IRQ_NO_CLOCK_EINT2 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT2 0x0100 /* IM_CLOCK_DETECT_EINT2 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT2_MASK 0x0100 /* IM_CLOCK_DETECT_EINT2 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT2_SHIFT 8 /* IM_CLOCK_DETECT_EINT2 */ +#define CLEARWATER_IM_CLOCK_DETECT_EINT2_WIDTH 1 /* IM_CLOCK_DETECT_EINT2 */ +#define CLEARWATER_IM_BOOT_DONE_EINT2 0x0080 /* IM_BOOT_DONE_EINT2 */ +#define CLEARWATER_IM_BOOT_DONE_EINT2_MASK 0x0080 /* IM_BOOT_DONE_EINT2 */ +#define CLEARWATER_IM_BOOT_DONE_EINT2_SHIFT 7 /* IM_BOOT_DONE_EINT2 */ +#define CLEARWATER_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */ + +/* + * R6465 (0x1941) - IRQ2 Mask 2 + */ +#define CLEARWATER_IM_FLL3_LOCK_EINT2 0x0400 /* IM_FLL3_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL3_LOCK_EINT2_MASK 0x0400 /* IM_FLL3_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL3_LOCK_EINT2_SHIFT 10 /* IM_FLL3_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL3_LOCK_EINT2_WIDTH 1 /* IM_FLL3_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT2 0x0200 /* IM_FLL2_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT2_MASK 0x0200 /* IM_FLL2_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT2_SHIFT 9 /* IM_FLL2_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT2 0x0100 /* IM_FLL1_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT2_MASK 0x0100 /* IM_FLL1_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT2_SHIFT 8 /* IM_FLL1_LOCK_EINT2 */ +#define CLEARWATER_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */ + +/* + * R6469 (0x1945) - IRQ2 Mask 6 + */ +#define CLEARWATER_IM_MICDET_EINT2 0x0100 /* IM_MICDET_EINT2 */ +#define CLEARWATER_IM_MICDET_EINT2_MASK 0x0100 /* IM_MICDET_EINT2 */ +#define CLEARWATER_IM_MICDET_EINT2_SHIFT 8 /* IM_MICDET_EINT2 */ +#define CLEARWATER_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */ +#define CLEARWATER_IM_HPDET_EINT2 0x0001 /* IM_HPDET_EINT2 */ +#define CLEARWATER_IM_HPDET_EINT2_MASK 0x0001 /* IM_HPDET_EINT2 */ +#define CLEARWATER_IM_HPDET_EINT2_SHIFT 0 /* IM_HPDET_EINT2 */ +#define CLEARWATER_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */ + +/* + * R6470 (0x1946) - IRQ2 Mask 7 + */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT2 0x0020 /* IM_MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT2_MASK 0x0020 /* IM_MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT2_SHIFT 5 /* IM_MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_FALL_EINT2_WIDTH 1 /* IM_MICD_CLAMP_FALL_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT2 0x0010 /* IM_MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT2_MASK 0x0010 /* IM_MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT2_SHIFT 4 /* IM_MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_IM_MICD_CLAMP_RISE_EINT2_WIDTH 1 /* IM_MICD_CLAMP_RISE_EINT2 */ +#define CLEARWATER_IM_JD2_FALL_EINT2 0x0008 /* IM_JD2_FALL_EINT2 */ +#define CLEARWATER_IM_JD2_FALL_EINT2_MASK 0x0008 /* IM_JD2_FALL_EINT2 */ +#define CLEARWATER_IM_JD2_FALL_EINT2_SHIFT 3 /* IM_JD2_FALL_EINT2 */ +#define CLEARWATER_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */ +#define CLEARWATER_IM_JD2_RISE_EINT2 0x0004 /* IM_JD2_RISE_EINT2 */ +#define CLEARWATER_IM_JD2_RISE_EINT2_MASK 0x0004 /* IM_JD2_RISE_EINT2 */ +#define CLEARWATER_IM_JD2_RISE_EINT2_SHIFT 2 /* IM_JD2_RISE_EINT2 */ +#define CLEARWATER_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */ +#define CLEARWATER_IM_JD1_FALL_EINT2 0x0002 /* IM_JD1_FALL_EINT2 */ +#define CLEARWATER_IM_JD1_FALL_EINT2_MASK 0x0002 /* IM_JD1_FALL_EINT2 */ +#define CLEARWATER_IM_JD1_FALL_EINT2_SHIFT 1 /* IM_JD1_FALL_EINT2 */ +#define CLEARWATER_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */ +#define CLEARWATER_IM_JD1_RISE_EINT2 0x0001 /* IM_JD1_RISE_EINT2 */ +#define CLEARWATER_IM_JD1_RISE_EINT2_MASK 0x0001 /* IM_JD1_RISE_EINT2 */ +#define CLEARWATER_IM_JD1_RISE_EINT2_SHIFT 0 /* IM_JD1_RISE_EINT2 */ +#define CLEARWATER_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */ + +/* + * R6472 (0x1948) - IRQ2 Mask 9 + */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT2 0x0800 /* IM_ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT2_MASK 0x0800 /* IM_ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT2_SHIFT 11 /* IM_ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT2 0x0400 /* IM_ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT2_MASK 0x0400 /* IM_ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT2_SHIFT 10 /* IM_ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC2_IN1_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT2 0x0200 /* IM_ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT2_MASK 0x0200 /* IM_ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT2_SHIFT 9 /* IM_ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN2_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_IN2_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT2 0x0100 /* IM_ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT2_MASK 0x0100 /* IM_ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT2_SHIFT 8 /* IM_ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_ASRC1_IN1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_IN1_LOCK_EINT2 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT2 0x0002 /* IM_DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT2_MASK 0x0002 /* IM_DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT2_SHIFT 1 /* IM_DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT2 0x0001 /* IM_DRC1_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT2_MASK 0x0001 /* IM_DRC1_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT2_SHIFT 0 /* IM_DRC1_SIG_DET_EINT2 */ +#define CLEARWATER_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */ + +/* + * R6474 (0x194A) - IRQ2 Mask 11 + */ +#define CLEARWATER_IM_DSP_IRQ16_EINT2 0x8000 /* IM_DSP_IRQ16_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ16_EINT2_MASK 0x8000 /* IM_DSP_IRQ16_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ16_EINT2_SHIFT 15 /* IM_DSP_IRQ16_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ16_EINT2_WIDTH 1 /* IM_DSP_IRQ16_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT2 0x4000 /* IM_DSP_IRQ15_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT2_MASK 0x4000 /* IM_DSP_IRQ15_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT2_SHIFT 14 /* IM_DSP_IRQ15_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ15_EINT2_WIDTH 1 /* IM_DSP_IRQ15_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT2 0x2000 /* IM_DSP_IRQ14_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT2_MASK 0x2000 /* IM_DSP_IRQ14_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT2_SHIFT 13 /* IM_DSP_IRQ14_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ14_EINT2_WIDTH 1 /* IM_DSP_IRQ14_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT2 0x1000 /* IM_DSP_IRQ13_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT2_MASK 0x1000 /* IM_DSP_IRQ13_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT2_SHIFT 12 /* IM_DSP_IRQ13_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ13_EINT2_WIDTH 1 /* IM_DSP_IRQ13_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT2 0x0800 /* IM_DSP_IRQ12_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT2_MASK 0x0800 /* IM_DSP_IRQ12_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT2_SHIFT 11 /* IM_DSP_IRQ12_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ12_EINT2_WIDTH 1 /* IM_DSP_IRQ12_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT2 0x0400 /* IM_DSP_IRQ11_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT2_MASK 0x0400 /* IM_DSP_IRQ11_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT2_SHIFT 10 /* IM_DSP_IRQ11_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ11_EINT2_WIDTH 1 /* IM_DSP_IRQ11_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT2 0x0200 /* IM_DSP_IRQ10_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT2_MASK 0x0200 /* IM_DSP_IRQ10_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT2_SHIFT 9 /* IM_DSP_IRQ10_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ10_EINT2_WIDTH 1 /* IM_DSP_IRQ10_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT2 0x0100 /* IM_DSP_IRQ9_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT2_MASK 0x0100 /* IM_DSP_IRQ9_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT2_SHIFT 8 /* IM_DSP_IRQ9_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ9_EINT2_WIDTH 1 /* IM_DSP_IRQ9_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT2 0x0080 /* IM_DSP_IRQ8_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT2_MASK 0x0080 /* IM_DSP_IRQ8_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT2_SHIFT 7 /* IM_DSP_IRQ8_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ8_EINT2_WIDTH 1 /* IM_DSP_IRQ8_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT2 0x0040 /* IM_DSP_IRQ7_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT2_MASK 0x0040 /* IM_DSP_IRQ7_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT2_SHIFT 6 /* IM_DSP_IRQ7_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ7_EINT2_WIDTH 1 /* IM_DSP_IRQ7_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT2 0x0020 /* IM_DSP_IRQ6_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT2_MASK 0x0020 /* IM_DSP_IRQ6_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT2_SHIFT 5 /* IM_DSP_IRQ6_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ6_EINT2_WIDTH 1 /* IM_DSP_IRQ6_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT2 0x0010 /* IM_DSP_IRQ5_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT2_MASK 0x0010 /* IM_DSP_IRQ5_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT2_SHIFT 4 /* IM_DSP_IRQ5_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ5_EINT2_WIDTH 1 /* IM_DSP_IRQ5_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT2 0x0008 /* IM_DSP_IRQ4_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT2_MASK 0x0008 /* IM_DSP_IRQ4_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT2_SHIFT 3 /* IM_DSP_IRQ4_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ4_EINT2_WIDTH 1 /* IM_DSP_IRQ4_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT2 0x0004 /* IM_DSP_IRQ3_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT2_MASK 0x0004 /* IM_DSP_IRQ3_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT2_SHIFT 2 /* IM_DSP_IRQ3_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ3_EINT2_WIDTH 1 /* IM_DSP_IRQ3_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */ +#define CLEARWATER_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */ + +/* + * R6272 (0x1880) - IRQ1 Raw Status 1 + */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS1 0x8000 /* DSP_SHARED_WR_COLL_STS1 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS1_MASK 0x8000 /* DSP_SHARED_WR_COLL_STS1 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS1_SHIFT 15 /* DSP_SHARED_WR_COLL_STS1 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS1_WIDTH 1 /* DSP_SHARED_WR_COLL_STS1 */ +#define CLEARWATER_CTRLIF_ERR_STS1 0x1000 /* CTRLIF_ERR_STS1 */ +#define CLEARWATER_CTRLIF_ERR_STS1_MASK 0x1000 /* CTRLIF_ERR_STS1 */ +#define CLEARWATER_CTRLIF_ERR_STS1_SHIFT 12 /* CTRLIF_ERR_STS1 */ +#define CLEARWATER_CTRLIF_ERR_STS1_WIDTH 1 /* CTRLIF_ERR_STS1 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS1 0x0200 /* IRQ_NO_CLOCK_STS1 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS1_MASK 0x0200 /* IRQ_NO_CLOCK_STS1 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS1_SHIFT 9 /* IRQ_NO_CLOCK_STS1 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS1_WIDTH 1 /* IRQ_NO_CLOCK_STS1 */ +#define CLEARWATER_CLOCK_DETECT_STS1 0x0100 /* CLOCK_DETECT_STS1 */ +#define CLEARWATER_CLOCK_DETECT_STS1_MASK 0x0100 /* CLOCK_DETECT_STS1 */ +#define CLEARWATER_CLOCK_DETECT_STS1_SHIFT 8 /* CLOCK_DETECT_STS1 */ +#define CLEARWATER_CLOCK_DETECT_STS1_WIDTH 1 /* CLOCK_DETECT_STS1 */ +#define CLEARWATER_BOOT_DONE_STS1 0x0080 /* BOOT_DONE_STS1 */ +#define CLEARWATER_BOOT_DONE_STS1_MASK 0x0080 /* BOOT_DONE_STS1 */ +#define CLEARWATER_BOOT_DONE_STS1_SHIFT 7 /* BOOT_DONE_STS1 */ +#define CLEARWATER_BOOT_DONE_STS1_WIDTH 1 /* BOOT_DONE_STS1 */ + +/* + * R6273 (0x1881) - IRQ1 Raw Status 2 + */ +#define MOON_FLLAO_LOCK_STS1 0x0800 /* FLLAO_LOCK_STS1 */ +#define MOON_FLLAO_LOCK_STS1_MASK 0x0800 /* FLLAO_LOCK_STS1 */ +#define MOON_FLLAO_LOCK_STS1_SHIFT 11 /* FLLAO_LOCK_STS1 */ +#define MOON_FLLAO_LOCK_STS1_WIDTH 1 /* FLLAO_LOCK_STS1 */ +#define CLEARWATER_FLL3_LOCK_STS1 0x0400 /* FLL3_LOCK_STS1 */ +#define CLEARWATER_FLL3_LOCK_STS1_MASK 0x0400 /* FLL3_LOCK_STS1 */ +#define CLEARWATER_FLL3_LOCK_STS1_SHIFT 10 /* FLL3_LOCK_STS1 */ +#define CLEARWATER_FLL3_LOCK_STS1_WIDTH 1 /* FLL3_LOCK_STS1 */ +#define CLEARWATER_FLL2_LOCK_STS1 0x0200 /* FLL2_LOCK_STS1 */ +#define CLEARWATER_FLL2_LOCK_STS1_MASK 0x0200 /* FLL2_LOCK_STS1 */ +#define CLEARWATER_FLL2_LOCK_STS1_SHIFT 9 /* FLL2_LOCK_STS1 */ +#define CLEARWATER_FLL2_LOCK_STS1_WIDTH 1 /* FLL2_LOCK_STS1 */ +#define CLEARWATER_FLL1_LOCK_STS1 0x0100 /* FLL1_LOCK_STS1 */ +#define CLEARWATER_FLL1_LOCK_STS1_MASK 0x0100 /* FLL1_LOCK_STS1 */ +#define CLEARWATER_FLL1_LOCK_STS1_SHIFT 8 /* FLL1_LOCK_STS1 */ +#define CLEARWATER_FLL1_LOCK_STS1_WIDTH 1 /* FLL1_LOCK_STS1 */ + +/* + * R6277 (0x1885) - IRQ1 Raw Status 6 + */ +#define CLEARWATER_MICDET_STS1 0x0100 /* MICDET_STS1 */ +#define CLEARWATER_MICDET_STS1_MASK 0x0100 /* MICDET_STS1 */ +#define CLEARWATER_MICDET_STS1_SHIFT 8 /* MICDET_STS1 */ +#define CLEARWATER_MICDET_STS1_WIDTH 1 /* MICDET_STS1 */ +#define CLEARWATER_HPDET_STS1 0x0001 /* HPDET_STS1 */ +#define CLEARWATER_HPDET_STS1_MASK 0x0001 /* HPDET_STS1 */ +#define CLEARWATER_HPDET_STS1_SHIFT 0 /* HPDET_STS1 */ +#define CLEARWATER_HPDET_STS1_WIDTH 1 /* HPDET_STS1 */ + +/* + * R6278 (0x1886) - IRQ1 Raw Status 7 + */ +#define CLEARWATER_MICD_CLAMP_FALL_STS1 0x0020 /* MICD_CLAMP_FALL_STS1 */ +#define CLEARWATER_MICD_CLAMP_FALL_STS1_MASK 0x0020 /* MICD_CLAMP_FALL_STS1 */ +#define CLEARWATER_MICD_CLAMP_FALL_STS1_SHIFT 5 /* MICD_CLAMP_FALL_STS1 */ +#define CLEARWATER_MICD_CLAMP_FALL_STS1_WIDTH 1 /* MICD_CLAMP_FALL_STS1 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS1 0x0010 /* MICD_CLAMP_RISE_STS1 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS1_MASK 0x0010 /* MICD_CLAMP_RISE_STS1 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS1_SHIFT 4 /* MICD_CLAMP_RISE_STS1 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS1_WIDTH 1 /* MICD_CLAMP_RISE_STS1 */ +#define CLEARWATER_JD2_FALL_STS1 0x0008 /* JD2_FALL_STS1 */ +#define CLEARWATER_JD2_FALL_STS1_MASK 0x0008 /* JD2_FALL_STS1 */ +#define CLEARWATER_JD2_FALL_STS1_SHIFT 3 /* JD2_FALL_STS1 */ +#define CLEARWATER_JD2_FALL_STS1_WIDTH 1 /* JD2_FALL_STS1 */ +#define CLEARWATER_JD2_RISE_STS1 0x0004 /* JD2_RISE_STS1 */ +#define CLEARWATER_JD2_RISE_STS1_MASK 0x0004 /* JD2_RISE_STS1 */ +#define CLEARWATER_JD2_RISE_STS1_SHIFT 2 /* JD2_RISE_STS1 */ +#define CLEARWATER_JD2_RISE_STS1_WIDTH 1 /* JD2_RISE_STS1 */ +#define CLEARWATER_JD1_FALL_STS1 0x0002 /* JD1_FALL_STS1 */ +#define CLEARWATER_JD1_FALL_STS1_MASK 0x0002 /* JD1_FALL_STS1 */ +#define CLEARWATER_JD1_FALL_STS1_SHIFT 1 /* JD1_FALL_STS1 */ +#define CLEARWATER_JD1_FALL_STS1_WIDTH 1 /* JD1_FALL_STS1 */ +#define CLEARWATER_JD1_RISE_STS1 0x0001 /* JD1_RISE_STS1 */ +#define CLEARWATER_JD1_RISE_STS1_MASK 0x0001 /* JD1_RISE_STS1 */ +#define CLEARWATER_JD1_RISE_STS1_SHIFT 0 /* JD1_RISE_STS1 */ +#define CLEARWATER_JD1_RISE_STS1_WIDTH 1 /* JD1_RISE_STS1 */ + +/* + * R6280 (0x1888) - IRQ1 Raw Status 9 + */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS1 0x0800 /* ASRC2_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS1_MASK 0x0800 /* ASRC2_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS1_SHIFT 11 /* ASRC2_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS1_WIDTH 1 /* ASRC2_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS1 0x0400 /* ASRC2_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS1_MASK 0x0400 /* ASRC2_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS1_SHIFT 10 /* ASRC2_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS1_WIDTH 1 /* ASRC2_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS1 0x0200 /* ASRC1_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS1_MASK 0x0200 /* ASRC1_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS1_SHIFT 9 /* ASRC1_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS1_WIDTH 1 /* ASRC1_IN2_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS1 0x0100 /* ASRC1_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS1_MASK 0x0100 /* ASRC1_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS1_SHIFT 8 /* ASRC1_IN1_LOCK_STS1 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS1_WIDTH 1 /* ASRC1_IN1_LOCK_STS1 */ +#define CLEARWATER_DRC2_SIG_DET_STS1 0x0002 /* DRC2_SIG_DET_STS1 */ +#define CLEARWATER_DRC2_SIG_DET_STS1_MASK 0x0002 /* DRC2_SIG_DET_STS1 */ +#define CLEARWATER_DRC2_SIG_DET_STS1_SHIFT 1 /* DRC2_SIG_DET_STS1 */ +#define CLEARWATER_DRC2_SIG_DET_STS1_WIDTH 1 /* DRC2_SIG_DET_STS1 */ +#define CLEARWATER_DRC1_SIG_DET_STS1 0x0001 /* DRC1_SIG_DET_STS1 */ +#define CLEARWATER_DRC1_SIG_DET_STS1_MASK 0x0001 /* DRC1_SIG_DET_STS1 */ +#define CLEARWATER_DRC1_SIG_DET_STS1_SHIFT 0 /* DRC1_SIG_DET_STS1 */ +#define CLEARWATER_DRC1_SIG_DET_STS1_WIDTH 1 /* DRC1_SIG_DET_STS1 */ + +/* + * R6282 (0x188A) - IRQ1 Raw Status 11 + */ +#define CLEARWATER_DSP_IRQ16_STS1 0x8000 /* DSP_IRQ16_STS1 */ +#define CLEARWATER_DSP_IRQ16_STS1_MASK 0x8000 /* DSP_IRQ16_STS1 */ +#define CLEARWATER_DSP_IRQ16_STS1_SHIFT 15 /* DSP_IRQ16_STS1 */ +#define CLEARWATER_DSP_IRQ16_STS1_WIDTH 1 /* DSP_IRQ16_STS1 */ +#define CLEARWATER_DSP_IRQ15_STS1 0x4000 /* DSP_IRQ15_STS1 */ +#define CLEARWATER_DSP_IRQ15_STS1_MASK 0x4000 /* DSP_IRQ15_STS1 */ +#define CLEARWATER_DSP_IRQ15_STS1_SHIFT 14 /* DSP_IRQ15_STS1 */ +#define CLEARWATER_DSP_IRQ15_STS1_WIDTH 1 /* DSP_IRQ15_STS1 */ +#define CLEARWATER_DSP_IRQ14_STS1 0x2000 /* DSP_IRQ14_STS1 */ +#define CLEARWATER_DSP_IRQ14_STS1_MASK 0x2000 /* DSP_IRQ14_STS1 */ +#define CLEARWATER_DSP_IRQ14_STS1_SHIFT 13 /* DSP_IRQ14_STS1 */ +#define CLEARWATER_DSP_IRQ14_STS1_WIDTH 1 /* DSP_IRQ14_STS1 */ +#define CLEARWATER_DSP_IRQ13_STS1 0x1000 /* DSP_IRQ13_STS1 */ +#define CLEARWATER_DSP_IRQ13_STS1_MASK 0x1000 /* DSP_IRQ13_STS1 */ +#define CLEARWATER_DSP_IRQ13_STS1_SHIFT 12 /* DSP_IRQ13_STS1 */ +#define CLEARWATER_DSP_IRQ13_STS1_WIDTH 1 /* DSP_IRQ13_STS1 */ +#define CLEARWATER_DSP_IRQ12_STS1 0x0800 /* DSP_IRQ12_STS1 */ +#define CLEARWATER_DSP_IRQ12_STS1_MASK 0x0800 /* DSP_IRQ12_STS1 */ +#define CLEARWATER_DSP_IRQ12_STS1_SHIFT 11 /* DSP_IRQ12_STS1 */ +#define CLEARWATER_DSP_IRQ12_STS1_WIDTH 1 /* DSP_IRQ12_STS1 */ +#define CLEARWATER_DSP_IRQ11_STS1 0x0400 /* DSP_IRQ11_STS1 */ +#define CLEARWATER_DSP_IRQ11_STS1_MASK 0x0400 /* DSP_IRQ11_STS1 */ +#define CLEARWATER_DSP_IRQ11_STS1_SHIFT 10 /* DSP_IRQ11_STS1 */ +#define CLEARWATER_DSP_IRQ11_STS1_WIDTH 1 /* DSP_IRQ11_STS1 */ +#define CLEARWATER_DSP_IRQ10_STS1 0x0200 /* DSP_IRQ10_STS1 */ +#define CLEARWATER_DSP_IRQ10_STS1_MASK 0x0200 /* DSP_IRQ10_STS1 */ +#define CLEARWATER_DSP_IRQ10_STS1_SHIFT 9 /* DSP_IRQ10_STS1 */ +#define CLEARWATER_DSP_IRQ10_STS1_WIDTH 1 /* DSP_IRQ10_STS1 */ +#define CLEARWATER_DSP_IRQ9_STS1 0x0100 /* DSP_IRQ9_STS1 */ +#define CLEARWATER_DSP_IRQ9_STS1_MASK 0x0100 /* DSP_IRQ9_STS1 */ +#define CLEARWATER_DSP_IRQ9_STS1_SHIFT 8 /* DSP_IRQ9_STS1 */ +#define CLEARWATER_DSP_IRQ9_STS1_WIDTH 1 /* DSP_IRQ9_STS1 */ +#define CLEARWATER_DSP_IRQ8_STS1 0x0080 /* DSP_IRQ8_STS1 */ +#define CLEARWATER_DSP_IRQ8_STS1_MASK 0x0080 /* DSP_IRQ8_STS1 */ +#define CLEARWATER_DSP_IRQ8_STS1_SHIFT 7 /* DSP_IRQ8_STS1 */ +#define CLEARWATER_DSP_IRQ8_STS1_WIDTH 1 /* DSP_IRQ8_STS1 */ +#define CLEARWATER_DSP_IRQ7_STS1 0x0040 /* DSP_IRQ7_STS1 */ +#define CLEARWATER_DSP_IRQ7_STS1_MASK 0x0040 /* DSP_IRQ7_STS1 */ +#define CLEARWATER_DSP_IRQ7_STS1_SHIFT 6 /* DSP_IRQ7_STS1 */ +#define CLEARWATER_DSP_IRQ7_STS1_WIDTH 1 /* DSP_IRQ7_STS1 */ +#define CLEARWATER_DSP_IRQ6_STS1 0x0020 /* DSP_IRQ6_STS1 */ +#define CLEARWATER_DSP_IRQ6_STS1_MASK 0x0020 /* DSP_IRQ6_STS1 */ +#define CLEARWATER_DSP_IRQ6_STS1_SHIFT 5 /* DSP_IRQ6_STS1 */ +#define CLEARWATER_DSP_IRQ6_STS1_WIDTH 1 /* DSP_IRQ6_STS1 */ +#define CLEARWATER_DSP_IRQ5_STS1 0x0010 /* DSP_IRQ5_STS1 */ +#define CLEARWATER_DSP_IRQ5_STS1_MASK 0x0010 /* DSP_IRQ5_STS1 */ +#define CLEARWATER_DSP_IRQ5_STS1_SHIFT 4 /* DSP_IRQ5_STS1 */ +#define CLEARWATER_DSP_IRQ5_STS1_WIDTH 1 /* DSP_IRQ5_STS1 */ +#define CLEARWATER_DSP_IRQ4_STS1 0x0008 /* DSP_IRQ4_STS1 */ +#define CLEARWATER_DSP_IRQ4_STS1_MASK 0x0008 /* DSP_IRQ4_STS1 */ +#define CLEARWATER_DSP_IRQ4_STS1_SHIFT 3 /* DSP_IRQ4_STS1 */ +#define CLEARWATER_DSP_IRQ4_STS1_WIDTH 1 /* DSP_IRQ4_STS1 */ +#define CLEARWATER_DSP_IRQ3_STS1 0x0004 /* DSP_IRQ3_STS1 */ +#define CLEARWATER_DSP_IRQ3_STS1_MASK 0x0004 /* DSP_IRQ3_STS1 */ +#define CLEARWATER_DSP_IRQ3_STS1_SHIFT 2 /* DSP_IRQ3_STS1 */ +#define CLEARWATER_DSP_IRQ3_STS1_WIDTH 1 /* DSP_IRQ3_STS1 */ +#define CLEARWATER_DSP_IRQ2_STS1 0x0002 /* DSP_IRQ2_STS1 */ +#define CLEARWATER_DSP_IRQ2_STS1_MASK 0x0002 /* DSP_IRQ2_STS1 */ +#define CLEARWATER_DSP_IRQ2_STS1_SHIFT 1 /* DSP_IRQ2_STS1 */ +#define CLEARWATER_DSP_IRQ2_STS1_WIDTH 1 /* DSP_IRQ2_STS1 */ +#define CLEARWATER_DSP_IRQ1_STS1 0x0001 /* DSP_IRQ1_STS1 */ +#define CLEARWATER_DSP_IRQ1_STS1_MASK 0x0001 /* DSP_IRQ1_STS1 */ +#define CLEARWATER_DSP_IRQ1_STS1_SHIFT 0 /* DSP_IRQ1_STS1 */ +#define CLEARWATER_DSP_IRQ1_STS1_WIDTH 1 /* DSP_IRQ1_STS1 */ + + +/* + * R6283 (0x188B) - IRQ1 Raw Status 12 + */ +#define CLEARWATER_SPKOUTR_SC_STS1 0x0080 /* SPKOUTR_SC_STS1 */ +#define CLEARWATER_SPKOUTR_SC_STS1_MASK 0x0080 /* SPKOUTR_SC_STS1 */ +#define CLEARWATER_SPKOUTR_SC_STS1_SHIFT 7 /* SPKOUTR_SC_STS1 */ +#define CLEARWATER_SPKOUTR_SC_STS1_WIDTH 1 /* SPKOUTR_SC_STS1 */ +#define CLEARWATER_SPKOUTL_SC_STS1 0x0040 /* SPKOUTL_SC_STS1 */ +#define CLEARWATER_SPKOUTL_SC_STS1_MASK 0x0040 /* SPKOUTL_SC_STS1 */ +#define CLEARWATER_SPKOUTL_SC_STS1_SHIFT 6 /* SPKOUTL_SC_STS1 */ +#define CLEARWATER_SPKOUTL_SC_STS1_WIDTH 1 /* SPKOUTL_SC_STS1 */ +#define CLEARWATER_HP3R_SC_STS1 0x0020 /* HP3R_SC_STS1 */ +#define CLEARWATER_HP3R_SC_STS1_MASK 0x0020 /* HP3R_SC_STS1 */ +#define CLEARWATER_HP3R_SC_STS1_SHIFT 5 /* HP3R_SC_STS1 */ +#define CLEARWATER_HP3R_SC_STS1_WIDTH 1 /* HP3R_SC_STS1 */ +#define CLEARWATER_HP3L_SC_STS1 0x0010 /* HP3L_SC_STS1 */ +#define CLEARWATER_HP3L_SC_STS1_MASK 0x0010 /* HP3L_SC_STS1 */ +#define CLEARWATER_HP3L_SC_STS1_SHIFT 4 /* HP3L_SC_STS1 */ +#define CLEARWATER_HP3L_SC_STS1_WIDTH 1 /* HP3L_SC_STS1 */ +#define CLEARWATER_HP2R_SC_STS1 0x0008 /* HP2R_SC_STS1 */ +#define CLEARWATER_HP2R_SC_STS1_MASK 0x0008 /* HP2R_SC_STS1 */ +#define CLEARWATER_HP2R_SC_STS1_SHIFT 3 /* HP2R_SC_STS1 */ +#define CLEARWATER_HP2R_SC_STS1_WIDTH 1 /* HP2R_SC_STS1 */ +#define CLEARWATER_HP2L_SC_STS1 0x0004 /* HP2L_SC_STS1 */ +#define CLEARWATER_HP2L_SC_STS1_MASK 0x0004 /* HP2L_SC_STS1 */ +#define CLEARWATER_HP2L_SC_STS1_SHIFT 2 /* HP2L_SC_STS1 */ +#define CLEARWATER_HP2L_SC_STS1_WIDTH 1 /* HP2L_SC_STS1 */ +#define CLEARWATER_HP1R_SC_STS1 0x0002 /* HP1R_SC_STS1 */ +#define CLEARWATER_HP1R_SC_STS1_MASK 0x0002 /* HP1R_SC_STS1 */ +#define CLEARWATER_HP1R_SC_STS1_SHIFT 1 /* HP1R_SC_STS1 */ +#define CLEARWATER_HP1R_SC_STS1_WIDTH 1 /* HP1R_SC_STS1 */ +#define CLEARWATER_HP1L_SC_STS1 0x0001 /* HP1L_SC_STS1 */ +#define CLEARWATER_HP1L_SC_STS1_MASK 0x0001 /* HP1L_SC_STS1 */ +#define CLEARWATER_HP1L_SC_STS1_SHIFT 0 /* HP1L_SC_STS1 */ +#define CLEARWATER_HP1L_SC_STS1_WIDTH 1 /* HP1L_SC_STS1 */ + +/* + * R6284 (0x188C) - IRQ1 Raw Status 13 + */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS1 0x0080 /* SPKOUTR_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS1_MASK 0x0080 /* SPKOUTR_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS1_SHIFT 7 /* SPKOUTR_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS1_WIDTH 1 /* SPKOUTR_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS1 0x0040 /* SPKOUTL_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS1_MASK 0x0040 /* SPKOUTL_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS1_SHIFT 6 /* SPKOUTL_ENABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS1_WIDTH 1 /* SPKOUTL_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS1 0x0020 /* HP3R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS1_MASK 0x0020 /* HP3R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS1_SHIFT 5 /* HP3R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS1_WIDTH 1 /* HP3R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS1 0x0010 /* HP3L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS1_MASK 0x0010 /* HP3L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS1_SHIFT 4 /* HP3L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS1_WIDTH 1 /* HP3L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS1 0x0008 /* HP2R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS1_MASK 0x0008 /* HP2R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS1_SHIFT 3 /* HP2R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS1_WIDTH 1 /* HP2R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS1 0x0004 /* HP2L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS1_MASK 0x0004 /* HP2L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS1_SHIFT 2 /* HP2L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS1_WIDTH 1 /* HP2L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS1 0x0002 /* HP1R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS1_MASK 0x0002 /* HP1R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS1_SHIFT 1 /* HP1R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS1_WIDTH 1 /* HP1R_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS1 0x0001 /* HP1L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS1_MASK 0x0001 /* HP1L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS1_SHIFT 0 /* HP1L_ENABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS1_WIDTH 1 /* HP1L_ENABLE_DONE_STS1 */ + +/* + * R6285 (0x188D) - IRQ1 Raw Status 14 + */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS1 0x0080 /* SPKOUTR_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS1_MASK 0x0080 /* SPKOUTR_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS1_SHIFT 7 /* SPKOUTR_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS1_WIDTH 1 /* SPKOUTR_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS1 0x0040 /* SPKOUTL_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS1_MASK 0x0040 /* SPKOUTL_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS1_SHIFT 6 /* SPKOUTL_DISABLE_DONE_STS1 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS1_WIDTH 1 /* SPKOUTL_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS1 0x0020 /* HP3R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS1_MASK 0x0020 /* HP3R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS1_SHIFT 5 /* HP3R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS1_WIDTH 1 /* HP3R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS1 0x0010 /* HP3L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS1_MASK 0x0010 /* HP3L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS1_SHIFT 4 /* HP3L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS1_WIDTH 1 /* HP3L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS1 0x0008 /* HP2R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS1_MASK 0x0008 /* HP2R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS1_SHIFT 3 /* HP2R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS1_WIDTH 1 /* HP2R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS1 0x0004 /* HP2L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS1_MASK 0x0004 /* HP2L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS1_SHIFT 2 /* HP2L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS1_WIDTH 1 /* HP2L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS1 0x0002 /* HP1R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS1_MASK 0x0002 /* HP1R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS1_SHIFT 1 /* HP1R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS1_WIDTH 1 /* HP1R_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS1 0x0001 /* HP1L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS1_MASK 0x0001 /* HP1L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS1_SHIFT 0 /* HP1L_DISABLE_DONE_STS1 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS1_WIDTH 1 /* HP1L_DISABLE_DONE_STS1 */ + +/* + * R6286 (0x188E) - IRQ1 Raw Status 15 + */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS1 0x0004 /* SPK_OVERHEAT_WARN_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS1_MASK 0x0004 /* SPK_OVERHEAT_WARN_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS1_SHIFT 2 /* SPK_OVERHEAT_WARN_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS1_WIDTH 1 /* SPK_OVERHEAT_WARN_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_STS1 0x0002 /* SPK_OVERHEAT_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_STS1_MASK 0x0002 /* SPK_OVERHEAT_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_STS1_SHIFT 1 /* SPK_OVERHEAT_STS1 */ +#define CLEARWATER_SPK_OVERHEAT_STS1_WIDTH 1 /* SPK_OVERHEAT_STS1 */ +#define CLEARWATER_SPK_SHUTDOWN_STS1 0x0001 /* SPK_SHUTDOWN_STS1 */ +#define CLEARWATER_SPK_SHUTDOWN_STS1_MASK 0x0001 /* SPK_SHUTDOWN_STS1 */ +#define CLEARWATER_SPK_SHUTDOWN_STS1_SHIFT 0 /* SPK_SHUTDOWN_STS1 */ +#define CLEARWATER_SPK_SHUTDOWN_STS1_WIDTH 1 /* SPK_SHUTDOWN_STS1 */ + +/* + * R6475 (0x194B) - IRQ2 Mask 12 + */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT2 0x0080 /* IM_SPKOUTR_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT2_MASK 0x0080 /* IM_SPKOUTR_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT2_SHIFT 7 /* IM_SPKOUTR_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_SC_EINT2_WIDTH 1 /* IM_SPKOUTR_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT2 0x0040 /* IM_SPKOUTL_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT2_MASK 0x0040 /* IM_SPKOUTL_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT2_SHIFT 6 /* IM_SPKOUTL_SC_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_SC_EINT2_WIDTH 1 /* IM_SPKOUTL_SC_EINT2 */ +#define CLEARWATER_IM_HP3R_SC_EINT2 0x0020 /* IM_HP3R_SC_EINT2 */ +#define CLEARWATER_IM_HP3R_SC_EINT2_MASK 0x0020 /* IM_HP3R_SC_EINT2 */ +#define CLEARWATER_IM_HP3R_SC_EINT2_SHIFT 5 /* IM_HP3R_SC_EINT2 */ +#define CLEARWATER_IM_HP3R_SC_EINT2_WIDTH 1 /* IM_HP3R_SC_EINT2 */ +#define CLEARWATER_IM_HP3L_SC_EINT2 0x0010 /* IM_HP3L_SC_EINT2 */ +#define CLEARWATER_IM_HP3L_SC_EINT2_MASK 0x0010 /* IM_HP3L_SC_EINT2 */ +#define CLEARWATER_IM_HP3L_SC_EINT2_SHIFT 4 /* IM_HP3L_SC_EINT2 */ +#define CLEARWATER_IM_HP3L_SC_EINT2_WIDTH 1 /* IM_HP3L_SC_EINT2 */ +#define CLEARWATER_IM_HP2R_SC_EINT2 0x0008 /* IM_HP2R_SC_EINT2 */ +#define CLEARWATER_IM_HP2R_SC_EINT2_MASK 0x0008 /* IM_HP2R_SC_EINT2 */ +#define CLEARWATER_IM_HP2R_SC_EINT2_SHIFT 3 /* IM_HP2R_SC_EINT2 */ +#define CLEARWATER_IM_HP2R_SC_EINT2_WIDTH 1 /* IM_HP2R_SC_EINT2 */ +#define CLEARWATER_IM_HP2L_SC_EINT2 0x0004 /* IM_HP2L_SC_EINT2 */ +#define CLEARWATER_IM_HP2L_SC_EINT2_MASK 0x0004 /* IM_HP2L_SC_EINT2 */ +#define CLEARWATER_IM_HP2L_SC_EINT2_SHIFT 2 /* IM_HP2L_SC_EINT2 */ +#define CLEARWATER_IM_HP2L_SC_EINT2_WIDTH 1 /* IM_HP2L_SC_EINT2 */ +#define CLEARWATER_IM_HP1R_SC_EINT2 0x0002 /* IM_HP1R_SC_EINT2 */ +#define CLEARWATER_IM_HP1R_SC_EINT2_MASK 0x0002 /* IM_HP1R_SC_EINT2 */ +#define CLEARWATER_IM_HP1R_SC_EINT2_SHIFT 1 /* IM_HP1R_SC_EINT2 */ +#define CLEARWATER_IM_HP1R_SC_EINT2_WIDTH 1 /* IM_HP1R_SC_EINT2 */ +#define CLEARWATER_IM_HP1L_SC_EINT2 0x0001 /* IM_HP1L_SC_EINT2 */ +#define CLEARWATER_IM_HP1L_SC_EINT2_MASK 0x0001 /* IM_HP1L_SC_EINT2 */ +#define CLEARWATER_IM_HP1L_SC_EINT2_SHIFT 0 /* IM_HP1L_SC_EINT2 */ +#define CLEARWATER_IM_HP1L_SC_EINT2_WIDTH 1 /* IM_HP1L_SC_EINT2 */ + +/* + * R6476 (0x194C) - IRQ2 Mask 13 + */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT2 0x0080 /* IM_SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT2_MASK 0x0080 /* IM_SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT2_SHIFT 7 /* IM_SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_ENABLE_DONE_EINT2_WIDTH 1 /* IM_SPKOUTR_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT2 0x0040 /* IM_SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT2_MASK 0x0040 /* IM_SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT2_SHIFT 6 /* IM_SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_ENABLE_DONE_EINT2_WIDTH 1 /* IM_SPKOUTL_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT2 0x0020 /* IM_HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT2_MASK 0x0020 /* IM_HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT2_SHIFT 5 /* IM_HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_ENABLE_DONE_EINT2_WIDTH 1 /* IM_HP3R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT2 0x0010 /* IM_HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT2_MASK 0x0010 /* IM_HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT2_SHIFT 4 /* IM_HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_ENABLE_DONE_EINT2_WIDTH 1 /* IM_HP3L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT2 0x0008 /* IM_HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT2_MASK 0x0008 /* IM_HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT2_SHIFT 3 /* IM_HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_ENABLE_DONE_EINT2_WIDTH 1 /* IM_HP2R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT2 0x0004 /* IM_HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT2_MASK 0x0004 /* IM_HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT2_SHIFT 2 /* IM_HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_ENABLE_DONE_EINT2_WIDTH 1 /* IM_HP2L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT2 0x0002 /* IM_HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT2_MASK 0x0002 /* IM_HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT2_SHIFT 1 /* IM_HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_ENABLE_DONE_EINT2_WIDTH 1 /* IM_HP1R_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT2 0x0001 /* IM_HP1L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT2_MASK 0x0001 /* IM_HP1L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT2_SHIFT 0 /* IM_HP1L_ENABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_ENABLE_DONE_EINT2_WIDTH 1 /* IM_HP1L_ENABLE_DONE_EINT2 */ + +/* + * R6477 (0x194D) - IRQ2 Mask 14 + */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT2 0x0080 /* IM_SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT2_MASK 0x0080 /* IM_SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT2_SHIFT 7 /* IM_SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTR_DISABLE_DONE_EINT2_WIDTH 1 /* IM_SPKOUTR_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT2 0x0040 /* IM_SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT2_MASK 0x0040 /* IM_SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT2_SHIFT 6 /* IM_SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_SPKOUTL_DISABLE_DONE_EINT2_WIDTH 1 /* IM_SPKOUTL_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT2 0x0020 /* IM_HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT2_MASK 0x0020 /* IM_HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT2_SHIFT 5 /* IM_HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3R_DISABLE_DONE_EINT2_WIDTH 1 /* IM_HP3R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT2 0x0010 /* IM_HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT2_MASK 0x0010 /* IM_HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT2_SHIFT 4 /* IM_HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP3L_DISABLE_DONE_EINT2_WIDTH 1 /* IM_HP3L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT2 0x0008 /* IM_HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT2_MASK 0x0008 /* IM_HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT2_SHIFT 3 /* IM_HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2R_DISABLE_DONE_EINT2_WIDTH 1 /* IM_HP2R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT2 0x0004 /* IM_HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT2_MASK 0x0004 /* IM_HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT2_SHIFT 2 /* IM_HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP2L_DISABLE_DONE_EINT2_WIDTH 1 /* IM_HP2L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT2 0x0002 /* IM_HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT2_MASK 0x0002 /* IM_HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT2_SHIFT 1 /* IM_HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1R_DISABLE_DONE_EINT2_WIDTH 1 /* IM_HP1R_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT2 0x0001 /* IM_HP1L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT2_MASK 0x0001 /* IM_HP1L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT2_SHIFT 0 /* IM_HP1L_DISABLE_DONE_EINT2 */ +#define CLEARWATER_IM_HP1L_DISABLE_DONE_EINT2_WIDTH 1 /* IM_HP1L_DISABLE_DONE_EINT2 */ + +/* + * R6478 (0x194E) - IRQ2 Mask 15 + */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT2 0x0004 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT2_MASK 0x0004 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT2_SHIFT 2 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT2 0x0002 /* IM_SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT2_MASK 0x0002 /* IM_SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT2_SHIFT 1 /* IM_SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_IM_SPK_OVERHEAT_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_EINT2 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT2 0x0001 /* IM_SPK_SHUTDOWN_EINT2 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT2_MASK 0x0001 /* IM_SPK_SHUTDOWN_EINT2 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT2_SHIFT 0 /* IM_SPK_SHUTDOWN_EINT2 */ +#define CLEARWATER_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */ + +/* + * R6528 (0x1980) - IRQ2 Raw Status 1 + */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS2 0x8000 /* DSP_SHARED_WR_COLL_STS2 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS2_MASK 0x8000 /* DSP_SHARED_WR_COLL_STS2 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS2_SHIFT 15 /* DSP_SHARED_WR_COLL_STS2 */ +#define CLEARWATER_DSP_SHARED_WR_COLL_STS2_WIDTH 1 /* DSP_SHARED_WR_COLL_STS2 */ +#define CLEARWATER_CTRLIF_ERR_STS2 0x1000 /* CTRLIF_ERR_STS2 */ +#define CLEARWATER_CTRLIF_ERR_STS2_MASK 0x1000 /* CTRLIF_ERR_STS2 */ +#define CLEARWATER_CTRLIF_ERR_STS2_SHIFT 12 /* CTRLIF_ERR_STS2 */ +#define CLEARWATER_CTRLIF_ERR_STS2_WIDTH 1 /* CTRLIF_ERR_STS2 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS2 0x0200 /* IRQ_NO_CLOCK_STS2 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS2_MASK 0x0200 /* IRQ_NO_CLOCK_STS2 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS2_SHIFT 9 /* IRQ_NO_CLOCK_STS2 */ +#define CLEARWATER_IRQ_NO_CLOCK_STS2_WIDTH 1 /* IRQ_NO_CLOCK_STS2 */ +#define CLEARWATER_CLOCK_DETECT_STS2 0x0100 /* CLOCK_DETECT_STS2 */ +#define CLEARWATER_CLOCK_DETECT_STS2_MASK 0x0100 /* CLOCK_DETECT_STS2 */ +#define CLEARWATER_CLOCK_DETECT_STS2_SHIFT 8 /* CLOCK_DETECT_STS2 */ +#define CLEARWATER_CLOCK_DETECT_STS2_WIDTH 1 /* CLOCK_DETECT_STS2 */ +#define CLEARWATER_BOOT_DONE_STS2 0x0080 /* BOOT_DONE_STS2 */ +#define CLEARWATER_BOOT_DONE_STS2_MASK 0x0080 /* BOOT_DONE_STS2 */ +#define CLEARWATER_BOOT_DONE_STS2_SHIFT 7 /* BOOT_DONE_STS2 */ +#define CLEARWATER_BOOT_DONE_STS2_WIDTH 1 /* BOOT_DONE_STS2 */ + +/* + * R6529 (0x1981) - IRQ2 Raw Status 2 + */ +#define CLEARWATER_FLL3_LOCK_STS2 0x0400 /* FLL3_LOCK_STS2 */ +#define CLEARWATER_FLL3_LOCK_STS2_MASK 0x0400 /* FLL3_LOCK_STS2 */ +#define CLEARWATER_FLL3_LOCK_STS2_SHIFT 10 /* FLL3_LOCK_STS2 */ +#define CLEARWATER_FLL3_LOCK_STS2_WIDTH 1 /* FLL3_LOCK_STS2 */ +#define CLEARWATER_FLL2_LOCK_STS2 0x0200 /* FLL2_LOCK_STS2 */ +#define CLEARWATER_FLL2_LOCK_STS2_MASK 0x0200 /* FLL2_LOCK_STS2 */ +#define CLEARWATER_FLL2_LOCK_STS2_SHIFT 9 /* FLL2_LOCK_STS2 */ +#define CLEARWATER_FLL2_LOCK_STS2_WIDTH 1 /* FLL2_LOCK_STS2 */ +#define CLEARWATER_FLL1_LOCK_STS2 0x0100 /* FLL1_LOCK_STS2 */ +#define CLEARWATER_FLL1_LOCK_STS2_MASK 0x0100 /* FLL1_LOCK_STS2 */ +#define CLEARWATER_FLL1_LOCK_STS2_SHIFT 8 /* FLL1_LOCK_STS2 */ +#define CLEARWATER_FLL1_LOCK_STS2_WIDTH 1 /* FLL1_LOCK_STS2 */ + +/* + * R6533 (0x1985) - IRQ2 Raw Status 6 + */ +#define CLEARWATER_MICDET_STS2 0x0100 /* MICDET_STS2 */ +#define CLEARWATER_MICDET_STS2_MASK 0x0100 /* MICDET_STS2 */ +#define CLEARWATER_MICDET_STS2_SHIFT 8 /* MICDET_STS2 */ +#define CLEARWATER_MICDET_STS2_WIDTH 1 /* MICDET_STS2 */ +#define CLEARWATER_HPDET_STS2 0x0001 /* HPDET_STS2 */ +#define CLEARWATER_HPDET_STS2_MASK 0x0001 /* HPDET_STS2 */ +#define CLEARWATER_HPDET_STS2_SHIFT 0 /* HPDET_STS2 */ +#define CLEARWATER_HPDET_STS2_WIDTH 1 /* HPDET_STS2 */ + +/* + * R6534 (0x1986) - IRQ2 Raw Status 7 + */ +#define CLEARWATER_MICD_CLAMP_FALL_STS2 0x0020 /* MICD_CLAMP_FALL_STS2 */ +#define CLEARWATER_MICD_CLAMP_FALL_STS2_MASK 0x0020 /* MICD_CLAMP_FALL_STS2 */ +#define CLEARWATER_MICD_CLAMP_FALL_STS2_SHIFT 5 /* MICD_CLAMP_FALL_STS2 */ +#define CLEARWATER_MICD_CLAMP_FALL_STS2_WIDTH 1 /* MICD_CLAMP_FALL_STS2 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS2 0x0010 /* MICD_CLAMP_RISE_STS2 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS2_MASK 0x0010 /* MICD_CLAMP_RISE_STS2 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS2_SHIFT 4 /* MICD_CLAMP_RISE_STS2 */ +#define CLEARWATER_MICD_CLAMP_RISE_STS2_WIDTH 1 /* MICD_CLAMP_RISE_STS2 */ +#define CLEARWATER_JD2_FALL_STS2 0x0008 /* JD2_FALL_STS2 */ +#define CLEARWATER_JD2_FALL_STS2_MASK 0x0008 /* JD2_FALL_STS2 */ +#define CLEARWATER_JD2_FALL_STS2_SHIFT 3 /* JD2_FALL_STS2 */ +#define CLEARWATER_JD2_FALL_STS2_WIDTH 1 /* JD2_FALL_STS2 */ +#define CLEARWATER_JD2_RISE_STS2 0x0004 /* JD2_RISE_STS2 */ +#define CLEARWATER_JD2_RISE_STS2_MASK 0x0004 /* JD2_RISE_STS2 */ +#define CLEARWATER_JD2_RISE_STS2_SHIFT 2 /* JD2_RISE_STS2 */ +#define CLEARWATER_JD2_RISE_STS2_WIDTH 1 /* JD2_RISE_STS2 */ +#define CLEARWATER_JD1_FALL_STS2 0x0002 /* JD1_FALL_STS2 */ +#define CLEARWATER_JD1_FALL_STS2_MASK 0x0002 /* JD1_FALL_STS2 */ +#define CLEARWATER_JD1_FALL_STS2_SHIFT 1 /* JD1_FALL_STS2 */ +#define CLEARWATER_JD1_FALL_STS2_WIDTH 1 /* JD1_FALL_STS2 */ +#define CLEARWATER_JD1_RISE_STS2 0x0001 /* JD1_RISE_STS2 */ +#define CLEARWATER_JD1_RISE_STS2_MASK 0x0001 /* JD1_RISE_STS2 */ +#define CLEARWATER_JD1_RISE_STS2_SHIFT 0 /* JD1_RISE_STS2 */ +#define CLEARWATER_JD1_RISE_STS2_WIDTH 1 /* JD1_RISE_STS2 */ + +/* + * R6536 (0x1988) - IRQ2 Raw Status 9 + */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS2 0x0800 /* ASRC2_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS2_MASK 0x0800 /* ASRC2_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS2_SHIFT 11 /* ASRC2_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN2_LOCK_STS2_WIDTH 1 /* ASRC2_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS2 0x0400 /* ASRC2_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS2_MASK 0x0400 /* ASRC2_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS2_SHIFT 10 /* ASRC2_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC2_IN1_LOCK_STS2_WIDTH 1 /* ASRC2_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS2 0x0200 /* ASRC1_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS2_MASK 0x0200 /* ASRC1_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS2_SHIFT 9 /* ASRC1_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN2_LOCK_STS2_WIDTH 1 /* ASRC1_IN2_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS2 0x0100 /* ASRC1_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS2_MASK 0x0100 /* ASRC1_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS2_SHIFT 8 /* ASRC1_IN1_LOCK_STS2 */ +#define CLEARWATER_ASRC1_IN1_LOCK_STS2_WIDTH 1 /* ASRC1_IN1_LOCK_STS2 */ +#define CLEARWATER_DRC2_SIG_DET_STS2 0x0002 /* DRC2_SIG_DET_STS2 */ +#define CLEARWATER_DRC2_SIG_DET_STS2_MASK 0x0002 /* DRC2_SIG_DET_STS2 */ +#define CLEARWATER_DRC2_SIG_DET_STS2_SHIFT 1 /* DRC2_SIG_DET_STS2 */ +#define CLEARWATER_DRC2_SIG_DET_STS2_WIDTH 1 /* DRC2_SIG_DET_STS2 */ +#define CLEARWATER_DRC1_SIG_DET_STS2 0x0001 /* DRC1_SIG_DET_STS2 */ +#define CLEARWATER_DRC1_SIG_DET_STS2_MASK 0x0001 /* DRC1_SIG_DET_STS2 */ +#define CLEARWATER_DRC1_SIG_DET_STS2_SHIFT 0 /* DRC1_SIG_DET_STS2 */ +#define CLEARWATER_DRC1_SIG_DET_STS2_WIDTH 1 /* DRC1_SIG_DET_STS2 */ + +/* + * R6538 (0x198A) - IRQ2 Raw Status 11 + */ +#define CLEARWATER_DSP_IRQ26_STS2 0x8000 /* DSP_IRQ26_STS2 */ +#define CLEARWATER_DSP_IRQ26_STS2_MASK 0x8000 /* DSP_IRQ26_STS2 */ +#define CLEARWATER_DSP_IRQ26_STS2_SHIFT 15 /* DSP_IRQ26_STS2 */ +#define CLEARWATER_DSP_IRQ26_STS2_WIDTH 1 /* DSP_IRQ26_STS2 */ +#define CLEARWATER_DSP_IRQ25_STS2 0x4000 /* DSP_IRQ25_STS2 */ +#define CLEARWATER_DSP_IRQ25_STS2_MASK 0x4000 /* DSP_IRQ25_STS2 */ +#define CLEARWATER_DSP_IRQ25_STS2_SHIFT 14 /* DSP_IRQ25_STS2 */ +#define CLEARWATER_DSP_IRQ25_STS2_WIDTH 1 /* DSP_IRQ25_STS2 */ +#define CLEARWATER_DSP_IRQ24_STS2 0x2000 /* DSP_IRQ24_STS2 */ +#define CLEARWATER_DSP_IRQ24_STS2_MASK 0x2000 /* DSP_IRQ24_STS2 */ +#define CLEARWATER_DSP_IRQ24_STS2_SHIFT 13 /* DSP_IRQ24_STS2 */ +#define CLEARWATER_DSP_IRQ24_STS2_WIDTH 1 /* DSP_IRQ24_STS2 */ +#define CLEARWATER_DSP_IRQ23_STS2 0x1000 /* DSP_IRQ23_STS2 */ +#define CLEARWATER_DSP_IRQ23_STS2_MASK 0x1000 /* DSP_IRQ23_STS2 */ +#define CLEARWATER_DSP_IRQ23_STS2_SHIFT 12 /* DSP_IRQ23_STS2 */ +#define CLEARWATER_DSP_IRQ23_STS2_WIDTH 1 /* DSP_IRQ23_STS2 */ +#define CLEARWATER_DSP_IRQ22_STS2 0x0800 /* DSP_IRQ22_STS2 */ +#define CLEARWATER_DSP_IRQ22_STS2_MASK 0x0800 /* DSP_IRQ22_STS2 */ +#define CLEARWATER_DSP_IRQ22_STS2_SHIFT 11 /* DSP_IRQ22_STS2 */ +#define CLEARWATER_DSP_IRQ22_STS2_WIDTH 1 /* DSP_IRQ22_STS2 */ +#define CLEARWATER_DSP_IRQ21_STS2 0x0400 /* DSP_IRQ21_STS2 */ +#define CLEARWATER_DSP_IRQ21_STS2_MASK 0x0400 /* DSP_IRQ21_STS2 */ +#define CLEARWATER_DSP_IRQ21_STS2_SHIFT 10 /* DSP_IRQ21_STS2 */ +#define CLEARWATER_DSP_IRQ21_STS2_WIDTH 1 /* DSP_IRQ21_STS2 */ +#define CLEARWATER_DSP_IRQ20_STS2 0x0200 /* DSP_IRQ20_STS2 */ +#define CLEARWATER_DSP_IRQ20_STS2_MASK 0x0200 /* DSP_IRQ20_STS2 */ +#define CLEARWATER_DSP_IRQ20_STS2_SHIFT 9 /* DSP_IRQ20_STS2 */ +#define CLEARWATER_DSP_IRQ20_STS2_WIDTH 1 /* DSP_IRQ20_STS2 */ +#define CLEARWATER_DSP_IRQ9_STS2 0x0100 /* DSP_IRQ9_STS2 */ +#define CLEARWATER_DSP_IRQ9_STS2_MASK 0x0100 /* DSP_IRQ9_STS2 */ +#define CLEARWATER_DSP_IRQ9_STS2_SHIFT 8 /* DSP_IRQ9_STS2 */ +#define CLEARWATER_DSP_IRQ9_STS2_WIDTH 1 /* DSP_IRQ9_STS2 */ +#define CLEARWATER_DSP_IRQ8_STS2 0x0080 /* DSP_IRQ8_STS2 */ +#define CLEARWATER_DSP_IRQ8_STS2_MASK 0x0080 /* DSP_IRQ8_STS2 */ +#define CLEARWATER_DSP_IRQ8_STS2_SHIFT 7 /* DSP_IRQ8_STS2 */ +#define CLEARWATER_DSP_IRQ8_STS2_WIDTH 1 /* DSP_IRQ8_STS2 */ +#define CLEARWATER_DSP_IRQ7_STS2 0x0040 /* DSP_IRQ7_STS2 */ +#define CLEARWATER_DSP_IRQ7_STS2_MASK 0x0040 /* DSP_IRQ7_STS2 */ +#define CLEARWATER_DSP_IRQ7_STS2_SHIFT 6 /* DSP_IRQ7_STS2 */ +#define CLEARWATER_DSP_IRQ7_STS2_WIDTH 1 /* DSP_IRQ7_STS2 */ +#define CLEARWATER_DSP_IRQ6_STS2 0x0020 /* DSP_IRQ6_STS2 */ +#define CLEARWATER_DSP_IRQ6_STS2_MASK 0x0020 /* DSP_IRQ6_STS2 */ +#define CLEARWATER_DSP_IRQ6_STS2_SHIFT 5 /* DSP_IRQ6_STS2 */ +#define CLEARWATER_DSP_IRQ6_STS2_WIDTH 1 /* DSP_IRQ6_STS2 */ +#define CLEARWATER_DSP_IRQ5_STS2 0x0010 /* DSP_IRQ5_STS2 */ +#define CLEARWATER_DSP_IRQ5_STS2_MASK 0x0010 /* DSP_IRQ5_STS2 */ +#define CLEARWATER_DSP_IRQ5_STS2_SHIFT 4 /* DSP_IRQ5_STS2 */ +#define CLEARWATER_DSP_IRQ5_STS2_WIDTH 1 /* DSP_IRQ5_STS2 */ +#define CLEARWATER_DSP_IRQ4_STS2 0x0008 /* DSP_IRQ4_STS2 */ +#define CLEARWATER_DSP_IRQ4_STS2_MASK 0x0008 /* DSP_IRQ4_STS2 */ +#define CLEARWATER_DSP_IRQ4_STS2_SHIFT 3 /* DSP_IRQ4_STS2 */ +#define CLEARWATER_DSP_IRQ4_STS2_WIDTH 1 /* DSP_IRQ4_STS2 */ +#define CLEARWATER_DSP_IRQ3_STS2 0x0004 /* DSP_IRQ3_STS2 */ +#define CLEARWATER_DSP_IRQ3_STS2_MASK 0x0004 /* DSP_IRQ3_STS2 */ +#define CLEARWATER_DSP_IRQ3_STS2_SHIFT 2 /* DSP_IRQ3_STS2 */ +#define CLEARWATER_DSP_IRQ3_STS2_WIDTH 1 /* DSP_IRQ3_STS2 */ +#define CLEARWATER_DSP_IRQ2_STS2 0x0002 /* DSP_IRQ2_STS2 */ +#define CLEARWATER_DSP_IRQ2_STS2_MASK 0x0002 /* DSP_IRQ2_STS2 */ +#define CLEARWATER_DSP_IRQ2_STS2_SHIFT 1 /* DSP_IRQ2_STS2 */ +#define CLEARWATER_DSP_IRQ2_STS2_WIDTH 1 /* DSP_IRQ2_STS2 */ +#define CLEARWATER_DSP_IRQ1_STS2 0x0001 /* DSP_IRQ1_STS2 */ +#define CLEARWATER_DSP_IRQ1_STS2_MASK 0x0001 /* DSP_IRQ1_STS2 */ +#define CLEARWATER_DSP_IRQ1_STS2_SHIFT 0 /* DSP_IRQ1_STS2 */ +#define CLEARWATER_DSP_IRQ1_STS2_WIDTH 1 /* DSP_IRQ1_STS2 */ + + +/* + * R6539 (0x198B) - IRQ2 Raw Status 12 + */ +#define CLEARWATER_SPKOUTR_SC_STS2 0x0080 /* SPKOUTR_SC_STS2 */ +#define CLEARWATER_SPKOUTR_SC_STS2_MASK 0x0080 /* SPKOUTR_SC_STS2 */ +#define CLEARWATER_SPKOUTR_SC_STS2_SHIFT 7 /* SPKOUTR_SC_STS2 */ +#define CLEARWATER_SPKOUTR_SC_STS2_WIDTH 1 /* SPKOUTR_SC_STS2 */ +#define CLEARWATER_SPKOUTL_SC_STS2 0x0040 /* SPKOUTL_SC_STS2 */ +#define CLEARWATER_SPKOUTL_SC_STS2_MASK 0x0040 /* SPKOUTL_SC_STS2 */ +#define CLEARWATER_SPKOUTL_SC_STS2_SHIFT 6 /* SPKOUTL_SC_STS2 */ +#define CLEARWATER_SPKOUTL_SC_STS2_WIDTH 1 /* SPKOUTL_SC_STS2 */ +#define CLEARWATER_HP3R_SC_STS2 0x0020 /* HP3R_SC_STS2 */ +#define CLEARWATER_HP3R_SC_STS2_MASK 0x0020 /* HP3R_SC_STS2 */ +#define CLEARWATER_HP3R_SC_STS2_SHIFT 5 /* HP3R_SC_STS2 */ +#define CLEARWATER_HP3R_SC_STS2_WIDTH 1 /* HP3R_SC_STS2 */ +#define CLEARWATER_HP3L_SC_STS2 0x0010 /* HP3L_SC_STS2 */ +#define CLEARWATER_HP3L_SC_STS2_MASK 0x0010 /* HP3L_SC_STS2 */ +#define CLEARWATER_HP3L_SC_STS2_SHIFT 4 /* HP3L_SC_STS2 */ +#define CLEARWATER_HP3L_SC_STS2_WIDTH 1 /* HP3L_SC_STS2 */ +#define CLEARWATER_HP2R_SC_STS2 0x0008 /* HP2R_SC_STS2 */ +#define CLEARWATER_HP2R_SC_STS2_MASK 0x0008 /* HP2R_SC_STS2 */ +#define CLEARWATER_HP2R_SC_STS2_SHIFT 3 /* HP2R_SC_STS2 */ +#define CLEARWATER_HP2R_SC_STS2_WIDTH 1 /* HP2R_SC_STS2 */ +#define CLEARWATER_HP2L_SC_STS2 0x0004 /* HP2L_SC_STS2 */ +#define CLEARWATER_HP2L_SC_STS2_MASK 0x0004 /* HP2L_SC_STS2 */ +#define CLEARWATER_HP2L_SC_STS2_SHIFT 2 /* HP2L_SC_STS2 */ +#define CLEARWATER_HP2L_SC_STS2_WIDTH 1 /* HP2L_SC_STS2 */ +#define CLEARWATER_HP1R_SC_STS2 0x0002 /* HP1R_SC_STS2 */ +#define CLEARWATER_HP1R_SC_STS2_MASK 0x0002 /* HP1R_SC_STS2 */ +#define CLEARWATER_HP1R_SC_STS2_SHIFT 1 /* HP1R_SC_STS2 */ +#define CLEARWATER_HP1R_SC_STS2_WIDTH 1 /* HP1R_SC_STS2 */ +#define CLEARWATER_HP1L_SC_STS2 0x0001 /* HP1L_SC_STS2 */ +#define CLEARWATER_HP1L_SC_STS2_MASK 0x0001 /* HP1L_SC_STS2 */ +#define CLEARWATER_HP1L_SC_STS2_SHIFT 0 /* HP1L_SC_STS2 */ +#define CLEARWATER_HP1L_SC_STS2_WIDTH 1 /* HP1L_SC_STS2 */ + +/* + * R6540 (0x198C) - IRQ2 Raw Status 13 + */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS2 0x0080 /* SPKOUTR_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS2_MASK 0x0080 /* SPKOUTR_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS2_SHIFT 7 /* SPKOUTR_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTR_ENABLE_DONE_STS2_WIDTH 1 /* SPKOUTR_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS2 0x0040 /* SPKOUTL_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS2_MASK 0x0040 /* SPKOUTL_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS2_SHIFT 6 /* SPKOUTL_ENABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_ENABLE_DONE_STS2_WIDTH 1 /* SPKOUTL_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS2 0x0020 /* HP3R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS2_MASK 0x0020 /* HP3R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS2_SHIFT 5 /* HP3R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_ENABLE_DONE_STS2_WIDTH 1 /* HP3R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS2 0x0010 /* HP3L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS2_MASK 0x0010 /* HP3L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS2_SHIFT 4 /* HP3L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_ENABLE_DONE_STS2_WIDTH 1 /* HP3L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS2 0x0008 /* HP2R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS2_MASK 0x0008 /* HP2R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS2_SHIFT 3 /* HP2R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_ENABLE_DONE_STS2_WIDTH 1 /* HP2R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS2 0x0004 /* HP2L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS2_MASK 0x0004 /* HP2L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS2_SHIFT 2 /* HP2L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_ENABLE_DONE_STS2_WIDTH 1 /* HP2L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS2 0x0002 /* HP1R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS2_MASK 0x0002 /* HP1R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS2_SHIFT 1 /* HP1R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_ENABLE_DONE_STS2_WIDTH 1 /* HP1R_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS2 0x0001 /* HP1L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS2_MASK 0x0001 /* HP1L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS2_SHIFT 0 /* HP1L_ENABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_ENABLE_DONE_STS2_WIDTH 1 /* HP1L_ENABLE_DONE_STS2 */ + +/* + * R6541 (0x198D) - IRQ2 Raw Status 14 + */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS2 0x0080 /* SPKOUTR_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS2_MASK 0x0080 /* SPKOUTR_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS2_SHIFT 7 /* SPKOUTR_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTR_DISABLE_DONE_STS2_WIDTH 1 /* SPKOUTR_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS2 0x0040 /* SPKOUTL_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS2_MASK 0x0040 /* SPKOUTL_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS2_SHIFT 6 /* SPKOUTL_DISABLE_DONE_STS2 */ +#define CLEARWATER_SPKOUTL_DISABLE_DONE_STS2_WIDTH 1 /* SPKOUTL_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS2 0x0020 /* HP3R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS2_MASK 0x0020 /* HP3R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS2_SHIFT 5 /* HP3R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3R_DISABLE_DONE_STS2_WIDTH 1 /* HP3R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS2 0x0010 /* HP3L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS2_MASK 0x0010 /* HP3L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS2_SHIFT 4 /* HP3L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP3L_DISABLE_DONE_STS2_WIDTH 1 /* HP3L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS2 0x0008 /* HP2R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS2_MASK 0x0008 /* HP2R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS2_SHIFT 3 /* HP2R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2R_DISABLE_DONE_STS2_WIDTH 1 /* HP2R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS2 0x0004 /* HP2L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS2_MASK 0x0004 /* HP2L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS2_SHIFT 2 /* HP2L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP2L_DISABLE_DONE_STS2_WIDTH 1 /* HP2L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS2 0x0002 /* HP1R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS2_MASK 0x0002 /* HP1R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS2_SHIFT 1 /* HP1R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1R_DISABLE_DONE_STS2_WIDTH 1 /* HP1R_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS2 0x0001 /* HP1L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS2_MASK 0x0001 /* HP1L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS2_SHIFT 0 /* HP1L_DISABLE_DONE_STS2 */ +#define CLEARWATER_HP1L_DISABLE_DONE_STS2_WIDTH 1 /* HP1L_DISABLE_DONE_STS2 */ + +/* + * R6542 (0x198E) - IRQ2 Raw Status 15 + */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS2 0x0004 /* SPK_OVERHEAT_WARN_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS2_MASK 0x0004 /* SPK_OVERHEAT_WARN_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS2_SHIFT 2 /* SPK_OVERHEAT_WARN_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_WARN_STS2_WIDTH 1 /* SPK_OVERHEAT_WARN_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_STS2 0x0002 /* SPK_OVERHEAT_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_STS2_MASK 0x0002 /* SPK_OVERHEAT_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_STS2_SHIFT 1 /* SPK_OVERHEAT_STS2 */ +#define CLEARWATER_SPK_OVERHEAT_STS2_WIDTH 1 /* SPK_OVERHEAT_STS2 */ +#define CLEARWATER_SPK_SHUTDOWN_STS2 0x0001 /* SPK_SHUTDOWN_STS2 */ +#define CLEARWATER_SPK_SHUTDOWN_STS2_MASK 0x0001 /* SPK_SHUTDOWN_STS2 */ +#define CLEARWATER_SPK_SHUTDOWN_STS2_SHIFT 0 /* SPK_SHUTDOWN_STS2 */ +#define CLEARWATER_SPK_SHUTDOWN_STS2_WIDTH 1 /* SPK_SHUTDOWN_STS2 */ + +/* + * R6662 (0x1A06) - Interrupt Debounce 7 + */ +#define CLEARWATER_MICD_CLAMP_DB 0x0010 /* MICD_CLAMP_DB */ +#define CLEARWATER_MICD_CLAMP_DB_MASK 0x0010 /* MICD_CLAMP_DB */ +#define CLEARWATER_MICD_CLAMP_DB_SHIFT 4 /* MICD_CLAMP_DB */ +#define CLEARWATER_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */ +#define CLEARWATER_JD2_DB 0x0004 /* JD2_DB */ +#define CLEARWATER_JD2_DB_MASK 0x0004 /* JD2_DB */ +#define CLEARWATER_JD2_DB_SHIFT 2 /* JD2_DB */ +#define CLEARWATER_JD2_DB_WIDTH 1 /* JD2_DB */ +#define CLEARWATER_JD1_DB 0x0001 /* JD1_DB */ +#define CLEARWATER_JD1_DB_MASK 0x0001 /* JD1_DB */ +#define CLEARWATER_JD1_DB_SHIFT 0 /* JD1_DB */ +#define CLEARWATER_JD1_DB_WIDTH 1 /* JD1_DB */ + +/* + * R6670 (0x1A0E) - Interrupt Debounce 15 + */ +#define CLEARWATER_SPK_OVERHEAT_WARN_DB 0x0004 /* SPK_OVERHEAT_WARN_DB */ +#define CLEARWATER_SPK_OVERHEAT_WARN_DB_MASK 0x0004 /* SPK_OVERHEAT_WARN_DB */ +#define CLEARWATER_SPK_OVERHEAT_WARN_DB_SHIFT 2 /* SPK_OVERHEAT_WARN_DB */ +#define CLEARWATER_SPK_OVERHEAT_WARN_DB_WIDTH 1 /* SPK_OVERHEAT_WARN_DB */ +#define CLEARWATER_SPK_OVERHEAT_DB 0x0002 /* SPK_OVERHEAT_DB */ +#define CLEARWATER_SPK_OVERHEAT_DB_MASK 0x0002 /* SPK_OVERHEAT_DB */ +#define CLEARWATER_SPK_OVERHEAT_DB_SHIFT 1 /* SPK_OVERHEAT_DB */ +#define CLEARWATER_SPK_OVERHEAT_DB_WIDTH 1 /* SPK_OVERHEAT_DB */ + +/* + * R6848 (0x1AC0) - GPIO Debounce Config + */ +#define CLEARWATER_GP_DBTIME_MASK 0x000F /* GP_DBTIME - [3:0] */ +#define CLEARWATER_GP_DBTIME_SHIFT 0 /* GP_DBTIME - [3:0] */ +#define CLEARWATER_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [3:0] */ + +/* + * R13304 (0x33F8) - OTP HPDET Calibration 1 + */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_11 0xFF000000 /* HP_OFFSET_11 - [31:24] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_11_MASK 0xFF000000 /* HP_OFFSET_11 - [31:24] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_11_SHIFT 24 /* HP_OFFSET_11 - [31:24] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_11_WIDTH 8 /* HP_OFFSET_11 - [31:24] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_10 0x00FF0000 /* HP_OFFSET_10 - [23:16] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_10_MASK 0x00FF0000 /* HP_OFFSET_10 - [23:16] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_10_SHIFT 16 /* HP_OFFSET_10 - [23:16] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_10_WIDTH 8 /* HP_OFFSET_10 - [23:16] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_01 0x0000FF00 /* HP_OFFSET_01 - [15:8] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_01_MASK 0x0000FF00 /* HP_OFFSET_01 - [15:8] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_01_SHIFT 8 /* HP_OFFSET_01 - [15:8] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_01_WIDTH 8 /* HP_OFFSET_01 - [15:8] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_00 0x000000FF /* HP_OFFSET_10 - [7:0] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_00_MASK 0x000000FF /* HP_OFFSET_10 - [7:0] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_00_SHIFT 0 /* HP_OFFSET_10 - [7:0] */ +#define CLEARWATER_OTP_HPDET_CALIB_OFFSET_00_WIDTH 8 /* HP_OFFSET_10 - [7:0] */ + +/* + * R13306 (0x33FA) - OTP HPDET Calibration 2 + */ +#define CLEARWATER_OTP_HPDET_GRADIENT_1X 0xFF00 /* HP_GRADIENT_1X - [15:8] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_1X_MASK 0xFF00 /* HP_GRADIENT_1X - [15:8] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_1X_SHIFT 8 /* HP_GRADIENT_1X - [15:8] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_1X_WIDTH 8 /* HP_GRADIENT_1X - [15:8] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_0X 0x00FF /* HP_GRADIENT_0X - [7:0] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_0X_MASK 0x00FF /* HP_GRADIENT_0X - [7:0] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_0X_SHIFT 0 /* HP_GRADIENT_0X - [7:0] */ +#define CLEARWATER_OTP_HPDET_GRADIENT_0X_WIDTH 8 /* HP_GRADIENT_0X - [7:0] */ + #endif diff --git a/include/linux/regmap.h b/include/linux/regmap.h index e73b72512fd..b85c4b3874d 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -49,6 +49,20 @@ struct reg_default { unsigned int def; }; +/** + * Register/value pairs for sequences of writes with an optional delay in + * microseconds to be applied after each write. + * + * @reg: Register address. + * @def: Register value. + * @delay_us: Delay to be applied after the register write in microseconds + */ +struct reg_sequence { + unsigned int reg; + unsigned int def; + unsigned int delay_us; +}; + #ifdef CONFIG_REGMAP enum regmap_endian { @@ -385,10 +399,10 @@ int regmap_raw_write(struct regmap *map, unsigned int reg, const void *val, size_t val_len); int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val, size_t val_count); -int regmap_multi_reg_write(struct regmap *map, const struct reg_default *regs, +int regmap_multi_reg_write(struct regmap *map, const struct reg_sequence *regs, int num_regs); int regmap_multi_reg_write_bypassed(struct regmap *map, - const struct reg_default *regs, + const struct reg_sequence *regs, int num_regs); int regmap_raw_write_async(struct regmap *map, unsigned int reg, const void *val, size_t val_len); @@ -413,7 +427,7 @@ void regcache_cache_only(struct regmap *map, bool enable); void regcache_cache_bypass(struct regmap *map, bool enable); void regcache_mark_dirty(struct regmap *map); -int regmap_register_patch(struct regmap *map, const struct reg_default *regs, +int regmap_register_patch(struct regmap *map, const struct reg_sequence *regs, int num_regs); static inline bool regmap_reg_in_range(unsigned int reg, diff --git a/include/linux/switch-arizona.h b/include/linux/switch-arizona.h new file mode 100644 index 00000000000..eafcc376b95 --- /dev/null +++ b/include/linux/switch-arizona.h @@ -0,0 +1,97 @@ +/* + * extcon-arizona.h - Extcon driver Wolfson Arizona devices + * + * Copyright (C) 2014 Wolfson Microelectronics plc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SWITCH_ARIZONA_H_ +#define _SWITCH_ARIZONA_H_ + +#include +#include + +#define ARIZONA_ACCDET_MODE_MIC 0 +#define ARIZONA_ACCDET_MODE_HPL 1 +#define ARIZONA_ACCDET_MODE_HPR 2 +#define ARIZONA_ACCDET_MODE_HPM 4 +#define ARIZONA_ACCDET_MODE_ADC 7 +#define ARIZONA_ACCDET_MODE_INVALID 8 + +#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \ + ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \ + ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \ + ARIZONA_MICD_LVL_7) + +#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7) + +#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8) + +struct arizona_extcon_info; + +struct arizona_jd_state { + int mode; + + int (*start)(struct arizona_extcon_info *); + void (*restart)(struct arizona_extcon_info *); + int (*reading)(struct arizona_extcon_info *, int); + void (*stop)(struct arizona_extcon_info *); + + int (*timeout_ms)(struct arizona_extcon_info *); + void (*timeout)(struct arizona_extcon_info *); +}; + +int arizona_jds_set_state(struct arizona_extcon_info *info, + const struct arizona_jd_state *new_state); + +extern void arizona_set_headphone_imp(struct arizona_extcon_info *info, + int imp); + +extern const struct arizona_jd_state arizona_hpdet_moisture; +extern const struct arizona_jd_state arizona_hpdet_moisture_r; +extern const struct arizona_jd_state arizona_hpdet_left; +extern const struct arizona_jd_state arizona_hpdet_right; +extern const struct arizona_jd_state arizona_micd_button; +extern const struct arizona_jd_state arizona_micd_microphone; +extern const struct arizona_jd_state arizona_micd_adc_mic; +extern const struct arizona_jd_state arizona_hpdet_acc_id; +extern const struct arizona_jd_state arizona_antenna_moisture; +extern const struct arizona_jd_state arizona_antenna_moisture_r; +extern const struct arizona_jd_state arizona_antenna_mic_det; +extern const struct arizona_jd_state arizona_antenna_oc_det; +extern const struct arizona_jd_state arizona_antenna_hp_det; +extern const struct arizona_jd_state arizona_antenna_hpr_det; +extern const struct arizona_jd_state arizona_antenna_button_det; +extern const struct arizona_jd_state arizona_antenna_button_check; +extern const struct arizona_jd_state arizona_antenna_remove_det; + +extern int arizona_hpdet_start(struct arizona_extcon_info *info); +extern void arizona_hpdet_restart(struct arizona_extcon_info *info); +extern void arizona_hpdet_stop(struct arizona_extcon_info *info); +extern int arizona_hpdet_reading(struct arizona_extcon_info *info, int val); + +extern int arizona_micd_start(struct arizona_extcon_info *info); +extern void arizona_micd_stop(struct arizona_extcon_info *info); +extern int arizona_micd_button_reading(struct arizona_extcon_info *info, + int val); + +extern int arizona_micd_mic_start(struct arizona_extcon_info *info); +extern void arizona_micd_mic_stop(struct arizona_extcon_info *info); +extern int arizona_micd_mic_reading(struct arizona_extcon_info *info, int val); +extern int arizona_micd_mic_timeout_ms(struct arizona_extcon_info *info); +extern void arizona_micd_mic_timeout(struct arizona_extcon_info *info); + +extern void arizona_extcon_report(struct arizona_extcon_info *info, int state); + +extern int arizona_extcon_take_manual_mic_reading(struct arizona_extcon_info *info); + +#endif diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index 8bb3a7b11f8..e3290fd998b 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -104,6 +104,9 @@ struct device; { .id = snd_soc_dapm_value_mux, .name = wname, .reg = wreg, \ .shift = wshift, .invert = winvert, .kcontrol_news = wcontrols, \ .num_kcontrols = 1} +#define SND_SOC_DAPM_DEMUX(wname, wreg, wshift, winvert, wcontrols) \ +{ .id = snd_soc_dapm_demux, .name = wname, .reg = wreg, .shift = wshift, \ + .invert = winvert, .kcontrol_news = wcontrols, .num_kcontrols = 1} /* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ #define SOC_PGA_ARRAY(wname, wreg, wshift, winvert,\ @@ -156,6 +159,11 @@ struct device; { .id = snd_soc_dapm_virt_mux, .name = wname, .reg = wreg, .shift = wshift, \ .invert = winvert, .kcontrol_news = wcontrols, .num_kcontrols = 1, \ .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_DEMUX_E(wname, wreg, wshift, winvert, wcontrols, wevent, \ + wflags) \ +{ .id = snd_soc_dapm_demux, .name = wname, .reg = wreg, .shift = wshift, \ + .invert = winvert, .kcontrol_news = wcontrols, .num_kcontrols = 1, \ + .event = wevent, .event_flags = wflags} /* additional sequencing control within an event type */ #define SND_SOC_DAPM_PGA_S(wname, wsubseq, wreg, wshift, winvert, \ @@ -432,6 +440,7 @@ enum snd_soc_dapm_type { snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */ snd_soc_dapm_virt_mux, /* virtual version of snd_soc_dapm_mux */ snd_soc_dapm_value_mux, /* selects 1 analog signal from many inputs */ + snd_soc_dapm_demux, /* connects the input to one of multiple outputs */ snd_soc_dapm_mixer, /* mixes several analog signals together */ snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */ snd_soc_dapm_pga, /* programmable gain/attenuation (volume) */ @@ -500,6 +509,7 @@ struct snd_soc_dapm_path { struct list_head list_source; struct list_head list_sink; + struct list_head list_kcontrol; struct list_head list; }; @@ -568,6 +578,10 @@ struct snd_soc_dapm_update { int val; }; +struct snd_soc_dapm_wcache { + struct snd_soc_dapm_widget *widget; +}; + /* DAPM context */ struct snd_soc_dapm_context { enum snd_soc_bias_level bias_level; @@ -591,6 +605,9 @@ struct snd_soc_dapm_context { int (*stream_event)(struct snd_soc_dapm_context *dapm, int event); + struct snd_soc_dapm_wcache path_sink_cache; + struct snd_soc_dapm_wcache path_source_cache; + #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_dapm; #endif diff --git a/include/sound/soc.h b/include/sound/soc.h index 4de92a7e99a..30c8bdc51c7 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -246,6 +246,8 @@ .info = snd_soc_info_enum_ext, \ .get = xhandler_get, .put = xhandler_put, \ .private_value = (unsigned long)&xenum } +#define SOC_VALUE_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) \ + SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) #define SND_SOC_BYTES(xname, xbase, xregs) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ @@ -262,6 +264,13 @@ {.base = xbase, .num_regs = xregs, \ .mask = xmask }) } +#define SND_SOC_BYTES_EXT(xname, xcount, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&(struct soc_bytes_ext) \ + {.max = xcount} } + #define SOC_SINGLE_XR_SX(xname, xregbase, xregcount, xnbits, \ xmin, xmax, xinvert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ @@ -491,6 +500,8 @@ void snd_soc_card_change_online_state(struct snd_soc_card *soc_card, struct snd_kcontrol *snd_soc_cnew(const struct snd_kcontrol_new *_template, void *data, const char *long_name, const char *prefix); +struct snd_kcontrol *snd_soc_card_get_kcontrol(struct snd_soc_card *soc_card, + const char *name); int snd_soc_add_codec_controls(struct snd_soc_codec *codec, const struct snd_kcontrol_new *controls, int num_controls); int snd_soc_add_platform_controls(struct snd_soc_platform *platform, @@ -546,6 +557,8 @@ int snd_soc_bytes_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int snd_soc_bytes_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int snd_soc_bytes_info_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *ucontrol); int snd_soc_info_xr_sx(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo); int snd_soc_get_xr_sx(struct snd_kcontrol *kcontrol, @@ -1145,6 +1158,10 @@ struct soc_bytes { u32 mask; }; +struct soc_bytes_ext { + int max; +}; + /* multi register control */ struct soc_mreg_control { long min, max; diff --git a/include/uapi/sound/compress_offload.h b/include/uapi/sound/compress_offload.h index a2f5baa4011..08b6af5e265 100644 --- a/include/uapi/sound/compress_offload.h +++ b/include/uapi/sound/compress_offload.h @@ -39,7 +39,7 @@ struct snd_compressed_buffer { __u32 fragment_size; __u32 fragments; -}; +} __attribute__((packed, aligned(4))); /** * struct snd_compr_params: compressed stream params @@ -51,7 +51,7 @@ struct snd_compr_params { struct snd_compressed_buffer buffer; struct snd_codec codec; __u8 no_wake_mode; -}; +} __attribute__((packed, aligned(4))); /** * struct snd_compr_tstamp: timestamp descriptor @@ -71,7 +71,7 @@ struct snd_compr_tstamp { __u32 pcm_io_frames; __u32 sampling_rate; uint64_t timestamp; -}; +} __attribute__((packed, aligned(4))); /** * struct snd_compr_avail: avail descriptor @@ -81,7 +81,7 @@ struct snd_compr_tstamp { struct snd_compr_avail { __u64 avail; struct snd_compr_tstamp tstamp; -} __attribute__((packed)); +} __attribute__((packed, aligned(4))); enum snd_compr_direction { SND_COMPRESS_PLAYBACK = 0, @@ -108,7 +108,7 @@ struct snd_compr_caps { __u32 max_fragments; __u32 codecs[MAX_NUM_CODECS]; __u32 reserved[11]; -}; +} __attribute__((packed, aligned(4))); /** * struct snd_compr_codec_caps: query capability of codec @@ -120,7 +120,7 @@ struct snd_compr_codec_caps { __u32 codec; __u32 num_descriptors; struct snd_codec_desc descriptor[MAX_NUM_CODEC_DESCRIPTORS]; -}; +} __attribute__((packed, aligned(4))); /** * struct snd_compr_audio_info: compressed input audio information @@ -153,7 +153,7 @@ enum { struct snd_compr_metadata { __u32 key; __u32 value[8]; -}; +} __attribute__((packed, aligned(4))); /** * compress path ioctl definitions diff --git a/include/uapi/sound/compress_params.h b/include/uapi/sound/compress_params.h index b2697b41e1f..2afba80aa9a 100644 --- a/include/uapi/sound/compress_params.h +++ b/include/uapi/sound/compress_params.h @@ -57,6 +57,7 @@ #define MAX_NUM_CODECS 32 #define MAX_NUM_CODEC_DESCRIPTORS 32 #define MAX_NUM_BITRATES 32 +#define MAX_NUM_SAMPLE_RATES 32 /* compressed TX */ #define MAX_NUM_FRAMES_PER_BUFFER 1 @@ -294,7 +295,7 @@ struct snd_enc_vorbis { __u32 max_bit_rate; __u32 min_bit_rate; __u32 downmix; -}; +} __attribute__((packed, aligned(4))); /** @@ -310,7 +311,7 @@ struct snd_enc_real { __u32 quant_bits; __u32 start_region; __u32 num_regions; -}; +} __attribute__((packed, aligned(4))); /** * struct snd_enc_flac @@ -334,28 +335,28 @@ struct snd_enc_real { struct snd_enc_flac { __u32 num; __u32 gain; -}; +} __attribute__((packed, aligned(4))); struct snd_enc_generic { __u32 bw; /* encoder bandwidth */ __s32 reserved[15]; -}; +} __attribute__((packed, aligned(4))); struct snd_dec_ddp { __u32 params_length; __u32 params_id[18]; __u32 params_value[18]; -}; +} __attribute__((packed, aligned(4))); struct snd_dec_flac { __u16 sample_size; __u16 min_blk_size; __u16 max_blk_size; __u16 min_frame_size; __u16 max_frame_size; -}; +} __attribute__((packed, aligned(4))); struct snd_dec_vorbis { __u32 bit_stream_fmt; -}; +} __attribute__((packed, aligned(4))); struct snd_dec_alac { __u32 frame_length; @@ -370,7 +371,7 @@ struct snd_dec_alac { __u32 avg_bit_rate; __u32 sample_rate; __u32 channel_layout_tag; -}; +} __attribute__((packed, aligned(4))); struct snd_dec_ape { __u16 compatible_version; @@ -383,7 +384,7 @@ struct snd_dec_ape { __u16 num_channels; __u32 sample_rate; __u32 seek_table_present; -}; +} __attribute__((packed, aligned(4))); union snd_codec_options { struct snd_enc_wma wma; @@ -396,11 +397,12 @@ union snd_codec_options { struct snd_dec_vorbis vorbis_dec; struct snd_dec_alac alac; struct snd_dec_ape ape; -}; +} __attribute__((packed, aligned(4))); /** struct snd_codec_desc - description of codec capabilities * @max_ch: Maximum number of audio channels - * @sample_rates: Sampling rates in Hz, use SNDRV_PCM_RATE_xxx for this + * @sample_rates: Sampling rates in Hz, use values like 48000 for this + * @num_sample_rates: Number of valid values in sample_rates array * @bit_rate: Indexed array containing supported bit rates * @num_bitrates: Number of valid values in bit_rate array * @rate_control: value is specified by SND_RATECONTROLMODE defines. @@ -422,7 +424,8 @@ union snd_codec_options { struct snd_codec_desc { __u32 max_ch; - __u32 sample_rates; + __u32 sample_rates[MAX_NUM_SAMPLE_RATES]; + __u32 num_sample_rates; __u32 bit_rate[MAX_NUM_BITRATES]; __u32 num_bitrates; __u32 rate_control; @@ -431,7 +434,7 @@ struct snd_codec_desc { __u32 formats; __u32 min_buffer; __u32 reserved[15]; -}; +} __attribute__((packed, aligned(4))); /** struct snd_codec * @id: Identifies the supported audio encoder/decoder. @@ -440,7 +443,8 @@ struct snd_codec_desc { * @ch_out: Number of output channels. In case of contradiction between * this field and the channelMode field, the channelMode field * overrides. - * @sample_rate: Audio sample rate of input data + * @sample_rate: Audio sample rate of input data in Hz, use values like 48000 + * for this. * @bit_rate: Bitrate of encoded data. May be ignored by decoders * @rate_control: Encoding rate control. See SND_RATECONTROLMODE defines. * Encoders may rely on profiles for quality levels. @@ -472,6 +476,6 @@ struct snd_codec { __u32 compr_passthr; union snd_codec_options options; __u32 reserved[3]; -}; +} __attribute__((packed, aligned(4))); #endif diff --git a/sound/core/compress_offload.c b/sound/core/compress_offload.c index 9adcfbf563b..e4ab93ee1b2 100644 --- a/sound/core/compress_offload.c +++ b/sound/core/compress_offload.c @@ -517,9 +517,6 @@ static int snd_compress_check_input(struct snd_compr_params *params) if (params->codec.ch_in == 0 || params->codec.ch_out == 0) return -EINVAL; - if (!(params->codec.sample_rate & SNDRV_PCM_RATE_8000_192000)) - return -EINVAL; - return 0; } diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 6c6d891abaa..fc981817c2f 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -35,6 +35,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_CS42L73 if I2C select SND_SOC_CS4270 if I2C select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI + select SND_SOC_LARGO if MFD_LARGO select SND_SOC_CX20442 if TTY select SND_SOC_DA7210 if I2C select SND_SOC_DA7213 if I2C @@ -80,7 +81,11 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM2000 if I2C select SND_SOC_WM5100 if I2C select SND_SOC_WM5102 if MFD_WM5102 - select SND_SOC_WM5110 if MFD_WM5110 + select SND_SOC_FLORIDA if MFD_FLORIDA + select SND_SOC_CLEARWATER if MFD_CLEARWATER + select SND_SOC_MARLEY if MFD_MARLEY + select SND_SOC_MOON if MFD_MOON + select SND_SOC_CS47L15 if MFD_CS47L15 select SND_SOC_WM8350 if MFD_WM8350 select SND_SOC_WM8400 if MFD_WM8400 select SND_SOC_WM8510 if SND_SOC_I2C_AND_SPI @@ -118,6 +123,8 @@ config SND_SOC_ALL_CODECS select SND_SOC_WM8994 if MFD_WM8994 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI select SND_SOC_WM8996 if I2C + select SND_SOC_WM8997 if MFD_WM8997 + select SND_SOC_VEGAS if MFD_VEGAS select SND_SOC_WM9081 if I2C select SND_SOC_WM9090 if I2C select SND_SOC_WM9705 if SND_SOC_AC97_BUS @@ -140,9 +147,23 @@ config SND_SOC_88PM860X config SND_SOC_ARIZONA tristate default y if SND_SOC_WM5102=y - default y if SND_SOC_WM5110=y + default y if SND_SOC_FLORIDA=y + default y if SND_SOC_CLEARWATER=y + default y if SND_SOC_MARLEY=y + default y if SND_SOC_MOON=y + default y if SND_SOC_WM8997=y + default y if SND_SOC_VEGAS=y + default y if SND_SOC_LARGO=y + default y if SND_SOC_CS47L15=y default m if SND_SOC_WM5102=m - default m if SND_SOC_WM5110=m + default m if SND_SOC_FLORIDA=m + default m if SND_SOC_CLEARWATER=m + default m if SND_SOC_MARLEY=m + default m if SND_SOC_MOON=m + default m if SND_SOC_WM8997=m + default m if SND_SOC_VEGAS=m + default m if SND_SOC_LARGO=m + default m if SND_SOC_CS47L15=m config SND_SOC_WM_HUBS tristate @@ -152,9 +173,19 @@ config SND_SOC_WM_HUBS config SND_SOC_WM_ADSP tristate default y if SND_SOC_WM5102=y + default y if SND_SOC_FLORIDA=y + default y if SND_SOC_CLEARWATER=y + default y if SND_SOC_MOON=y default y if SND_SOC_WM2200=y + default y if SND_SOC_LARGO=y + default y if SND_SOC_MARLEY=y default m if SND_SOC_WM5102=m + default m if SND_SOC_FLORIDA=m + default m if SND_SOC_CLEARWATER=m + default m if SND_SOC_MOON=m default m if SND_SOC_WM2200=m + default m if SND_SOC_LARGO=m + default m if SND_SOC_MARLEY=m config SND_SOC_AB8500_CODEC tristate @@ -238,6 +269,9 @@ config SND_SOC_CS4270_VD33_ERRATA config SND_SOC_CS4271 tristate +config SND_SOC_LARGO + tristate + config SND_SOC_CX20442 tristate depends on TTY @@ -426,7 +460,19 @@ config SND_SOC_WM5100 config SND_SOC_WM5102 tristate -config SND_SOC_WM5110 +config SND_SOC_FLORIDA + tristate + +config SND_SOC_CLEARWATER + tristate + +config SND_SOC_MARLEY + tristate + +config SND_SOC_MOON + tristate + +config SND_SOC_CS47L15 tristate config SND_SOC_WM8350 @@ -540,6 +586,12 @@ config SND_SOC_WM8995 config SND_SOC_WM8996 tristate +config SND_SOC_WM8997 + tristate + +config SND_SOC_VEGAS + tristate + config SND_SOC_WM9081 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 73baa99493f..bf0360b8987 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -22,6 +22,7 @@ snd-soc-cs42l52-objs := cs42l52.o snd-soc-cs42l73-objs := cs42l73.o snd-soc-cs4270-objs := cs4270.o snd-soc-cs4271-objs := cs4271.o +snd-soc-largo-objs := largo.o snd-soc-cx20442-objs := cx20442.o snd-soc-da7210-objs := da7210.o snd-soc-da7213-objs := da7213.o @@ -94,7 +95,11 @@ snd-soc-wm2000-objs := wm2000.o snd-soc-wm2200-objs := wm2200.o snd-soc-wm5100-objs := wm5100.o wm5100-tables.o snd-soc-wm5102-objs := wm5102.o -snd-soc-wm5110-objs := wm5110.o +snd-soc-florida-objs := florida.o +snd-soc-clearwater-objs := clearwater.o +snd-soc-marley-objs := marley.o +snd-soc-moon-objs := moon.o +snd-soc-cs47l15-objs := cs47l15.o snd-soc-wm8350-objs := wm8350.o snd-soc-wm8400-objs := wm8400.o snd-soc-wm8510-objs := wm8510.o @@ -132,6 +137,8 @@ snd-soc-wm8991-objs := wm8991.o snd-soc-wm8993-objs := wm8993.o snd-soc-wm8994-objs := wm8994.o wm8958-dsp2.o snd-soc-wm8995-objs := wm8995.o +snd-soc-wm8997-objs := wm8997.o +snd-soc-vegas-objs := vegas.o snd-soc-wm9081-objs := wm9081.o snd-soc-wm9090-objs := wm9090.o snd-soc-wm9705-objs := wm9705.o @@ -172,6 +179,7 @@ obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o +obj-$(CONFIG_SND_SOC_LARGO) += snd-soc-largo.o obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o @@ -234,7 +242,11 @@ obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o obj-$(CONFIG_SND_SOC_WM2200) += snd-soc-wm2200.o obj-$(CONFIG_SND_SOC_WM5100) += snd-soc-wm5100.o obj-$(CONFIG_SND_SOC_WM5102) += snd-soc-wm5102.o -obj-$(CONFIG_SND_SOC_WM5110) += snd-soc-wm5110.o +obj-$(CONFIG_SND_SOC_FLORIDA) += snd-soc-florida.o +obj-$(CONFIG_SND_SOC_CLEARWATER) += snd-soc-clearwater.o +obj-$(CONFIG_SND_SOC_MARLEY) += snd-soc-marley.o +obj-$(CONFIG_SND_SOC_MOON) += snd-soc-moon.o +obj-$(CONFIG_SND_SOC_CS47L15) += snd-soc-cs47l15.o obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o obj-$(CONFIG_SND_SOC_WM8400) += snd-soc-wm8400.o obj-$(CONFIG_SND_SOC_WM8510) += snd-soc-wm8510.o @@ -272,6 +284,8 @@ obj-$(CONFIG_SND_SOC_WM8991) += snd-soc-wm8991.o obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o +obj-$(CONFIG_SND_SOC_WM8997) += snd-soc-wm8997.o +obj-$(CONFIG_SND_SOC_VEGAS) += snd-soc-vegas.o obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o obj-$(CONFIG_SND_SOC_WM9090) += snd-soc-wm9090.o obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c index 56815af4e00..c76653f9a02 100644 --- a/sound/soc/codecs/arizona.c +++ b/sound/soc/codecs/arizona.c @@ -1,6 +1,7 @@ /* * arizona.c - Wolfson Arizona class device shared support * + * Copyright 2014 Cirrus Logic * Copyright 2012 Wolfson Microelectronics plc * * Author: Mark Brown @@ -14,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +54,29 @@ #define ARIZONA_AIF_RX_ENABLES 0x1A #define ARIZONA_AIF_FORCE_WRITE 0x1B +#define ARIZONA_FLL_VCO_CORNER 141900000 +#define ARIZONA_FLL_MAX_FREF 13500000 +#define ARIZONA_FLL_MAX_N 1023 +#define ARIZONA_FLLAO_MAX_FREF 12288000 +#define ARIZONA_FLLAO_MIN_N 4 +#define ARIZONA_FLLAO_MAX_N 1023 +#define ARIZONA_FLLAO_MAX_FBDIV 254 +#define ARIZONA_FLL_MIN_FVCO 90000000 +#define ARIZONA_FLL_MAX_FRATIO 16 +#define ARIZONA_FLL_MAX_REFDIV 8 +#define ARIZONA_FLL_MIN_OUTDIV 2 +#define ARIZONA_FLL_MAX_OUTDIV 7 +#define ARIZONA_FLL_SYNC_OFFSET 0x10 + +#define ARIZONA_FMT_DSP_MODE_A 0 +#define ARIZONA_FMT_DSP_MODE_B 1 +#define ARIZONA_FMT_I2S_MODE 2 +#define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3 + +#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ +#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ +#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ + #define arizona_fll_err(_fll, fmt, ...) \ dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) #define arizona_fll_warn(_fll, fmt, ...) \ @@ -66,39 +91,468 @@ #define arizona_aif_dbg(_dai, fmt, ...) \ dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) -static int arizona_spk_ev(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) +static const int arizona_aif1_inputs[32] = { + ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE, + ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE, + ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE, + ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE, + ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE, +}; + +static const int arizona_aif2_inputs[32] = { + ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX7MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX7MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX7MIX_INPUT_4_SOURCE, + ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE, + ARIZONA_AIF2TX8MIX_INPUT_2_SOURCE, + ARIZONA_AIF2TX8MIX_INPUT_3_SOURCE, + ARIZONA_AIF2TX8MIX_INPUT_4_SOURCE, +}; + +static const int arizona_aif3_inputs[8] = { + ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE, + ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE, + ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE, + ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE, + ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE, + ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE, + ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE, + ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE, +}; + +static const int arizona_aif4_inputs[8] = { + ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE, + ARIZONA_AIF4TX1MIX_INPUT_2_SOURCE, + ARIZONA_AIF4TX1MIX_INPUT_3_SOURCE, + ARIZONA_AIF4TX1MIX_INPUT_4_SOURCE, + ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE, + ARIZONA_AIF4TX2MIX_INPUT_2_SOURCE, + ARIZONA_AIF4TX2MIX_INPUT_3_SOURCE, + ARIZONA_AIF4TX2MIX_INPUT_4_SOURCE, +}; + +static unsigned int arizona_aif_sources_cache[ARRAY_SIZE(arizona_aif1_inputs)]; + +struct fllao_patch { + unsigned int fin; + unsigned int fout; + struct reg_sequence *patch; + unsigned int patch_size; +}; + +static struct reg_sequence fll_ao_32K_49M_patch[] = { + { MOON_FLLAO_CONTROL_2, 0x02EE }, + { MOON_FLLAO_CONTROL_3, 0x0000 }, + { MOON_FLLAO_CONTROL_4, 0x0001 }, + { MOON_FLLAO_CONTROL_5, 0x0002 }, + { MOON_FLLAO_CONTROL_6, 0x8001 }, + { MOON_FLLAO_CONTROL_7, 0x0004 }, + { MOON_FLLAO_CONTROL_8, 0x0077 }, + { MOON_FLLAO_CONTROL_10, 0x06D8 }, + { MOON_FLLAO_CONTROL_11, 0x0085 }, + { MOON_FLLAO_CONTROL_2, 0x82EE }, +}; + +static struct reg_sequence fll_ao_32K_45M_patch[] = { + { MOON_FLLAO_CONTROL_2, 0x02B1 }, + { MOON_FLLAO_CONTROL_3, 0x0001 }, + { MOON_FLLAO_CONTROL_4, 0x0010 }, + { MOON_FLLAO_CONTROL_5, 0x0002 }, + { MOON_FLLAO_CONTROL_6, 0x8001 }, + { MOON_FLLAO_CONTROL_7, 0x0004 }, + { MOON_FLLAO_CONTROL_8, 0x0077 }, + { MOON_FLLAO_CONTROL_10, 0x06D8 }, + { MOON_FLLAO_CONTROL_11, 0x0005 }, + { MOON_FLLAO_CONTROL_2, 0x82B1 }, +}; + +static const struct fllao_patch fllao_settings[] = { + { + .fin = 32768, + .fout = 49152000, + .patch = fll_ao_32K_49M_patch, + .patch_size = ARRAY_SIZE(fll_ao_32K_49M_patch), + + }, + { + .fin = 32768, + .fout = 45158400, + .patch = fll_ao_32K_45M_patch, + .patch_size = ARRAY_SIZE(fll_ao_32K_45M_patch), + }, +}; + +static int arizona_get_sources(struct arizona *arizona, + struct snd_soc_dai *dai, + const int **source, int *lim) { - struct snd_soc_codec *codec = w->codec; - struct arizona *arizona = dev_get_drvdata(codec->dev->parent); - struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); - bool manual_ena = false; - int val; + int ret = 0; - switch (arizona->type) { - case WM5102: - switch (arizona->rev) { - case 0: + *lim = dai->driver->playback.channels_max * 4; + + switch (dai->driver->base) { + case ARIZONA_AIF1_BCLK_CTRL: + *source = arizona_aif1_inputs; + break; + case ARIZONA_AIF2_BCLK_CTRL: + *source = arizona_aif2_inputs; + break; + case ARIZONA_AIF3_BCLK_CTRL: + *source = arizona_aif3_inputs; + break; + case ARIZONA_AIF4_BCLK_CTRL: + *source = arizona_aif4_inputs; + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +int arizona_cache_and_clear_sources(struct arizona *arizona, + const int *sources, + unsigned int *cache, + int lim) +{ + int ret = 0; + int i; + + for (i = 0; i < lim; i++) { + ret = regmap_read(arizona->regmap, + sources[i], + &cache[i]); + + dev_dbg(arizona->dev, + "%s addr: 0x%04x value: 0x%04x\n", + __func__, sources[i], cache[i]); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache AIF:0x%04x inputs: %d\n", + __func__, sources[i], ret); + cache[i] = 0; + continue; + } + + /* Don't bother to set to zero if it already is */ + if (!cache[i]) + continue; + + ret = regmap_write(arizona->regmap, + sources[i], + 0); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to clear AIF:0x%04x inputs: %d\n", + __func__, sources[i], ret); break; - default: - manual_ena = true; + } + + } + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_cache_and_clear_sources); + +void clearwater_spin_sysclk(struct arizona *arizona) +{ + unsigned int val; + int ret, i; + + /* Skip this if the chip is down */ + if (pm_runtime_suspended(arizona->dev)) + return; + + /* + * Just read a register a few times to ensure the internal + * oscillator sends out a few clocks. + */ + for (i = 0; i < 4; i++) { + ret = regmap_read(arizona->regmap, + ARIZONA_SOFTWARE_RESET, + &val); + if (ret != 0) + dev_err(arizona->dev, + "%s Failed to read register: %d (%d)\n", + __func__, ret, i); + } + + udelay(300); +} +EXPORT_SYMBOL_GPL(clearwater_spin_sysclk); + +int arizona_restore_sources(struct arizona *arizona, + const int *sources, + unsigned int *cache, + int lim) +{ + int ret = 0; + int i; + + for (i = 0; i < lim; i++) { + + dev_dbg(arizona->dev, + "%s addr: 0x%04x value: 0x%04x\n", + __func__, sources[i], cache[i]); + + /* All mixers will be at zero no need to write to zero again */ + if (!cache[i]) + continue; + + ret = regmap_write(arizona->regmap, + sources[i], + cache[i]); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to restore AIF:0x%04x inputs: %d\n", + __func__, sources[i], ret); break; } + + } + + return ret; + +} +EXPORT_SYMBOL_GPL(arizona_restore_sources); + +static int arizona_check_speaker_overheat(struct arizona *arizona, + bool *warn, bool *shutdown) +{ + unsigned int reg, mask_warn, mask_shutdown, val; + int ret; + + switch (arizona->type) { + case WM8997: + case WM5102: + case WM8280: + case WM5110: + case WM8998: + case WM1814: + case CS47L24: + case WM1831: + reg = ARIZONA_INTERRUPT_RAW_STATUS_3; + mask_warn = ARIZONA_SPK_OVERHEAT_WARN_STS; + mask_shutdown = ARIZONA_SPK_OVERHEAT_STS; + break; + default: + reg = CLEARWATER_IRQ1_RAW_STATUS_15; + mask_warn = CLEARWATER_SPK_OVERHEAT_WARN_STS1; + mask_shutdown = CLEARWATER_SPK_OVERHEAT_STS1; + break; + } + + ret = regmap_read(arizona->regmap, reg, &val); + if (ret) { + dev_err(arizona->dev, "Failed to read thermal status: %d\n", + ret); + return ret; + } + + *warn = val & mask_warn ? true : false; + *shutdown = val & mask_shutdown ? true : false; + return 0; +} + +static int vegas_spk_pre_enable(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + unsigned int mute_reg, mute_mask, thr2_mask; + + switch (w->shift) { + case ARIZONA_OUT4L_ENA_SHIFT: + mute_reg = ARIZONA_DAC_DIGITAL_VOLUME_4L; + mute_mask = ARIZONA_OUT4L_MUTE_MASK; + thr2_mask = CLEARWATER_EDRE_OUT4L_THR2_ENA_MASK; + break; + case ARIZONA_OUT4R_ENA_SHIFT: + mute_reg = ARIZONA_DAC_DIGITAL_VOLUME_4R; + mute_mask = ARIZONA_OUT4R_MUTE_MASK; + thr2_mask = CLEARWATER_EDRE_OUT4R_THR2_ENA_MASK; + break; + default: + return 0; + } + + /* mute to prevent pops */ + priv->spk_mute_cache &= ~mute_mask; + priv->spk_mute_cache |= snd_soc_read(codec, mute_reg) & mute_mask; + snd_soc_update_bits(codec, mute_reg, mute_mask, mute_mask); + + /* disable thr2 while we enable */ + priv->spk_thr2_cache &= ~thr2_mask; + priv->spk_thr2_cache |= + snd_soc_read(codec, CLEARWATER_EDRE_ENABLE) & thr2_mask; + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, thr2_mask, + 0); + + return 0; +} + +static int vegas_spk_post_enable(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + unsigned int mute_reg, mute_mask, thr1_mask, thr2_mask, val; + + switch (w->shift) { + case ARIZONA_OUT4L_ENA_SHIFT: + mute_reg = ARIZONA_DAC_DIGITAL_VOLUME_4L; + mute_mask = ARIZONA_OUT4L_MUTE_MASK; + thr1_mask = CLEARWATER_EDRE_OUT4L_THR1_ENA_MASK; + thr2_mask = CLEARWATER_EDRE_OUT4L_THR2_ENA_MASK; + break; + case ARIZONA_OUT4R_ENA_SHIFT: + mute_reg = ARIZONA_DAC_DIGITAL_VOLUME_4R; + mute_mask = ARIZONA_OUT4R_MUTE_MASK; + thr1_mask = CLEARWATER_EDRE_OUT4R_THR1_ENA_MASK; + thr2_mask = CLEARWATER_EDRE_OUT4R_THR2_ENA_MASK; + break; default: + return 0; + } + + /* write sequencer sets OUT4R_THR2_ENA - update cache */ + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, thr2_mask, thr2_mask); + + /* restore THR2 to what it was at the start of the sequence */ + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, thr2_mask, + priv->spk_thr2_cache); + + /* disable THR2 if THR1 disabled */ + val = snd_soc_read(codec, CLEARWATER_EDRE_ENABLE); + if ((val & thr1_mask) == 0) + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, thr2_mask, 0); + + /* restore mute state */ + snd_soc_update_bits(codec, mute_reg, mute_mask, priv->spk_mute_cache); + + return 0; +} + +static int vegas_spk_post_disable(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + unsigned int thr2_mask; + + switch (w->shift) { + case ARIZONA_OUT4L_ENA_SHIFT: + thr2_mask = CLEARWATER_EDRE_OUT4L_THR2_ENA_MASK; + break; + case ARIZONA_OUT4R_ENA_SHIFT: + thr2_mask = CLEARWATER_EDRE_OUT4R_THR2_ENA_MASK; break; + default: + return 0; } + /* Read the current value of THR2 in to the cache so we can restore + * it after the write sequencer has executed + */ + priv->spk_thr2_cache &= ~thr2_mask; + priv->spk_thr2_cache |= + snd_soc_read(codec, CLEARWATER_EDRE_ENABLE) & thr2_mask; + + /* write sequencer clears OUT4R_THR2_ENA - update cache */ + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, thr2_mask, 0); + + /* Restore the previous value after the write sequencer update */ + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, thr2_mask, + priv->spk_thr2_cache); + + return 0; +} + +static int arizona_spk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + bool warn, shutdown; + int ret; + switch (event) { case SND_SOC_DAPM_PRE_PMU: - if (!priv->spk_ena && manual_ena) { - snd_soc_write(codec, 0x4f5, 0x25a); - priv->spk_ena_pending = true; + switch (arizona->type) { + case WM8998: + case WM1814: + vegas_spk_pre_enable(w, kcontrol, event); + break; + default: + break; } break; case SND_SOC_DAPM_POST_PMU: - val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3); - if (val & ARIZONA_SPK_SHUTDOWN_STS) { + ret = arizona_check_speaker_overheat(arizona, &warn, &shutdown); + if (ret) + return ret; + + if (shutdown) { dev_crit(arizona->dev, "Speaker not enabled due to temperature\n"); return -EBUSY; @@ -107,27 +561,35 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1, 1 << w->shift, 1 << w->shift); - if (priv->spk_ena_pending) { - msleep(75); - snd_soc_write(codec, 0x4f5, 0xda); - priv->spk_ena_pending = false; - priv->spk_ena++; - } + switch (arizona->type) { + case WM8280: + case WM5110: + case WM1831: + case CS47L24: + msleep(10); + break; + case WM8998: + case WM1814: + msleep(10); /* wait for wseq to end */ + vegas_spk_post_enable(w, kcontrol, event); + break; + default: + break; + }; break; case SND_SOC_DAPM_PRE_PMD: - if (manual_ena) { - priv->spk_ena--; - if (!priv->spk_ena) - snd_soc_write(codec, 0x4f5, 0x25a); - } - snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1, 1 << w->shift, 0); break; case SND_SOC_DAPM_POST_PMD: - if (manual_ena) { - if (!priv->spk_ena) - snd_soc_write(codec, 0x4f5, 0x0da); + switch (arizona->type) { + case WM8998: + case WM1814: + msleep(5); /* wait for wseq to end */ + vegas_spk_post_disable(w, kcontrol, event); + break; + default: + break; } break; } @@ -138,17 +600,12 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w, static irqreturn_t arizona_thermal_warn(int irq, void *data) { struct arizona *arizona = data; - unsigned int val; + bool warn, shutdown; int ret; - ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3, - &val); - if (ret != 0) { - dev_err(arizona->dev, "Failed to read thermal status: %d\n", - ret); - } else if (val & ARIZONA_SPK_SHUTDOWN_WARN_STS) { + ret = arizona_check_speaker_overheat(arizona, &warn, &shutdown); + if ((ret == 0) && warn) dev_crit(arizona->dev, "Thermal warning\n"); - } return IRQ_HANDLED; } @@ -156,15 +613,11 @@ static irqreturn_t arizona_thermal_warn(int irq, void *data) static irqreturn_t arizona_thermal_shutdown(int irq, void *data) { struct arizona *arizona = data; - unsigned int val; + bool warn, shutdown; int ret; - ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3, - &val); - if (ret != 0) { - dev_err(arizona->dev, "Failed to read thermal status: %d\n", - ret); - } else if (val & ARIZONA_SPK_SHUTDOWN_STS) { + ret = arizona_check_speaker_overheat(arizona, &warn, &shutdown); + if ((ret == 0) && shutdown) { dev_crit(arizona->dev, "Thermal shutdown\n"); ret = regmap_update_bits(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, @@ -182,12 +635,14 @@ static irqreturn_t arizona_thermal_shutdown(int irq, void *data) static const struct snd_soc_dapm_widget arizona_spkl = SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM, ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU); + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU); static const struct snd_soc_dapm_widget arizona_spkr = SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM, ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU); + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU); int arizona_init_spk(struct snd_soc_codec *codec) { @@ -199,11 +654,22 @@ int arizona_init_spk(struct snd_soc_codec *codec) if (ret != 0) return ret; - ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkr, 1); - if (ret != 0) - return ret; + switch (arizona->type) { + case WM8997: + case WM1831: + case CS47L24: + case CS47L15: + case CS47L35: + break; + default: + ret = snd_soc_dapm_new_controls(&codec->dapm, + &arizona_spkr, 1); + if (ret != 0) + return ret; + break; + } - ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN_WARN, + ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN, "Thermal warning", arizona_thermal_warn, arizona); if (ret != 0) @@ -211,7 +677,7 @@ int arizona_init_spk(struct snd_soc_codec *codec) "Failed to get thermal warning IRQ: %d\n", ret); - ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN, + ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT, "Thermal shutdown", arizona_thermal_shutdown, arizona); if (ret != 0) @@ -223,14 +689,115 @@ int arizona_init_spk(struct snd_soc_codec *codec) } EXPORT_SYMBOL_GPL(arizona_init_spk); -const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { - "None", - "Tone Generator 1", - "Tone Generator 2", - "Haptics", - "AEC", - "Mic Mute Mixer", - "Noise Generator", +int arizona_mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct snd_soc_card *card = codec->card; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int val, mask; + int ret; + + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + ret = widget->power_check(widget); + if (ret) { + val = e->values[ucontrol->value.enumerated.item[0]]; + val <<= e->shift_l; + mask = e->mask << e->shift_l; + + mutex_lock(&arizona->rate_lock); + snd_soc_update_bits(codec, e->reg, mask, val); + mutex_unlock(&arizona->rate_lock); + } + + mutex_unlock(&card->dapm_mutex); + + return snd_soc_dapm_put_enum_virt(kcontrol, ucontrol); +} +EXPORT_SYMBOL_GPL(arizona_mux_put); + +int arizona_mux_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct soc_enum *e; + unsigned int val, mask; + int ret; + + e = (struct soc_enum *)w->kcontrols[0]->private_value; + mask = e->mask << e->shift_l; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + val = e->values[w->value] << e->shift_l; + break; + case SND_SOC_DAPM_PRE_PMD: + val = 0; + break; + default: + return -EINVAL; + } + + mutex_lock(&arizona->rate_lock); + ret = regmap_update_bits(arizona->regmap, e->reg, mask, val); + mutex_unlock(&arizona->rate_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_mux_event); + +static const struct snd_soc_dapm_route arizona_mono_routes[] = { + { "OUT1R", NULL, "OUT1L" }, + { "OUT2R", NULL, "OUT2L" }, + { "OUT3R", NULL, "OUT3L" }, + { "OUT4R", NULL, "OUT4L" }, + { "OUT5R", NULL, "OUT5L" }, + { "OUT6R", NULL, "OUT6L" }, +}; + +int arizona_init_mono(struct snd_soc_codec *codec) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int i; + + for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) { + if (arizona->pdata.out_mono[i]) + snd_soc_dapm_add_routes(&codec->dapm, + &arizona_mono_routes[i], 1); + } + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_init_mono); + +static const char * const arizona_dmic_refs[] = { + "MICVDD", + "MICBIAS1", + "MICBIAS2", + "MICBIAS3", +}; + +static const char * const cs47l15_dmic_refs[] = { + "MICVDD", + "MICBIAS1A", + "MICBIAS1B", + "MICBIAS1C", +}; + +static const char * const marley_dmic_refs[] = { + "MICVDD", + "MICBIAS1B", + "MICBIAS2A", + "MICBIAS2B", +}; + +static const char * const arizona_dmic_inputs[] = { "IN1L", "IN1R", "IN2L", @@ -239,29 +806,204 @@ const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { "IN3R", "IN4L", "IN4R", - "AIF1RX1", - "AIF1RX2", - "AIF1RX3", - "AIF1RX4", - "AIF1RX5", - "AIF1RX6", - "AIF1RX7", - "AIF1RX8", - "AIF2RX1", - "AIF2RX2", - "AIF3RX1", - "AIF3RX2", - "SLIMRX1", - "SLIMRX2", - "SLIMRX3", - "SLIMRX4", - "SLIMRX5", - "SLIMRX6", - "SLIMRX7", - "SLIMRX8", - "EQ1", - "EQ2", - "EQ3", +}; + +static const char * const clearwater_dmic_inputs[] = { + "IN1L Mux", + "IN1R", + "IN2L Mux", + "IN2R Mux", + "IN3L", + "IN3R", + "IN4L", + "IN4R", + "IN5L", + "IN5R", + "IN6L", + "IN6R", +}; + +static const char * const marley_dmic_inputs[] = { + "IN1L Mux", + "IN1R Mux", + "IN2L", + "IN2R", +}; + +static const char * const moon_dmic_inputs[] = { + "IN1L Mux", + "IN1R Mux", + "IN2L Mux", + "IN2R", + "IN3L", + "IN3R", + "IN4L", + "IN4R", + "IN5L", + "IN5R", +}; + +static const char * const cs47l15_dmic_inputs[] = { + "IN1L Mux", + "IN1R Mux", + "IN2L", + "IN2R", +}; + +int arizona_init_input(struct snd_soc_codec *codec) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + struct arizona_pdata *pdata = &arizona->pdata; + int i, ret; + struct snd_soc_dapm_route routes[2]; + + memset(&routes, 0, sizeof(routes)); + + for (i = 0; i < priv->num_inputs / 2; ++i) { + switch (arizona->type) { + case CS47L15: + routes[0].source = cs47l15_dmic_refs[pdata->dmic_ref[i]]; + routes[1].source = cs47l15_dmic_refs[pdata->dmic_ref[i]]; + break; + case CS47L35: + routes[0].source = marley_dmic_refs[pdata->dmic_ref[i]]; + routes[1].source = marley_dmic_refs[pdata->dmic_ref[i]]; + break; + default: + routes[0].source = + arizona_dmic_refs[pdata->dmic_ref[i]]; + routes[1].source = + arizona_dmic_refs[pdata->dmic_ref[i]]; + break; + } + + switch (arizona->type) { + case WM8285: + case WM1840: + routes[0].sink = clearwater_dmic_inputs[i * 2]; + routes[1].sink = clearwater_dmic_inputs[(i * 2) + 1]; + break; + case CS47L35: + routes[0].sink = marley_dmic_inputs[i * 2]; + routes[1].sink = marley_dmic_inputs[(i * 2) + 1]; + break; + case CS47L90: + case CS47L91: + routes[0].sink = moon_dmic_inputs[i * 2]; + routes[1].sink = moon_dmic_inputs[(i * 2) + 1]; + break; + case CS47L15: + routes[0].sink = cs47l15_dmic_inputs[i * 2]; + routes[1].sink = cs47l15_dmic_inputs[(i * 2) + 1]; + break; + default: + routes[0].sink = arizona_dmic_inputs[i * 2]; + routes[1].sink = arizona_dmic_inputs[(i * 2) + 1]; + break; + } + + ret = snd_soc_dapm_add_routes(&codec->dapm, routes, 2); + } + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_init_input); + +int arizona_init_gpio(struct snd_soc_codec *codec) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int i; + + mutex_lock(&codec->card->dapm_mutex); + + switch (arizona->type) { + case WM8280: + case WM5110: + case WM1831: + case CS47L24: + snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity"); + break; + default: + break; + } + + snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity"); + + for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { + switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) { + case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT: + snd_soc_dapm_enable_pin(&codec->dapm, + "DRC1 Signal Activity"); + break; + case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT: + snd_soc_dapm_enable_pin(&codec->dapm, + "DRC2 Signal Activity"); + break; + default: + break; + } + } + + mutex_unlock(&codec->card->dapm_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_init_gpio); + +const char * const arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { + "None", + "Tone Generator 1", + "Tone Generator 2", + "Haptics", + "AEC", + "AEC2", + "Mic Mute Mixer", + "Noise Generator", + "IN1L", + "IN1R", + "IN2L", + "IN2R", + "IN3L", + "IN3R", + "IN4L", + "IN4R", + "IN5L", + "IN5R", + "IN6L", + "IN6R", + "AIF1RX1", + "AIF1RX2", + "AIF1RX3", + "AIF1RX4", + "AIF1RX5", + "AIF1RX6", + "AIF1RX7", + "AIF1RX8", + "AIF2RX1", + "AIF2RX2", + "AIF2RX3", + "AIF2RX4", + "AIF2RX5", + "AIF2RX6", + "AIF2RX7", + "AIF2RX8", + "AIF3RX1", + "AIF3RX2", + "AIF4RX1", + "AIF4RX2", + "SLIMRX1", + "SLIMRX2", + "SLIMRX3", + "SLIMRX4", + "SLIMRX5", + "SLIMRX6", + "SLIMRX7", + "SLIMRX8", + "EQ1", + "EQ2", + "EQ3", "EQ4", "DRC1L", "DRC1R", @@ -295,6 +1037,24 @@ const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { "DSP4.4", "DSP4.5", "DSP4.6", + "DSP5.1", + "DSP5.2", + "DSP5.3", + "DSP5.4", + "DSP5.5", + "DSP5.6", + "DSP6.1", + "DSP6.2", + "DSP6.3", + "DSP6.4", + "DSP6.5", + "DSP6.6", + "DSP7.1", + "DSP7.2", + "DSP7.3", + "DSP7.4", + "DSP7.5", + "DSP7.6", "ASRC1L", "ASRC1R", "ASRC2L", @@ -323,15 +1083,20 @@ const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { "ISRC3DEC2", "ISRC3DEC3", "ISRC3DEC4", + "ISRC4INT1", + "ISRC4INT2", + "ISRC4DEC1", + "ISRC4DEC2", }; EXPORT_SYMBOL_GPL(arizona_mixer_texts); -int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { +unsigned int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 0x00, /* None */ 0x04, /* Tone */ 0x05, 0x06, /* Haptics */ 0x08, /* AEC */ + 0x09, /* AEC2 */ 0x0c, /* Noise mixer */ 0x0d, /* Comfort noise */ 0x10, /* IN1L */ @@ -342,6 +1107,10 @@ int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 0x15, 0x16, 0x17, + 0x18, + 0x19, + 0x1A, + 0x1B, 0x20, /* AIF1RX1 */ 0x21, 0x22, @@ -352,8 +1121,16 @@ int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 0x27, 0x28, /* AIF2RX1 */ 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, 0x30, /* AIF3RX1 */ 0x31, + 0x34, /* AIF4RX1 */ + 0x35, 0x38, /* SLIMRX1 */ 0x39, 0x3a, @@ -398,6 +1175,24 @@ int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 0x83, 0x84, 0x85, + 0x88, /* DSP5.1 */ + 0x89, + 0x8a, + 0x8b, + 0x8c, + 0x8d, + 0xc0, /* DSP6.1 */ + 0xc1, + 0xc2, + 0xc3, + 0xc4, + 0xc5, + 0xc8, /* DSP7.1 */ + 0xc9, + 0xca, + 0xcb, + 0xcc, + 0xcd, 0x90, /* ASRC1L */ 0x91, 0x92, @@ -426,97 +1221,1204 @@ int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = { 0xb5, 0xb6, 0xb7, + 0xb8, /* ISRC4INT1 */ + 0xb9, + 0xbc, /* ISRC4DEC1 */ + 0xbd, }; EXPORT_SYMBOL_GPL(arizona_mixer_values); -const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0); -EXPORT_SYMBOL_GPL(arizona_mixer_tlv); - -const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = { - "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate", -}; -EXPORT_SYMBOL_GPL(arizona_rate_text); - -const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = { - 0, 1, 2, 8, -}; -EXPORT_SYMBOL_GPL(arizona_rate_val); - - -const struct soc_enum arizona_isrc_fsl[] = { - SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2, - ARIZONA_ISRC1_FSL_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), - SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2, - ARIZONA_ISRC2_FSL_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), - SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2, - ARIZONA_ISRC3_FSL_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), -}; -EXPORT_SYMBOL_GPL(arizona_isrc_fsl); - -static const char *arizona_vol_ramp_text[] = { - "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", - "15ms/6dB", "30ms/6dB", -}; - -const struct soc_enum arizona_in_vd_ramp = - SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP, - ARIZONA_IN_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text); -EXPORT_SYMBOL_GPL(arizona_in_vd_ramp); - -const struct soc_enum arizona_in_vi_ramp = - SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP, - ARIZONA_IN_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text); -EXPORT_SYMBOL_GPL(arizona_in_vi_ramp); - -const struct soc_enum arizona_out_vd_ramp = - SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP, - ARIZONA_OUT_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text); -EXPORT_SYMBOL_GPL(arizona_out_vd_ramp); - -const struct soc_enum arizona_out_vi_ramp = - SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP, - ARIZONA_OUT_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text); -EXPORT_SYMBOL_GPL(arizona_out_vi_ramp); - -static const char *arizona_lhpf_mode_text[] = { - "Low-pass", "High-pass" +const char * const arizona_v2_mixer_texts[ARIZONA_V2_NUM_MIXER_INPUTS] = { + "None", + "Tone Generator 1", + "Tone Generator 2", + "Haptics", + "AEC", + "AEC2", + "Mic Mute Mixer", + "Noise Generator", + "IN1L", + "IN1R", + "IN2L", + "IN2R", + "IN3L", + "IN3R", + "IN4L", + "IN4R", + "IN5L", + "IN5R", + "IN6L", + "IN6R", + "AIF1RX1", + "AIF1RX2", + "AIF1RX3", + "AIF1RX4", + "AIF1RX5", + "AIF1RX6", + "AIF1RX7", + "AIF1RX8", + "AIF2RX1", + "AIF2RX2", + "AIF2RX3", + "AIF2RX4", + "AIF2RX5", + "AIF2RX6", + "AIF2RX7", + "AIF2RX8", + "AIF3RX1", + "AIF3RX2", + "AIF4RX1", + "AIF4RX2", + "SLIMRX1", + "SLIMRX2", + "SLIMRX3", + "SLIMRX4", + "SLIMRX5", + "SLIMRX6", + "SLIMRX7", + "SLIMRX8", + "EQ1", + "EQ2", + "EQ3", + "EQ4", + "DRC1L", + "DRC1R", + "DRC2L", + "DRC2R", + "LHPF1", + "LHPF2", + "LHPF3", + "LHPF4", + "DSP1.1", + "DSP1.2", + "DSP1.3", + "DSP1.4", + "DSP1.5", + "DSP1.6", + "DSP2.1", + "DSP2.2", + "DSP2.3", + "DSP2.4", + "DSP2.5", + "DSP2.6", + "DSP3.1", + "DSP3.2", + "DSP3.3", + "DSP3.4", + "DSP3.5", + "DSP3.6", + "DSP4.1", + "DSP4.2", + "DSP4.3", + "DSP4.4", + "DSP4.5", + "DSP4.6", + "DSP5.1", + "DSP5.2", + "DSP5.3", + "DSP5.4", + "DSP5.5", + "DSP5.6", + "DSP6.1", + "DSP6.2", + "DSP6.3", + "DSP6.4", + "DSP6.5", + "DSP6.6", + "DSP7.1", + "DSP7.2", + "DSP7.3", + "DSP7.4", + "DSP7.5", + "DSP7.6", + "ASRC1IN1L", + "ASRC1IN1R", + "ASRC1IN2L", + "ASRC1IN2R", + "ASRC2IN1L", + "ASRC2IN1R", + "ASRC2IN2L", + "ASRC2IN2R", + "ISRC1INT1", + "ISRC1INT2", + "ISRC1INT3", + "ISRC1INT4", + "ISRC1DEC1", + "ISRC1DEC2", + "ISRC1DEC3", + "ISRC1DEC4", + "ISRC2INT1", + "ISRC2INT2", + "ISRC2INT3", + "ISRC2INT4", + "ISRC2DEC1", + "ISRC2DEC2", + "ISRC2DEC3", + "ISRC2DEC4", + "ISRC3INT1", + "ISRC3INT2", + "ISRC3INT3", + "ISRC3INT4", + "ISRC3DEC1", + "ISRC3DEC2", + "ISRC3DEC3", + "ISRC3DEC4", + "ISRC4INT1", + "ISRC4INT2", + "ISRC4DEC1", + "ISRC4DEC2", + "DFC1", + "DFC2", + "DFC3", + "DFC4", + "DFC5", + "DFC6", + "DFC7", + "DFC8", }; +EXPORT_SYMBOL_GPL(arizona_v2_mixer_texts); -const struct soc_enum arizona_lhpf1_mode = - SOC_ENUM_SINGLE(ARIZONA_HPLPF1_1, ARIZONA_LHPF1_MODE_SHIFT, 2, - arizona_lhpf_mode_text); -EXPORT_SYMBOL_GPL(arizona_lhpf1_mode); - -const struct soc_enum arizona_lhpf2_mode = - SOC_ENUM_SINGLE(ARIZONA_HPLPF2_1, ARIZONA_LHPF2_MODE_SHIFT, 2, - arizona_lhpf_mode_text); -EXPORT_SYMBOL_GPL(arizona_lhpf2_mode); - -const struct soc_enum arizona_lhpf3_mode = - SOC_ENUM_SINGLE(ARIZONA_HPLPF3_1, ARIZONA_LHPF3_MODE_SHIFT, 2, - arizona_lhpf_mode_text); -EXPORT_SYMBOL_GPL(arizona_lhpf3_mode); - -const struct soc_enum arizona_lhpf4_mode = - SOC_ENUM_SINGLE(ARIZONA_HPLPF4_1, ARIZONA_LHPF4_MODE_SHIFT, 2, - arizona_lhpf_mode_text); -EXPORT_SYMBOL_GPL(arizona_lhpf4_mode); - -static const char *arizona_ng_hold_text[] = { - "30ms", "120ms", "250ms", "500ms", -}; +unsigned int arizona_v2_mixer_values[ARIZONA_V2_NUM_MIXER_INPUTS] = { + 0x00, /* None */ + 0x04, /* Tone */ + 0x05, + 0x06, /* Haptics */ + 0x08, /* AEC */ + 0x09, /* AEC2 */ + 0x0c, /* Noise mixer */ + 0x0d, /* Comfort noise */ + 0x10, /* IN1L */ + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1A, + 0x1B, + 0x20, /* AIF1RX1 */ + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, /* AIF2RX1 */ + 0x29, + 0x2a, + 0x2b, + 0x2c, + 0x2d, + 0x2e, + 0x2f, + 0x30, /* AIF3RX1 */ + 0x31, + 0x34, /* AIF4RX1 */ + 0x35, + 0x38, /* SLIMRX1 */ + 0x39, + 0x3a, + 0x3b, + 0x3c, + 0x3d, + 0x3e, + 0x3f, + 0x50, /* EQ1 */ + 0x51, + 0x52, + 0x53, + 0x58, /* DRC1L */ + 0x59, + 0x5a, + 0x5b, + 0x60, /* LHPF1 */ + 0x61, + 0x62, + 0x63, + 0x68, /* DSP1.1 */ + 0x69, + 0x6a, + 0x6b, + 0x6c, + 0x6d, + 0x70, /* DSP2.1 */ + 0x71, + 0x72, + 0x73, + 0x74, + 0x75, + 0x78, /* DSP3.1 */ + 0x79, + 0x7a, + 0x7b, + 0x7c, + 0x7d, + 0x80, /* DSP4.1 */ + 0x81, + 0x82, + 0x83, + 0x84, + 0x85, + 0x88, /* DSP5.1 */ + 0x89, + 0x8a, + 0x8b, + 0x8c, + 0x8d, + 0xc0, /* DSP6.1 */ + 0xc1, + 0xc2, + 0xc3, + 0xc4, + 0xc5, + 0xc8, /* DSP7.1 */ + 0xc9, + 0xca, + 0xcb, + 0xcc, + 0xcd, + 0x90, /* ASRC1IN1L */ + 0x91, + 0x92, + 0x93, + 0x94, /* ASRC2IN1L */ + 0x95, + 0x96, + 0x97, + 0xa0, /* ISRC1INT1 */ + 0xa1, + 0xa2, + 0xa3, + 0xa4, /* ISRC1DEC1 */ + 0xa5, + 0xa6, + 0xa7, + 0xa8, /* ISRC2DEC1 */ + 0xa9, + 0xaa, + 0xab, + 0xac, /* ISRC2INT1 */ + 0xad, + 0xae, + 0xaf, + 0xb0, /* ISRC3DEC1 */ + 0xb1, + 0xb2, + 0xb3, + 0xb4, /* ISRC3INT1 */ + 0xb5, + 0xb6, + 0xb7, + 0xb8, /* ISRC4INT1 */ + 0xb9, + 0xbc, /* ISRC4DEC1 */ + 0xbd, + 0xf8, /* DFC1 */ + 0xf9, + 0xfa, + 0xfb, + 0xfc, + 0xfd, + 0xfe, + 0xff, /* DFC8 */ +}; +EXPORT_SYMBOL_GPL(arizona_v2_mixer_values); + +const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0); +EXPORT_SYMBOL_GPL(arizona_mixer_tlv); -const struct soc_enum arizona_ng_hold = - SOC_ENUM_SINGLE(ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_HOLD_SHIFT, - 4, arizona_ng_hold_text); +const char * const arizona_sample_rate_text[ARIZONA_SAMPLE_RATE_ENUM_SIZE] = { + "12kHz", "24kHz", "48kHz", "96kHz", "192kHz", + "11.025kHz", "22.05kHz", "44.1kHz", "88.2kHz", "176.4kHz", + "4kHz", "8kHz", "16kHz", "32kHz", +}; +EXPORT_SYMBOL_GPL(arizona_sample_rate_text); + +const unsigned int arizona_sample_rate_val[ARIZONA_SAMPLE_RATE_ENUM_SIZE] = { + 0x01, 0x02, 0x03, 0x04, 0x05, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, + 0x10, 0x11, 0x12, 0x13, +}; +EXPORT_SYMBOL_GPL(arizona_sample_rate_val); + +const char *arizona_sample_rate_val_to_name(unsigned int rate_val) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(arizona_sample_rate_val); ++i) { + if (arizona_sample_rate_val[i] == rate_val) + return arizona_sample_rate_text[i]; + } + + return "Illegal"; +} +EXPORT_SYMBOL_GPL(arizona_sample_rate_val_to_name); + +const struct soc_enum arizona_sample_rate[] = { + SOC_VALUE_ENUM_SINGLE(ARIZONA_SAMPLE_RATE_2, + ARIZONA_SAMPLE_RATE_2_SHIFT, 0x1f, + ARIZONA_SAMPLE_RATE_ENUM_SIZE, + arizona_sample_rate_text, + arizona_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_SAMPLE_RATE_3, + ARIZONA_SAMPLE_RATE_3_SHIFT, 0x1f, + ARIZONA_SAMPLE_RATE_ENUM_SIZE, + arizona_sample_rate_text, + arizona_sample_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ASYNC_SAMPLE_RATE_2, + ARIZONA_ASYNC_SAMPLE_RATE_2_SHIFT, 0x1f, + ARIZONA_SAMPLE_RATE_ENUM_SIZE, + arizona_sample_rate_text, + arizona_sample_rate_val), + +}; +EXPORT_SYMBOL_GPL(arizona_sample_rate); + +const char * const arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = { + "SYNCCLK rate 1", "SYNCCLK rate 2", "SYNCCLK rate 3", + "ASYNCCLK rate", "ASYNCCLK rate 2", +}; +EXPORT_SYMBOL_GPL(arizona_rate_text); + +const struct soc_enum arizona_output_rate = + SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_RATE_1, + ARIZONA_OUT_RATE_SHIFT, + 0x0f, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val); +EXPORT_SYMBOL_GPL(arizona_output_rate); + +const struct soc_enum arizona_input_rate = + SOC_VALUE_ENUM_SINGLE(ARIZONA_INPUT_RATE, + ARIZONA_IN_RATE_SHIFT, + 0x0f, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val); +EXPORT_SYMBOL_GPL(arizona_input_rate); + +const struct soc_enum moon_input_rate[] = { + SOC_VALUE_ENUM_SINGLE(MOON_IN1L_RATE_CONTROL, + MOON_IN1L_RATE_SHIFT, + MOON_IN1L_RATE_MASK >> MOON_IN1L_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN1R_RATE_CONTROL, + MOON_IN1R_RATE_SHIFT, + MOON_IN1R_RATE_MASK >> MOON_IN1R_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN2L_RATE_CONTROL, + MOON_IN2L_RATE_SHIFT, + MOON_IN2L_RATE_MASK >> MOON_IN2L_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN2R_RATE_CONTROL, + MOON_IN2R_RATE_SHIFT, + MOON_IN2R_RATE_MASK >> MOON_IN2R_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN3L_RATE_CONTROL, + MOON_IN3L_RATE_SHIFT, + MOON_IN3L_RATE_MASK >> MOON_IN3L_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN3R_RATE_CONTROL, + MOON_IN3R_RATE_SHIFT, + MOON_IN3R_RATE_MASK >> MOON_IN3R_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN4L_RATE_CONTROL, + MOON_IN4L_RATE_SHIFT, + MOON_IN4L_RATE_MASK >> MOON_IN4L_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN4R_RATE_CONTROL, + MOON_IN4R_RATE_SHIFT, + MOON_IN4R_RATE_MASK >> MOON_IN4R_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN5L_RATE_CONTROL, + MOON_IN5L_RATE_SHIFT, + MOON_IN5L_RATE_MASK >> MOON_IN5L_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(MOON_IN5R_RATE_CONTROL, + MOON_IN5R_RATE_SHIFT, + MOON_IN5R_RATE_MASK >> MOON_IN5R_RATE_SHIFT, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val), +}; +EXPORT_SYMBOL_GPL(moon_input_rate); + +const char * const moon_dfc_width_text[MOON_DFC_WIDTH_ENUM_SIZE] = { + "8bit", "16bit", "20bit", "24bit", "32bit", +}; +EXPORT_SYMBOL_GPL(moon_dfc_width_text); + +const unsigned int moon_dfc_width_val[MOON_DFC_WIDTH_ENUM_SIZE] = { + 7, 15, 19, 23, 31, +}; +EXPORT_SYMBOL_GPL(moon_dfc_width_val); + +const char * const moon_dfc_type_text[MOON_DFC_TYPE_ENUM_SIZE] = { + "Fixed", "Unsigned Fixed", "Single Precision Floating", + "Half Precision Floating", "Arm Alternative Floating", +}; +EXPORT_SYMBOL_GPL(moon_dfc_type_text); + +const unsigned int moon_dfc_type_val[MOON_DFC_TYPE_ENUM_SIZE] = { + 0, 1, 2, 4, 5, +}; +EXPORT_SYMBOL_GPL(moon_dfc_type_val); + + +const struct soc_enum moon_dfc_width[] = { + SOC_VALUE_ENUM_SINGLE(MOON_DFC1_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC1_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC2_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC2_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC3_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC3_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC4_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC4_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC5_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC5_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC6_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC6_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC7_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC7_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC8_RX, + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + MOON_DFC1_RX_DATA_WIDTH_MASK >> + MOON_DFC1_RX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC8_TX, + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + MOON_DFC1_TX_DATA_WIDTH_MASK >> + MOON_DFC1_TX_DATA_WIDTH_SHIFT, + ARRAY_SIZE(moon_dfc_width_text), + moon_dfc_width_text, + moon_dfc_width_val), +}; +EXPORT_SYMBOL_GPL(moon_dfc_width); + +const struct soc_enum moon_dfc_type[] = { + SOC_VALUE_ENUM_SINGLE(MOON_DFC1_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC1_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC2_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC2_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC3_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC3_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC4_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC4_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC5_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC5_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC6_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC6_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC7_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC7_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC8_RX, + MOON_DFC1_RX_DATA_TYPE_SHIFT, + MOON_DFC1_RX_DATA_TYPE_MASK >> + MOON_DFC1_RX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), + SOC_VALUE_ENUM_SINGLE(MOON_DFC8_TX, + MOON_DFC1_TX_DATA_TYPE_SHIFT, + MOON_DFC1_TX_DATA_TYPE_MASK >> + MOON_DFC1_TX_DATA_TYPE_SHIFT, + ARRAY_SIZE(moon_dfc_type_text), + moon_dfc_type_text, + moon_dfc_type_val), +}; +EXPORT_SYMBOL_GPL(moon_dfc_type); + +const struct soc_enum arizona_fx_rate = + SOC_VALUE_ENUM_SINGLE(ARIZONA_FX_CTRL1, + ARIZONA_FX_RATE_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val); +EXPORT_SYMBOL_GPL(arizona_fx_rate); + +const struct soc_enum arizona_spdif_rate = + SOC_VALUE_ENUM_SINGLE(ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_RATE_SHIFT, + 0x0f, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, + arizona_rate_val); +EXPORT_SYMBOL_GPL(arizona_spdif_rate); + +const unsigned int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = { + 0x0, 0x1, 0x2, 0x8, 0x9, +}; +EXPORT_SYMBOL_GPL(arizona_rate_val); + +const struct soc_enum arizona_isrc_fsh[] = { + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1, + ARIZONA_ISRC1_FSH_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1, + ARIZONA_ISRC2_FSH_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1, + ARIZONA_ISRC3_FSH_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_4_CTRL_1, + ARIZONA_ISRC4_FSH_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + +}; +EXPORT_SYMBOL_GPL(arizona_isrc_fsh); + +const struct soc_enum arizona_isrc_fsl[] = { + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2, + ARIZONA_ISRC1_FSL_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2, + ARIZONA_ISRC2_FSL_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2, + ARIZONA_ISRC3_FSL_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_4_CTRL_2, + ARIZONA_ISRC4_FSL_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + +}; +EXPORT_SYMBOL_GPL(arizona_isrc_fsl); + +const struct soc_enum arizona_asrc_rate1 = + SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1, + ARIZONA_ASRC_RATE1_SHIFT, 0xf, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val); +EXPORT_SYMBOL_GPL(arizona_asrc_rate1); + +const struct soc_enum arizona_asrc_rate2 = + SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE2, + ARIZONA_ASRC_RATE2_SHIFT, 0xf, + ARIZONA_ASYNC_RATE_ENUM_SIZE, + arizona_rate_text + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_val + ARIZONA_SYNC_RATE_ENUM_SIZE); +EXPORT_SYMBOL_GPL(arizona_asrc_rate2); + +const struct soc_enum clearwater_asrc1_rate[] = { + SOC_VALUE_ENUM_SINGLE(CLEARWATER_ASRC1_RATE1, + CLEARWATER_ASRC1_RATE1_SHIFT, 0xf, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(CLEARWATER_ASRC1_RATE2, + CLEARWATER_ASRC1_RATE1_SHIFT, 0xf, + ARIZONA_ASYNC_RATE_ENUM_SIZE, + arizona_rate_text + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_val + ARIZONA_SYNC_RATE_ENUM_SIZE), + +}; +EXPORT_SYMBOL_GPL(clearwater_asrc1_rate); + +const struct soc_enum clearwater_asrc2_rate[] = { + SOC_VALUE_ENUM_SINGLE(CLEARWATER_ASRC2_RATE1, + CLEARWATER_ASRC2_RATE1_SHIFT, 0xf, + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(CLEARWATER_ASRC2_RATE2, + CLEARWATER_ASRC2_RATE2_SHIFT, 0xf, + ARIZONA_ASYNC_RATE_ENUM_SIZE, + arizona_rate_text + ARIZONA_SYNC_RATE_ENUM_SIZE, + arizona_rate_val + ARIZONA_SYNC_RATE_ENUM_SIZE), + +}; +EXPORT_SYMBOL_GPL(clearwater_asrc2_rate); + +static const char * const arizona_vol_ramp_text[] = { + "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", + "15ms/6dB", "30ms/6dB", +}; + +const SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp, + ARIZONA_INPUT_VOLUME_RAMP, + ARIZONA_IN_VD_RAMP_SHIFT, + arizona_vol_ramp_text); +EXPORT_SYMBOL_GPL(arizona_in_vd_ramp); + +const SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp, + ARIZONA_INPUT_VOLUME_RAMP, + ARIZONA_IN_VI_RAMP_SHIFT, + arizona_vol_ramp_text); +EXPORT_SYMBOL_GPL(arizona_in_vi_ramp); + +const SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp, + ARIZONA_OUTPUT_VOLUME_RAMP, + ARIZONA_OUT_VD_RAMP_SHIFT, + arizona_vol_ramp_text); +EXPORT_SYMBOL_GPL(arizona_out_vd_ramp); + +const SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp, + ARIZONA_OUTPUT_VOLUME_RAMP, + ARIZONA_OUT_VI_RAMP_SHIFT, + arizona_vol_ramp_text); +EXPORT_SYMBOL_GPL(arizona_out_vi_ramp); + +static const char * const arizona_lhpf_mode_text[] = { + "Low-pass", "High-pass" +}; + +const SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode, + ARIZONA_HPLPF1_1, + ARIZONA_LHPF1_MODE_SHIFT, + arizona_lhpf_mode_text); +EXPORT_SYMBOL_GPL(arizona_lhpf1_mode); + +const SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode, + ARIZONA_HPLPF2_1, + ARIZONA_LHPF2_MODE_SHIFT, + arizona_lhpf_mode_text); +EXPORT_SYMBOL_GPL(arizona_lhpf2_mode); + +const SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode, + ARIZONA_HPLPF3_1, + ARIZONA_LHPF3_MODE_SHIFT, + arizona_lhpf_mode_text); +EXPORT_SYMBOL_GPL(arizona_lhpf3_mode); + +const SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode, + ARIZONA_HPLPF4_1, + ARIZONA_LHPF4_MODE_SHIFT, + arizona_lhpf_mode_text); +EXPORT_SYMBOL_GPL(arizona_lhpf4_mode); + +static const char * const arizona_ng_hold_text[] = { + "30ms", "120ms", "250ms", "500ms", +}; + +const SOC_ENUM_SINGLE_DECL(arizona_ng_hold, + ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_HOLD_SHIFT, + arizona_ng_hold_text); EXPORT_SYMBOL_GPL(arizona_ng_hold); +static const char * const arizona_in_hpf_cut_text[] = { + "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz" +}; + +const SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum, + ARIZONA_HPF_CONTROL, + ARIZONA_IN_HPF_CUT_SHIFT, + arizona_in_hpf_cut_text); +EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum); + +static const char * const arizona_in_dmic_osr_text[] = { + "1.536MHz", "3.072MHz", "6.144MHz", "768kHz", +}; + +const struct soc_enum arizona_in_dmic_osr[] = { + SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT, + ARRAY_SIZE(arizona_in_dmic_osr_text), + arizona_in_dmic_osr_text), + SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT, + ARRAY_SIZE(arizona_in_dmic_osr_text), + arizona_in_dmic_osr_text), + SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT, + ARRAY_SIZE(arizona_in_dmic_osr_text), + arizona_in_dmic_osr_text), + SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT, + ARRAY_SIZE(arizona_in_dmic_osr_text), + arizona_in_dmic_osr_text), +}; +EXPORT_SYMBOL_GPL(arizona_in_dmic_osr); + +static const char * const clearwater_in_dmic_osr_text[CLEARWATER_OSR_ENUM_SIZE] = { + "384kHz", "768kHz", "1.536MHz", "3.072MHz", "6.144MHz", +}; + +static const unsigned int clearwater_in_dmic_osr_val[CLEARWATER_OSR_ENUM_SIZE] = { + 2, 3, 4, 5, 6, +}; + +const struct soc_enum clearwater_in_dmic_osr[] = { + SOC_VALUE_ENUM_SINGLE(ARIZONA_DMIC1L_CONTROL, CLEARWATER_IN1_OSR_SHIFT, + 0x7, CLEARWATER_OSR_ENUM_SIZE, + clearwater_in_dmic_osr_text, clearwater_in_dmic_osr_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DMIC2L_CONTROL, CLEARWATER_IN2_OSR_SHIFT, + 0x7, CLEARWATER_OSR_ENUM_SIZE, + clearwater_in_dmic_osr_text, clearwater_in_dmic_osr_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DMIC3L_CONTROL, CLEARWATER_IN3_OSR_SHIFT, + 0x7, CLEARWATER_OSR_ENUM_SIZE, + clearwater_in_dmic_osr_text, clearwater_in_dmic_osr_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DMIC4L_CONTROL, CLEARWATER_IN4_OSR_SHIFT, + 0x7, CLEARWATER_OSR_ENUM_SIZE, + clearwater_in_dmic_osr_text, clearwater_in_dmic_osr_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DMIC5L_CONTROL, CLEARWATER_IN5_OSR_SHIFT, + 0x7, CLEARWATER_OSR_ENUM_SIZE, + clearwater_in_dmic_osr_text, clearwater_in_dmic_osr_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DMIC6L_CONTROL, CLEARWATER_IN6_OSR_SHIFT, + 0x7, CLEARWATER_OSR_ENUM_SIZE, + clearwater_in_dmic_osr_text, clearwater_in_dmic_osr_val), +}; +EXPORT_SYMBOL_GPL(clearwater_in_dmic_osr); + +static const char * const arizona_anc_input_src_text[] = { + "None", "IN1", "IN2", "IN3", "IN4", "IN5", "IN6", +}; + +static const char * const arizona_anc_channel_src_text[] = { + "None", "Left", "Right", "Combine", +}; + +const struct soc_enum arizona_anc_input_src[] = { + SOC_ENUM_SINGLE(ARIZONA_ANC_SRC, + ARIZONA_IN_RXANCL_SEL_SHIFT, + ARRAY_SIZE(arizona_anc_input_src_text), + arizona_anc_input_src_text), + SOC_ENUM_SINGLE(ARIZONA_FCL_ADC_REFORMATTER_CONTROL, + ARIZONA_FCL_MIC_MODE_SEL, + ARRAY_SIZE(arizona_anc_channel_src_text), + arizona_anc_channel_src_text), + SOC_ENUM_SINGLE(ARIZONA_ANC_SRC, + ARIZONA_IN_RXANCR_SEL_SHIFT, + ARRAY_SIZE(arizona_anc_input_src_text), + arizona_anc_input_src_text), + SOC_ENUM_SINGLE(ARIZONA_FCR_ADC_REFORMATTER_CONTROL, + ARIZONA_FCR_MIC_MODE_SEL, + ARRAY_SIZE(arizona_anc_channel_src_text), + arizona_anc_channel_src_text), +}; +EXPORT_SYMBOL_GPL(arizona_anc_input_src); + +const struct soc_enum clearwater_anc_input_src[] = { + SOC_ENUM_SINGLE(ARIZONA_ANC_SRC, + ARIZONA_IN_RXANCL_SEL_SHIFT, + ARRAY_SIZE(arizona_anc_input_src_text), + arizona_anc_input_src_text), + SOC_ENUM_SINGLE(ARIZONA_FCL_ADC_REFORMATTER_CONTROL, + ARIZONA_FCL_MIC_MODE_SEL, + ARRAY_SIZE(arizona_anc_channel_src_text), + arizona_anc_channel_src_text), + SOC_ENUM_SINGLE(ARIZONA_ANC_SRC, + ARIZONA_IN_RXANCR_SEL_SHIFT, + ARRAY_SIZE(arizona_anc_input_src_text), + arizona_anc_input_src_text), + SOC_ENUM_SINGLE(CLEARWATER_FCR_ADC_REFORMATTER_CONTROL, + ARIZONA_FCR_MIC_MODE_SEL, + ARRAY_SIZE(arizona_anc_channel_src_text), + arizona_anc_channel_src_text), +}; +EXPORT_SYMBOL_GPL(clearwater_anc_input_src); + +static const char * const arizona_anc_ng_texts[] = { + "None", + "Internal", + "External", +}; + +const struct soc_enum arizona_anc_ng_enum = +SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(arizona_anc_ng_texts), + arizona_anc_ng_texts); +EXPORT_SYMBOL_GPL(arizona_anc_ng_enum); + +static const char * const arizona_output_anc_src_text[] = { + "None", "RXANCL", "RXANCR", +}; + +const struct soc_enum arizona_output_anc_src[] = { + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1L, + ARIZONA_OUT1L_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1R, + ARIZONA_OUT1R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2L, + ARIZONA_OUT2L_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_2R, + ARIZONA_OUT2R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3L, + ARIZONA_OUT3L_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_DAC_VOLUME_LIMIT_3R, + ARIZONA_OUT3R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_4L, + ARIZONA_OUT4L_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_4R, + ARIZONA_OUT4R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_5L, + ARIZONA_OUT5L_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_5R, + ARIZONA_OUT5R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_6L, + ARIZONA_OUT6L_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_6R, + ARIZONA_OUT6R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), +}; +EXPORT_SYMBOL_GPL(arizona_output_anc_src); + +const struct soc_enum clearwater_output_anc_src_defs[] = { + SOC_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3R, + ARIZONA_OUT3R_ANC_SRC_SHIFT, + ARRAY_SIZE(arizona_output_anc_src_text), + arizona_output_anc_src_text), +}; +EXPORT_SYMBOL_GPL(clearwater_output_anc_src_defs); + +static const char * const arizona_ip_mode_text[2] = { + "Analog", "Digital", +}; + +const struct soc_enum arizona_ip_mode[] = { + SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_MODE_SHIFT, + ARRAY_SIZE(arizona_ip_mode_text), arizona_ip_mode_text), + SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_MODE_SHIFT, + ARRAY_SIZE(arizona_ip_mode_text), arizona_ip_mode_text), + SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_MODE_SHIFT, + ARRAY_SIZE(arizona_ip_mode_text), arizona_ip_mode_text), +}; +EXPORT_SYMBOL_GPL(arizona_ip_mode); + +int arizona_ip_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int reg, ret = 0; + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + /* Cannot change input mode on an active input*/ + reg = snd_soc_read(codec, ARIZONA_INPUT_ENABLES); + + switch (e->reg) { + case ARIZONA_IN1L_CONTROL: + if (reg & (ARIZONA_IN1L_ENA_MASK |ARIZONA_IN1R_ENA_MASK)) { + ret = -EBUSY; + goto exit; + } + break; + case ARIZONA_IN2L_CONTROL: + if (reg & (ARIZONA_IN2L_ENA_MASK |ARIZONA_IN2R_ENA_MASK)) { + ret = -EBUSY; + goto exit; + } + break; + case ARIZONA_IN3L_CONTROL: + if (reg & (ARIZONA_IN3L_ENA_MASK |ARIZONA_IN3R_ENA_MASK)) { + ret = -EBUSY; + goto exit; + } + break; + default: + ret = -EINVAL; + goto exit; + break; + } + + ret = snd_soc_put_enum_double(kcontrol, ucontrol); +exit: + mutex_unlock(&codec->card->dapm_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_ip_mode_put); + +int moon_in_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int reg, mask; + int ret = 0; + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + /* Cannot change rate on an active input */ + reg = snd_soc_read(codec, ARIZONA_INPUT_ENABLES); + mask = (e->reg - ARIZONA_IN1L_CONTROL) / 4; + mask ^= 0x1; /* Flip bottom bit for channel order */ + + if ((reg) & (1 << mask)) { + ret = -EBUSY; + goto exit; + } + + ret = snd_soc_put_value_enum_double(kcontrol, ucontrol); +exit: + mutex_unlock(&codec->card->dapm_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(moon_in_rate_put); + +int moon_dfc_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int reg = e->reg; + unsigned int val; + int ret = 0; + + reg = ((reg / 6) * 6) - 2; + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + /* Cannot change dfc settings when its on */ + val = snd_soc_read(codec, reg); + if (val & MOON_DFC1_ENA) { + ret = -EBUSY; + goto exit; + } + + ret = snd_soc_put_value_enum_double(kcontrol, ucontrol); +exit: + mutex_unlock(&codec->card->dapm_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(moon_dfc_put); + +int moon_lp_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + unsigned int reg, mask; + int ret; + + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + /* Cannot change lp mode on an active input */ + reg = snd_soc_read(codec, ARIZONA_INPUT_ENABLES); + mask = (mc->reg - ARIZONA_ADC_DIGITAL_VOLUME_1L) / 4; + mask ^= 0x1; /* Flip bottom bit for channel order */ + + if ((reg) & (1 << mask)) { + ret = -EBUSY; + dev_err(codec->dev, + "Can't change lp mode on an active input\n"); + goto exit; + } + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + +exit: + mutex_unlock(&codec->card->dapm_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(moon_lp_mode_put); + static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena) { struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); @@ -534,26 +2436,81 @@ static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena) ARIZONA_IN_VU, val); } +static int arizona_update_input(struct arizona* arizona, bool enable) +{ + unsigned int val; + + switch (arizona->type) { + case WM8280: + case WM5110: + if (arizona->rev >= 6) + return 0; + break; + default: + return 0; + } + + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + + if (enable) { + arizona_florida_mute_analog(arizona, ARIZONA_IN1L_MUTE); + + msleep(10); + + regmap_write(arizona->regmap, 0x3A6, 0x5555); + regmap_write(arizona->regmap, 0x3A5, 0x3); + } else { + regmap_read(arizona->regmap, 0x3A5, &val); + if (val) { + msleep(10); + regmap_write(arizona->regmap, 0x3A5, 0x0); + regmap_write(arizona->regmap, 0x3A6, 0x0); + msleep(5); + } + + arizona_florida_mute_analog(arizona, 0); + } + + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + + return 0; +} + int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + unsigned int ctrl; unsigned int reg; - if (w->shift % 2) + if (w->shift % 2) { reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8); - else + ctrl = reg - 1; + } else { reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8); + ctrl = reg - 5; + } switch (event) { case SND_SOC_DAPM_PRE_PMU: priv->in_pending++; + + /* Check for analogue input */ + if ((snd_soc_read(w->codec, ctrl) & 0x0400) == 0) + arizona_update_input(priv->arizona, true); + break; case SND_SOC_DAPM_POST_PMU: + priv->in_pending--; + + if (priv->in_pending == 0) + arizona_update_input(priv->arizona, false); + snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0); /* If this is the last input pending then allow VU */ - priv->in_pending--; if (priv->in_pending == 0) { msleep(1); arizona_in_set_vu(w->codec, 1); @@ -575,11 +2532,103 @@ int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, } EXPORT_SYMBOL_GPL(arizona_in_ev); +static void clearwater_hp_post_enable(struct snd_soc_dapm_widget *w) +{ + unsigned int val; + + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + case ARIZONA_OUT1R_ENA_SHIFT: + val = snd_soc_read(w->codec, ARIZONA_OUTPUT_ENABLES_1); + val &= (ARIZONA_OUT1L_ENA | ARIZONA_OUT1R_ENA); + + if (val == (ARIZONA_OUT1L_ENA | ARIZONA_OUT1R_ENA)) + snd_soc_update_bits(w->codec, + CLEARWATER_EDRE_HP_STEREO_CONTROL, + ARIZONA_HP1_EDRE_STEREO_MASK, + ARIZONA_HP1_EDRE_STEREO); + break; + + default: + break; + } +} + +static void clearwater_hp_post_disable(struct snd_soc_dapm_widget *w) +{ + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + snd_soc_write(w->codec, + ARIZONA_DCS_HP1L_CONTROL, + 0x2006); + break; + case ARIZONA_OUT1R_ENA_SHIFT: + snd_soc_write(w->codec, + ARIZONA_DCS_HP1R_CONTROL, + 0x2006); + break; + default: + return; + } + + /* Only get to here for OUT1L and OUT1R */ + snd_soc_update_bits(w->codec, + CLEARWATER_EDRE_HP_STEREO_CONTROL, + ARIZONA_HP1_EDRE_STEREO_MASK, + 0); +} + +int clearwater_put_dre(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + int ret; + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + + mutex_unlock(&codec->card->dapm_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(clearwater_put_dre); + int arizona_out_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + struct arizona *arizona = priv->arizona; + int out_up_delay; + + switch (arizona->type) { + case CS47L90: + case CS47L91: + out_up_delay = 6; + break; + default: + out_up_delay = 17; + break; + } + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + case ARIZONA_OUT1R_ENA_SHIFT: + case ARIZONA_OUT2L_ENA_SHIFT: + case ARIZONA_OUT2R_ENA_SHIFT: + case ARIZONA_OUT3L_ENA_SHIFT: + case ARIZONA_OUT3R_ENA_SHIFT: + priv->out_up_pending++; + priv->out_up_delay += out_up_delay; + break; + default: + break; + } + break; + case SND_SOC_DAPM_POST_PMU: switch (w->shift) { case ARIZONA_OUT1L_ENA_SHIFT: @@ -588,9 +2637,54 @@ int arizona_out_ev(struct snd_soc_dapm_widget *w, case ARIZONA_OUT2R_ENA_SHIFT: case ARIZONA_OUT3L_ENA_SHIFT: case ARIZONA_OUT3R_ENA_SHIFT: - msleep(17); + priv->out_up_pending--; + if (!priv->out_up_pending) { + if (priv->out_up_pending < 20) { + int delay = priv->out_up_delay * 1000; + + usleep_range(delay, delay + 1000); + } else { + msleep(priv->out_up_delay); + } + priv->out_up_delay = 0; + } + break; + + default: + break; + } + break; + + case SND_SOC_DAPM_PRE_PMD: + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + case ARIZONA_OUT1R_ENA_SHIFT: + case ARIZONA_OUT2L_ENA_SHIFT: + case ARIZONA_OUT2R_ENA_SHIFT: + case ARIZONA_OUT3L_ENA_SHIFT: + case ARIZONA_OUT3R_ENA_SHIFT: + priv->out_down_pending++; + priv->out_down_delay++; + break; + default: break; + } + break; + case SND_SOC_DAPM_POST_PMD: + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + case ARIZONA_OUT1R_ENA_SHIFT: + case ARIZONA_OUT2L_ENA_SHIFT: + case ARIZONA_OUT2R_ENA_SHIFT: + case ARIZONA_OUT3L_ENA_SHIFT: + case ARIZONA_OUT3R_ENA_SHIFT: + priv->out_down_pending--; + if (!priv->out_down_pending) { + msleep(priv->out_down_delay); + priv->out_down_delay = 0; + } + break; default: break; } @@ -608,50 +2702,249 @@ int arizona_hp_ev(struct snd_soc_dapm_widget *w, struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); unsigned int mask = 1 << w->shift; unsigned int val; + unsigned int ep_sel = 0; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + val = mask; + break; + case SND_SOC_DAPM_PRE_PMD: + val = 0; + break; + case SND_SOC_DAPM_PRE_PMU: + case SND_SOC_DAPM_POST_PMD: + return arizona_out_ev(w, kcontrol, event); + default: + return -EINVAL; + } + + /* Store the desired state for the HP outputs */ + priv->arizona->hp_ena &= ~mask; + priv->arizona->hp_ena |= val; + + /* in case of Marley and Gaines check if OUT1 is routed to EPOUT, + * do not disable OUT1 in this case */ + switch (priv->arizona->type) { + case CS47L15: + case CS47L35: + regmap_read(priv->arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, + &ep_sel); + ep_sel &= ARIZONA_EP_SEL_MASK; + break; + default: + break; + } + + /* Force off if HPDET clamp is active */ + if ((priv->arizona->hpdet_clamp || + priv->arizona->hp_impedance_x100 <= + OHM_TO_HOHM(priv->arizona->pdata.hpdet_short_circuit_imp)) && + !ep_sel) + val = 0; + + snd_soc_update_bits(w->codec, ARIZONA_OUTPUT_ENABLES_1, mask, val); + + return arizona_out_ev(w, kcontrol, event); +} +EXPORT_SYMBOL_GPL(arizona_hp_ev); + +int clearwater_hp_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + int ret; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + case SND_SOC_DAPM_PRE_PMD: + return arizona_hp_ev(w, kcontrol, event); + case SND_SOC_DAPM_POST_PMU: + ret = arizona_hp_ev(w, kcontrol, event); + if (ret < 0) + return ret; + + clearwater_hp_post_enable(w); + return 0; + case SND_SOC_DAPM_POST_PMD: + ret = arizona_hp_ev(w, kcontrol, event); + clearwater_hp_post_disable(w); + return ret; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(clearwater_hp_ev); + +int arizona_anc_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + unsigned int val; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + val = 1 << w->shift; + break; + case SND_SOC_DAPM_PRE_PMD: + val = 1 << (w->shift + 1); + break; + default: + return 0; + } + + snd_soc_write(w->codec, ARIZONA_CLOCK_CONTROL, val); + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_anc_ev); + +unsigned int arizona_hpimp_cb(struct device *dev) +{ + struct arizona *arizona = dev_get_drvdata(dev); + + return arizona->hp_impedance_x100; +} +EXPORT_SYMBOL_GPL(arizona_hpimp_cb); + +static int arizona_dvfs_enable(struct snd_soc_codec *codec) +{ + const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int ret; + + ret = regulator_set_voltage(arizona->dcvdd, 1800000, 1800000); + if (ret) { + dev_err(codec->dev, "Failed to boost DCVDD: %d\n", ret); + return ret; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, + ARIZONA_SUBSYS_MAX_FREQ, + ARIZONA_SUBSYS_MAX_FREQ); + if (ret) { + dev_err(codec->dev, "Failed to enable subsys max: %d\n", ret); + regulator_set_voltage(arizona->dcvdd, 1200000, 1800000); + return ret; + } + + return 0; +} + +static int arizona_dvfs_disable(struct snd_soc_codec *codec) +{ + const struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int ret; + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_DYNAMIC_FREQUENCY_SCALING_1, + ARIZONA_SUBSYS_MAX_FREQ, 0); + if (ret) { + dev_err(codec->dev, "Failed to disable subsys max: %d\n", ret); + return ret; + } + + ret = regulator_set_voltage(arizona->dcvdd, 1200000, 1800000); + if (ret) { + dev_err(codec->dev, "Failed to unboost DCVDD: %d\n", ret); + return ret; + } + + return 0; +} + +int arizona_dvfs_up(struct snd_soc_codec *codec, unsigned int flags) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + mutex_lock(&priv->dvfs_lock); + + if (!priv->dvfs_cached && !priv->dvfs_reqs) { + ret = arizona_dvfs_enable(codec); + if (ret) + goto err; + } + + priv->dvfs_reqs |= flags; +err: + mutex_unlock(&priv->dvfs_lock); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_dvfs_up); + +int arizona_dvfs_down(struct snd_soc_codec *codec, unsigned int flags) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + unsigned int old_reqs; + int ret = 0; + + mutex_lock(&priv->dvfs_lock); + + old_reqs = priv->dvfs_reqs; + priv->dvfs_reqs &= ~flags; + + if (!priv->dvfs_cached && old_reqs && !priv->dvfs_reqs) + ret = arizona_dvfs_disable(codec); + + mutex_unlock(&priv->dvfs_lock); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_dvfs_down); + +int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + int ret = 0; + + mutex_lock(&priv->dvfs_lock); switch (event) { case SND_SOC_DAPM_POST_PMU: - val = mask; + if (priv->dvfs_reqs) + ret = arizona_dvfs_enable(codec); + + priv->dvfs_cached = false; break; case SND_SOC_DAPM_PRE_PMD: - val = 0; + /* We must ensure DVFS is disabled before the codec goes into + * suspend so that we are never in an illegal state of DVFS + * enabled without enough DCVDD + */ + priv->dvfs_cached = true; + + if (priv->dvfs_reqs) + ret = arizona_dvfs_disable(codec); break; default: - return -EINVAL; + break; } - /* Store the desired state for the HP outputs */ - priv->arizona->hp_ena &= ~mask; - priv->arizona->hp_ena |= val; - - /* Force off if HPDET magic is active */ - if (priv->arizona->hpdet_magic) - val = 0; - - snd_soc_update_bits(w->codec, ARIZONA_OUTPUT_ENABLES_1, mask, val); + mutex_unlock(&priv->dvfs_lock); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev); - return arizona_out_ev(w, kcontrol, event); +void arizona_init_dvfs(struct arizona_priv *priv) +{ + mutex_init(&priv->dvfs_lock); } -EXPORT_SYMBOL_GPL(arizona_hp_ev); +EXPORT_SYMBOL_GPL(arizona_init_dvfs); -static unsigned int arizona_sysclk_48k_rates[] = { +static unsigned int arizona_opclk_ref_48k_rates[] = { 6144000, 12288000, 24576000, 49152000, - 73728000, - 98304000, - 147456000, }; -static unsigned int arizona_sysclk_44k1_rates[] = { +static unsigned int arizona_opclk_ref_44k1_rates[] = { 5644800, 11289600, 22579200, 45158400, - 67737600, - 90316800, - 135475200, }; static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk, @@ -660,7 +2953,24 @@ static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk, struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); unsigned int reg; unsigned int *rates; - int ref, div, refclk; + int ref, refclk; + unsigned int div, div_incr; + + switch (priv->arizona->type) { + case WM5102: + case WM5110: + case WM8280: + case WM8998: + case WM1814: + case CS47L24: + case WM1831: + case WM8997: + div_incr = 1; + break; + default: + div_incr = 2; + break; + } switch (clk) { case ARIZONA_CLK_OPCLK: @@ -676,13 +2986,13 @@ static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk, } if (refclk % 8000) - rates = arizona_sysclk_44k1_rates; + rates = arizona_opclk_ref_44k1_rates; else - rates = arizona_sysclk_48k_rates; + rates = arizona_opclk_ref_48k_rates; - for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) && + for (ref = 0; ref < ARRAY_SIZE(arizona_opclk_ref_48k_rates) && rates[ref] <= refclk; ref++) { - div = 1; + div = div_incr; while (rates[ref] / div >= freq && div < 32) { if (rates[ref] / div == freq) { dev_dbg(codec->dev, "Configured %dHz OPCLK\n", @@ -695,7 +3005,7 @@ static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk, ref); return 0; } - div++; + div += div_incr; } } @@ -703,70 +3013,281 @@ static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk, return -EINVAL; } -int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id, - int source, unsigned int freq, int dir) +static int arizona_get_sysclk_setting(unsigned int freq) { - struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); - struct arizona *arizona = priv->arizona; - char *name; - unsigned int reg; - unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK; - unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT; - unsigned int *clk; - - switch (clk_id) { - case ARIZONA_CLK_SYSCLK: - name = "SYSCLK"; - reg = ARIZONA_SYSTEM_CLOCK_1; - clk = &priv->sysclk; - mask |= ARIZONA_SYSCLK_FRAC; - break; - case ARIZONA_CLK_ASYNCCLK: - name = "ASYNCCLK"; - reg = ARIZONA_ASYNC_CLOCK_1; - clk = &priv->asyncclk; - break; - case ARIZONA_CLK_OPCLK: - case ARIZONA_CLK_ASYNC_OPCLK: - return arizona_set_opclk(codec, clk_id, freq); + switch (freq) { + case 0: + case 5644800: + case 6144000: + return 0; + case 11289600: + case 12288000: + return ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + case 22579200: + case 24576000: + return ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + case 45158400: + case 49152000: + return ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + case 67737600: + case 73728000: + return ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + case 90316800: + case 98304000: + return ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + case 135475200: + case 147456000: + return ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; default: return -EINVAL; } +} +static int clearwater_get_sysclk_setting(unsigned int freq) +{ switch (freq) { - case 5644800: - case 6144000: - break; + case 0: + case 5644800: + case 6144000: + return 0; case 11289600: case 12288000: - val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; - break; + return ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; case 22579200: case 24576000: - val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; - break; + return ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; case 45158400: case 49152000: - val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; - break; - case 67737600: - case 73728000: - val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; - break; + return ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; case 90316800: case 98304000: - val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; - break; + return CLEARWATER_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + default: + return -EINVAL; + } +} + +static int clearwater_get_dspclk_setting(unsigned int freq, + struct arizona *arizona, + int source) +{ + switch (freq) { + case 0: + return 0; + case 45158400: + case 49152000: + switch (arizona->type) { + case WM1840: + case WM8285: + if (arizona->rev >= 3 && + source == CLEARWATER_CLK_SRC_FLL1_DIV6) + return ARIZONA_CLK_49MHZ << + ARIZONA_SYSCLK_FREQ_SHIFT; + else + return -EINVAL; + default: + return -EINVAL; + } case 135475200: case 147456000: - val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + return CLEARWATER_DSP_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT; + default: + return -EINVAL; + } +} + +static void clearwater_get_dsp_reg_seq(unsigned int cur, unsigned int tar, + unsigned int reg, unsigned int mask, + struct reg_sequence *s) +{ + /* To transition DSPCLK to a new source and frequency we must: + * - Disable DSPCLK_ENA + * - Wait 34us + * - Write the new source, freq and enable in one write + */ + unsigned int tmp; + + mask |= CLEARWATER_DSP_CLK_ENA_MASK; + + s[0].reg = reg; + s[0].def = (cur & ~CLEARWATER_DSP_CLK_ENA_MASK); + /* The required delay is one worst case clock period (32kHz) + 2 us */ + s[0].delay_us = 34; + + /* Clear the fields we care about */ + tmp = (cur & ~mask); + + /* Update the fields */ + tmp |= tar & mask; + + /* Re-set the enable bit */ + tmp |= CLEARWATER_DSP_CLK_ENA_MASK; + + s[1].reg = reg; + s[1].def = tmp; + s[1].delay_us = 0; +} + +static int moon_get_dspclk_setting(unsigned int freq, unsigned int *val) +{ + if (freq > 150000000) + return -EINVAL; + + /* freq * (2^6) / (10^6) */ + *val = freq / 15625; + + return 0; +} + +int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id, + int source, unsigned int freq, int dir) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int ret = 0; + char *name; + unsigned int reg; + unsigned int reg2, val2; + unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK; + unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT; + int clk_freq; + int *clk; + unsigned int dspclk_change = 0; + unsigned int dspclk_val; + struct reg_sequence dspclk_seq[2]; + + reg2 = val2 = 0; + + switch (arizona->type) { + case WM8997: + case WM8998: + case WM1814: + case WM5102: + case WM8280: + case WM5110: + case WM1831: + case CS47L24: + switch (clk_id) { + case ARIZONA_CLK_SYSCLK: + name = "SYSCLK"; + reg = ARIZONA_SYSTEM_CLOCK_1; + clk = &priv->sysclk; + mask |= ARIZONA_SYSCLK_FRAC; + clk_freq = arizona_get_sysclk_setting(freq); + break; + case ARIZONA_CLK_ASYNCCLK: + name = "ASYNCCLK"; + reg = ARIZONA_ASYNC_CLOCK_1; + clk = &priv->asyncclk; + clk_freq = arizona_get_sysclk_setting(freq); + break; + case ARIZONA_CLK_OPCLK: + case ARIZONA_CLK_ASYNC_OPCLK: + return arizona_set_opclk(codec, clk_id, freq); + default: + return -EINVAL; + } break; - case 0: + case CS47L35: + case WM8285: + case WM1840: + switch (clk_id) { + case ARIZONA_CLK_SYSCLK: + name = "SYSCLK"; + reg = ARIZONA_SYSTEM_CLOCK_1; + clk = &priv->sysclk; + clk_freq = clearwater_get_sysclk_setting(freq); + mask |= ARIZONA_SYSCLK_FRAC; + break; + case ARIZONA_CLK_ASYNCCLK: + name = "ASYNCCLK"; + reg = ARIZONA_ASYNC_CLOCK_1; + clk = &priv->asyncclk; + clk_freq = clearwater_get_sysclk_setting(freq); + break; + case ARIZONA_CLK_OPCLK: + case ARIZONA_CLK_ASYNC_OPCLK: + return arizona_set_opclk(codec, clk_id, freq); + case ARIZONA_CLK_DSPCLK: + name = "DSPCLK"; + reg = CLEARWATER_DSP_CLOCK_1; + clk = &priv->dspclk; + clk_freq = clearwater_get_dspclk_setting(freq, + arizona, + source); + switch (arizona->type) { + case WM1840: + case WM8285: + dspclk_change = 1; + break; + default: + break; + } + + break; + default: + return -EINVAL; + } + break; + default: + switch (clk_id) { + case ARIZONA_CLK_SYSCLK: + name = "SYSCLK"; + reg = ARIZONA_SYSTEM_CLOCK_1; + clk = &priv->sysclk; + clk_freq = clearwater_get_sysclk_setting(freq); + mask |= ARIZONA_SYSCLK_FRAC; + break; + case ARIZONA_CLK_ASYNCCLK: + name = "ASYNCCLK"; + reg = ARIZONA_ASYNC_CLOCK_1; + clk = &priv->asyncclk; + clk_freq = clearwater_get_sysclk_setting(freq); + break; + case ARIZONA_CLK_OPCLK: + case ARIZONA_CLK_ASYNC_OPCLK: + return arizona_set_opclk(codec, clk_id, freq); + case ARIZONA_CLK_DSPCLK: + name = "DSPCLK"; + reg = CLEARWATER_DSP_CLOCK_1; + mask = ARIZONA_SYSCLK_SRC_MASK; + reg2 = CLEARWATER_DSP_CLOCK_2; + clk = &priv->dspclk; + ret = moon_get_dspclk_setting(freq, &val2); + break; + default: + return -EINVAL; + } + break; + } + + if (reg2) { + if (ret < 0) { + dev_err(arizona->dev, "Failed to get clk setting for %dHZ\n", + freq); + return ret; + } + ret = regmap_write(arizona->regmap, + reg2, val2); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to set dsp freq to %d\n", val2); + return ret; + } + } else { + if (clk_freq < 0) { + dev_err(arizona->dev, "Failed to get clk setting for %dHZ\n", + freq); + return ret; + } + + val |= clk_freq; + } + + if (freq == 0) { dev_dbg(arizona->dev, "%s cleared\n", name); *clk = freq; return 0; - default: - return -EINVAL; } *clk = freq; @@ -776,14 +3297,59 @@ int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id, dev_dbg(arizona->dev, "%s set to %uHz", name, freq); - return regmap_update_bits(arizona->regmap, reg, mask, val); + /* For the cases where we are changing DSPCLK on the fly we need to + * make sure DSPCLK_ENA is disabled for at least 32uS before changing it + */ + if (dspclk_change) { + mutex_lock(&arizona->dspclk_ena_lock); + + /* Is DSPCLK_ENA on? */ + ret = regmap_read(arizona->regmap, reg, &dspclk_val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read 0x%04x: %d\n", + reg, ret); + goto err; + } + + if (dspclk_val & CLEARWATER_DSP_CLK_ENA_MASK) { + clearwater_get_dsp_reg_seq(dspclk_val, val, reg, mask, + dspclk_seq); + + ret = regmap_multi_reg_write(arizona->regmap, + dspclk_seq, + ARRAY_SIZE(dspclk_seq)); + + if (ret != 0) { + dev_err(arizona->dev, + "Failed to write dspclk_seq: %d\n", + ret); + goto err; + } + } else { + ret = regmap_update_bits(arizona->regmap, reg, mask, + val); + } + + mutex_unlock(&arizona->dspclk_ena_lock); + } else { + ret = regmap_update_bits(arizona->regmap, reg, mask, val); + } + + return ret; + +err: + mutex_unlock(&arizona->dspclk_ena_lock); + return ret; } EXPORT_SYMBOL_GPL(arizona_set_sysclk); static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct snd_soc_codec *codec = dai->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; int lrclk, bclk, mode, base; + unsigned int mask; base = dai->driver->base; @@ -792,10 +3358,26 @@ static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_DSP_A: - mode = 0; + mode = ARIZONA_FMT_DSP_MODE_A; + break; + case SND_SOC_DAIFMT_DSP_B: + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) + != SND_SOC_DAIFMT_CBM_CFM) { + arizona_aif_err(dai, "DSP_B not valid in slave mode\n"); + return -EINVAL; + } + mode = ARIZONA_FMT_DSP_MODE_B; break; case SND_SOC_DAIFMT_I2S: - mode = 2; + mode = ARIZONA_FMT_I2S_MODE; + break; + case SND_SOC_DAIFMT_LEFT_J: + if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) + != SND_SOC_DAIFMT_CBM_CFM) { + arizona_aif_err(dai, "LEFT_J not valid in slave mode\n"); + return -EINVAL; + } + mode = ARIZONA_FMT_LEFT_JUSTIFIED_MODE; break; default: arizona_aif_err(dai, "Unsupported DAI format %d\n", @@ -845,9 +3427,22 @@ static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_PIN_CTRL, ARIZONA_AIF1TX_LRCLK_INV | ARIZONA_AIF1TX_LRCLK_MSTR, lrclk); + + mask = ARIZONA_AIF1RX_LRCLK_INV | ARIZONA_AIF1RX_LRCLK_MSTR; + switch (arizona->type) { + case CS47L90: + case CS47L91: + mask |= ARIZONA_AIF1RX_LRCLK_ADV; + if (arizona->pdata.lrclk_adv[dai->id - 1] && + mode == SND_SOC_DAIFMT_DSP_A) + lrclk |= ARIZONA_AIF1RX_LRCLK_ADV; + break; + default: + break; + } + snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_PIN_CTRL, - ARIZONA_AIF1RX_LRCLK_INV | - ARIZONA_AIF1RX_LRCLK_MSTR, lrclk); + mask, lrclk); snd_soc_update_bits(codec, base + ARIZONA_AIF_FORMAT, ARIZONA_AIF1_FMT_MASK, mode); @@ -876,29 +3471,6 @@ static const int arizona_48k_bclk_rates[] = { 24576000, }; -static const unsigned int arizona_48k_rates[] = { - 12000, - 24000, - 48000, - 96000, - 192000, - 384000, - 768000, - 4000, - 8000, - 16000, - 32000, - 64000, - 128000, - 256000, - 512000, -}; - -static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = { - .count = ARRAY_SIZE(arizona_48k_rates), - .list = arizona_48k_rates, -}; - static const int arizona_44k1_bclk_rates[] = { -1, 44100, @@ -921,22 +3493,7 @@ static const int arizona_44k1_bclk_rates[] = { 22579200, }; -static const unsigned int arizona_44k1_rates[] = { - 11025, - 22050, - 44100, - 88200, - 176400, - 352800, - 705600, -}; - -static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = { - .count = ARRAY_SIZE(arizona_44k1_rates), - .list = arizona_44k1_rates, -}; - -static int arizona_sr_vals[] = { +static const unsigned int arizona_sr_vals[] = { 0, 12000, 24000, @@ -963,20 +3520,75 @@ static int arizona_sr_vals[] = { 512000, }; +#define ARIZONA_48K_RATE_MASK 0x0F003E +#define ARIZONA_44K1_RATE_MASK 0x003E00 +#define ARIZONA_RATE_MASK (ARIZONA_48K_RATE_MASK | ARIZONA_44K1_RATE_MASK) + +static const struct snd_pcm_hw_constraint_list arizona_constraint = { + .count = ARRAY_SIZE(arizona_sr_vals), + .list = arizona_sr_vals, +}; + +int arizona_put_sample_rate_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int val; + unsigned int flag; + int ret; + + ret = snd_soc_put_value_enum_double(kcontrol, ucontrol); + if (ret == 0) + return 0; /* register value wasn't changed */ + + val = e->values[ucontrol->value.enumerated.item[0]]; + + switch (e->reg) { + case ARIZONA_SAMPLE_RATE_2: + flag = ARIZONA_DVFS_SR2_RQ; + break; + + case ARIZONA_SAMPLE_RATE_3: + flag = ARIZONA_DVFS_SR3_RQ; + break; + + case ARIZONA_ASYNC_SAMPLE_RATE_2: + flag = ARIZONA_DVFS_ASR2_RQ; + break; + + default: + return ret; + } + + if (arizona_sr_vals[val] >= 88200) { + ret = arizona_dvfs_up(codec, flag); + if (ret != 0) + dev_err(codec->dev, "Failed to raise DVFS %d\n", ret); + } else { + ret = arizona_dvfs_down(codec, flag); + } + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_put_sample_rate_enum); + static int arizona_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; - const struct snd_pcm_hw_constraint_list *constraint; unsigned int base_rate; switch (dai_priv->clk) { case ARIZONA_CLK_SYSCLK: + case ARIZONA_CLK_SYSCLK_2: + case ARIZONA_CLK_SYSCLK_3: base_rate = priv->sysclk; break; case ARIZONA_CLK_ASYNCCLK: + case ARIZONA_CLK_ASYNCCLK_2: base_rate = priv->asyncclk; break; default: @@ -984,16 +3596,44 @@ static int arizona_startup(struct snd_pcm_substream *substream, } if (base_rate == 0) - return 0; - - if (base_rate % 8000) - constraint = &arizona_44k1_constraint; + dai_priv->constraint.mask = ARIZONA_RATE_MASK; + else if (base_rate % 4000) + dai_priv->constraint.mask = ARIZONA_44K1_RATE_MASK; else - constraint = &arizona_48k_constraint; + dai_priv->constraint.mask = ARIZONA_48K_RATE_MASK; + + return snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, + &dai_priv->constraint); +} + +static void arizona_wm5102_set_dac_comp(struct snd_soc_codec *codec, + unsigned int rate) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + + switch (arizona->type) { + case WM5102: + break; + default: + return; + } - return snd_pcm_hw_constraint_list(substream->runtime, 0, - SNDRV_PCM_HW_PARAM_RATE, - constraint); + mutex_lock(&arizona->reg_setting_lock); + snd_soc_write(codec, 0x80, 0x3); + if (rate >= 176400) { + mutex_lock(&codec->mutex); + snd_soc_write(codec, ARIZONA_DAC_COMP_1, + arizona->out_comp_coeff); + snd_soc_write(codec, ARIZONA_DAC_COMP_2, + arizona->out_comp_enabled); + mutex_unlock(&codec->mutex); + } else { + snd_soc_write(codec, ARIZONA_DAC_COMP_2, 0x0); + } + snd_soc_write(codec, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); } static int arizona_hw_params_rate(struct snd_pcm_substream *substream, @@ -1004,7 +3644,11 @@ static int arizona_hw_params_rate(struct snd_pcm_substream *substream, struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; int base = dai->driver->base; - int i, sr_val; + int ret = 0, err; + int i, sr_val, lim = 0; + const int *sources = NULL; + unsigned int cur, tar; + bool change_rate = false; /* * We will need to be more flexible than this in future, @@ -1020,28 +3664,177 @@ static int arizona_hw_params_rate(struct snd_pcm_substream *substream, } sr_val = i; + switch (priv->arizona->type) { + case WM5102: + case WM8997: + case WM8998: + case WM1814: + if (arizona_sr_vals[sr_val] >= 88200) + ret = arizona_dvfs_up(codec, + ARIZONA_DVFS_SR1_RQ); + else + ret = arizona_dvfs_down(codec, + ARIZONA_DVFS_SR1_RQ); + + if (ret != 0) { + arizona_aif_err(dai, "Failed to change DVFS %d\n", ret); + return ret; + } + break; + + default: + break; + } + + if (base) { + switch (dai_priv->clk) { + case ARIZONA_CLK_SYSCLK: + tar = 0 << ARIZONA_AIF1_RATE_SHIFT; + break; + case ARIZONA_CLK_SYSCLK_2: + tar = 1 << ARIZONA_AIF1_RATE_SHIFT; + break; + case ARIZONA_CLK_SYSCLK_3: + tar = 2 << ARIZONA_AIF1_RATE_SHIFT; + break; + case ARIZONA_CLK_ASYNCCLK: + tar = 8 << ARIZONA_AIF1_RATE_SHIFT; + break; + case ARIZONA_CLK_ASYNCCLK_2: + tar = 9 << ARIZONA_AIF1_RATE_SHIFT; + break; + default: + return -EINVAL; + } + + ret = regmap_read(priv->arizona->regmap, + base + ARIZONA_AIF_RATE_CTRL, &cur); + if (ret != 0) { + arizona_aif_err(dai, "Failed to check rate: %d\n", ret); + return ret; + } + + if ((cur & ARIZONA_AIF1_RATE_MASK) != + (tar & ARIZONA_AIF1_RATE_MASK)) + change_rate = true; + + if (change_rate) { + ret = arizona_get_sources(priv->arizona, dai, + &sources, &lim); + if (ret != 0) { + arizona_aif_err(dai, + "Failed to get aif sources %d\n", + ret); + return ret; + } + + mutex_lock(&priv->arizona->rate_lock); + + ret = arizona_cache_and_clear_sources( + priv->arizona, + sources, + arizona_aif_sources_cache, + lim); + if (ret != 0) { + arizona_aif_err(dai, + "Failed to clear aif sources: %d\n", + ret); + goto out; + } + + clearwater_spin_sysclk(priv->arizona); + } + } + switch (dai_priv->clk) { case ARIZONA_CLK_SYSCLK: + arizona_wm5102_set_dac_comp(codec, params_rate(params)); + snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1, ARIZONA_SAMPLE_RATE_1_MASK, sr_val); if (base) snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, - ARIZONA_AIF1_RATE_MASK, 0); + ARIZONA_AIF1_RATE_MASK, + 0 << ARIZONA_AIF1_RATE_SHIFT); + break; + case ARIZONA_CLK_SYSCLK_2: + arizona_wm5102_set_dac_comp(codec, params_rate(params)); + + snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_2, + ARIZONA_SAMPLE_RATE_2_MASK, sr_val); + if (base) + snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, + ARIZONA_AIF1_RATE_MASK, + 1 << ARIZONA_AIF1_RATE_SHIFT); + break; + case ARIZONA_CLK_SYSCLK_3: + arizona_wm5102_set_dac_comp(codec, params_rate(params)); + + snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_3, + ARIZONA_SAMPLE_RATE_3_MASK, sr_val); + if (base) + snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, + ARIZONA_AIF1_RATE_MASK, + 2 << ARIZONA_AIF1_RATE_SHIFT); break; case ARIZONA_CLK_ASYNCCLK: snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1, - ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val); + ARIZONA_ASYNC_SAMPLE_RATE_1_MASK, sr_val); if (base) snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, ARIZONA_AIF1_RATE_MASK, 8 << ARIZONA_AIF1_RATE_SHIFT); break; + case ARIZONA_CLK_ASYNCCLK_2: + snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_2, + ARIZONA_ASYNC_SAMPLE_RATE_2_MASK, sr_val); + if (base) + snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL, + ARIZONA_AIF1_RATE_MASK, + 9 << ARIZONA_AIF1_RATE_SHIFT); + break; default: arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk); - return -EINVAL; + ret = -EINVAL; } - return 0; + if (change_rate) + clearwater_spin_sysclk(priv->arizona); + +out: + if (change_rate) { + err = arizona_restore_sources(priv->arizona, sources, + arizona_aif_sources_cache, lim); + if (err != 0) { + arizona_aif_err(dai, + "Failed to restore sources: %d\n", + err); + } + + mutex_unlock(&priv->arizona->rate_lock); + } + return ret; +} + +static bool arizona_aif_cfg_changed(struct snd_soc_codec *codec, + int base, int bclk, int lrclk, int frame) +{ + int val; + + val = snd_soc_read(codec, base + ARIZONA_AIF_BCLK_CTRL); + if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK)) + return true; + + val = snd_soc_read(codec, base + ARIZONA_AIF_TX_BCLK_RATE); + if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK)) + return true; + + val = snd_soc_read(codec, base + ARIZONA_AIF_FRAME_CTRL_1); + if (frame != (val & (ARIZONA_AIF1TX_WL_MASK | + ARIZONA_AIF1TX_SLOT_LEN_MASK))) + return true; + + return false; } static int arizona_hw_params(struct snd_pcm_substream *substream, @@ -1054,26 +3847,44 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, int base = dai->driver->base; const int *rates; int i, ret, val; + int channels = params_channels(params); int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1]; + int tdm_width = arizona->tdm_width[dai->id - 1]; + int tdm_slots = arizona->tdm_slots[dai->id - 1]; int bclk, lrclk, wl, frame, bclk_target; + bool reconfig; + unsigned int aif_tx_state = 0, aif_rx_state = 0; if (params_rate(params) % 4000) rates = &arizona_44k1_bclk_rates[0]; else rates = &arizona_48k_bclk_rates[0]; - bclk_target = snd_soc_params_to_bclk(params); - if (chan_limit && chan_limit < params_channels(params)) { + wl = snd_pcm_format_width(params_format(params)); + + if (tdm_slots) { + arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n", + tdm_slots, tdm_width); + bclk_target = tdm_slots * tdm_width * params_rate(params); + channels = tdm_slots; + } else { + bclk_target = snd_soc_params_to_bclk(params); + tdm_width = wl; + } + + if (chan_limit && chan_limit < channels) { arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit); - bclk_target /= params_channels(params); + bclk_target /= channels; bclk_target *= chan_limit; } - /* Force stereo for I2S mode */ + /* Force multiple of 2 channels for I2S mode */ val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT); - if (params_channels(params) == 1 && (val & ARIZONA_AIF1_FMT_MASK)) { + val &= ARIZONA_AIF1_FMT_MASK; + if ((channels & 1) && (val == ARIZONA_FMT_I2S_MODE)) { arizona_aif_dbg(dai, "Forcing stereo mode\n"); - bclk_target *= 2; + bclk_target /= channels; + bclk_target *= channels + 1; } for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) { @@ -1094,35 +3905,62 @@ static int arizona_hw_params(struct snd_pcm_substream *substream, arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n", rates[bclk], rates[bclk] / lrclk); - wl = snd_pcm_format_width(params_format(params)); - frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl; + frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width; + + reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame); + + if (reconfig) { + /* Save AIF TX/RX state */ + aif_tx_state = snd_soc_read(codec, + base + ARIZONA_AIF_TX_ENABLES); + aif_rx_state = snd_soc_read(codec, + base + ARIZONA_AIF_RX_ENABLES); + /* Disable AIF TX/RX before reconfiguring it */ + snd_soc_update_bits(codec, + base + ARIZONA_AIF_TX_ENABLES, 0xff, 0x0); + snd_soc_update_bits(codec, + base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0); + } ret = arizona_hw_params_rate(substream, params, dai); if (ret != 0) - return ret; - - snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL, - ARIZONA_AIF1_BCLK_FREQ_MASK, bclk); - snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE, - ARIZONA_AIF1TX_BCPF_MASK, lrclk); - snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE, - ARIZONA_AIF1RX_BCPF_MASK, lrclk); - snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1, - ARIZONA_AIF1TX_WL_MASK | - ARIZONA_AIF1TX_SLOT_LEN_MASK, frame); - snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2, - ARIZONA_AIF1RX_WL_MASK | - ARIZONA_AIF1RX_SLOT_LEN_MASK, frame); + goto restore_aif; + + if (reconfig) { + snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL, + ARIZONA_AIF1_BCLK_FREQ_MASK, bclk); + snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE, + ARIZONA_AIF1TX_BCPF_MASK, lrclk); + snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE, + ARIZONA_AIF1RX_BCPF_MASK, lrclk); + snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1, + ARIZONA_AIF1TX_WL_MASK | + ARIZONA_AIF1TX_SLOT_LEN_MASK, frame); + snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2, + ARIZONA_AIF1RX_WL_MASK | + ARIZONA_AIF1RX_SLOT_LEN_MASK, frame); + } - return 0; +restore_aif: + if (reconfig) { + /* Restore AIF TX/RX state */ + snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_ENABLES, + 0xff, aif_tx_state); + snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_ENABLES, + 0xff, aif_rx_state); + } + return ret; } -static const char *arizona_dai_clk_str(int clk_id) +static const char * const arizona_dai_clk_str(int clk_id) { switch (clk_id) { case ARIZONA_CLK_SYSCLK: + case ARIZONA_CLK_SYSCLK_2: + case ARIZONA_CLK_SYSCLK_3: return "SYSCLK"; case ARIZONA_CLK_ASYNCCLK: + case ARIZONA_CLK_ASYNCCLK_2: return "ASYNCCLK"; default: return "Unknown clock"; @@ -1139,7 +3977,10 @@ static int arizona_dai_set_sysclk(struct snd_soc_dai *dai, switch (clk_id) { case ARIZONA_CLK_SYSCLK: + case ARIZONA_CLK_SYSCLK_2: + case ARIZONA_CLK_SYSCLK_3: case ARIZONA_CLK_ASYNCCLK: + case ARIZONA_CLK_ASYNCCLK_2: break; default: return -EINVAL; @@ -1161,13 +4002,30 @@ static int arizona_dai_set_sysclk(struct snd_soc_dai *dai, routes[0].sink = dai->driver->capture.stream_name; routes[1].sink = dai->driver->playback.stream_name; - routes[0].source = arizona_dai_clk_str(dai_priv->clk); - routes[1].source = arizona_dai_clk_str(dai_priv->clk); - snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes)); + switch (clk_id) { + case ARIZONA_CLK_SYSCLK: + case ARIZONA_CLK_SYSCLK_2: + case ARIZONA_CLK_SYSCLK_3: + routes[0].source = arizona_dai_clk_str(dai_priv->clk); + routes[1].source = arizona_dai_clk_str(dai_priv->clk); + snd_soc_dapm_del_routes(&codec->dapm, routes, + ARRAY_SIZE(routes)); + break; + default: + break; + } - routes[0].source = arizona_dai_clk_str(clk_id); - routes[1].source = arizona_dai_clk_str(clk_id); - snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes)); + switch (clk_id) { + case ARIZONA_CLK_ASYNCCLK: + case ARIZONA_CLK_ASYNCCLK_2: + routes[0].source = arizona_dai_clk_str(clk_id); + routes[1].source = arizona_dai_clk_str(clk_id); + snd_soc_dapm_add_routes(&codec->dapm, routes, + ARRAY_SIZE(routes)); + break; + default: + break; + } dai_priv->clk = clk_id; @@ -1189,36 +4047,87 @@ static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate) ARIZONA_AIF1_TRI, reg); } +static void arizona_set_channels_to_mask(struct snd_soc_dai *dai, + unsigned int base, + int channels, unsigned int mask) +{ + struct snd_soc_codec *codec = dai->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int slot, i; + + for (i = 0; i < channels; ++i) { + slot = ffs(mask) - 1; + if (slot < 0) + return; + + regmap_write(arizona->regmap, base + i, slot); + + mask &= ~(1 << slot); + } + + if (mask) + arizona_aif_warn(dai, "Too many channels in TDM mask\n"); +} + +static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int slot_width) +{ + struct snd_soc_codec *codec = dai->codec; + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int base = dai->driver->base; + int rx_max_chan = dai->driver->playback.channels_max; + int tx_max_chan = dai->driver->capture.channels_max; + + /* Only support TDM for the physical AIFs */ + if (dai->id > ARIZONA_MAX_AIF) + return -ENOTSUPP; + + if (slots == 0) { + tx_mask = (1 << tx_max_chan) - 1; + rx_mask = (1 << rx_max_chan) - 1; + } + + arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3, + tx_max_chan, tx_mask); + arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11, + rx_max_chan, rx_mask); + + arizona->tdm_width[dai->id - 1] = slot_width; + arizona->tdm_slots[dai->id - 1] = slots; + + return 0; +} + const struct snd_soc_dai_ops arizona_dai_ops = { .startup = arizona_startup, .set_fmt = arizona_set_fmt, + .set_tdm_slot = arizona_set_tdm_slot, .hw_params = arizona_hw_params, .set_sysclk = arizona_dai_set_sysclk, .set_tristate = arizona_set_tristate, }; EXPORT_SYMBOL_GPL(arizona_dai_ops); +const struct snd_soc_dai_ops arizona_simple_dai_ops = { + .startup = arizona_startup, + .hw_params = arizona_hw_params_rate, + .set_sysclk = arizona_dai_set_sysclk, +}; +EXPORT_SYMBOL_GPL(arizona_simple_dai_ops); + int arizona_init_dai(struct arizona_priv *priv, int id) { struct arizona_dai_priv *dai_priv = &priv->dai[id]; dai_priv->clk = ARIZONA_CLK_SYSCLK; + dai_priv->constraint = arizona_constraint; return 0; } EXPORT_SYMBOL_GPL(arizona_init_dai); -static irqreturn_t arizona_fll_clock_ok(int irq, void *data) -{ - struct arizona_fll *fll = data; - - arizona_fll_dbg(fll, "clock OK\n"); - - complete(&fll->ok); - - return IRQ_HANDLED; -} - static struct { unsigned int min; unsigned int max; @@ -1232,104 +4141,276 @@ static struct { { 1000000, 13500000, 0, 1 }, }; -static struct { +static const unsigned int pseudo_fref_max[ARIZONA_FLL_MAX_FRATIO] = { + 13500000, + 6144000, + 6144000, + 3072000, + 3072000, + 2822400, + 2822400, + 1536000, + 1536000, + 1536000, + 1536000, + 1536000, + 1536000, + 1536000, + 1536000, + 768000, +}; + +struct arizona_fll_gain { unsigned int min; unsigned int max; u16 gain; -} fll_gains[] = { +}; + +static struct arizona_fll_gain fll_gains[] = { { 0, 256000, 0 }, { 256000, 1000000, 2 }, { 1000000, 13500000, 4 }, }; -struct arizona_fll_cfg { - int n; - int theta; - int lambda; - int refdiv; - int outdiv; - int fratio; - int gain; +static struct arizona_fll_gain fll_moon_gains[] = { + { 0, 100000, 0 }, + { 100000, 375000, 2 }, + { 375000, 1500000, 3 }, + { 1500000, 6000000, 4 }, + { 6000000, 13500000, 5 }, }; -static int arizona_calc_fll(struct arizona_fll *fll, - struct arizona_fll_cfg *cfg, - unsigned int Fref, - unsigned int Fout) +static int arizona_validate_fll(struct arizona_fll *fll, + unsigned int fin, + unsigned int fvco) +{ + if (fll->fvco && fvco != fll->fvco) { + arizona_fll_err(fll, + "Can't change output on active FLL\n"); + return -EINVAL; + } + + if (fin / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) { + arizona_fll_err(fll, + "Can't scale %dMHz in to <=13.5MHz\n", + fin); + return -EINVAL; + } + + return 0; +} + +static int arizona_find_fratio(struct arizona_fll *fll, unsigned int fref, + unsigned int fvco, int *fratio, bool sync) { - unsigned int target, div, gcd_fll; int i, ratio; - arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, Fout); + switch (fll->arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + break; + case CS47L35: + /* rev A0 is like Clearwater, so break */ + if (fll->arizona->rev == 0) + break; + /* rev A1 works similar to Moon, so fall through to default */ + default: + if (!sync) { + ratio = 1; + while ((fvco / (ratio * fref)) > ARIZONA_FLL_MAX_N) + ratio++; + *fratio = ratio - 1; + return ratio; + } + break; + } + + /* Find an appropriate FLL_FRATIO */ + for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { + if (fll_fratios[i].min <= fref && fref <= fll_fratios[i].max) { + if (fratio) + *fratio = fll_fratios[i].fratio; + return fll_fratios[i].ratio; + } + } + + return -EINVAL; +} + +static int arizona_calc_fratio(struct arizona_fll *fll, + struct arizona_fll_cfg *cfg, + unsigned int fvco, + unsigned int fin, bool sync) +{ + int init_ratio, ratio; + int refdiv, div; + unsigned int fref = fin; - /* Fref must be <=13.5MHz */ + /* Fref must be <=13.5MHz, find initial refdiv */ div = 1; cfg->refdiv = 0; - while ((Fref / div) > 13500000) { + while (fref > ARIZONA_FLL_MAX_FREF) { div *= 2; + fref /= 2; cfg->refdiv++; - if (div > 8) { - arizona_fll_err(fll, - "Can't scale %dMHz in to <=13.5MHz\n", - Fref); + if (div > ARIZONA_FLL_MAX_REFDIV) return -EINVAL; - } } - /* Apply the division for our remaining calculations */ - Fref /= div; + /* Find an appropriate FLL_FRATIO */ + init_ratio = arizona_find_fratio(fll, fref, fvco, &cfg->fratio, sync); + if (init_ratio < 0) { + arizona_fll_err(fll, "Unable to find FRATIO for fref=%uHz\n", + fref); + return init_ratio; + } - /* Fvco should be over the targt; don't check the upper bound */ - div = 1; - while (Fout * div < 90000000 * fll->vco_mult) { - div++; - if (div > 7) { - arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n", - Fout); - return -EINVAL; + switch (fll->arizona->type) { + case WM5102: + case WM8997: + return init_ratio; + case WM8280: + case WM5110: + if (fll->arizona->rev < 3 || sync) + return init_ratio; + break; + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + if (fref == 11289600 && fvco == 90316800) { + if (!sync) + cfg->fratio = init_ratio - 1; + return init_ratio; } - } - target = Fout * div / fll->vco_mult; - cfg->outdiv = div; - arizona_fll_dbg(fll, "Fvco=%dHz\n", target); + if (sync) + return init_ratio; + break; + case CS47L35: + if (fll->arizona->rev == 0) { + if (fref == 11289600 && fvco == 90316800) { + if (!sync) + cfg->fratio = init_ratio - 1; + return init_ratio; + } - /* Find an appropraite FLL_FRATIO and factor it out of the target */ - for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { - if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { - cfg->fratio = fll_fratios[i].fratio; - ratio = fll_fratios[i].ratio; + if (sync) + return init_ratio; break; } - } - if (i == ARRAY_SIZE(fll_fratios)) { - arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n", - Fref); - return -EINVAL; + return init_ratio; + default: + return init_ratio; } - for (i = 0; i < ARRAY_SIZE(fll_gains); i++) { - if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) { - cfg->gain = fll_gains[i].gain; - break; + cfg->fratio = init_ratio - 1; + + /* Adjust FRATIO/refdiv to avoid integer mode if possible */ + refdiv = cfg->refdiv; + + arizona_fll_dbg(fll, "pseudo: initial ratio=%u fref=%u refdiv=%u\n", + init_ratio, fref, refdiv); + + while (div <= ARIZONA_FLL_MAX_REFDIV) { + /* start from init_ratio because this may already give a + * fractional N.K + */ + for (ratio = init_ratio; ratio > 0; ratio--) { + if (fvco % (ratio * fref)) { + cfg->refdiv = refdiv; + cfg->fratio = ratio - 1; + arizona_fll_dbg(fll, + "pseudo: found fref=%u refdiv=%d(%d) ratio=%d\n", + fref, refdiv, div, ratio); + return ratio; + } } + + for (ratio = init_ratio + 1; ratio <= ARIZONA_FLL_MAX_FRATIO; + ratio++) { + if ((ARIZONA_FLL_VCO_CORNER / 2) / + (fll->vco_mult * ratio) < fref) { + arizona_fll_dbg(fll, "pseudo: hit VCO corner\n"); + break; + } + + if (fref > pseudo_fref_max[ratio - 1]) { + arizona_fll_dbg(fll, + "pseudo: exceeded max fref(%u) for ratio=%u\n", + pseudo_fref_max[ratio - 1], + ratio); + break; + } + + if (fvco % (ratio * fref)) { + cfg->refdiv = refdiv; + cfg->fratio = ratio - 1; + arizona_fll_dbg(fll, + "pseudo: found fref=%u refdiv=%d(%d) ratio=%d\n", + fref, refdiv, div, ratio); + return ratio; + } + } + + div *= 2; + fref /= 2; + refdiv++; + init_ratio = arizona_find_fratio(fll, fref, fvco, NULL, sync); + arizona_fll_dbg(fll, + "pseudo: change fref=%u refdiv=%d(%d) ratio=%u\n", + fref, refdiv, div, init_ratio); } - if (i == ARRAY_SIZE(fll_gains)) { - arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n", - Fref); - return -EINVAL; - } - cfg->n = target / (ratio * Fref); + arizona_fll_warn(fll, "Falling back to integer mode operation\n"); + return cfg->fratio + 1; +} + +static int arizona_calc_fll(struct arizona_fll *fll, + struct arizona_fll_cfg *cfg, + unsigned int fin, bool sync) +{ + unsigned int fvco, gcd_fll; + int i, ratio; + unsigned int fref; + struct arizona_fll_gain *fll_gain; + unsigned int size_fll_gain; + + arizona_fll_dbg(fll, "fin=%u fout=%u\n", fin, fll->fout); + + fvco = fll->fvco; + cfg->outdiv = fll->outdiv; + + arizona_fll_dbg(fll, "fvco=%dHz\n", fvco); + + /* Find an appropriate FLL_FRATIO and refdiv */ + ratio = arizona_calc_fratio(fll, cfg, fvco, fin, sync); + if (ratio < 0) + return ratio; - if (target % (ratio * Fref)) { - gcd_fll = gcd(target, ratio * Fref); + /* Apply the division for our remaining calculations */ + fref = fin / (1 << cfg->refdiv); + + cfg->n = fvco / (ratio * fref); + + if (fvco % (ratio * fref)) { + gcd_fll = gcd(fvco, ratio * fref); arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll); - cfg->theta = (target - (cfg->n * ratio * Fref)) + cfg->theta = (fvco - (cfg->n * ratio * fref)) / gcd_fll; - cfg->lambda = (ratio * Fref) / gcd_fll; + cfg->lambda = (ratio * fref) / gcd_fll; } else { cfg->theta = 0; cfg->lambda = 0; @@ -1344,130 +4425,319 @@ static int arizona_calc_fll(struct arizona_fll *fll, cfg->lambda >>= 1; } - arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n", + fll_gain = fll_gains; + size_fll_gain = ARRAY_SIZE(fll_gains); + + switch (fll->arizona->type) { + default: + if (!sync) { + cfg->intg_gain = fref > 768000 ? 3 : 2; + fll_gain = fll_moon_gains; + size_fll_gain = ARRAY_SIZE(fll_moon_gains); + } + /* fall-through */ + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + for (i = 0; i < size_fll_gain; i++) { + if (fll_gain[i].min <= fref && + fref <= fll_gain[i].max) { + cfg->gain = fll_gain[i].gain; + break; + } + } + if (i == size_fll_gain) { + arizona_fll_err(fll, "Unable to find gain for fref=%uHz\n", + fref); + return -EINVAL; + } + break; + } + + arizona_fll_dbg(fll, "N=%d THETA=%d LAMBDA=%d\n", cfg->n, cfg->theta, cfg->lambda); - arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n", - cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv); - arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain); + arizona_fll_dbg(fll, "FRATIO=0x%x(%d) OUTDIV=%d REFCLK_DIV=0x%x(%d)\n", + cfg->fratio, ratio, cfg->outdiv, + cfg->refdiv, 1 << cfg->refdiv); + arizona_fll_dbg(fll, "GAIN=0x%x(%d)\n", cfg->gain, 1 << cfg->gain); return 0; } -static void arizona_apply_fll(struct arizona *arizona, unsigned int base, +static bool arizona_apply_fll(struct arizona *arizona, unsigned int base, struct arizona_fll_cfg *cfg, int source, - bool sync) + int gain, bool sync) { - regmap_update_bits(arizona->regmap, base + 3, - ARIZONA_FLL1_THETA_MASK, cfg->theta); - regmap_update_bits(arizona->regmap, base + 4, - ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda); - regmap_update_bits(arizona->regmap, base + 5, + bool change, fll_change; + + fll_change = false; + regmap_update_bits_check(arizona->regmap, base + 3, + ARIZONA_FLL1_THETA_MASK, cfg->theta, &change); + fll_change |= change; + regmap_update_bits_check(arizona->regmap, base + 4, + ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda, &change); + fll_change |= change; + regmap_update_bits_check(arizona->regmap, base + 5, ARIZONA_FLL1_FRATIO_MASK, - cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT); - regmap_update_bits(arizona->regmap, base + 6, + cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT, &change); + fll_change |= change; + regmap_update_bits_check(arizona->regmap, base + 6, ARIZONA_FLL1_CLK_REF_DIV_MASK | ARIZONA_FLL1_CLK_REF_SRC_MASK, cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT | - source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT); + source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT, &change); + fll_change |= change; + + if (sync) { + regmap_update_bits_check(arizona->regmap, base + 0x7, + ARIZONA_FLL1_GAIN_MASK, + gain << ARIZONA_FLL1_GAIN_SHIFT, &change); + fll_change |= change; + } else { + regmap_update_bits(arizona->regmap, base + 0x5, + ARIZONA_FLL1_OUTDIV_MASK, + cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT); + regmap_update_bits_check(arizona->regmap, base + 0x9, + ARIZONA_FLL1_GAIN_MASK, + gain << ARIZONA_FLL1_GAIN_SHIFT, &change); + fll_change |= change; + } + + regmap_update_bits_check(arizona->regmap, base + 2, + ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK, + ARIZONA_FLL1_CTRL_UPD | cfg->n, &change); + fll_change |= change; + + return fll_change; +} + +static int arizona_is_enabled_fll(struct arizona_fll *fll) +{ + struct arizona *arizona = fll->arizona; + unsigned int reg; + int ret; + + ret = regmap_read(arizona->regmap, fll->base + 1, ®); + if (ret != 0) { + arizona_fll_err(fll, "Failed to read current state: %d\n", + ret); + return ret; + } + + return reg & ARIZONA_FLL1_ENA; +} + +static int arizona_wait_for_fll(struct arizona_fll *fll, bool requested) +{ + struct arizona *arizona = fll->arizona; + unsigned int reg, mask; + unsigned int val = 0; + bool status; + int i; + + arizona_fll_dbg(fll, "Waiting for FLL...\n"); + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM1831: + case CS47L24: + reg = ARIZONA_INTERRUPT_RAW_STATUS_5; + mask = ARIZONA_FLL1_CLOCK_OK_STS; + break; + default: + reg = CLEARWATER_IRQ1_RAW_STATUS_2; + mask = CLEARWATER_FLL1_LOCK_STS1; + break; + } + + for (i = 0; i < 30; i++) { + regmap_read(arizona->regmap, reg, &val); + status = val & (mask << (fll->id - 1)); + if (status == requested) + return 0; + + switch (i) { + case 0 ... 5: + usleep_range(75, 125); + break; + case 11 ... 20: + usleep_range(750, 1250); + break; + case 21 ... 30: + msleep(20); + break; + } + } - if (sync) - regmap_update_bits(arizona->regmap, base + 0x7, - ARIZONA_FLL1_GAIN_MASK, - cfg->gain << ARIZONA_FLL1_GAIN_SHIFT); - else - regmap_update_bits(arizona->regmap, base + 0x9, - ARIZONA_FLL1_GAIN_MASK, - cfg->gain << ARIZONA_FLL1_GAIN_SHIFT); + arizona_fll_warn(fll, "Timed out waiting for lock\n"); - regmap_update_bits(arizona->regmap, base + 2, - ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK, - ARIZONA_FLL1_CTRL_UPD | cfg->n); + return -ETIMEDOUT; } -static bool arizona_is_enabled_fll(struct arizona_fll *fll) +static int arizona_enable_fll(struct arizona_fll *fll) { struct arizona *arizona = fll->arizona; - unsigned int reg; - int ret; + bool use_sync = false; + int already_enabled = arizona_is_enabled_fll(fll); + struct arizona_fll_cfg cfg; + bool fll_change, change; + unsigned int fsync_freq; + int gain; - ret = regmap_read(arizona->regmap, fll->base + 1, ®); - if (ret != 0) { - arizona_fll_err(fll, "Failed to read current state: %d\n", - ret); - return ret; - } + if (already_enabled < 0) + return already_enabled; - return reg & ARIZONA_FLL1_ENA; -} + arizona_fll_dbg(fll, "Enabling FLL, initially %s\n", + already_enabled?"enabled":"disabled"); -static void arizona_enable_fll(struct arizona_fll *fll, - struct arizona_fll_cfg *ref, - struct arizona_fll_cfg *sync) -{ - struct arizona *arizona = fll->arizona; - int ret; + if (already_enabled) { + /* Facilitate smooth refclk across the transition */ + regmap_update_bits(fll->arizona->regmap, fll->base + 0x9, + ARIZONA_FLL1_GAIN_MASK, 0); + regmap_update_bits(fll->arizona->regmap, fll->base + 1, + ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN); + udelay(32); + } /* * If we have both REFCLK and SYNCCLK then enable both, * otherwise apply the SYNCCLK settings to REFCLK. */ - if (fll->ref_src >= 0 && fll->ref_src != fll->sync_src) { - regmap_update_bits(arizona->regmap, fll->base + 5, - ARIZONA_FLL1_OUTDIV_MASK, - ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT); + if (fll->ref_src >= 0 && fll->ref_freq && + fll->ref_src != fll->sync_src) { + arizona_calc_fll(fll, &cfg, fll->ref_freq, false); - arizona_apply_fll(arizona, fll->base, ref, fll->ref_src, - false); - if (fll->sync_src >= 0) - arizona_apply_fll(arizona, fll->base + 0x10, sync, - fll->sync_src, true); + fll_change = arizona_apply_fll(arizona, fll->base, &cfg, + fll->ref_src, + cfg.gain, false); + if (fll->sync_src >= 0) { + arizona_calc_fll(fll, &cfg, fll->sync_freq, true); + fsync_freq = fll->sync_freq / (1 << cfg.refdiv); + fll_change |= arizona_apply_fll(arizona, + fll->base + fll->sync_offset, + &cfg, fll->sync_src, + cfg.gain, true); + use_sync = true; + } } else if (fll->sync_src >= 0) { - regmap_update_bits(arizona->regmap, fll->base + 5, - ARIZONA_FLL1_OUTDIV_MASK, - sync->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT); + arizona_calc_fll(fll, &cfg, fll->sync_freq, false); + + gain = cfg.gain; + + switch (fll->arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + case CS47L35: + break; + default: + if (cfg.theta == 0) + gain = cfg.intg_gain; + break; + } - arizona_apply_fll(arizona, fll->base, sync, - fll->sync_src, false); + fll_change = arizona_apply_fll(arizona, fll->base, &cfg, + fll->sync_src, gain, false); - regmap_update_bits(arizona->regmap, fll->base + 0x11, + regmap_update_bits(arizona->regmap, fll->base + + fll->sync_offset + 0x1, ARIZONA_FLL1_SYNC_ENA, 0); } else { arizona_fll_err(fll, "No clocks provided\n"); - return; + return -EINVAL; } /* * Increase the bandwidth if we're not using a low frequency * sync source. */ - if (fll->sync_src >= 0 && fll->sync_freq > 100000) - regmap_update_bits(arizona->regmap, fll->base + 0x17, + if (use_sync && fsync_freq > 128000) + regmap_update_bits(arizona->regmap, fll->base + + fll->sync_offset + 0x7, ARIZONA_FLL1_SYNC_BW, 0); else - regmap_update_bits(arizona->regmap, fll->base + 0x17, - ARIZONA_FLL1_SYNC_BW, ARIZONA_FLL1_SYNC_BW); + regmap_update_bits(arizona->regmap, fll->base + + fll->sync_offset + 0x7, + ARIZONA_FLL1_SYNC_BW, + ARIZONA_FLL1_SYNC_BW); - if (!arizona_is_enabled_fll(fll)) - pm_runtime_get(arizona->dev); + switch (fll->arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM8285: + case WM1840: + case WM1831: + case CS47L24: + break; + case CS47L35: + if (fll->arizona->rev == 0) + break; + /* for rev A1 fall through */ + default: + if ((!use_sync) && (cfg.theta == 0)) + regmap_update_bits_check(arizona->regmap, + fll->base + 0xA, + ARIZONA_FLL1_PHASE_ENA_MASK | + ARIZONA_FLL1_PHASE_GAIN_MASK, + (1 << ARIZONA_FLL1_PHASE_ENA_SHIFT) | + (2 << ARIZONA_FLL1_PHASE_GAIN_SHIFT), + &change); + else + regmap_update_bits_check(arizona->regmap, + fll->base + 0xA, + ARIZONA_FLL1_PHASE_ENA_MASK | + ARIZONA_FLL1_PHASE_GAIN_MASK, + 2 << ARIZONA_FLL1_PHASE_GAIN_SHIFT, + &change); + fll_change |= change; + break; + } - /* Clear any pending completions */ - try_wait_for_completion(&fll->ok); + if (!already_enabled) + pm_runtime_get(arizona->dev); regmap_update_bits(arizona->regmap, fll->base + 1, ARIZONA_FLL1_FREERUN, 0); regmap_update_bits(arizona->regmap, fll->base + 1, ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA); - if (fll->ref_src >= 0 && fll->sync_src >= 0 && - fll->ref_src != fll->sync_src) - regmap_update_bits(arizona->regmap, fll->base + 0x11, + if (use_sync) + regmap_update_bits(arizona->regmap, fll->base + + fll->sync_offset + 0x1, ARIZONA_FLL1_SYNC_ENA, ARIZONA_FLL1_SYNC_ENA); - ret = wait_for_completion_timeout(&fll->ok, - msecs_to_jiffies(250)); - if (ret == 0) - arizona_fll_warn(fll, "Timed out waiting for lock\n"); + if (already_enabled) + regmap_update_bits(arizona->regmap, fll->base + 1, + ARIZONA_FLL1_FREERUN, 0); + + if (fll_change || !already_enabled) + arizona_wait_for_fll(fll, true); + + return 0; } static void arizona_disable_fll(struct arizona_fll *fll) @@ -1475,100 +4745,237 @@ static void arizona_disable_fll(struct arizona_fll *fll) struct arizona *arizona = fll->arizona; bool change; + arizona_fll_dbg(fll, "Disabling FLL\n"); + regmap_update_bits(arizona->regmap, fll->base + 1, ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN); regmap_update_bits_check(arizona->regmap, fll->base + 1, ARIZONA_FLL1_ENA, 0, &change); - regmap_update_bits(arizona->regmap, fll->base + 0x11, + regmap_update_bits(arizona->regmap, fll->base + + fll->sync_offset + 0x1, ARIZONA_FLL1_SYNC_ENA, 0); + regmap_update_bits(arizona->regmap, fll->base + 1, + ARIZONA_FLL1_FREERUN, 0); + + arizona_wait_for_fll(fll, false); if (change) pm_runtime_put_autosuspend(arizona->dev); } int arizona_set_fll_refclk(struct arizona_fll *fll, int source, - unsigned int Fref, unsigned int Fout) + unsigned int fin, unsigned int fout) { - struct arizona_fll_cfg ref, sync; - int ret; + int ret = 0; - if (fll->ref_src == source && fll->ref_freq == Fref) + if (fll->ref_src == source && fll->ref_freq == fin) return 0; - if (fll->fout && Fref > 0) { - ret = arizona_calc_fll(fll, &ref, Fref, fll->fout); + if (fll->fout && fin > 0) { + ret = arizona_validate_fll(fll, fin, fll->fvco); if (ret != 0) return ret; - - if (fll->sync_src >= 0) { - ret = arizona_calc_fll(fll, &sync, fll->sync_freq, - fll->fout); - if (ret != 0) - return ret; - } } fll->ref_src = source; - fll->ref_freq = Fref; + fll->ref_freq = fin; - if (fll->fout && Fref > 0) { - arizona_enable_fll(fll, &ref, &sync); + if (fll->fout && fin > 0) { + ret = arizona_enable_fll(fll); } - return 0; + return ret; } EXPORT_SYMBOL_GPL(arizona_set_fll_refclk); int arizona_set_fll(struct arizona_fll *fll, int source, - unsigned int Fref, unsigned int Fout) + unsigned int fin, unsigned int fout) { - struct arizona_fll_cfg ref, sync; - int ret; + unsigned int fvco = 0; + int div = 0; + int ret = 0; if (fll->sync_src == source && - fll->sync_freq == Fref && fll->fout == Fout) + fll->sync_freq == fin && fll->fout == fout) return 0; - if (Fout) { + if (fout) { + div = fll->min_outdiv; + while (fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) { + div++; + if (div > fll->max_outdiv) { + arizona_fll_err(fll, + "No FLL_OUTDIV for Fout=%uHz\n", + fout); + return -EINVAL; + } + } + fvco = fout * div / fll->vco_mult; + if (fll->ref_src >= 0) { - ret = arizona_calc_fll(fll, &ref, fll->ref_freq, - Fout); + ret = arizona_validate_fll(fll, fll->ref_freq, fvco); if (ret != 0) return ret; } - ret = arizona_calc_fll(fll, &sync, Fref, Fout); + ret = arizona_validate_fll(fll, fin, fvco); if (ret != 0) return ret; } fll->sync_src = source; - fll->sync_freq = Fref; - fll->fout = Fout; + fll->sync_freq = fin; + fll->fvco = fvco; + fll->outdiv = div; + fll->fout = fout; - if (Fout) { - arizona_enable_fll(fll, &ref, &sync); - } else { + if (fout) + ret = arizona_enable_fll(fll); + else arizona_disable_fll(fll); + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_set_fll); + +static int arizona_enable_fll_ao(struct arizona_fll *fll, + struct reg_sequence *patch, unsigned int patch_size) +{ + struct arizona *arizona = fll->arizona; + int already_enabled = arizona_is_enabled_fll(fll); + unsigned int i; + + if (already_enabled < 0) + return already_enabled; + + arizona_fll_dbg(fll, "Enabling FLL, initially %s\n", + already_enabled ? "enabled" : "disabled"); + + /* FLL_AO_HOLD must be set before configuring any registers */ + regmap_update_bits(fll->arizona->regmap, fll->base + 1, + MOON_FLL_AO_HOLD, MOON_FLL_AO_HOLD); + + /* the default patch is for mclk2 as source, + modify the patch to apply fll->ref_src */ + for (i = 0; i < patch_size; i++) { + if (patch[i].reg == MOON_FLLAO_CONTROL_6) { + patch[i].def &= ~MOON_FLL_AO_REFCLK_SRC_MASK; + patch[i].def |= + (fll->ref_src << MOON_FLL_AO_REFCLK_SRC_SHIFT) + & MOON_FLL_AO_REFCLK_SRC_MASK; + } } + regmap_multi_reg_write(arizona->regmap, patch, + patch_size); + + if (!already_enabled) + pm_runtime_get(arizona->dev); + + regmap_update_bits(arizona->regmap, fll->base + 1, + MOON_FLL_AO_ENA, MOON_FLL_AO_ENA); + + /* Release the hold so that fll_ao locks to external frequency */ + regmap_update_bits(arizona->regmap, fll->base + 1, + MOON_FLL_AO_HOLD, 0); + + if (!already_enabled) + arizona_wait_for_fll(fll, true); + return 0; } -EXPORT_SYMBOL_GPL(arizona_set_fll); + +static int arizona_disable_fll_ao(struct arizona_fll *fll) +{ + struct arizona *arizona = fll->arizona; + bool change; + + arizona_fll_dbg(fll, "Disabling FLL\n"); + + regmap_update_bits(arizona->regmap, fll->base + 1, + MOON_FLL_AO_HOLD, MOON_FLL_AO_HOLD); + regmap_update_bits_check(arizona->regmap, fll->base + 1, + MOON_FLL_AO_ENA, 0, &change); + + arizona_wait_for_fll(fll, false); + + /* ctrl_up gates the writes to all fll_ao register, + setting it to 0 here ensures that after a runtime + suspend/resume cycle when one enables the + fllao then ctrl_up is the last bit that is configured + by the fllao enable code rather than the cache + sync operation which would have updated it + much earlier before writing out all fllao registers */ + regmap_update_bits(arizona->regmap, fll->base + 2, + MOON_FLL_AO_CTRL_UPD_MASK, 0); + + if (change) + pm_runtime_put_autosuspend(arizona->dev); + + return 0; +} + +int arizona_set_fll_ao(struct arizona_fll *fll, int source, + unsigned int fin, unsigned int fout) +{ + int ret = 0; + struct arizona_fll_cfg *cfg = &(fll->ref_cfg); + unsigned int i; + + if (fll->ref_src == source && + fll->ref_freq == fin && fll->fout == fout) + return 0; + + if ((fout) && (cfg->fin != fin || + cfg->fvco != fout)) { + for (i = 0; i < ARRAY_SIZE(fllao_settings); i++) { + if (fllao_settings[i].fin == fin && + fllao_settings[i].fout == fout) + break; + } + + if (i == ARRAY_SIZE(fllao_settings)) { + arizona_fll_err(fll, + "No matching configuration for FLL_AO\n"); + return -EINVAL; + } + + cfg->patch = fllao_settings[i].patch; + cfg->patch_size = fllao_settings[i].patch_size; + cfg->fin = fin; + cfg->fvco = fout; + } + + fll->ref_src = source; + fll->ref_freq = fin; + fll->fout = fout; + + if (fout) + ret = arizona_enable_fll_ao(fll, cfg->patch, cfg->patch_size); + else + arizona_disable_fll_ao(fll); + + return ret; +} +EXPORT_SYMBOL_GPL(arizona_set_fll_ao); int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, int ok_irq, struct arizona_fll *fll) { - int ret; unsigned int val; - init_completion(&fll->ok); - fll->id = id; fll->base = base; fll->arizona = arizona; fll->sync_src = ARIZONA_FLL_SRC_NONE; + if (!fll->min_outdiv) + fll->min_outdiv = ARIZONA_FLL_MIN_OUTDIV; + if (!fll->max_outdiv) + fll->max_outdiv = ARIZONA_FLL_MAX_OUTDIV; + if (!fll->sync_offset) + fll->sync_offset = ARIZONA_FLL_SYNC_OFFSET; + /* Configure default refclk to 32kHz if we have one */ regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val); switch (val & ARIZONA_CLK_32K_SRC_MASK) { @@ -1581,17 +4988,6 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, } fll->ref_freq = 32768; - snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id); - snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name), - "FLL%d clock OK", id); - - ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name, - arizona_fll_clock_ok, fll); - if (ret != 0) { - dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n", - id, ret); - } - regmap_update_bits(arizona->regmap, fll->base + 1, ARIZONA_FLL1_FREERUN, 0); @@ -1633,6 +5029,326 @@ int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff) } EXPORT_SYMBOL_GPL(arizona_set_output_mode); +int arizona_set_hpdet_cb(struct snd_soc_codec *codec, + void (*hpdet_cb)(unsigned int measurement)) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + arizona->pdata.hpdet_cb = hpdet_cb; + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_set_hpdet_cb); + +int arizona_set_micd_cb(struct snd_soc_codec *codec, + void (*micd_cb)(bool mic)) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + arizona->pdata.micd_cb = micd_cb; + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_set_micd_cb); + +int arizona_set_ez2ctrl_cb(struct snd_soc_codec *codec, + void (*ez2ctrl_trigger)(void)) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + arizona->pdata.ez2ctrl_trigger = ez2ctrl_trigger; + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_set_ez2ctrl_cb); + +int arizona_set_custom_jd(struct snd_soc_codec *codec, + const struct arizona_jd_state *custom_jd) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + arizona->pdata.custom_jd = custom_jd; + + return 0; +} +EXPORT_SYMBOL_GPL(arizona_set_custom_jd); + +struct regmap *arizona_get_regmap_dsp(struct snd_soc_codec *codec) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + switch (arizona->type) { + case WM5102: + case WM5110: + case WM8997: + case WM8280: + case WM8998: + case WM1814: + case WM1831: + case CS47L24: + return arizona->regmap; + default: + return arizona->regmap_32bit; + } +} +EXPORT_SYMBOL_GPL(arizona_get_regmap_dsp); + +struct arizona_extcon_info * +arizona_get_extcon_info(struct snd_soc_codec *codec) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + return arizona->extcon_info; +} +EXPORT_SYMBOL_GPL(arizona_get_extcon_info); + +static int arizona_set_force_bypass(struct snd_soc_codec *codec, + bool set_bypass) +{ + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct arizona_micbias *micbias = arizona->pdata.micbias; + unsigned int i, cp_bypass = 0, micbias_bypass = 0; + unsigned int num_micbiases; + + if (set_bypass) { + cp_bypass = ARIZONA_CPMIC_BYPASS; + micbias_bypass = ARIZONA_MICB1_BYPASS; + } + + if (arizona->micvdd_regulated) { + if (set_bypass) + snd_soc_dapm_disable_pin(arizona->dapm, + "MICSUPP"); + else + snd_soc_dapm_force_enable_pin(arizona->dapm, + "MICSUPP"); + + snd_soc_dapm_sync(arizona->dapm); + + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_CHARGE_PUMP_1, + ARIZONA_CPMIC_BYPASS, cp_bypass); + } + + arizona_get_num_micbias(arizona, &num_micbiases, NULL); + + for (i = 0; i < num_micbiases; i++) { + if ((set_bypass) || + (!micbias[i].bypass && micbias[i].mV)) + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_BIAS_CTRL_1 + i, + ARIZONA_MICB1_BYPASS, + micbias_bypass); + } + + return 0; +} + +int arizona_enable_force_bypass(struct snd_soc_codec *codec) +{ + return arizona_set_force_bypass(codec, true); +} +EXPORT_SYMBOL_GPL(arizona_enable_force_bypass); + +int arizona_disable_force_bypass(struct snd_soc_codec *codec) +{ + return arizona_set_force_bypass(codec, false); +} +EXPORT_SYMBOL_GPL(arizona_disable_force_bypass); + +static bool arizona_eq_filter_unstable(bool mode, __be16 _a, __be16 _b) +{ + s16 a = be16_to_cpu(_a); + s16 b = be16_to_cpu(_b); + + if (!mode) { + return abs(a) >= 4096; + } else { + if (abs(b) >= 4096) + return true; + + return (abs((a << 16) / (4096 - b)) >= 4096 << 4); + } +} + +int arizona_eq_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct soc_bytes *params = (void *)kcontrol->private_value; + unsigned int val; + __be16 *data; + int len; + int ret; + + len = params->num_regs * regmap_get_val_bytes(arizona->regmap); + + data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA); + if (!data) + return -ENOMEM; + + data[0] &= cpu_to_be16(ARIZONA_EQ1_B1_MODE); + + if (arizona_eq_filter_unstable(!!data[0], data[1], data[2]) || + arizona_eq_filter_unstable(true, data[4], data[5]) || + arizona_eq_filter_unstable(true, data[8], data[9]) || + arizona_eq_filter_unstable(true, data[12], data[13]) || + arizona_eq_filter_unstable(false, data[16], data[17])) { + dev_err(arizona->dev, "Rejecting unstable EQ coefficients\n"); + ret = -EINVAL; + goto out; + } + + ret = regmap_read(arizona->regmap, params->base, &val); + if (ret != 0) + goto out; + + val &= ~ARIZONA_EQ1_B1_MODE; + data[0] |= cpu_to_be16(val); + + ret = regmap_raw_write(arizona->regmap, params->base, data, len); + +out: + kfree(data); + return ret; +} +EXPORT_SYMBOL_GPL(arizona_eq_coeff_put); + +int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + __be16 *data = (__be16 *)ucontrol->value.bytes.data; + s16 val = be16_to_cpu(*data); + + if (abs(val) >= 4096) { + dev_err(arizona->dev, "Rejecting unstable LHPF coefficients\n"); + return -EINVAL; + } + + return snd_soc_bytes_put(kcontrol, ucontrol); +} +EXPORT_SYMBOL_GPL(arizona_lhpf_coeff_put); + +static int arizona_adsp2v2_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[e->shift_l]; + unsigned int item; + + mutex_lock(&dsp->rate_lock); + + for (item = 0; item < e->max; item++) { + if (e->values[item] == dsp->rate_cache) { + ucontrol->value.enumerated.item[0] = item; + mutex_unlock(&dsp->rate_lock); + return 0; + } + } + + mutex_unlock(&dsp->rate_lock); + + return -EINVAL; +} + +static int arizona_adsp2v2_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[e->shift_l]; + unsigned int item = ucontrol->value.enumerated.item[0]; + unsigned int val; + int ret = 0; + + if (item >= e->max) + return -EINVAL; + + mutex_lock(&dsp->rate_lock); + + if (e->values[item] != dsp->rate_cache) { + val = e->values[item]; + dsp->rate_cache = val; + + if (dsp->running) { + ret = dsp->rate_put_cb(dsp, ADSP2V2_RATE_MASK, + val << ADSP2V2_RATE_SHIFT); + } + } + + mutex_unlock(&dsp->rate_lock); + + return ret; +} + +static const struct soc_enum arizona_adsp2_rate_enum[] = { + SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1, + ARIZONA_DSP1_RATE_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1, + ARIZONA_DSP1_RATE_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1, + ARIZONA_DSP1_RATE_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1, + ARIZONA_DSP1_RATE_SHIFT, 0xf, + ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), +}; + +const struct snd_kcontrol_new arizona_adsp2_rate_controls[] = { + SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum[0]), + SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum[1]), + SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum[2]), + SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum[3]), +}; +EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls); + +static const struct soc_enum arizona_adsp2v2_rate_enum[] = { + SOC_VALUE_ENUM_SINGLE(0, 0, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(0, 1, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(0, 2, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(0, 3, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(0, 4, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(0, 5, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), + SOC_VALUE_ENUM_SINGLE(0, 6, 0xf, ARIZONA_RATE_ENUM_SIZE, + arizona_rate_text, arizona_rate_val), +}; + +const struct snd_kcontrol_new arizona_adsp2v2_rate_controls[] = { + SOC_ENUM_EXT("DSP1 Rate", arizona_adsp2v2_rate_enum[0], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), + SOC_ENUM_EXT("DSP2 Rate", arizona_adsp2v2_rate_enum[1], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), + SOC_ENUM_EXT("DSP3 Rate", arizona_adsp2v2_rate_enum[2], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), + SOC_ENUM_EXT("DSP4 Rate", arizona_adsp2v2_rate_enum[3], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), + SOC_ENUM_EXT("DSP5 Rate", arizona_adsp2v2_rate_enum[4], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), + SOC_ENUM_EXT("DSP6 Rate", arizona_adsp2v2_rate_enum[5], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), + SOC_ENUM_EXT("DSP7 Rate", arizona_adsp2v2_rate_enum[6], + arizona_adsp2v2_rate_get, arizona_adsp2v2_rate_put), +}; +EXPORT_SYMBOL_GPL(arizona_adsp2v2_rate_controls); + MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support"); MODULE_AUTHOR("Mark Brown "); MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/arizona.h b/sound/soc/codecs/arizona.h index af39f100642..8949bfc6797 100644 --- a/sound/soc/codecs/arizona.h +++ b/sound/soc/codecs/arizona.h @@ -23,14 +23,23 @@ #define ARIZONA_CLK_ASYNCCLK 2 #define ARIZONA_CLK_OPCLK 3 #define ARIZONA_CLK_ASYNC_OPCLK 4 - -#define ARIZONA_CLK_SRC_MCLK1 0x0 -#define ARIZONA_CLK_SRC_MCLK2 0x1 -#define ARIZONA_CLK_SRC_FLL1 0x4 -#define ARIZONA_CLK_SRC_FLL2 0x5 -#define ARIZONA_CLK_SRC_AIF1BCLK 0x8 -#define ARIZONA_CLK_SRC_AIF2BCLK 0x9 -#define ARIZONA_CLK_SRC_AIF3BCLK 0xa +#define ARIZONA_CLK_SYSCLK_2 5 +#define ARIZONA_CLK_SYSCLK_3 6 +#define ARIZONA_CLK_ASYNCCLK_2 7 +#define ARIZONA_CLK_DSPCLK 8 + +#define ARIZONA_CLK_SRC_MCLK1 0x0 +#define ARIZONA_CLK_SRC_MCLK2 0x1 +#define ARIZONA_CLK_SRC_FLL1 0x4 +#define ARIZONA_CLK_SRC_FLL2 0x5 +#define ARIZONA_CLK_SRC_FLL3 0x6 +#define ARIZONA_CLK_SRC_FLLAO_HI 0x7 +#define CLEARWATER_CLK_SRC_FLL1_DIV6 0x7 +#define ARIZONA_CLK_SRC_AIF1BCLK 0x8 +#define ARIZONA_CLK_SRC_AIF2BCLK 0x9 +#define ARIZONA_CLK_SRC_AIF3BCLK 0xa +#define ARIZONA_CLK_SRC_AIF4BCLK 0xb +#define ARIZONA_CLK_SRC_FLLAO 0xF #define ARIZONA_FLL_SRC_NONE -1 #define ARIZONA_FLL_SRC_MCLK1 0 @@ -41,9 +50,11 @@ #define ARIZONA_FLL_SRC_AIF1BCLK 8 #define ARIZONA_FLL_SRC_AIF2BCLK 9 #define ARIZONA_FLL_SRC_AIF3BCLK 10 +#define ARIZONA_FLL_SRC_AIF4BCLK 11 #define ARIZONA_FLL_SRC_AIF1LRCLK 12 #define ARIZONA_FLL_SRC_AIF2LRCLK 13 #define ARIZONA_FLL_SRC_AIF3LRCLK 14 +#define ARIZONA_FLL_SRC_AIF4LRCLK 15 #define ARIZONA_MIXER_VOL_MASK 0x00FE #define ARIZONA_MIXER_VOL_SHIFT 1 @@ -54,17 +65,34 @@ #define ARIZONA_CLK_24MHZ 2 #define ARIZONA_CLK_49MHZ 3 #define ARIZONA_CLK_73MHZ 4 +#define CLEARWATER_CLK_98MHZ 4 #define ARIZONA_CLK_98MHZ 5 #define ARIZONA_CLK_147MHZ 6 -#define ARIZONA_MAX_DAI 4 -#define ARIZONA_MAX_ADSP 4 +#define CLEARWATER_DSP_CLK_9MHZ 0 +#define CLEARWATER_DSP_CLK_18MHZ 1 +#define CLEARWATER_DSP_CLK_36MHZ 2 +#define CLEARWATER_DSP_CLK_73MHZ 3 +#define CLEARWATER_DSP_CLK_147MHZ 4 + +#define ARIZONA_MAX_DAI 11 +#define ARIZONA_MAX_ADSP 7 + +#define ARIZONA_DVFS_SR1_RQ 0x001 +#define ARIZONA_DVFS_SR2_RQ 0x002 +#define ARIZONA_DVFS_SR3_RQ 0x004 +#define ARIZONA_DVFS_ASR1_RQ 0x008 +#define ARIZONA_DVFS_ASR2_RQ 0x010 +#define ARIZONA_DVFS_ADSP1_RQ 0x100 struct arizona; struct wm_adsp; +struct arizona_jd_state; struct arizona_dai_priv { int clk; + + struct snd_pcm_hw_constraint_list constraint; }; struct arizona_priv { @@ -72,20 +100,37 @@ struct arizona_priv { struct arizona *arizona; int sysclk; int asyncclk; + int dspclk; struct arizona_dai_priv dai[ARIZONA_MAX_DAI]; int num_inputs; unsigned int in_pending; - unsigned int spk_ena:2; - unsigned int spk_ena_pending:1; + unsigned int out_up_pending; + unsigned int out_up_delay; + unsigned int out_down_pending; + unsigned int out_down_delay; + + unsigned int spk_mute_cache; + unsigned int spk_thr2_cache; + unsigned int dvfs_reqs; + struct mutex dvfs_lock; + bool dvfs_cached; }; -#define ARIZONA_NUM_MIXER_INPUTS 99 +#define ARIZONA_NUM_MIXER_INPUTS 134 +#define ARIZONA_V2_NUM_MIXER_INPUTS 146 extern const unsigned int arizona_mixer_tlv[]; -extern const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS]; -extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS]; +extern const char * const arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS]; +extern unsigned int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS]; +extern const char * const arizona_v2_mixer_texts[ARIZONA_V2_NUM_MIXER_INPUTS]; +extern unsigned int arizona_v2_mixer_values[ARIZONA_V2_NUM_MIXER_INPUTS]; + +#define ARIZONA_GAINMUX_CONTROLS(name, base) \ + SOC_SINGLE_RANGE_TLV(name " Input Volume", base + 1, \ + ARIZONA_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ + arizona_mixer_tlv) #define ARIZONA_MIXER_CONTROLS(name, base) \ SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base + 1, \ @@ -105,9 +150,13 @@ extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS]; SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \ arizona_mixer_texts, arizona_mixer_values) -#define ARIZONA_MUX_CTL_DECL(name) \ - const struct snd_kcontrol_new name##_mux = \ - SOC_DAPM_VALUE_ENUM("Route", name##_enum) +#define ARIZONA_MUX_CTL_DECL(xname) \ + const struct snd_kcontrol_new xname##_mux = { \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Route", \ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_dapm_get_enum_virt, \ + .put = arizona_mux_put, \ + .private_value = (unsigned long)&xname##_enum } #define ARIZONA_MUX_ENUMS(name, base_reg) \ static ARIZONA_MUX_ENUM_DECL(name##_enum, base_reg); \ @@ -127,8 +176,33 @@ extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS]; ARIZONA_MUX_ENUMS(name##_aux5, base_reg + 32); \ ARIZONA_MUX_ENUMS(name##_aux6, base_reg + 40) -#define ARIZONA_MUX(name, ctrl) \ - SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) +#define CLEARWATER_MUX_ENUM_DECL(name, reg) \ + SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \ + arizona_v2_mixer_texts, arizona_v2_mixer_values) + +#define CLEARWATER_MUX_ENUMS(name, base_reg) \ + static CLEARWATER_MUX_ENUM_DECL(name##_enum, base_reg); \ + static ARIZONA_MUX_CTL_DECL(name) + +#define CLEARWATER_MIXER_ENUMS(name, base_reg) \ + CLEARWATER_MUX_ENUMS(name##_in1, base_reg); \ + CLEARWATER_MUX_ENUMS(name##_in2, base_reg + 2); \ + CLEARWATER_MUX_ENUMS(name##_in3, base_reg + 4); \ + CLEARWATER_MUX_ENUMS(name##_in4, base_reg + 6) + +#define CLEARWATER_DSP_AUX_ENUMS(name, base_reg) \ + CLEARWATER_MUX_ENUMS(name##_aux1, base_reg); \ + CLEARWATER_MUX_ENUMS(name##_aux2, base_reg + 8); \ + CLEARWATER_MUX_ENUMS(name##_aux3, base_reg + 16); \ + CLEARWATER_MUX_ENUMS(name##_aux4, base_reg + 24); \ + CLEARWATER_MUX_ENUMS(name##_aux5, base_reg + 32); \ + CLEARWATER_MUX_ENUMS(name##_aux6, base_reg + 40) + +#define ARIZONA_MUX(wname, wctrl) \ +{ .id = snd_soc_dapm_value_mux, .name = wname, .reg = SND_SOC_NOPM, \ + .shift = 0, .invert = 0, .kcontrol_news = wctrl, \ + .num_kcontrols = 1, .event = arizona_mux_event, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } #define ARIZONA_MUX_WIDGETS(name, name_str) \ ARIZONA_MUX(name_str " Input", &name##_mux) @@ -150,7 +224,8 @@ extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS]; ARIZONA_MUX(name_str " Aux 5", &name##_aux5_mux), \ ARIZONA_MUX(name_str " Aux 6", &name##_aux6_mux) -#define ARIZONA_MUX_ROUTES(name) \ +#define ARIZONA_MUX_ROUTES(widget, name) \ + { widget, NULL, name " Input" }, \ ARIZONA_MIXER_INPUT_ROUTES(name " Input") #define ARIZONA_MIXER_ROUTES(widget, name) \ @@ -165,26 +240,75 @@ extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS]; ARIZONA_MIXER_INPUT_ROUTES(name " Input 4") #define ARIZONA_DSP_ROUTES(name) \ - { name, NULL, name " Aux 1" }, \ - { name, NULL, name " Aux 2" }, \ - { name, NULL, name " Aux 3" }, \ - { name, NULL, name " Aux 4" }, \ - { name, NULL, name " Aux 5" }, \ - { name, NULL, name " Aux 6" }, \ + { name, NULL, name " Preloader"}, \ + { name " Preloader", NULL, name " Aux 1" }, \ + { name " Preloader", NULL, name " Aux 2" }, \ + { name " Preloader", NULL, name " Aux 3" }, \ + { name " Preloader", NULL, name " Aux 4" }, \ + { name " Preloader", NULL, name " Aux 5" }, \ + { name " Preloader", NULL, name " Aux 6" }, \ ARIZONA_MIXER_INPUT_ROUTES(name " Aux 1"), \ ARIZONA_MIXER_INPUT_ROUTES(name " Aux 2"), \ ARIZONA_MIXER_INPUT_ROUTES(name " Aux 3"), \ ARIZONA_MIXER_INPUT_ROUTES(name " Aux 4"), \ ARIZONA_MIXER_INPUT_ROUTES(name " Aux 5"), \ ARIZONA_MIXER_INPUT_ROUTES(name " Aux 6"), \ - ARIZONA_MIXER_ROUTES(name, name "L"), \ - ARIZONA_MIXER_ROUTES(name, name "R") - -#define ARIZONA_RATE_ENUM_SIZE 4 -extern const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE]; -extern const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE]; - + ARIZONA_MIXER_ROUTES(name " Preloader", name "L"), \ + ARIZONA_MIXER_ROUTES(name " Preloader", name "R") + +#define ARIZONA_SAMPLE_RATE_CONTROL(name, domain) \ + SOC_VALUE_ENUM(name, arizona_sample_rate[(domain) - 2]) + +#define ARIZONA_SAMPLE_RATE_CONTROL_DVFS(name, domain) \ + SOC_VALUE_ENUM_EXT(name, arizona_sample_rate[(domain) - 2], \ + snd_soc_get_value_enum_double, \ + arizona_put_sample_rate_enum) + +#define ARIZONA_EQ_CONTROL(xname, xbase) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = arizona_eq_coeff_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) { .base = xbase, \ + .num_regs = 20, .mask = ~ARIZONA_EQ1_B1_MODE }) } + +#define ARIZONA_LHPF_CONTROL(xname, xbase) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = arizona_lhpf_coeff_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) { .base = xbase, \ + .num_regs = 1 }) } + +#define CLEARWATER_OSR_ENUM_SIZE 5 +#define ARIZONA_RATE_ENUM_SIZE 5 +#define ARIZONA_SYNC_RATE_ENUM_SIZE 3 +#define ARIZONA_ASYNC_RATE_ENUM_SIZE 2 +#define ARIZONA_SAMPLE_RATE_ENUM_SIZE 14 +#define MOON_DFC_TYPE_ENUM_SIZE 5 +#define MOON_DFC_WIDTH_ENUM_SIZE 5 + +extern const char * const arizona_rate_text[ARIZONA_RATE_ENUM_SIZE]; +extern const unsigned int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE]; +extern const char * const arizona_sample_rate_text[ARIZONA_SAMPLE_RATE_ENUM_SIZE]; +extern const unsigned int arizona_sample_rate_val[ARIZONA_SAMPLE_RATE_ENUM_SIZE]; +extern const char * const moon_dfc_width_text[MOON_DFC_WIDTH_ENUM_SIZE]; +extern const unsigned int moon_dfc_width_val[MOON_DFC_WIDTH_ENUM_SIZE]; +extern const char * const moon_dfc_type_text[MOON_DFC_TYPE_ENUM_SIZE]; +extern const unsigned int moon_dfc_type_val[MOON_DFC_TYPE_ENUM_SIZE]; + +extern const struct soc_enum arizona_sample_rate[]; extern const struct soc_enum arizona_isrc_fsl[]; +extern const struct soc_enum arizona_isrc_fsh[]; +extern const struct soc_enum arizona_asrc_rate1; +extern const struct soc_enum arizona_asrc_rate2; +extern const struct soc_enum clearwater_asrc1_rate[]; +extern const struct soc_enum clearwater_asrc2_rate[]; +extern const struct soc_enum arizona_input_rate; +extern const struct soc_enum arizona_output_rate; +extern const struct soc_enum arizona_fx_rate; +extern const struct soc_enum arizona_spdif_rate; +extern const struct soc_enum moon_input_rate[]; +extern const struct soc_enum moon_dfc_width[]; +extern const struct soc_enum moon_dfc_type[]; extern const struct soc_enum arizona_in_vi_ramp; extern const struct soc_enum arizona_in_vd_ramp; @@ -198,6 +322,31 @@ extern const struct soc_enum arizona_lhpf3_mode; extern const struct soc_enum arizona_lhpf4_mode; extern const struct soc_enum arizona_ng_hold; +extern const struct soc_enum arizona_in_hpf_cut_enum; +extern const struct soc_enum arizona_in_dmic_osr[]; +extern const struct soc_enum clearwater_in_dmic_osr[]; + +extern const struct soc_enum arizona_anc_input_src[]; +extern const struct soc_enum clearwater_anc_input_src[]; +extern const struct soc_enum arizona_anc_ng_enum; +extern const struct soc_enum arizona_output_anc_src[]; +extern const struct soc_enum clearwater_output_anc_src_defs[]; +extern const struct soc_enum arizona_ip_mode[]; + +extern int arizona_ip_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern int moon_in_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern int moon_dfc_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern int moon_lp_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern const struct snd_kcontrol_new arizona_adsp2_rate_controls[]; +extern const struct snd_kcontrol_new arizona_adsp2v2_rate_controls[]; extern int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, @@ -208,43 +357,126 @@ extern int arizona_out_ev(struct snd_soc_dapm_widget *w, extern int arizona_hp_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); +extern int clearwater_hp_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); +extern int arizona_anc_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event); + +extern unsigned int arizona_hpimp_cb(struct device *dev); + +extern int arizona_mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +extern int arizona_mux_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +extern int arizona_put_sample_rate_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern int arizona_eq_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +extern int arizona_lhpf_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); extern int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id, int source, unsigned int freq, int dir); -extern const struct snd_soc_dai_ops arizona_dai_ops; +extern int arizona_cache_and_clear_sources(struct arizona *arizona, + const int *sources, + unsigned int *cache, + int lim); -#define ARIZONA_FLL_NAME_LEN 20 +extern int arizona_restore_sources(struct arizona *arizona, + const int *sources, + unsigned int *cache, + int lim); + +extern void clearwater_spin_sysclk(struct arizona *arizona); + +extern const struct snd_soc_dai_ops arizona_dai_ops; +extern const struct snd_soc_dai_ops arizona_simple_dai_ops; + +struct arizona_fll_cfg { + unsigned int fin; + unsigned int fvco; + int n; + int theta; + int lambda; + int refdiv; + int outdiv; + int fratio; + int gain; + int intg_gain; + struct reg_sequence *patch; + unsigned int patch_size; +}; struct arizona_fll { struct arizona *arizona; int id; unsigned int base; + unsigned int sync_offset; unsigned int vco_mult; - struct completion ok; + unsigned int fvco; + int min_outdiv; + int max_outdiv; + int outdiv; unsigned int fout; int sync_src; unsigned int sync_freq; int ref_src; unsigned int ref_freq; - char lock_name[ARIZONA_FLL_NAME_LEN]; - char clock_ok_name[ARIZONA_FLL_NAME_LEN]; + struct arizona_fll_cfg ref_cfg; }; +extern int arizona_dvfs_up(struct snd_soc_codec *codec, unsigned int flags); +extern int arizona_dvfs_down(struct snd_soc_codec *codec, unsigned int flags); +extern int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +extern void arizona_init_dvfs(struct arizona_priv *priv); + extern int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq, int ok_irq, struct arizona_fll *fll); extern int arizona_set_fll_refclk(struct arizona_fll *fll, int source, - unsigned int Fref, unsigned int Fout); + unsigned int fin, unsigned int fout); extern int arizona_set_fll(struct arizona_fll *fll, int source, - unsigned int Fref, unsigned int Fout); + unsigned int fin, unsigned int fout); +extern int arizona_set_fll_ao(struct arizona_fll *fll, int source, + unsigned int fin, unsigned int fout); extern int arizona_init_spk(struct snd_soc_codec *codec); +extern int arizona_init_gpio(struct snd_soc_codec *codec); +extern int arizona_init_mono(struct snd_soc_codec *codec); +extern int arizona_init_input(struct snd_soc_codec *codec); extern int arizona_init_dai(struct arizona_priv *priv, int dai); int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff); +extern int arizona_set_hpdet_cb(struct snd_soc_codec *codec, + void (*hpdet_cb)(unsigned int measurement)); +extern int arizona_set_micd_cb(struct snd_soc_codec *codec, + void (*micd_cb)(bool mic)); +extern int arizona_set_ez2ctrl_cb(struct snd_soc_codec *codec, + void (*ez2ctrl_trigger)(void)); +extern int arizona_set_custom_jd(struct snd_soc_codec *codec, + const struct arizona_jd_state *custom_jd); + +extern int clearwater_put_dre(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +extern struct regmap *arizona_get_regmap_dsp(struct snd_soc_codec *codec); + +extern struct arizona_extcon_info * +arizona_get_extcon_info(struct snd_soc_codec *codec); + +extern int arizona_enable_force_bypass(struct snd_soc_codec *codec); +extern int arizona_disable_force_bypass(struct snd_soc_codec *codec); + +extern const char *arizona_sample_rate_val_to_name(unsigned int rate_val); + #endif diff --git a/sound/soc/codecs/clearwater.c b/sound/soc/codecs/clearwater.c new file mode 100644 index 00000000000..64ef6c64e7f --- /dev/null +++ b/sound/soc/codecs/clearwater.c @@ -0,0 +1,3150 @@ +/* + * clearwater.c -- ALSA SoC Audio driver for CLEARWATER-class devices + * + * Copyright 2014 Cirrus Logic + * + * Author: Nariman Poushin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "wm_adsp.h" +#include "clearwater.h" + +#define CLEARWATER_NUM_ADSP 7 + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU + * are counted as one DAI + */ +#define CLEARWATER_NUM_COMPR_DAI 2 + +#define CLEARWATER_FRF_COEFFICIENT_LEN 4 + +static int clearwater_frf_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define CLEARWATER_FRF_BYTES(xname, xbase, xregs) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = clearwater_frf_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } + +/* 2 mixer inputs with a stride of n in the register address */ +#define CLEARWATER_MIXER_INPUTS_2_N(_reg, n) \ + (_reg), \ + (_reg) + (1 * (n)) + +/* 4 mixer inputs with a stride of n in the register address */ +#define CLEARWATER_MIXER_INPUTS_4_N(_reg, n) \ + CLEARWATER_MIXER_INPUTS_2_N(_reg, n), \ + CLEARWATER_MIXER_INPUTS_2_N(_reg + (2 * n), n) + +#define CLEARWATER_DSP_MIXER_INPUTS(_reg) \ + CLEARWATER_MIXER_INPUTS_4_N(_reg, 2), \ + CLEARWATER_MIXER_INPUTS_4_N(_reg + 8, 2), \ + CLEARWATER_MIXER_INPUTS_4_N(_reg + 16, 8), \ + CLEARWATER_MIXER_INPUTS_2_N(_reg + 48, 8) + +static const int clearwater_fx_inputs[] = { + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_EQ1MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_EQ2MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_EQ3MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_EQ4MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_DRC1LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_DRC1RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_DRC2LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_DRC2RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_HPLP1MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_HPLP2MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_HPLP3MIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_HPLP4MIX_INPUT_1_SOURCE, 2), +}; + +static const int clearwater_asrc1_1_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_asrc1_2_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_asrc2_1_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_asrc2_2_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc1_fsl_inputs[] = { + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc1_fsh_inputs[] = { + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc2_fsl_inputs[] = { + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc2_fsh_inputs[] = { + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc3_fsl_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc3_fsh_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc4_fsl_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_isrc4_fsh_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_out_inputs[] = { + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT1LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT1RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT2LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT2RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT3LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT3RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT4LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT4RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT5LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT5RMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT6LMIX_INPUT_1_SOURCE, 2), + CLEARWATER_MIXER_INPUTS_4_N(ARIZONA_OUT6RMIX_INPUT_1_SOURCE, 2), +}; + +static const int clearwater_spd1_inputs[] = { + CLEARWATER_MIXER_INPUTS_2_N(ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE, 8), +}; + +static const int clearwater_dsp1_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +}; + +static const int clearwater_dsp2_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +}; + +static const int clearwater_dsp3_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +}; + +static const int clearwater_dsp4_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(ARIZONA_DSP4LMIX_INPUT_1_SOURCE), +}; + +static const int clearwater_dsp5_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(CLEARWATER_DSP5LMIX_INPUT_1_SOURCE), +}; + +static const int clearwater_dsp6_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(CLEARWATER_DSP6LMIX_INPUT_1_SOURCE), +}; + +static const int clearwater_dsp7_inputs[] = { + CLEARWATER_DSP_MIXER_INPUTS(CLEARWATER_DSP7LMIX_INPUT_1_SOURCE), +}; + +static int clearwater_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define CLEARWATER_RATE_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_get_value_enum_double, .put = clearwater_rate_put, \ + .private_value = (unsigned long)&xenum } + +struct clearwater_priv; + +struct clearwater_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; + bool trig; + struct mutex trig_lock; + struct clearwater_priv *priv; +}; + +struct clearwater_priv { + struct arizona_priv core; + struct arizona_fll fll[3]; + struct clearwater_compr compr_info[CLEARWATER_NUM_COMPR_DAI]; + + struct mutex fw_lock; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[CLEARWATER_NUM_COMPR_DAI] = { + { + .dai_name = "clearwater-dsp-voicectrl", + .adsp_num = 5, + }, + { + .dai_name = "clearwater-dsp-trace", + .adsp_num = 0, + }, +}; + +static const struct wm_adsp_region clearwater_dsp1_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x080000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, +}; + +static const struct wm_adsp_region clearwater_dsp2_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x100000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x160000 }, + { .type = WMFW_ADSP2_XM, .base = 0x120000 }, + { .type = WMFW_ADSP2_YM, .base = 0x140000 }, +}; + +static const struct wm_adsp_region clearwater_dsp3_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x180000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x1a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x1c0000 }, +}; + +static const struct wm_adsp_region clearwater_dsp4_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x200000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x260000 }, + { .type = WMFW_ADSP2_XM, .base = 0x220000 }, + { .type = WMFW_ADSP2_YM, .base = 0x240000 }, +}; + +static const struct wm_adsp_region clearwater_dsp5_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x280000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x2e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x2a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x2c0000 }, +}; + +static const struct wm_adsp_region clearwater_dsp6_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x300000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x360000 }, + { .type = WMFW_ADSP2_XM, .base = 0x320000 }, + { .type = WMFW_ADSP2_YM, .base = 0x340000 }, +}; + +static const struct wm_adsp_region clearwater_dsp7_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x380000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x3e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x3a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x3c0000 }, +}; + +static const struct wm_adsp_region *clearwater_dsp_regions[] = { + clearwater_dsp1_regions, + clearwater_dsp2_regions, + clearwater_dsp3_regions, + clearwater_dsp4_regions, + clearwater_dsp5_regions, + clearwater_dsp6_regions, + clearwater_dsp7_regions, +}; + +static const int wm_adsp2_control_bases[] = { + CLEARWATER_DSP1_CONFIG, + CLEARWATER_DSP2_CONFIG, + CLEARWATER_DSP3_CONFIG, + CLEARWATER_DSP4_CONFIG, + CLEARWATER_DSP5_CONFIG, + CLEARWATER_DSP6_CONFIG, + CLEARWATER_DSP7_CONFIG, +}; + +static const char * const clearwater_inmux_texts[] = { + "A", + "B", +}; + +static const SOC_ENUM_SINGLE_DECL(clearwater_in1mux_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_SHIFT, + clearwater_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(clearwater_in2muxl_enum, + ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_SRC_SHIFT, + clearwater_inmux_texts); +static const SOC_ENUM_SINGLE_DECL(clearwater_in2muxr_enum, + ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_SRC_SHIFT, + clearwater_inmux_texts); + +static const struct snd_kcontrol_new clearwater_in1mux = + SOC_DAPM_ENUM("IN1L Mux", clearwater_in1mux_enum); + +static const struct snd_kcontrol_new clearwater_in2mux[2] = { + SOC_DAPM_ENUM("IN2L Mux", clearwater_in2muxl_enum), + SOC_DAPM_ENUM("IN2R Mux", clearwater_in2muxr_enum), +}; + +static int clearwater_frf_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes *params = (void *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int ret, len; + void *data; + + len = params->num_regs * codec->val_bytes; + + data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA); + if (!data) { + ret = -ENOMEM; + goto out; + } + + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + + ret = regmap_raw_write(codec->control_data, params->base, + data, len); + + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + +out: + kfree(data); + return ret; +} + +/* Allow the worst case number of sources (FX Rate currently) */ +static unsigned int mixer_sources_cache[ARRAY_SIZE(clearwater_fx_inputs)]; + +static int clearwater_get_sources(unsigned int reg, + const int **cur_sources, int *lim) +{ + int ret = 0; + + switch (reg) { + case ARIZONA_FX_CTRL1: + *cur_sources = clearwater_fx_inputs; + *lim = ARRAY_SIZE(clearwater_fx_inputs); + break; + case CLEARWATER_ASRC1_RATE1: + *cur_sources = clearwater_asrc1_1_inputs; + *lim = ARRAY_SIZE(clearwater_asrc1_1_inputs); + break; + case CLEARWATER_ASRC1_RATE2: + *cur_sources = clearwater_asrc1_2_inputs; + *lim = ARRAY_SIZE(clearwater_asrc1_2_inputs); + break; + case CLEARWATER_ASRC2_RATE1: + *cur_sources = clearwater_asrc2_1_inputs; + *lim = ARRAY_SIZE(clearwater_asrc2_1_inputs); + break; + case CLEARWATER_ASRC2_RATE2: + *cur_sources = clearwater_asrc2_2_inputs; + *lim = ARRAY_SIZE(clearwater_asrc2_2_inputs); + break; + case ARIZONA_ISRC_1_CTRL_1: + *cur_sources = clearwater_isrc1_fsh_inputs; + *lim = ARRAY_SIZE(clearwater_isrc1_fsh_inputs); + break; + case ARIZONA_ISRC_1_CTRL_2: + *cur_sources = clearwater_isrc1_fsl_inputs; + *lim = ARRAY_SIZE(clearwater_isrc1_fsl_inputs); + break; + case ARIZONA_ISRC_2_CTRL_1: + *cur_sources = clearwater_isrc2_fsh_inputs; + *lim = ARRAY_SIZE(clearwater_isrc2_fsh_inputs); + break; + case ARIZONA_ISRC_2_CTRL_2: + *cur_sources = clearwater_isrc2_fsl_inputs; + *lim = ARRAY_SIZE(clearwater_isrc2_fsl_inputs); + break; + case ARIZONA_ISRC_3_CTRL_1: + *cur_sources = clearwater_isrc3_fsh_inputs; + *lim = ARRAY_SIZE(clearwater_isrc3_fsh_inputs); + break; + case ARIZONA_ISRC_3_CTRL_2: + *cur_sources = clearwater_isrc3_fsl_inputs; + *lim = ARRAY_SIZE(clearwater_isrc3_fsl_inputs); + break; + case ARIZONA_ISRC_4_CTRL_1: + *cur_sources = clearwater_isrc4_fsh_inputs; + *lim = ARRAY_SIZE(clearwater_isrc4_fsh_inputs); + break; + case ARIZONA_ISRC_4_CTRL_2: + *cur_sources = clearwater_isrc4_fsl_inputs; + *lim = ARRAY_SIZE(clearwater_isrc4_fsl_inputs); + break; + case ARIZONA_OUTPUT_RATE_1: + *cur_sources = clearwater_out_inputs; + *lim = ARRAY_SIZE(clearwater_out_inputs); + break; + case ARIZONA_SPD1_TX_CONTROL: + *cur_sources = clearwater_spd1_inputs; + *lim = ARRAY_SIZE(clearwater_spd1_inputs); + break; + case CLEARWATER_DSP1_CONFIG: + *cur_sources = clearwater_dsp1_inputs; + *lim = ARRAY_SIZE(clearwater_dsp1_inputs); + break; + case CLEARWATER_DSP2_CONFIG: + *cur_sources = clearwater_dsp2_inputs; + *lim = ARRAY_SIZE(clearwater_dsp2_inputs); + break; + case CLEARWATER_DSP3_CONFIG: + *cur_sources = clearwater_dsp3_inputs; + *lim = ARRAY_SIZE(clearwater_dsp3_inputs); + break; + case CLEARWATER_DSP4_CONFIG: + *cur_sources = clearwater_dsp4_inputs; + *lim = ARRAY_SIZE(clearwater_dsp4_inputs); + break; + case CLEARWATER_DSP5_CONFIG: + *cur_sources = clearwater_dsp5_inputs; + *lim = ARRAY_SIZE(clearwater_dsp5_inputs); + break; + case CLEARWATER_DSP6_CONFIG: + *cur_sources = clearwater_dsp6_inputs; + *lim = ARRAY_SIZE(clearwater_dsp6_inputs); + break; + case CLEARWATER_DSP7_CONFIG: + *cur_sources = clearwater_dsp7_inputs; + *lim = ARRAY_SIZE(clearwater_dsp7_inputs); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int clearwater_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret, err; + int lim; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + struct clearwater_priv *clearwater = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &clearwater->core; + struct arizona *arizona = priv->arizona; + + const int *cur_sources; + + unsigned int val, cur; + unsigned int mask; + + if (ucontrol->value.enumerated.item[0] > e->max - 1) + return -EINVAL; + + val = e->values[ucontrol->value.enumerated.item[0]] << e->shift_l; + mask = e->mask << e->shift_l; + + ret = regmap_read(arizona->regmap, e->reg, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current reg: %d\n", ret); + return ret; + } + + if ((cur & mask) == (val & mask)) + return 0; + + ret = clearwater_get_sources((int)e->reg, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + e->reg, + ret); + return ret; + } + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + /* Apply the rate through the original callback */ + clearwater_spin_sysclk(arizona); + ret = snd_soc_update_bits_locked(codec, e->reg, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int clearwater_adsp_rate_put_cb(struct wm_adsp *adsp, + unsigned int mask, + unsigned int val) +{ + int ret, err; + int lim; + const int *cur_sources; + struct arizona *arizona = dev_get_drvdata(adsp->dev); + unsigned int cur; + + ret = regmap_read(adsp->regmap, adsp->base, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current: %d\n", ret); + return ret; + } + + if ((val & mask) == (cur & mask)) + return 0; + + ret = clearwater_get_sources(adsp->base, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + adsp->base, + ret); + return ret; + } + + dev_dbg(arizona->dev, "%s for DSP%d\n", __func__, adsp->num); + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + clearwater_spin_sysclk(arizona); + /* Apply the rate */ + ret = regmap_update_bits(adsp->regmap, adsp->base, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int clearwater_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct clearwater_priv *clearwater = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &clearwater->core; + struct arizona *arizona = priv->arizona; + + clearwater_spin_sysclk(arizona); + + return 0; +} + +static int clearwater_dspclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct clearwater_priv *clearwater = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &clearwater->core; + struct arizona *arizona = priv->arizona; + + switch (event) { + case SND_SOC_DAPM_PRE_REG: + mutex_lock(&arizona->dspclk_ena_lock); + break; + case SND_SOC_DAPM_POST_REG: + mutex_unlock(&arizona->dspclk_ena_lock); + break; + } + + return 0; +} + +static int clearwater_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct clearwater_priv *clearwater = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &clearwater->core; + struct arizona *arizona = priv->arizona; + unsigned int freq; + int i, ret; + + ret = regmap_read(arizona->regmap, CLEARWATER_DSP_CLOCK_1, &freq); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read CLEARWATER_DSP_CLOCK_1: %d\n", ret); + return ret; + } + + freq &= CLEARWATER_DSP_CLK_FREQ_LEGACY_MASK; + freq >>= CLEARWATER_DSP_CLK_FREQ_LEGACY_SHIFT; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + for (i = 0; i < ARRAY_SIZE(clearwater->compr_info); ++i) { + if (clearwater->compr_info[i].adsp_compr.dsp->num != + w->shift + 1) + continue; + + mutex_lock(&clearwater->compr_info[i].trig_lock); + clearwater->compr_info[i].trig = false; + mutex_unlock(&clearwater->compr_info[i].trig_lock); + } + break; + default: + break; + } + + return wm_adsp2_early_event(w, kcontrol, event, freq); +} + +static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); + +#define CLEARWATER_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0) + +#define CLEARWATER_RXANC_INPUT_ROUTES(widget, name) \ + { widget, NULL, name " NG Mux" }, \ + { name " NG Internal", NULL, "RXANC NG Clock" }, \ + { name " NG Internal", NULL, name " Channel" }, \ + { name " NG External", NULL, "RXANC NG External Clock" }, \ + { name " NG External", NULL, name " Channel" }, \ + { name " NG Mux", "None", name " Channel" }, \ + { name " NG Mux", "Internal", name " NG Internal" }, \ + { name " NG Mux", "External", name " NG External" }, \ + { name " Channel", "Left", name " Left Input" }, \ + { name " Channel", "Combine", name " Left Input" }, \ + { name " Channel", "Right", name " Right Input" }, \ + { name " Channel", "Combine", name " Right Input" }, \ + { name " Left Input", "IN1", "IN1L PGA" }, \ + { name " Right Input", "IN1", "IN1R PGA" }, \ + { name " Left Input", "IN2", "IN2L PGA" }, \ + { name " Right Input", "IN2", "IN2R PGA" }, \ + { name " Left Input", "IN3", "IN3L PGA" }, \ + { name " Right Input", "IN3", "IN3R PGA" }, \ + { name " Left Input", "IN4", "IN4L PGA" }, \ + { name " Right Input", "IN4", "IN4R PGA" }, \ + { name " Left Input", "IN5", "IN5L PGA" }, \ + { name " Right Input", "IN5", "IN5R PGA" }, \ + { name " Left Input", "IN6", "IN6L PGA" }, \ + { name " Right Input", "IN6", "IN6R PGA" } + +#define CLEARWATER_RXANC_OUTPUT_ROUTES(widget, name) \ + { widget, NULL, name " ANC Source" }, \ + { name " ANC Source", "RXANCL", "RXANCL" }, \ + { name " ANC Source", "RXANCR", "RXANCR" } + +static int clearwater_cp_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + unsigned int val; + + regmap_read(arizona->regmap, CLEARWATER_CP_MODE, &val); + if (val == 0x400) + ucontrol->value.enumerated.item[0] = 0; + else + ucontrol->value.enumerated.item[0] = 1; + + return 0; +} + +static int clearwater_cp_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int val = ucontrol->value.enumerated.item[0]; + + if (val > e->max - 1) + return -EINVAL; + + mutex_lock(&arizona->reg_setting_lock); + if (val ==0) { /* Default */ + regmap_write(arizona->regmap, 0x80, 0x1); + regmap_write(arizona->regmap, CLEARWATER_CP_MODE, 0x400); + regmap_write(arizona->regmap, 0x80, 0x0); + } else {/* Inverting */ + regmap_write(arizona->regmap, 0x80, 0x1); + regmap_write(arizona->regmap, CLEARWATER_CP_MODE, 0x407); + regmap_write(arizona->regmap, 0x80, 0x0); + } + mutex_unlock(&arizona->reg_setting_lock); + + return 0; +} + +static const char * const clearwater_cp_mode_text[2] = { + "Default", "Inverting", +}; + +static const struct soc_enum clearwater_cp_mode[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(clearwater_cp_mode_text), + clearwater_cp_mode_text), +}; + +static const struct snd_kcontrol_new clearwater_snd_controls[] = { +SOC_VALUE_ENUM("IN1 OSR", clearwater_in_dmic_osr[0]), +SOC_VALUE_ENUM("IN2 OSR", clearwater_in_dmic_osr[1]), +SOC_VALUE_ENUM("IN3 OSR", clearwater_in_dmic_osr[2]), +SOC_VALUE_ENUM("IN4 OSR", clearwater_in_dmic_osr[3]), +SOC_VALUE_ENUM("IN5 OSR", clearwater_in_dmic_osr[4]), +SOC_VALUE_ENUM("IN6 OSR", clearwater_in_dmic_osr[5]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN3L HPF Switch", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN3R HPF Switch", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN4L HPF Switch", ARIZONA_IN4L_CONTROL, + ARIZONA_IN4L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN4R HPF Switch", ARIZONA_IN4R_CONTROL, + ARIZONA_IN4R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN5L HPF Switch", ARIZONA_IN5L_CONTROL, + ARIZONA_IN5L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN5R HPF Switch", ARIZONA_IN5R_CONTROL, + ARIZONA_IN5R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN6L HPF Switch", ARIZONA_IN6L_CONTROL, + ARIZONA_IN6L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN6R HPF Switch", ARIZONA_IN6R_CONTROL, + ARIZONA_IN6R_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, + ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R, + ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN5L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_5L, + ARIZONA_IN5L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN5R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_5R, + ARIZONA_IN5R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN6L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_6L, + ARIZONA_IN6L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN6R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_6R, + ARIZONA_IN6R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM_EXT("IN1 Mode", arizona_ip_mode[0], + snd_soc_get_enum_double, arizona_ip_mode_put), +SOC_ENUM_EXT("IN2 Mode", arizona_ip_mode[1], + snd_soc_get_enum_double, arizona_ip_mode_put), +SOC_ENUM_EXT("IN3 Mode", arizona_ip_mode[2], + snd_soc_get_enum_double, arizona_ip_mode_put), +SOC_ENUM_EXT("CP Mode", clearwater_cp_mode[0], + clearwater_cp_mode_get, clearwater_cp_mode_put), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +SND_SOC_BYTES("RXANC Coefficients", ARIZONA_ANC_COEFF_START, + ARIZONA_ANC_COEFF_END - ARIZONA_ANC_COEFF_START + 1), +SND_SOC_BYTES("RXANCL Config", ARIZONA_FCL_FILTER_CONTROL, 1), +SND_SOC_BYTES("RXANCL Coefficients", ARIZONA_FCL_COEFF_START, + ARIZONA_FCL_COEFF_END - ARIZONA_FCL_COEFF_START + 1), +SND_SOC_BYTES("RXANCR Config", CLEARWATER_FCR_FILTER_CONTROL, 1), +SND_SOC_BYTES("RXANCR Coefficients", CLEARWATER_FCR_COEFF_START, + CLEARWATER_FCR_COEFF_END - CLEARWATER_FCR_COEFF_START + 1), + +CLEARWATER_FRF_BYTES("FRF COEFF 1L", CLEARWATER_FRF_COEFFICIENT_1L_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 1R", CLEARWATER_FRF_COEFFICIENT_1R_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 2L", CLEARWATER_FRF_COEFFICIENT_2L_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 2R", CLEARWATER_FRF_COEFFICIENT_2R_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 3L", CLEARWATER_FRF_COEFFICIENT_3L_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 3R", CLEARWATER_FRF_COEFFICIENT_3R_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 4L", CLEARWATER_FRF_COEFFICIENT_4L_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 4R", CLEARWATER_FRF_COEFFICIENT_4R_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 5L", CLEARWATER_FRF_COEFFICIENT_5L_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 5R", CLEARWATER_FRF_COEFFICIENT_5R_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 6L", CLEARWATER_FRF_COEFFICIENT_6L_1, + CLEARWATER_FRF_COEFFICIENT_LEN), +CLEARWATER_FRF_BYTES("FRF COEFF 6R", CLEARWATER_FRF_COEFFICIENT_6R_1, + CLEARWATER_FRF_COEFFICIENT_LEN), + +SND_SOC_BYTES("DAC COMP 1", CLEARWATER_DAC_COMP_1, 1), +SND_SOC_BYTES("DAC COMP 2", CLEARWATER_DAC_COMP_2, 1), + +ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), +SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), +SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), +SND_SOC_BYTES_MASK("DRC2", CLEARWATER_DRC2_CTRL1, 5, + ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +SOC_VALUE_ENUM("Sample Rate 2", arizona_sample_rate[0]), +SOC_VALUE_ENUM("Sample Rate 3", arizona_sample_rate[1]), +SOC_VALUE_ENUM("ASYNC Sample Rate 2", arizona_sample_rate[2]), + +CLEARWATER_RATE_ENUM("FX Rate", arizona_fx_rate), + +CLEARWATER_RATE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +CLEARWATER_RATE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +CLEARWATER_RATE_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]), +CLEARWATER_RATE_ENUM("ISRC4 FSL", arizona_isrc_fsl[3]), +CLEARWATER_RATE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +CLEARWATER_RATE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), +CLEARWATER_RATE_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]), +CLEARWATER_RATE_ENUM("ISRC4 FSH", arizona_isrc_fsh[3]), +CLEARWATER_RATE_ENUM("ASRC1 Rate 1", clearwater_asrc1_rate[0]), +CLEARWATER_RATE_ENUM("ASRC1 Rate 2", clearwater_asrc1_rate[1]), +CLEARWATER_RATE_ENUM("ASRC2 Rate 1", clearwater_asrc2_rate[0]), +CLEARWATER_RATE_ENUM("ASRC2 Rate 2", clearwater_asrc2_rate[1]), + +ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP4L", ARIZONA_DSP4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP4R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP5L", CLEARWATER_DSP5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP5R", CLEARWATER_DSP5RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP6L", CLEARWATER_DSP6LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP6R", CLEARWATER_DSP6RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP7L", CLEARWATER_DSP7LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP7R", CLEARWATER_DSP7RMIX_INPUT_1_SOURCE), + +SOC_SINGLE_TLV("Noise Generator Volume", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv), + +ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT2L", ARIZONA_OUT2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT2R", ARIZONA_OUT2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT3L", ARIZONA_OUT3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT3R", ARIZONA_OUT3RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT2L", ARIZONA_OUT6LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT2R", ARIZONA_OUT6RMIX_INPUT_1_SOURCE), + +SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_SHIFT, 1, 0), +SOC_SINGLE("HPOUT2 SC Protect Switch", ARIZONA_HP2_SHORT_CIRCUIT_CTRL, + ARIZONA_HP2_SC_ENA_SHIFT, 1, 0), +SOC_SINGLE("HPOUT3 SC Protect Switch", ARIZONA_HP3_SHORT_CIRCUIT_CTRL, + ARIZONA_HP3_SC_ENA_SHIFT, 1, 0), + +SOC_SINGLE("HPOUT1L ONEFLT Switch", ARIZONA_HP_TEST_CTRL_5, + ARIZONA_HP1L_ONEFLT_SHIFT, 1, 0), +SOC_SINGLE("HPOUT1R ONEFLT Switch", ARIZONA_HP_TEST_CTRL_6, + ARIZONA_HP1R_ONEFLT_SHIFT, 1, 0), + +SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L, + ARIZONA_OUT5_OSR_SHIFT, 1, 0), +SOC_SINGLE("SPKDAT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_6L, + ARIZONA_OUT6_OSR_SHIFT, 1, 0), + +SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("HPOUT3 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_6L, + ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_6L, + ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), +SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT, + ARIZONA_SPK2R_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_EXT("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE1L_ENA_SHIFT, VEGAS_DRE1R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), +SOC_DOUBLE_EXT("HPOUT2 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE2L_ENA_SHIFT, VEGAS_DRE2R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), +SOC_DOUBLE_EXT("HPOUT3 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE3L_ENA_SHIFT, VEGAS_DRE3R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), + +SOC_DOUBLE("HPOUT1 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT1L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT1R_THR1_ENA_SHIFT, 1, 0), +SOC_DOUBLE("HPOUT2 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT2L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT2R_THR1_ENA_SHIFT, 1, 0), +SOC_DOUBLE("HPOUT3 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT3L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT3R_THR1_ENA_SHIFT, 1, 0), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +CLEARWATER_RATE_ENUM("SPDIF Rate", arizona_spdif_rate), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +CLEARWATER_RATE_ENUM("Output Rate 1", arizona_output_rate), +SOC_VALUE_ENUM("In Rate", arizona_input_rate), + +CLEARWATER_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +CLEARWATER_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +CLEARWATER_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), +CLEARWATER_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R), +CLEARWATER_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L), +CLEARWATER_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R), +CLEARWATER_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), +CLEARWATER_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R), +CLEARWATER_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +CLEARWATER_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), +CLEARWATER_NG_SRC("SPKDAT2L", ARIZONA_NOISE_GATE_SELECT_6L), +CLEARWATER_NG_SRC("SPKDAT2R", ARIZONA_NOISE_GATE_SELECT_6R), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX7", ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX8", ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF4TX1", ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF4TX2", ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE), + +ARIZONA_GAINMUX_CONTROLS("SPDIFTX1", ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SPDIFTX2", ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE), +}; + +CLEARWATER_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP4L, ARIZONA_DSP4LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP4R, ARIZONA_DSP4RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP4, ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP5L, CLEARWATER_DSP5LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP5R, CLEARWATER_DSP5RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP5, CLEARWATER_DSP5AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP6L, CLEARWATER_DSP6LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP6R, CLEARWATER_DSP6RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP6, CLEARWATER_DSP6AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP7L, CLEARWATER_DSP7LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP7R, CLEARWATER_DSP7RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP7, CLEARWATER_DSP7AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT3L, ARIZONA_OUT3LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT3R, ARIZONA_OUT3RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT2L, ARIZONA_OUT6LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT2R, ARIZONA_OUT6RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX7, ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX8, ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF4TX1, ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF4TX2, ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(SPD1TX1, ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(SPD1TX2, ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ASRC1IN1L, CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC1IN1R, CLEARWATER_ASRC1_1RMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC1IN2L, CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC1IN2R, CLEARWATER_ASRC1_2RMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN1L, CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN1R, CLEARWATER_ASRC2_1RMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN2L, CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN2R, CLEARWATER_ASRC2_2RMIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC3INT1, ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC3INT2, ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC3DEC1, ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC3DEC2, ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC4INT1, ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC4INT2, ARIZONA_ISRC4INT2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC4DEC1, ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC4DEC2, ARIZONA_ISRC4DEC2MIX_INPUT_1_SOURCE); + +static const char * const clearwater_dsp_output_texts[] = { + "None", + "DSP6", +}; + +static const struct soc_enum clearwater_dsp_output_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(clearwater_dsp_output_texts), + clearwater_dsp_output_texts); + +static const struct snd_kcontrol_new clearwater_dsp_output_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", clearwater_dsp_output_enum), +}; + +static const char * const clearwater_memory_mux_texts[] = { + "None", + "Shared Memory", +}; + +static const struct soc_enum clearwater_memory_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(clearwater_memory_mux_texts), + clearwater_memory_mux_texts); + +static const struct snd_kcontrol_new clearwater_memory_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP2 Virtual Input", clearwater_memory_enum), + SOC_DAPM_ENUM_VIRT("DSP3 Virtual Input", clearwater_memory_enum), +}; + +static const char * const clearwater_aec_loopback_texts[] = { + "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R", + "SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", "SPKDAT2L", "SPKDAT2R", +}; + +static const unsigned int clearwater_aec_loopback_values[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, +}; + +static const struct soc_enum clearwater_aec1_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(clearwater_aec_loopback_texts), + clearwater_aec_loopback_texts, + clearwater_aec_loopback_values); + +static const struct soc_enum clearwater_aec2_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_2, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(clearwater_aec_loopback_texts), + clearwater_aec_loopback_texts, + clearwater_aec_loopback_values); + +static const struct snd_kcontrol_new clearwater_aec_loopback_mux[] = { + SOC_DAPM_VALUE_ENUM("AEC1 Loopback", clearwater_aec1_loopback), + SOC_DAPM_VALUE_ENUM("AEC2 Loopback", clearwater_aec2_loopback), +}; + +static const struct snd_kcontrol_new clearwater_anc_input_mux[] = { + SOC_DAPM_ENUM("RXANCL Input", clearwater_anc_input_src[0]), + SOC_DAPM_ENUM("RXANCL Channel", clearwater_anc_input_src[1]), + SOC_DAPM_ENUM("RXANCR Input", clearwater_anc_input_src[2]), + SOC_DAPM_ENUM("RXANCR Channel", clearwater_anc_input_src[3]), +}; + +static const struct snd_kcontrol_new clearwater_anc_ng_mux = + SOC_DAPM_ENUM_VIRT("RXANC NG Source", arizona_anc_ng_enum); + +static const struct snd_kcontrol_new clearwater_output_anc_src[] = { + SOC_DAPM_ENUM("HPOUT1L ANC Source", arizona_output_anc_src[0]), + SOC_DAPM_ENUM("HPOUT1R ANC Source", arizona_output_anc_src[1]), + SOC_DAPM_ENUM("HPOUT2L ANC Source", arizona_output_anc_src[2]), + SOC_DAPM_ENUM("HPOUT2R ANC Source", arizona_output_anc_src[3]), + SOC_DAPM_ENUM("HPOUT3L ANC Source", arizona_output_anc_src[4]), + SOC_DAPM_ENUM("HPOUT3R ANC Source", clearwater_output_anc_src_defs[0]), + SOC_DAPM_ENUM("SPKOUTL ANC Source", arizona_output_anc_src[6]), + SOC_DAPM_ENUM("SPKOUTR ANC Source", arizona_output_anc_src[7]), + SOC_DAPM_ENUM("SPKDAT1L ANC Source", arizona_output_anc_src[8]), + SOC_DAPM_ENUM("SPKDAT1R ANC Source", arizona_output_anc_src[9]), + SOC_DAPM_ENUM("SPKDAT2L ANC Source", arizona_output_anc_src[10]), + SOC_DAPM_ENUM("SPKDAT2R ANC Source", arizona_output_anc_src[11]), +}; + +static const struct snd_soc_dapm_widget clearwater_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, + 0, clearwater_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, + ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK, + ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("DSPCLK", CLEARWATER_DSP_CLOCK_1, 6, + 0, clearwater_dspclk_ev, + SND_SOC_DAPM_PRE_REG | SND_SOC_DAPM_POST_REG), + + +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD4", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_INPUT("IN1AL"), +SND_SOC_DAPM_INPUT("IN1B"), +SND_SOC_DAPM_INPUT("IN1R"), +SND_SOC_DAPM_INPUT("IN2AL"), +SND_SOC_DAPM_INPUT("IN2AR"), +SND_SOC_DAPM_INPUT("IN2BL"), +SND_SOC_DAPM_INPUT("IN2BR"), +SND_SOC_DAPM_INPUT("IN3L"), +SND_SOC_DAPM_INPUT("IN3R"), +SND_SOC_DAPM_INPUT("IN4L"), +SND_SOC_DAPM_INPUT("IN4R"), +SND_SOC_DAPM_INPUT("IN5L"), +SND_SOC_DAPM_INPUT("IN5R"), +SND_SOC_DAPM_INPUT("IN6L"), +SND_SOC_DAPM_INPUT("IN6R"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &clearwater_in1mux), +SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &clearwater_in2mux[0]), +SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &clearwater_in2mux[1]), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN3L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN3R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN4L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN4R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN5L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN5L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN5R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN5R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN6L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN6L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN6R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN6R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS4", ARIZONA_MIC_BIAS_CTRL_4, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Noise Generator", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_PGA("ASRC1IN1L", CLEARWATER_ASRC1_ENABLE, CLEARWATER_ASRC1_IN1L_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC1IN1R", CLEARWATER_ASRC1_ENABLE, CLEARWATER_ASRC1_IN1R_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC1IN2L", CLEARWATER_ASRC1_ENABLE, CLEARWATER_ASRC1_IN2L_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC1IN2R", CLEARWATER_ASRC1_ENABLE, CLEARWATER_ASRC1_IN2R_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_PGA("ASRC2IN1L", CLEARWATER_ASRC2_ENABLE, CLEARWATER_ASRC2_IN1L_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC2IN1R", CLEARWATER_ASRC2_ENABLE, CLEARWATER_ASRC2_IN1R_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC2IN2L", CLEARWATER_ASRC2_ENABLE, CLEARWATER_ASRC2_IN2L_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC2IN2R", CLEARWATER_ASRC2_ENABLE, CLEARWATER_ASRC2_IN2R_ENA_SHIFT, + 0, NULL, 0), + +WM_ADSP2("DSP1", 0, clearwater_adsp_power_ev), +WM_ADSP2("DSP2", 1, clearwater_adsp_power_ev), +WM_ADSP2("DSP3", 2, clearwater_adsp_power_ev), +WM_ADSP2("DSP4", 3, clearwater_adsp_power_ev), +WM_ADSP2("DSP5", 4, clearwater_adsp_power_ev), +WM_ADSP2("DSP6", 5, clearwater_adsp_power_ev), +WM_ADSP2("DSP7", 6, clearwater_adsp_power_ev), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3INT1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3DEC1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC4INT1", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC4INT2", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC4DEC1", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC4DEC2", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_VALUE_MUX("AEC1 Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &clearwater_aec_loopback_mux[0]), +SND_SOC_DAPM_VALUE_MUX("AEC2 Loopback", ARIZONA_DAC_AEC_CONTROL_2, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &clearwater_aec_loopback_mux[1]), + + +SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM, + ARIZONA_EXT_NG_SEL_SET_SHIFT, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM, + ARIZONA_CLK_NG_ENA_SET_SHIFT, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0, + &clearwater_anc_input_mux[0]), +SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0, + &clearwater_anc_input_mux[0]), +SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0, + &clearwater_anc_input_mux[1]), +SND_SOC_DAPM_VIRT_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, + &clearwater_anc_ng_mux), +SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0, + &clearwater_anc_input_mux[2]), +SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0, + &clearwater_anc_input_mux[2]), +SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0, + &clearwater_anc_input_mux[3]), +SND_SOC_DAPM_VIRT_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, + &clearwater_anc_ng_mux), + +SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, ARIZONA_CLK_L_ENA_SET_SHIFT, + 0, NULL, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, ARIZONA_CLK_R_ENA_SET_SHIFT, + 0, NULL, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[0]), +SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[1]), +SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[2]), +SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[3]), +SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[4]), +SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[5]), +SND_SOC_DAPM_MUX("SPKOUTL ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[6]), +SND_SOC_DAPM_MUX("SPKOUTR ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[7]), +SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[8]), +SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[9]), +SND_SOC_DAPM_MUX("SPKDAT2L ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[10]), +SND_SOC_DAPM_MUX("SPKDAT2R ANC Source", SND_SOC_NOPM, 0, 0, + &clearwater_output_anc_src[11]), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF4TX1", NULL, 0, + ARIZONA_AIF4_TX_ENABLES, ARIZONA_AIF4TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF4TX2", NULL, 0, + ARIZONA_AIF4_TX_ENABLES, ARIZONA_AIF4TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF4RX1", NULL, 0, + ARIZONA_AIF4_RX_ENABLES, ARIZONA_AIF4RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF4RX2", NULL, 0, + ARIZONA_AIF4_RX_ENABLES, ARIZONA_AIF4RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, clearwater_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, clearwater_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT6L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT6L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT6R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT6R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_PGA("SPD1TX1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL1_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("SPD1TX2", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL2_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_OUT_DRV("SPD1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_ENA_SHIFT, 0, NULL, 0), + +ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), +ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), +ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"), +ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), + +ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), +ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), +ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"), +ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"), +ARIZONA_MIXER_WIDGETS(OUT2L, "HPOUT2L"), +ARIZONA_MIXER_WIDGETS(OUT2R, "HPOUT2R"), +ARIZONA_MIXER_WIDGETS(OUT3L, "HPOUT3L"), +ARIZONA_MIXER_WIDGETS(OUT3R, "HPOUT3R"), +ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"), +ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"), +ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"), +ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"), +ARIZONA_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"), +ARIZONA_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), +ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"), +ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), +ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"), +ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"), +ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"), +ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"), +ARIZONA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"), +ARIZONA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MIXER_WIDGETS(AIF4TX1, "AIF4TX1"), +ARIZONA_MIXER_WIDGETS(AIF4TX2, "AIF4TX2"), + +ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"), +ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"), +ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"), + +ARIZONA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"), +ARIZONA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"), + +ARIZONA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"), +ARIZONA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"), +ARIZONA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"), +ARIZONA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"), +ARIZONA_MUX_WIDGETS(ASRC2IN1L, "ASRC2IN1L"), +ARIZONA_MUX_WIDGETS(ASRC2IN1R, "ASRC2IN1R"), +ARIZONA_MUX_WIDGETS(ASRC2IN2L, "ASRC2IN2L"), +ARIZONA_MUX_WIDGETS(ASRC2IN2R, "ASRC2IN2R"), + + +ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), +ARIZONA_DSP_WIDGETS(DSP2, "DSP2"), +ARIZONA_DSP_WIDGETS(DSP3, "DSP3"), +ARIZONA_DSP_WIDGETS(DSP4, "DSP4"), +ARIZONA_DSP_WIDGETS(DSP5, "DSP5"), +ARIZONA_DSP_WIDGETS(DSP6, "DSP6"), +ARIZONA_DSP_WIDGETS(DSP7, "DSP7"), + +SND_SOC_DAPM_VIRT_MUX("DSP2 Virtual Input", SND_SOC_NOPM, 0, 0, + &clearwater_memory_mux[0]), +SND_SOC_DAPM_VIRT_MUX("DSP3 Virtual Input", SND_SOC_NOPM, 0, 0, + &clearwater_memory_mux[1]), + +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &clearwater_dsp_output_mux[0]), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), +ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"), +ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), +ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"), +ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"), + +ARIZONA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), +ARIZONA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), +ARIZONA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), + +ARIZONA_MUX_WIDGETS(ISRC4DEC1, "ISRC4DEC1"), +ARIZONA_MUX_WIDGETS(ISRC4DEC2, "ISRC4DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC4INT1, "ISRC4INT1"), +ARIZONA_MUX_WIDGETS(ISRC4INT2, "ISRC4INT2"), + +SND_SOC_DAPM_OUTPUT("HPOUT1L"), +SND_SOC_DAPM_OUTPUT("HPOUT1R"), +SND_SOC_DAPM_OUTPUT("HPOUT2L"), +SND_SOC_DAPM_OUTPUT("HPOUT2R"), +SND_SOC_DAPM_OUTPUT("HPOUT3L"), +SND_SOC_DAPM_OUTPUT("HPOUT3R"), +SND_SOC_DAPM_OUTPUT("SPKOUTLN"), +SND_SOC_DAPM_OUTPUT("SPKOUTLP"), +SND_SOC_DAPM_OUTPUT("SPKOUTRN"), +SND_SOC_DAPM_OUTPUT("SPKOUTRP"), +SND_SOC_DAPM_OUTPUT("SPKDAT1L"), +SND_SOC_DAPM_OUTPUT("SPKDAT1R"), +SND_SOC_DAPM_OUTPUT("SPKDAT2L"), +SND_SOC_DAPM_OUTPUT("SPKDAT2R"), +SND_SOC_DAPM_OUTPUT("SPDIF"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC1 Loopback" }, \ + { name, "AEC2", "AEC2 Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "IN3L", "IN3L PGA" }, \ + { name, "IN3R", "IN3R PGA" }, \ + { name, "IN4L", "IN4L PGA" }, \ + { name, "IN4R", "IN4R PGA" }, \ + { name, "IN5L", "IN5L PGA" }, \ + { name, "IN5R", "IN5R PGA" }, \ + { name, "IN6L", "IN6L PGA" }, \ + { name, "IN6R", "IN6R PGA" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF1RX7", "AIF1RX7" }, \ + { name, "AIF1RX8", "AIF1RX8" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF2RX3", "AIF2RX3" }, \ + { name, "AIF2RX4", "AIF2RX4" }, \ + { name, "AIF2RX5", "AIF2RX5" }, \ + { name, "AIF2RX6", "AIF2RX6" }, \ + { name, "AIF2RX7", "AIF2RX7" }, \ + { name, "AIF2RX8", "AIF2RX8" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "AIF4RX1", "AIF4RX1" }, \ + { name, "AIF4RX2", "AIF4RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "SLIMRX5", "SLIMRX5" }, \ + { name, "SLIMRX6", "SLIMRX6" }, \ + { name, "SLIMRX7", "SLIMRX7" }, \ + { name, "SLIMRX8", "SLIMRX8" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ASRC1IN1L", "ASRC1IN1L" }, \ + { name, "ASRC1IN1R", "ASRC1IN1R" }, \ + { name, "ASRC1IN2L", "ASRC1IN2L" }, \ + { name, "ASRC1IN2R", "ASRC1IN2R" }, \ + { name, "ASRC2IN1L", "ASRC2IN1L" }, \ + { name, "ASRC2IN1R", "ASRC2IN1R" }, \ + { name, "ASRC2IN2L", "ASRC2IN2L" }, \ + { name, "ASRC2IN2R", "ASRC2IN2R" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2DEC3", "ISRC2DEC3" }, \ + { name, "ISRC2DEC4", "ISRC2DEC4" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC2INT3", "ISRC2INT3" }, \ + { name, "ISRC2INT4", "ISRC2INT4" }, \ + { name, "ISRC3DEC1", "ISRC3DEC1" }, \ + { name, "ISRC3DEC2", "ISRC3DEC2" }, \ + { name, "ISRC3INT1", "ISRC3INT1" }, \ + { name, "ISRC3INT2", "ISRC3INT2" }, \ + { name, "ISRC4DEC1", "ISRC4DEC1" }, \ + { name, "ISRC4DEC2", "ISRC4DEC2" }, \ + { name, "ISRC4INT1", "ISRC4INT1" }, \ + { name, "ISRC4INT2", "ISRC4INT2" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" }, \ + { name, "DSP2.1", "DSP2" }, \ + { name, "DSP2.2", "DSP2" }, \ + { name, "DSP2.3", "DSP2" }, \ + { name, "DSP2.4", "DSP2" }, \ + { name, "DSP2.5", "DSP2" }, \ + { name, "DSP2.6", "DSP2" }, \ + { name, "DSP3.1", "DSP3" }, \ + { name, "DSP3.2", "DSP3" }, \ + { name, "DSP3.3", "DSP3" }, \ + { name, "DSP3.4", "DSP3" }, \ + { name, "DSP3.5", "DSP3" }, \ + { name, "DSP3.6", "DSP3" }, \ + { name, "DSP4.1", "DSP4" }, \ + { name, "DSP4.2", "DSP4" }, \ + { name, "DSP4.3", "DSP4" }, \ + { name, "DSP4.4", "DSP4" }, \ + { name, "DSP4.5", "DSP4" }, \ + { name, "DSP4.6", "DSP4" }, \ + { name, "DSP5.1", "DSP5" }, \ + { name, "DSP5.2", "DSP5" }, \ + { name, "DSP5.3", "DSP5" }, \ + { name, "DSP5.4", "DSP5" }, \ + { name, "DSP5.5", "DSP5" }, \ + { name, "DSP5.6", "DSP5" }, \ + { name, "DSP6.1", "DSP6" }, \ + { name, "DSP6.2", "DSP6" }, \ + { name, "DSP6.3", "DSP6" }, \ + { name, "DSP6.4", "DSP6" }, \ + { name, "DSP6.5", "DSP6" }, \ + { name, "DSP6.6", "DSP6" }, \ + { name, "DSP7.1", "DSP7" }, \ + { name, "DSP7.2", "DSP7" }, \ + { name, "DSP7.3", "DSP7" }, \ + { name, "DSP7.4", "DSP7" }, \ + { name, "DSP7.5", "DSP7" }, \ + { name, "DSP7.6", "DSP7" } + +static const struct snd_soc_dapm_route clearwater_dapm_routes[] = { + { "AIF2 Capture", NULL, "DBVDD2" }, + { "AIF2 Playback", NULL, "DBVDD2" }, + + { "AIF3 Capture", NULL, "DBVDD3" }, + { "AIF3 Playback", NULL, "DBVDD3" }, + + { "AIF4 Capture", NULL, "DBVDD3" }, + { "AIF4 Playback", NULL, "DBVDD3" }, + + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + { "OUT2L", NULL, "CPVDD" }, + { "OUT2R", NULL, "CPVDD" }, + { "OUT3L", NULL, "CPVDD" }, + { "OUT3R", NULL, "CPVDD" }, + + { "OUT4L", NULL, "SPKVDDL" }, + { "OUT4R", NULL, "SPKVDDR" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT2L", NULL, "SYSCLK" }, + { "OUT2R", NULL, "SYSCLK" }, + { "OUT3L", NULL, "SYSCLK" }, + { "OUT3R", NULL, "SYSCLK" }, + { "OUT4L", NULL, "SYSCLK" }, + { "OUT4R", NULL, "SYSCLK" }, + { "OUT5L", NULL, "SYSCLK" }, + { "OUT5R", NULL, "SYSCLK" }, + { "OUT6L", NULL, "SYSCLK" }, + { "OUT6R", NULL, "SYSCLK" }, + + { "SPD1", NULL, "SYSCLK" }, + { "SPD1", NULL, "SPD1TX1" }, + { "SPD1", NULL, "SPD1TX2" }, + + { "IN1AL", NULL, "SYSCLK" }, + { "IN1B", NULL, "SYSCLK" }, + { "IN1R", NULL, "SYSCLK" }, + { "IN2AL", NULL, "SYSCLK" }, + { "IN2AR", NULL, "SYSCLK" }, + { "IN2BL", NULL, "SYSCLK" }, + { "IN2BR", NULL, "SYSCLK" }, + { "IN3L", NULL, "SYSCLK" }, + { "IN3R", NULL, "SYSCLK" }, + { "IN4L", NULL, "SYSCLK" }, + { "IN4R", NULL, "SYSCLK" }, + { "IN5L", NULL, "SYSCLK" }, + { "IN5R", NULL, "SYSCLK" }, + { "IN6L", NULL, "SYSCLK" }, + { "IN6R", NULL, "SYSCLK" }, + + { "IN4L", NULL, "DBVDD4" }, + { "IN4R", NULL, "DBVDD4" }, + { "IN5L", NULL, "DBVDD4" }, + { "IN5R", NULL, "DBVDD4" }, + { "IN6L", NULL, "DBVDD4" }, + { "IN6R", NULL, "DBVDD4" }, + + { "DSP1", NULL, "DSPCLK"}, + { "DSP2", NULL, "DSPCLK"}, + { "DSP3", NULL, "DSPCLK"}, + { "DSP4", NULL, "DSPCLK"}, + { "DSP5", NULL, "DSPCLK"}, + { "DSP6", NULL, "DSPCLK"}, + { "DSP7", NULL, "DSPCLK"}, + + { "MICBIAS1", NULL, "MICVDD" }, + { "MICBIAS2", NULL, "MICVDD" }, + { "MICBIAS3", NULL, "MICVDD" }, + { "MICBIAS4", NULL, "MICVDD" }, + + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Noise Generator", NULL, "NOISE" }, + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + { "AIF1 Capture", NULL, "AIF1TX7" }, + { "AIF1 Capture", NULL, "AIF1TX8" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + { "AIF1RX7", NULL, "AIF1 Playback" }, + { "AIF1RX8", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + { "AIF2 Capture", NULL, "AIF2TX3" }, + { "AIF2 Capture", NULL, "AIF2TX4" }, + { "AIF2 Capture", NULL, "AIF2TX5" }, + { "AIF2 Capture", NULL, "AIF2TX6" }, + { "AIF2 Capture", NULL, "AIF2TX7" }, + { "AIF2 Capture", NULL, "AIF2TX8" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + { "AIF2RX3", NULL, "AIF2 Playback" }, + { "AIF2RX4", NULL, "AIF2 Playback" }, + { "AIF2RX5", NULL, "AIF2 Playback" }, + { "AIF2RX6", NULL, "AIF2 Playback" }, + { "AIF2RX7", NULL, "AIF2 Playback" }, + { "AIF2RX8", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "AIF4 Capture", NULL, "AIF4TX1" }, + { "AIF4 Capture", NULL, "AIF4TX2" }, + + { "AIF4RX1", NULL, "AIF4 Playback" }, + { "AIF4RX2", NULL, "AIF4 Playback" }, + + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + { "SLIMRX3", NULL, "Slim1 Playback" }, + { "SLIMRX4", NULL, "Slim1 Playback" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX5", NULL, "Slim2 Playback" }, + { "SLIMRX6", NULL, "Slim2 Playback" }, + + { "Slim3 Capture", NULL, "SLIMTX7" }, + { "Slim3 Capture", NULL, "SLIMTX8" }, + + { "SLIMRX7", NULL, "Slim3 Playback" }, + { "SLIMRX8", NULL, "Slim3 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + { "AIF4 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + { "Slim3 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + { "AIF4 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + { "Slim3 Capture", NULL, "SYSCLK" }, + + { "Voice Control CPU", NULL, "Voice Control DSP" }, + { "Voice Control DSP", NULL, "DSP6" }, + { "Voice Control CPU", NULL, "SYSCLK" }, + { "Voice Control DSP", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP1" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, + + { "IN1L Mux", "A", "IN1AL" }, + { "IN1L Mux", "B", "IN1B" }, + + { "IN2L Mux", "A", "IN2AL" }, + { "IN2L Mux", "B", "IN2BL" }, + { "IN2R Mux", "A", "IN2AR" }, + { "IN2R Mux", "B", "IN2BR" }, + + { "IN1L PGA", NULL, "IN1L Mux" }, + { "IN1R PGA", NULL, "IN1R" }, + + { "IN2L PGA", NULL, "IN2L Mux" }, + { "IN2R PGA", NULL, "IN2R Mux" }, + + { "IN3L PGA", NULL, "IN3L" }, + { "IN3R PGA", NULL, "IN3R" }, + + { "IN4L PGA", NULL, "IN4L" }, + { "IN4R PGA", NULL, "IN4R" }, + + { "IN5L PGA", NULL, "IN5L" }, + { "IN5R PGA", NULL, "IN5R" }, + + { "IN6L PGA", NULL, "IN6L" }, + { "IN6R PGA", NULL, "IN6R" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), + ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), + ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), + ARIZONA_MIXER_ROUTES("OUT2R", "HPOUT2R"), + ARIZONA_MIXER_ROUTES("OUT3L", "HPOUT3L"), + ARIZONA_MIXER_ROUTES("OUT3R", "HPOUT3R"), + + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"), + ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"), + ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"), + ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"), + ARIZONA_MIXER_ROUTES("OUT6L", "SPKDAT2L"), + ARIZONA_MIXER_ROUTES("OUT6R", "SPKDAT2R"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"), + ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"), + ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"), + ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"), + ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"), + ARIZONA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"), + ARIZONA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MIXER_ROUTES("AIF4TX1", "AIF4TX1"), + ARIZONA_MIXER_ROUTES("AIF4TX2", "AIF4TX2"), + + ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"), + ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"), + ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"), + + ARIZONA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"), + ARIZONA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"), + + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), + ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), + ARIZONA_MIXER_ROUTES("EQ3", "EQ3"), + ARIZONA_MIXER_ROUTES("EQ4", "EQ4"), + + ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), + ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), + ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"), + ARIZONA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"), + ARIZONA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"), + ARIZONA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"), + ARIZONA_MUX_ROUTES("ASRC2IN1L", "ASRC2IN1L"), + ARIZONA_MUX_ROUTES("ASRC2IN1R", "ASRC2IN1R"), + ARIZONA_MUX_ROUTES("ASRC2IN2L", "ASRC2IN2L"), + ARIZONA_MUX_ROUTES("ASRC2IN2R", "ASRC2IN2R"), + + ARIZONA_DSP_ROUTES("DSP1"), + ARIZONA_DSP_ROUTES("DSP2"), + ARIZONA_DSP_ROUTES("DSP3"), + ARIZONA_DSP_ROUTES("DSP4"), + ARIZONA_DSP_ROUTES("DSP5"), + ARIZONA_DSP_ROUTES("DSP6"), + ARIZONA_DSP_ROUTES("DSP7"), + + { "DSP2 Preloader", NULL, "DSP2 Virtual Input" }, + { "DSP2 Virtual Input", "Shared Memory", "DSP3" }, + { "DSP3 Preloader", NULL, "DSP3 Virtual Input" }, + { "DSP3 Virtual Input", "Shared Memory", "DSP2" }, + + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP6", "DSP6" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"), + ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + ARIZONA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), + ARIZONA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), + + ARIZONA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), + ARIZONA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), + + ARIZONA_MUX_ROUTES("ISRC4INT1", "ISRC4INT1"), + ARIZONA_MUX_ROUTES("ISRC4INT2", "ISRC4INT2"), + + ARIZONA_MUX_ROUTES("ISRC4DEC1", "ISRC4DEC1"), + ARIZONA_MUX_ROUTES("ISRC4DEC2", "ISRC4DEC2"), + + { "AEC1 Loopback", "HPOUT1L", "OUT1L" }, + { "AEC1 Loopback", "HPOUT1R", "OUT1R" }, + { "AEC2 Loopback", "HPOUT1L", "OUT1L" }, + { "AEC2 Loopback", "HPOUT1R", "OUT1R" }, + { "HPOUT1L", NULL, "OUT1L" }, + { "HPOUT1R", NULL, "OUT1R" }, + + { "AEC1 Loopback", "HPOUT2L", "OUT2L" }, + { "AEC1 Loopback", "HPOUT2R", "OUT2R" }, + { "AEC2 Loopback", "HPOUT2L", "OUT2L" }, + { "AEC2 Loopback", "HPOUT2R", "OUT2R" }, + { "HPOUT2L", NULL, "OUT2L" }, + { "HPOUT2R", NULL, "OUT2R" }, + + { "AEC1 Loopback", "HPOUT3L", "OUT3L" }, + { "AEC1 Loopback", "HPOUT3R", "OUT3R" }, + { "AEC2 Loopback", "HPOUT3L", "OUT3L" }, + { "AEC2 Loopback", "HPOUT3R", "OUT3R" }, + { "HPOUT3L", NULL, "OUT3L" }, + { "HPOUT3R", NULL, "OUT3R" }, + + { "AEC1 Loopback", "SPKOUTL", "OUT4L" }, + { "AEC2 Loopback", "SPKOUTL", "OUT4L" }, + { "SPKOUTLN", NULL, "OUT4L" }, + { "SPKOUTLP", NULL, "OUT4L" }, + + { "AEC1 Loopback", "SPKOUTR", "OUT4R" }, + { "AEC2 Loopback", "SPKOUTR", "OUT4R" }, + { "SPKOUTRN", NULL, "OUT4R" }, + { "SPKOUTRP", NULL, "OUT4R" }, + + { "AEC1 Loopback", "SPKDAT1L", "OUT5L" }, + { "AEC1 Loopback", "SPKDAT1R", "OUT5R" }, + { "AEC2 Loopback", "SPKDAT1L", "OUT5L" }, + { "AEC2 Loopback", "SPKDAT1R", "OUT5R" }, + { "SPKDAT1L", NULL, "OUT5L" }, + { "SPKDAT1R", NULL, "OUT5R" }, + + { "AEC1 Loopback", "SPKDAT2L", "OUT6L" }, + { "AEC1 Loopback", "SPKDAT2R", "OUT6R" }, + { "AEC2 Loopback", "SPKDAT2L", "OUT6L" }, + { "AEC2 Loopback", "SPKDAT2R", "OUT6R" }, + { "SPKDAT2L", NULL, "OUT6L" }, + { "SPKDAT2R", NULL, "OUT6R" }, + + CLEARWATER_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"), + CLEARWATER_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"), + + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT4L", "SPKOUTL"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT4R", "SPKOUTR"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT6L", "SPKDAT2L"), + CLEARWATER_RXANC_OUTPUT_ROUTES("OUT6R", "SPKDAT2R"), + + { "SPDIF", NULL, "SPD1" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, + { "DRC2 Signal Activity", NULL, "DRC2L" }, + { "DRC2 Signal Activity", NULL, "DRC2R" }, +}; + +static int clearwater_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct clearwater_priv *clearwater = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case CLEARWATER_FLL1: + return arizona_set_fll(&clearwater->fll[0], source, Fref, Fout); + case CLEARWATER_FLL2: + return arizona_set_fll(&clearwater->fll[1], source, Fref, Fout); + case CLEARWATER_FLL3: + return arizona_set_fll(&clearwater->fll[2], source, Fref, Fout); + case CLEARWATER_FLL1_REFCLK: + return arizona_set_fll_refclk(&clearwater->fll[0], source, Fref, + Fout); + case CLEARWATER_FLL2_REFCLK: + return arizona_set_fll_refclk(&clearwater->fll[1], source, Fref, + Fout); + case CLEARWATER_FLL3_REFCLK: + return arizona_set_fll_refclk(&clearwater->fll[2], source, Fref, + Fout); + default: + return -EINVAL; + } +} + +#define CLEARWATER_RATES SNDRV_PCM_RATE_KNOT + +#define CLEARWATER_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver clearwater_dai[] = { + { + .name = "clearwater-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "clearwater-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "clearwater-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "clearwater-aif4", + .id = 4, + .base = ARIZONA_AIF4_BCLK_CTRL, + .playback = { + .stream_name = "AIF4 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "AIF4 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "clearwater-slim1", + .id = 5, + .playback = { + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "clearwater-slim2", + .id = 6, + .playback = { + .stream_name = "Slim2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "clearwater-slim3", + .id = 7, + .playback = { + .stream_name = "Slim3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .capture = { + .stream_name = "Slim3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "clearwater-cpu-voicectrl", + .capture = { + .stream_name = "Voice Control CPU", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "clearwater-dsp-voicectrl", + .capture = { + .stream_name = "Voice Control DSP", + .channels_min = 1, + .channels_max = 2, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + }, + { + .name = "clearwater-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 2, + .channels_max = 8, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "clearwater-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 2, + .channels_max = 8, + .rates = CLEARWATER_RATES, + .formats = CLEARWATER_FORMATS, + }, + }, +}; + +static void clearwater_compr_irq(struct clearwater_priv *clearwater, + struct clearwater_compr *compr) +{ + struct arizona *arizona = clearwater->core.arizona; + bool trigger = false; + int ret; + + ret = wm_adsp_compr_irq(&compr->adsp_compr, &trigger); + if (ret < 0) + return; + + if (trigger && arizona->pdata.ez2ctrl_trigger) { + mutex_lock(&compr->trig_lock); + if (!compr->trig) { + compr->trig = true; + + if (wm_adsp_fw_has_voice_trig(compr->adsp_compr.dsp)) + arizona->pdata.ez2ctrl_trigger(); + } + mutex_unlock(&compr->trig_lock); + } +} + +static irqreturn_t clearwater_adsp2_irq(int irq, void *data) +{ + struct clearwater_priv *clearwater = data; + int i; + + for (i = 0; i < ARRAY_SIZE(clearwater->compr_info); ++i) { + if (!clearwater->compr_info[i].adsp_compr.dsp->running) + continue; + + clearwater_compr_irq(clearwater, &clearwater->compr_info[i]); + } + return IRQ_HANDLED; +} + +static struct clearwater_compr *clearwater_get_compr( + struct snd_soc_pcm_runtime *rtd, + struct clearwater_priv *clearwater) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clearwater->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + clearwater->compr_info[i].dai_name) == 0) + return &clearwater->compr_info[i]; + } + + return NULL; +} + +static int clearwater_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct clearwater_priv *clearwater = snd_soc_codec_get_drvdata(rtd->codec); + struct clearwater_compr *compr; + + compr = clearwater_get_compr(rtd, clearwater); + if (!compr) { + dev_err(clearwater->core.arizona->dev, + "No compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int clearwater_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *adsp_compr = + (struct wm_adsp_compr *)stream->runtime->private_data; + struct clearwater_compr *compr = container_of(adsp_compr, + struct clearwater_compr, + adsp_compr); + struct arizona *arizona = compr->priv->core.arizona; + int ret; + + ret = wm_adsp_compr_trigger(stream, cmd); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (compr->trig) + /* + * If the firmware already triggered before the stream + * was opened trigger another interrupt so irq handler + * will run and process any outstanding data + */ + regmap_write(arizona->regmap, + CLEARWATER_ADSP2_IRQ0, 0x01); + break; + default: + break; + } + + return ret; +} + +static int clearwater_codec_probe(struct snd_soc_codec *codec) +{ + struct clearwater_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int i, ret; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_spk(codec); + arizona_init_gpio(codec); + arizona_init_mono(codec); + arizona_init_input(codec); + + for (i = 0; i < CLEARWATER_NUM_ADSP; ++i) { + ret = wm_adsp2_codec_probe(&priv->core.adsp[i], codec); + if (ret) + return ret; + } + + ret = snd_soc_add_codec_controls(codec, + arizona_adsp2v2_rate_controls, + CLEARWATER_NUM_ADSP); + if (ret) + return ret; + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + mutex_unlock(&codec->card->dapm_mutex); + + priv->core.arizona->dapm = &codec->dapm; + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", + clearwater_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_enable_pin(&codec->dapm, "DRC2 Signal Activity"); + mutex_unlock(&codec->card->dapm_mutex); + + ret = regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC2 IRQ for DSP: %d\n", + ret); + return ret; + } + + return 0; +} + +static int clearwater_codec_remove(struct snd_soc_codec *codec) +{ + struct clearwater_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int i; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + CLEARWATER_DRC2_SIG_DET_EINT2); + + for (i = 0; i < CLEARWATER_NUM_ADSP; ++i) + wm_adsp2_codec_remove(&priv->core.adsp[i], codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define CLEARWATER_DIG_VU 0x0200 + +static unsigned int clearwater_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, + ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, + ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, + ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, + ARIZONA_DAC_DIGITAL_VOLUME_6L, + ARIZONA_DAC_DIGITAL_VOLUME_6R, +}; + +static struct snd_soc_codec_driver soc_codec_dev_clearwater = { + .probe = clearwater_codec_probe, + .remove = clearwater_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = clearwater_set_fll, + + .controls = clearwater_snd_controls, + .num_controls = ARRAY_SIZE(clearwater_snd_controls), + .dapm_widgets = clearwater_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(clearwater_dapm_widgets), + .dapm_routes = clearwater_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(clearwater_dapm_routes), +}; + +static struct snd_compr_ops clearwater_compr_ops = { + .open = clearwater_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = clearwater_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver clearwater_compr_platform = { + .compr_ops = &clearwater_compr_ops, +}; + +static void clearwater_init_compr_info(struct clearwater_priv *clearwater) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(clearwater->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(clearwater->compr_info); ++i) { + clearwater->compr_info[i].priv = clearwater; + + clearwater->compr_info[i].dai_name = + compr_dai_mapping[i].dai_name; + + dsp = &clearwater->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &clearwater->compr_info[i].adsp_compr); + + mutex_init(&clearwater->compr_info[i].trig_lock); + } +} + +static void clearwater_destroy_compr_info(struct clearwater_priv *clearwater) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(clearwater->compr_info); ++i) + wm_adsp_compr_destroy(&clearwater->compr_info[i].adsp_compr); +} + +static int clearwater_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct clearwater_priv *clearwater; + int i, ret; + + BUILD_BUG_ON(ARRAY_SIZE(clearwater_dai) > ARIZONA_MAX_DAI); + + clearwater = devm_kzalloc(&pdev->dev, sizeof(struct clearwater_priv), + GFP_KERNEL); + if (clearwater == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, clearwater); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&clearwater->fw_lock); + + clearwater->core.arizona = arizona; + clearwater->core.num_inputs = 8; + + for (i = 0; i < CLEARWATER_NUM_ADSP; i++) { + clearwater->core.adsp[i].part = "clearwater"; + if (arizona->pdata.rev_specific_fw) + clearwater->core.adsp[i].part_rev = 'a' + arizona->rev; + clearwater->core.adsp[i].num = i + 1; + clearwater->core.adsp[i].type = WMFW_ADSP2; + clearwater->core.adsp[i].rev = 1; + clearwater->core.adsp[i].dev = arizona->dev; + clearwater->core.adsp[i].regmap = arizona->regmap_32bit; + + clearwater->core.adsp[i].base = wm_adsp2_control_bases[i]; + clearwater->core.adsp[i].mem = clearwater_dsp_regions[i]; + clearwater->core.adsp[i].num_mems + = ARRAY_SIZE(clearwater_dsp1_regions); + + if (arizona->pdata.num_fw_defs[i]) { + clearwater->core.adsp[i].firmwares + = arizona->pdata.fw_defs[i]; + + clearwater->core.adsp[i].num_firmwares + = arizona->pdata.num_fw_defs[i]; + } + + clearwater->core.adsp[i].rate_put_cb = + clearwater_adsp_rate_put_cb; + + clearwater->core.adsp[i].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&clearwater->core.adsp[i], &clearwater->fw_lock); + if (ret != 0) + return ret; + } + + clearwater_init_compr_info(clearwater); + + for (i = 0; i < ARRAY_SIZE(clearwater->fll); i++) { + clearwater->fll[i].vco_mult = 3; + clearwater->fll[i].min_outdiv = 3; + clearwater->fll[i].max_outdiv = 3; + } + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &clearwater->fll[0]); + arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1, + ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, + &clearwater->fll[1]); + arizona_init_fll(arizona, 3, ARIZONA_FLL3_CONTROL_1 - 1, + ARIZONA_IRQ_FLL3_LOCK, ARIZONA_IRQ_FLL3_CLOCK_OK, + &clearwater->fll[2]); + + for (i = 0; i < ARRAY_SIZE(clearwater_dai); i++) + arizona_init_dai(&clearwater->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(clearwater_digital_vu); i++) + regmap_update_bits(arizona->regmap, clearwater_digital_vu[i], + CLEARWATER_DIG_VU, CLEARWATER_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = snd_soc_register_platform(&pdev->dev, &clearwater_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_clearwater, + clearwater_dai, ARRAY_SIZE(clearwater_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + clearwater_destroy_compr_info(clearwater); + mutex_destroy(&clearwater->fw_lock); + + return ret; +} + +static int clearwater_remove(struct platform_device *pdev) +{ + struct clearwater_priv *clearwater = platform_get_drvdata(pdev); + int i; + + snd_soc_unregister_platform(&pdev->dev); + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + clearwater_destroy_compr_info(clearwater); + + for (i = 0; i < CLEARWATER_NUM_ADSP; i++) + wm_adsp2_remove(&clearwater->core.adsp[i]); + + mutex_destroy(&clearwater->fw_lock); + + return 0; +} + +static struct platform_driver clearwater_codec_driver = { + .driver = { + .name = "clearwater-codec", + .owner = THIS_MODULE, + }, + .probe = clearwater_probe, + .remove = clearwater_remove, +}; + +module_platform_driver(clearwater_codec_driver); + +MODULE_DESCRIPTION("ASoC CLEARWATER driver"); +MODULE_AUTHOR("Nariman Poushin "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:clearwater-codec"); diff --git a/sound/soc/codecs/clearwater.h b/sound/soc/codecs/clearwater.h new file mode 100644 index 00000000000..6d60e67fd79 --- /dev/null +++ b/sound/soc/codecs/clearwater.h @@ -0,0 +1,25 @@ +/* + * clearwater.h -- ALSA SoC Audio driver for Florida-class codecs + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _CLEARWATER_H +#define _CLEARWATER_H + +#include "arizona.h" + +#define CLEARWATER_FLL1 1 +#define CLEARWATER_FLL2 2 +#define CLEARWATER_FLL1_REFCLK 3 +#define CLEARWATER_FLL2_REFCLK 4 +#define CLEARWATER_FLL3 5 +#define CLEARWATER_FLL3_REFCLK 6 + +#endif diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c index b99af6362de..c6f37cbfd85 100644 --- a/sound/soc/codecs/cs42l52.c +++ b/sound/soc/codecs/cs42l52.c @@ -1175,7 +1175,7 @@ static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = { }; /* Current and threshold powerup sequence Pg37 */ -static const struct reg_default cs42l52_threshold_patch[] = { +static const struct reg_sequence cs42l52_threshold_patch[] = { { 0x00, 0x99 }, { 0x3E, 0xBA }, diff --git a/sound/soc/codecs/cs47l15.c b/sound/soc/codecs/cs47l15.c new file mode 100644 index 00000000000..79fe93eb2f1 --- /dev/null +++ b/sound/soc/codecs/cs47l15.c @@ -0,0 +1,2055 @@ +/* + * cs47l15.c -- ALSA SoC Audio driver for CS47L15 + * + * Copyright 2016 Cirrus Logic + * + * Author: Jaswinder Jassal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "wm_adsp.h" +#include "cs47l15.h" + +#define CS47L15_NUM_ADSP 1 + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU + * are counted as one DAI + */ +#define CS47L15_NUM_COMPR_DAI 1 + +#define CS47L15_FRF_COEFFICIENT_LEN 4 + +#define CS47L15_FLL_COUNT 2 + +/* Mid-mode registers */ +#define CS47L15_ADC_INT_BIAS_MASK 0x3800 +#define CS47L15_ADC_INT_BIAS_SHIFT 11 +#define CS47L15_PGA_BIAS_SEL_MASK 0x03 +#define CS47L15_PGA_BIAS_SEL_SHIFT 0 + +/* 2 mixer inputs with a stride of n in the register address */ +#define CS47L15_MIXER_INPUTS_2_N(_reg, n) \ + (_reg), \ + (_reg) + (1 * (n)) + +/* 4 mixer inputs with a stride of n in the register address */ +#define CS47L15_MIXER_INPUTS_4_N(_reg, n) \ + CS47L15_MIXER_INPUTS_2_N(_reg, n), \ + CS47L15_MIXER_INPUTS_2_N(_reg + (2 * n), n) + +#define CS47L15_DSP_MIXER_INPUTS(_reg) \ + CS47L15_MIXER_INPUTS_4_N(_reg, 2), \ + CS47L15_MIXER_INPUTS_4_N(_reg + 8, 2), \ + CS47L15_MIXER_INPUTS_4_N(_reg + 16, 8), \ + CS47L15_MIXER_INPUTS_2_N(_reg + 48, 8) + +static const int cs47l15_fx_inputs[] = { + CS47L15_MIXER_INPUTS_4_N(ARIZONA_EQ1MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_EQ2MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_EQ3MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_EQ4MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_DRC1LMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_DRC1RMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_DRC2LMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_DRC2RMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_HPLP1MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_HPLP2MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_HPLP3MIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_HPLP4MIX_INPUT_1_SOURCE, 2), +}; + +static const int cs47l15_isrc1_fsl_inputs[] = { + CS47L15_MIXER_INPUTS_4_N(ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int cs47l15_isrc1_fsh_inputs[] = { + CS47L15_MIXER_INPUTS_4_N(ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int cs47l15_isrc2_fsl_inputs[] = { + CS47L15_MIXER_INPUTS_4_N(ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int cs47l15_isrc2_fsh_inputs[] = { + CS47L15_MIXER_INPUTS_4_N(ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int cs47l15_out_inputs[] = { + CS47L15_MIXER_INPUTS_4_N(ARIZONA_OUT1LMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_OUT1RMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_OUT4LMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_OUT5LMIX_INPUT_1_SOURCE, 2), + CS47L15_MIXER_INPUTS_4_N(ARIZONA_OUT5RMIX_INPUT_1_SOURCE, 2), +}; + +static const int cs47l15_spd1_inputs[] = { + CS47L15_MIXER_INPUTS_2_N(ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE, 8), +}; + +static const int cs47l15_dsp1_inputs[] = { + CS47L15_DSP_MIXER_INPUTS(ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +}; + +static int cs47l15_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define CS47L15_RATE_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_get_enum_double, .put = cs47l15_rate_put, \ + .private_value = (unsigned long)&xenum } + +struct cs47l15_priv; + +struct cs47l15_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; + struct cs47l15_priv *priv; +}; + +struct cs47l15_priv { + struct arizona_priv core; + struct arizona_fll fll[CS47L15_FLL_COUNT]; + struct cs47l15_compr compr_info[CS47L15_NUM_COMPR_DAI]; + + bool trig; + struct mutex trig_lock; + struct mutex fw_lock; + bool in1_lp_mode; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[CS47L15_NUM_COMPR_DAI] = { + { + .dai_name = "cs47l15-dsp-trace", + .adsp_num = 0, + }, +}; + +static const struct wm_adsp_region cs47l15_dsp1_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x080000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, +}; + +static const char * const cs47l15_inmux_texts[] = { + "A", + "B", +}; + +static int cs47l15_in1mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = cs47l15->core.arizona; + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int mux, inmode; + unsigned int mode_val, src_val; + bool changed = false; + int ret; + + mux = ucontrol->value.enumerated.item[0]; + if (mux > 1) + return -EINVAL; + + /* L and R registers have same shift and mask */ + inmode = arizona->pdata.inmode[2 * mux]; + src_val = mux << ARIZONA_IN1L_SRC_SHIFT; + if (inmode & ARIZONA_INMODE_SE) + src_val |= 1 << ARIZONA_IN1L_SRC_SE_SHIFT; + + switch (arizona->pdata.inmode[0]) { + case ARIZONA_INMODE_DMIC: + if (mux) + mode_val = 0; /* B always analogue */ + else + mode_val = 1 << ARIZONA_IN1_MODE_SHIFT; + + ret = snd_soc_update_bits(codec, + ARIZONA_IN1L_CONTROL, + ARIZONA_IN1_MODE_MASK, + mode_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + /* IN1A is digital so L and R must change together */ + /* src_val setting same for both registers */ + ret = snd_soc_update_bits(codec, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_MASK | + ARIZONA_IN1L_SRC_SE_MASK, + src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + ret = snd_soc_update_bits(codec, + ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_MASK | + ARIZONA_IN1R_SRC_SE_MASK, + src_val); + + if (ret < 0) + return ret; + else if (ret) + changed = true; + break; + default: + /* both analogue */ + ret = snd_soc_update_bits(codec, + e->reg, + ARIZONA_IN1L_SRC_MASK | + ARIZONA_IN1L_SRC_SE_MASK, + src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + break; + } + + if (changed) + return snd_soc_dapm_mux_update_power(widget, kcontrol, + mux, e); + else + return 0; +} + +static const SOC_ENUM_SINGLE_DECL(cs47l15_in1muxl_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_SHIFT, + cs47l15_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(cs47l15_in1muxr_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_SHIFT, + cs47l15_inmux_texts); + +static const struct snd_kcontrol_new cs47l15_in1mux[2] = { + SOC_DAPM_ENUM_EXT("IN1L Mux", cs47l15_in1muxl_enum, + snd_soc_dapm_get_enum_double, cs47l15_in1mux_put), + SOC_DAPM_ENUM_EXT("IN1R Mux", cs47l15_in1muxr_enum, + snd_soc_dapm_get_enum_double, cs47l15_in1mux_put), +}; + +static const char * const cs47l15_outdemux_texts[] = { + "HPOUT", + "EPOUT", +}; + +static int cs47l15_put_demux(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct snd_soc_card *card = codec->card; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int ep_sel, mux, change; + unsigned int mask; + int ret, demux_change_ret; + bool restore_out = true, out_mono; + + if (ucontrol->value.enumerated.item[0] > e->max - 1) + return -EINVAL; + mux = ucontrol->value.enumerated.item[0]; + ep_sel = mux << e->shift_l; + mask = e->mask << e->shift_l; + + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + change = snd_soc_test_bits(codec, e->reg, mask, ep_sel); + /* if no change is required, skip */ + if (!change) + goto end; + + /* EP_SEL and OUT1_MONO should not be modified while HP or EP driver + * is enabled + */ + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret) + dev_warn(arizona->dev, + "Failed to disable outputs: %d\n", ret); + + usleep_range(2000, 3000); /* wait for wseq to complete */ + + /* [1] if HP detection clamp is applied while switching to HPOUT, OUT1 + * should remain disabled + */ + if (!ep_sel && (arizona->hpdet_clamp || + (arizona->hp_impedance_x100 <= + OHM_TO_HOHM(arizona->pdata.hpdet_short_circuit_imp)))) + restore_out = false; + + /* change demux setting */ + demux_change_ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_EP_SEL, ep_sel); + if (demux_change_ret) { + dev_err(arizona->dev, "Failed to set EP_SEL: %d\n", + demux_change_ret); + } else { /* provided the switch to HP/EP was successful, update output + mode accordingly */ + /* when switching to stereo headphone */ + if (!ep_sel && !arizona->pdata.out_mono[0]) + out_mono = false; + /* when switching to mono headphone, or any earpiece */ + else + out_mono = true; + + ret = arizona_set_output_mode(codec, 1, out_mono); + if (ret < 0) + dev_warn(arizona->dev, + "Failed to set output mode: %d\n", ret); + } + + /* restore outputs to the desired state, or keep them disabled provided + * condition [1] arose + */ + if (restore_out) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, + arizona->hp_ena); + if (ret) { + dev_warn(arizona->dev, + "Failed to restore outputs: %d\n", ret); + } else { + /* wait for wseq */ + if (arizona->hp_ena) + msleep(34); /* enable delay */ + else + usleep_range(2000, 3000); /* disable delay */ + } + } + +end: + mutex_unlock(&card->dapm_mutex); + + return snd_soc_dapm_put_enum_virt(kcontrol, ucontrol); +} + +static const SOC_ENUM_SINGLE_DECL(cs47l15_outdemux_enum, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_EP_SEL_SHIFT, + cs47l15_outdemux_texts); + +static const struct snd_kcontrol_new cs47l15_outdemux = + SOC_DAPM_ENUM_EXT("HPOUT1 Demux", cs47l15_outdemux_enum, + snd_soc_dapm_get_enum_double, cs47l15_put_demux); + +/* Allow the worst case number of sources (FX Rate currently) */ +static unsigned int mixer_sources_cache[ARRAY_SIZE(cs47l15_fx_inputs)]; + +static int cs47l15_get_sources(unsigned int reg, + const int **cur_sources, int *lim) +{ + int ret = 0; + + switch (reg) { + case ARIZONA_FX_CTRL1: + *cur_sources = cs47l15_fx_inputs; + *lim = ARRAY_SIZE(cs47l15_fx_inputs); + break; + case ARIZONA_ISRC_1_CTRL_1: + *cur_sources = cs47l15_isrc1_fsh_inputs; + *lim = ARRAY_SIZE(cs47l15_isrc1_fsh_inputs); + break; + case ARIZONA_ISRC_1_CTRL_2: + *cur_sources = cs47l15_isrc1_fsl_inputs; + *lim = ARRAY_SIZE(cs47l15_isrc1_fsl_inputs); + break; + case ARIZONA_ISRC_2_CTRL_1: + *cur_sources = cs47l15_isrc2_fsh_inputs; + *lim = ARRAY_SIZE(cs47l15_isrc2_fsh_inputs); + break; + case ARIZONA_ISRC_2_CTRL_2: + *cur_sources = cs47l15_isrc2_fsl_inputs; + *lim = ARRAY_SIZE(cs47l15_isrc2_fsl_inputs); + break; + case ARIZONA_OUTPUT_RATE_1: + *cur_sources = cs47l15_out_inputs; + *lim = ARRAY_SIZE(cs47l15_out_inputs); + break; + case ARIZONA_SPD1_TX_CONTROL: + *cur_sources = cs47l15_spd1_inputs; + *lim = ARRAY_SIZE(cs47l15_spd1_inputs); + break; + case CLEARWATER_DSP1_CONFIG: + *cur_sources = cs47l15_dsp1_inputs; + *lim = ARRAY_SIZE(cs47l15_dsp1_inputs); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int cs47l15_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret, err; + int lim; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &cs47l15->core; + struct arizona *arizona = priv->arizona; + + const int *cur_sources; + + unsigned int val, cur; + unsigned int mask; + + if (ucontrol->value.enumerated.item[0] > e->max - 1) + return -EINVAL; + + val = e->values[ucontrol->value.enumerated.item[0]] << e->shift_l; + mask = e->mask << e->shift_l; + + ret = regmap_read(arizona->regmap, e->reg, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current reg: %d\n", ret); + return ret; + } + + if ((cur & mask) == (val & mask)) + return 0; + + ret = cs47l15_get_sources((int)e->reg, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + e->reg, + ret); + return ret; + } + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + /* Apply the rate through the original callback */ + clearwater_spin_sysclk(arizona); + ret = snd_soc_update_bits_locked(codec, e->reg, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int cs47l15_adsp_rate_put_cb(struct wm_adsp *adsp, + unsigned int mask, + unsigned int val) +{ + int ret, err; + int lim; + const int *cur_sources; + struct arizona *arizona = dev_get_drvdata(adsp->dev); + unsigned int cur; + + ret = regmap_read(adsp->regmap, adsp->base, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current: %d\n", ret); + return ret; + } + + if ((val & mask) == (cur & mask)) + return 0; + + ret = cs47l15_get_sources(adsp->base, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + adsp->base, + ret); + return ret; + } + + dev_dbg(arizona->dev, "%s for DSP%d\n", __func__, adsp->num); + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + clearwater_spin_sysclk(arizona); + /* Apply the rate */ + ret = regmap_update_bits(adsp->regmap, adsp->base, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int cs47l15_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &cs47l15->core; + struct arizona *arizona = priv->arizona; + + clearwater_spin_sysclk(arizona); + + return 0; +} + +static int cs47l15_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &cs47l15->core; + struct arizona *arizona = priv->arizona; + unsigned int freq; + int ret; + + ret = regmap_read(arizona->regmap, CLEARWATER_DSP_CLOCK_2, &freq); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read CLEARWATER_DSP_CLOCK_2: %d\n", ret); + return ret; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + mutex_lock(&cs47l15->trig_lock); + cs47l15->trig = false; + mutex_unlock(&cs47l15->trig_lock); + break; + default: + break; + } + + return wm_adsp2_early_event(w, kcontrol, event, freq); +} + +static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -12000, 600, 0); + +#define CS47L15_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) + +static int cs47l15_in1_adc_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = cs47l15->in1_lp_mode ? 1 : 0; + + return 0; +} + +static int cs47l15_in1_adc_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + + switch (ucontrol->value.integer.value[0]) { + case 0: + /* Set IN1 to normal mode */ + snd_soc_update_bits(codec, ARIZONA_DMIC1L_CONTROL, + CLEARWATER_IN1_OSR_MASK, + 5 << CLEARWATER_IN1_OSR_SHIFT); + snd_soc_update_bits(codec, CS47L15_ADC_INT_BIAS, + CS47L15_ADC_INT_BIAS_MASK, + 4 << CS47L15_ADC_INT_BIAS_SHIFT); + snd_soc_update_bits(codec, CS47L15_PGA_BIAS_SEL, + CS47L15_PGA_BIAS_SEL_MASK, + 0); + cs47l15->in1_lp_mode = false; + break; + default: + /* Set IN1 to LP mode */ + snd_soc_update_bits(codec, ARIZONA_DMIC1L_CONTROL, + CLEARWATER_IN1_OSR_MASK, + 4 << CLEARWATER_IN1_OSR_SHIFT); + snd_soc_update_bits(codec, CS47L15_ADC_INT_BIAS, + CS47L15_ADC_INT_BIAS_MASK, + 1 << CS47L15_ADC_INT_BIAS_SHIFT); + snd_soc_update_bits(codec, CS47L15_PGA_BIAS_SEL, + CS47L15_PGA_BIAS_SEL_MASK, + 3 << CS47L15_PGA_BIAS_SEL_SHIFT); + cs47l15->in1_lp_mode = true; + break; + } + + return 0; +} + +static const struct snd_kcontrol_new cs47l15_snd_controls[] = { +SOC_VALUE_ENUM("IN1 OSR", clearwater_in_dmic_osr[0]), +SOC_VALUE_ENUM("IN2 OSR", clearwater_in_dmic_osr[1]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +SND_SOC_BYTES("FRF COEFF 1L", CLEARWATER_FRF_COEFFICIENT_1L_1, + CS47L15_FRF_COEFFICIENT_LEN), +SND_SOC_BYTES("FRF COEFF 1R", CLEARWATER_FRF_COEFFICIENT_1R_1, + CS47L15_FRF_COEFFICIENT_LEN), +SND_SOC_BYTES("FRF COEFF 4L", CLEARWATER_FRF_COEFFICIENT_4L_1, + CS47L15_FRF_COEFFICIENT_LEN), +SND_SOC_BYTES("FRF COEFF 5L", CLEARWATER_FRF_COEFFICIENT_5L_1, + CS47L15_FRF_COEFFICIENT_LEN), +SND_SOC_BYTES("FRF COEFF 5R", CLEARWATER_FRF_COEFFICIENT_5R_1, + CS47L15_FRF_COEFFICIENT_LEN), + +SND_SOC_BYTES("DAC COMP 1", CLEARWATER_DAC_COMP_1, 1), +SND_SOC_BYTES("DAC COMP 2", CLEARWATER_DAC_COMP_2, 1), + +ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), +SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), +SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), +SND_SOC_BYTES_MASK("DRC2", CLEARWATER_DRC2_CTRL1, 5, + ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +SND_SOC_BYTES("LHPF1 Coefficients", ARIZONA_HPLPF1_2, 1), +SND_SOC_BYTES("LHPF2 Coefficients", ARIZONA_HPLPF2_2, 1), +SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1), +SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +SOC_VALUE_ENUM("Sample Rate 2", arizona_sample_rate[0]), +SOC_VALUE_ENUM("Sample Rate 3", arizona_sample_rate[1]), + +CS47L15_RATE_ENUM("FX Rate", arizona_fx_rate), + +CS47L15_RATE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +CS47L15_RATE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +CS47L15_RATE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +CS47L15_RATE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), + +ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), + +SOC_SINGLE_TLV("Noise Generator Volume", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv), + +ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), + +SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_SHIFT, 1, 0), + +SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L, + ARIZONA_OUT5_OSR_SHIFT, 1, 0), + +SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), + +SOC_SINGLE("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_SINGLE_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_EXT("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE1L_ENA_SHIFT, VEGAS_DRE1R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), +SOC_DOUBLE("HPOUT1 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT1L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT1R_THR1_ENA_SHIFT, 1, 0), + +SOC_SINGLE("Speaker THR1 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT4L_THR1_ENA_SHIFT, 1, 0), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +CS47L15_RATE_ENUM("SPDIF Rate", arizona_spdif_rate), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +CS47L15_RATE_ENUM("Output Rate 1", arizona_output_rate), + +SOC_ENUM_EXT("IN1L Rate", moon_input_rate[0], + snd_soc_get_enum_double, moon_in_rate_put), +SOC_ENUM_EXT("IN1R Rate", moon_input_rate[1], + snd_soc_get_enum_double, moon_in_rate_put), + +SOC_SINGLE_BOOL_EXT("IN1 LP Mode Switch", 0, + cs47l15_in1_adc_get, cs47l15_in1_adc_put), + +SOC_ENUM_EXT("IN2L Rate", moon_input_rate[2], + snd_soc_get_enum_double, moon_in_rate_put), +SOC_ENUM_EXT("IN2R Rate", moon_input_rate[3], + snd_soc_get_enum_double, moon_in_rate_put), + +CS47L15_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +CS47L15_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), + +CS47L15_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), + +CS47L15_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +CS47L15_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_GAINMUX_CONTROLS("SPDIFTX1", ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SPDIFTX2", ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE), +}; + +CLEARWATER_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(SPD1TX1, ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(SPD1TX2, ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE); + +static const char * const cs47l15_dsp_output_texts[] = { + "None", + "DSP1", +}; + +static const struct soc_enum cs47l15_dsp_output_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(cs47l15_dsp_output_texts), + cs47l15_dsp_output_texts); + +static const struct snd_kcontrol_new cs47l15_dsp_output_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", cs47l15_dsp_output_enum), +}; + +static const char * const cs47l15_aec_loopback_texts[] = { + "HPOUT1L", "HPOUT1R", "SPKOUTL", "SPKDAT1L", "SPKDAT1R", +}; + +static const unsigned int cs47l15_aec_loopback_values[] = { + 0, 1, 6, 8, 9, +}; + +static const struct soc_enum cs47l15_aec_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(cs47l15_aec_loopback_texts), + cs47l15_aec_loopback_texts, + cs47l15_aec_loopback_values); + +static const struct snd_kcontrol_new cs47l15_aec_loopback_mux = + SOC_DAPM_VALUE_ENUM("AEC Loopback", cs47l15_aec_loopback); + +static const struct snd_soc_dapm_widget cs47l15_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, + 0, cs47l15_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("DSPCLK", CLEARWATER_DSP_CLOCK_1, 6, + 0, NULL, 0), + +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), + +SND_SOC_DAPM_INPUT("IN1AL"), +SND_SOC_DAPM_INPUT("IN1BL"), +SND_SOC_DAPM_INPUT("IN1AR"), +SND_SOC_DAPM_INPUT("IN1BR"), +SND_SOC_DAPM_INPUT("IN2L"), +SND_SOC_DAPM_INPUT("IN2R"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &cs47l15_in1mux[0]), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &cs47l15_in1mux[1]), + +SND_SOC_DAPM_DEMUX("HPOUT1 Demux", SND_SOC_NOPM, 0, 0, &cs47l15_outdemux), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("MICBIAS1A", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1A_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1B", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1B_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1C", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1C_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_PGA("SPD1TX1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL1_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("SPD1TX2", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL2_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_OUT_DRV("SPD1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_ENA_SHIFT, 0, NULL, 0), + +/* mux_in widgets : arranged in the order of sources + specified in ARIZONA_MIXER_INPUT_ROUTES */ + +SND_SOC_DAPM_PGA("Noise Generator", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &cs47l15_aec_loopback_mux), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0), + +WM_ADSP2("DSP1", 0, cs47l15_adsp_power_ev), + +ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), +ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), +ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"), +ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), + +ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), +ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), +ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"), +ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"), + +ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"), + +ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"), +ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), +ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"), +ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"), +ARIZONA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"), + +ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), + +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &cs47l15_dsp_output_mux[0]), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), +ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"), +ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), +ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"), +ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"), + +SND_SOC_DAPM_OUTPUT("HPOUT1L"), +SND_SOC_DAPM_OUTPUT("HPOUT1R"), + +SND_SOC_DAPM_OUTPUT("EPOUTP"), +SND_SOC_DAPM_OUTPUT("EPOUTN"), + +SND_SOC_DAPM_OUTPUT("SPKOUTLN"), +SND_SOC_DAPM_OUTPUT("SPKOUTLP"), + +SND_SOC_DAPM_OUTPUT("SPKDAT1L"), +SND_SOC_DAPM_OUTPUT("SPKDAT1R"), +SND_SOC_DAPM_OUTPUT("SPDIF"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF2RX3", "AIF2RX3" }, \ + { name, "AIF2RX4", "AIF2RX4" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2DEC3", "ISRC2DEC3" }, \ + { name, "ISRC2DEC4", "ISRC2DEC4" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC2INT3", "ISRC2INT3" }, \ + { name, "ISRC2INT4", "ISRC2INT4" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" } + +static const struct snd_soc_dapm_route cs47l15_dapm_routes[] = { + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + + { "OUT4L", NULL, "SPKVDD" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT4L", NULL, "SYSCLK" }, + { "OUT5L", NULL, "SYSCLK" }, + { "OUT5R", NULL, "SYSCLK" }, + + { "SPD1", NULL, "SYSCLK" }, + { "SPD1", NULL, "SPD1TX1" }, + { "SPD1", NULL, "SPD1TX2" }, + + { "IN1AL", NULL, "SYSCLK" }, + { "IN1BL", NULL, "SYSCLK" }, + { "IN1AR", NULL, "SYSCLK" }, + { "IN1BR", NULL, "SYSCLK" }, + + { "IN2L", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, + + { "DSP1", NULL, "DSPCLK"}, + + { "MICBIAS1", NULL, "MICVDD" }, + + { "MICBIAS1A", NULL, "MICBIAS1" }, + { "MICBIAS1B", NULL, "MICBIAS1" }, + { "MICBIAS1C", NULL, "MICBIAS1" }, + + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Noise Generator", NULL, "NOISE" }, + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + { "AIF2 Capture", NULL, "AIF2TX3" }, + { "AIF2 Capture", NULL, "AIF2TX4" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + { "AIF2RX3", NULL, "AIF2 Playback" }, + { "AIF2RX4", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP1" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, + + { "IN1L Mux", "A", "IN1AL" }, + { "IN1L Mux", "B", "IN1BL" }, + { "IN1R Mux", "A", "IN1AR" }, + { "IN1R Mux", "B", "IN1BR" }, + + { "IN1L PGA", NULL, "IN1L Mux" }, + { "IN1R PGA", NULL, "IN1R Mux" }, + + { "IN2L PGA", NULL, "IN2L" }, + { "IN2R PGA", NULL, "IN2R" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), + ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), + + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"), + + ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"), + ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"), + ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"), + ARIZONA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"), + + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), + ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), + ARIZONA_MIXER_ROUTES("EQ3", "EQ3"), + ARIZONA_MIXER_ROUTES("EQ4", "EQ4"), + + ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), + ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), + ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_DSP_ROUTES("DSP1"), + + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP1", "DSP1" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"), + ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + { "AEC Loopback", "HPOUT1L", "OUT1L" }, + { "AEC Loopback", "HPOUT1R", "OUT1R" }, + { "HPOUT1 Demux", NULL, "OUT1L" }, + { "HPOUT1 Demux", NULL, "OUT1R" }, + + + { "HPOUT1L", "HPOUT", "HPOUT1 Demux" }, + { "HPOUT1R", "HPOUT", "HPOUT1 Demux" }, + { "EPOUTP", "EPOUT", "HPOUT1 Demux" }, + { "EPOUTN", "EPOUT", "HPOUT1 Demux" }, + + { "AEC Loopback", "SPKOUTL", "OUT4L" }, + { "SPKOUTLN", NULL, "OUT4L" }, + { "SPKOUTLP", NULL, "OUT4L" }, + + { "AEC Loopback", "SPKDAT1L", "OUT5L" }, + { "AEC Loopback", "SPKDAT1R", "OUT5R" }, + { "SPKDAT1L", NULL, "OUT5L" }, + { "SPKDAT1R", NULL, "OUT5R" }, + + { "SPDIF", NULL, "SPD1" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, + { "DRC2 Signal Activity", NULL, "DRC2L" }, + { "DRC2 Signal Activity", NULL, "DRC2R" }, +}; + +static int cs47l15_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case CS47L15_FLL1: + return arizona_set_fll(&cs47l15->fll[0], source, Fref, Fout); + case CS47L15_FLLAO: + return arizona_set_fll_ao(&cs47l15->fll[1], source, Fref, Fout); + case CS47L15_FLL1_REFCLK: + return arizona_set_fll_refclk(&cs47l15->fll[0], source, Fref, + Fout); + default: + return -EINVAL; + } +} + +#define CS47L15_RATES SNDRV_PCM_RATE_KNOT + +#define CS47L15_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver cs47l15_dai[] = { + { + .name = "cs47l15-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "cs47l15-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "cs47l15-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "cs47l15-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 2, + .channels_max = 6, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "cs47l15-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 2, + .channels_max = 6, + .rates = CS47L15_RATES, + .formats = CS47L15_FORMATS, + }, + }, +}; + +static irqreturn_t cs47l15_adsp_bus_error(int irq, void *data) +{ + struct wm_adsp *adsp = (struct wm_adsp *)data; + return wm_adsp2_bus_error(adsp); +} + +static void cs47l15_compr_irq(struct cs47l15_priv *cs47l15, + struct cs47l15_compr *compr) +{ + bool trigger = false; + int ret; + + ret = wm_adsp_compr_irq(&compr->adsp_compr, &trigger); + if (ret < 0) + return; +} + +static irqreturn_t cs47l15_adsp2_irq(int irq, void *data) +{ + struct cs47l15_priv *cs47l15 = data; + struct arizona *arizona = cs47l15->core.arizona; + struct cs47l15_compr *compr; + int i; + + for (i = 0; i < ARRAY_SIZE(cs47l15->compr_info); ++i) { + if (!cs47l15->compr_info[i].adsp_compr.dsp->running) + continue; + + compr = &cs47l15->compr_info[i]; + cs47l15_compr_irq(cs47l15, compr); + } + + if (arizona->pdata.ez2ctrl_trigger) { + mutex_lock(&cs47l15->trig_lock); + if (!cs47l15->trig) { + cs47l15->trig = true; + + if (wm_adsp_fw_has_voice_trig(&cs47l15->core.adsp[0])) + arizona->pdata.ez2ctrl_trigger(); + } + mutex_unlock(&cs47l15->trig_lock); + } + return IRQ_HANDLED; +} + +static struct cs47l15_compr *cs47l15_get_compr(struct snd_soc_pcm_runtime *rtd, + struct cs47l15_priv *cs47l15) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs47l15->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + cs47l15->compr_info[i].dai_name) == 0) + return &cs47l15->compr_info[i]; + } + + return NULL; +} + +static int cs47l15_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct cs47l15_priv *cs47l15 = snd_soc_codec_get_drvdata(rtd->codec); + struct cs47l15_compr *compr; + + compr = cs47l15_get_compr(rtd, cs47l15); + if (!compr) { + dev_err(cs47l15->core.arizona->dev, + "No compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int cs47l15_codec_probe(struct snd_soc_codec *codec) +{ + struct cs47l15_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int ret; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_spk(codec); + arizona_init_gpio(codec); + arizona_init_mono(codec); + arizona_init_input(codec); + + ret = wm_adsp2_codec_probe(&priv->core.adsp[0], codec); + if (ret) + return ret; + + ret = snd_soc_add_codec_controls(codec, + arizona_adsp2v2_rate_controls, 1); + if (ret != 0) + return ret; + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + mutex_unlock(&codec->card->dapm_mutex); + + priv->core.arizona->dapm = &codec->dapm; + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", cs47l15_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + ret = arizona_request_irq(arizona, + MOON_IRQ_DSP1_BUS_ERROR, + "ADSP2 bus error", + cs47l15_adsp_bus_error, + &priv->core.adsp[0]); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to request DSP Lock region IRQ: %d\n", + ret); + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + return ret; + } + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_enable_pin(&codec->dapm, "DRC2 Signal Activity"); + mutex_unlock(&codec->card->dapm_mutex); + + ret = regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC2 IRQ for DSP: %d\n", + ret); + goto err_drc; + } + + return 0; + +err_drc: + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + arizona_free_irq(arizona, MOON_IRQ_DSP1_BUS_ERROR, + &priv->core.adsp[0]); + return ret; +} + +static int cs47l15_codec_remove(struct snd_soc_codec *codec) +{ + struct cs47l15_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + arizona_free_irq(arizona, MOON_IRQ_DSP1_BUS_ERROR, + &priv->core.adsp[0]); + regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + CLEARWATER_DRC2_SIG_DET_EINT2); + + wm_adsp2_codec_remove(&priv->core.adsp[0], codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define CS47L15_DIG_VU 0x0200 + +static unsigned int cs47l15_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, +}; + +static struct snd_soc_codec_driver soc_codec_dev_cs47l15 = { + .probe = cs47l15_codec_probe, + .remove = cs47l15_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = cs47l15_set_fll, + + .controls = cs47l15_snd_controls, + .num_controls = ARRAY_SIZE(cs47l15_snd_controls), + .dapm_widgets = cs47l15_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(cs47l15_dapm_widgets), + .dapm_routes = cs47l15_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(cs47l15_dapm_routes), +}; + +static struct snd_compr_ops cs47l15_compr_ops = { + .open = cs47l15_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = wm_adsp_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver cs47l15_compr_platform = { + .compr_ops = &cs47l15_compr_ops, +}; + +static void cs47l15_init_compr_info(struct cs47l15_priv *cs47l15) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(cs47l15->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(cs47l15->compr_info); ++i) { + cs47l15->compr_info[i].priv = cs47l15; + + cs47l15->compr_info[i].dai_name = + compr_dai_mapping[i].dai_name; + + dsp = &cs47l15->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &cs47l15->compr_info[i].adsp_compr); + } +} + +static void cs47l15_destroy_compr_info(struct cs47l15_priv *cs47l15) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(cs47l15->compr_info); ++i) + wm_adsp_compr_destroy(&cs47l15->compr_info[i].adsp_compr); +} + +static int cs47l15_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct cs47l15_priv *cs47l15; + int i, ret; + + BUILD_BUG_ON(ARRAY_SIZE(cs47l15_dai) > ARIZONA_MAX_DAI); + + cs47l15 = devm_kzalloc(&pdev->dev, sizeof(struct cs47l15_priv), + GFP_KERNEL); + if (cs47l15 == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, cs47l15); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&cs47l15->fw_lock); + mutex_init(&cs47l15->trig_lock); + + cs47l15->core.arizona = arizona; + cs47l15->core.num_inputs = 4; + + cs47l15->core.adsp[0].part = "cs47l15"; + if (arizona->pdata.rev_specific_fw) + cs47l15->core.adsp[0].part_rev = 'a' + arizona->rev; + cs47l15->core.adsp[0].num = 1; + cs47l15->core.adsp[0].type = WMFW_ADSP2; + cs47l15->core.adsp[0].rev = 2; + cs47l15->core.adsp[0].dev = arizona->dev; + cs47l15->core.adsp[0].regmap = arizona->regmap_32bit; + + cs47l15->core.adsp[0].base = CLEARWATER_DSP1_CONFIG; + cs47l15->core.adsp[0].mem = cs47l15_dsp1_regions; + cs47l15->core.adsp[0].num_mems + = ARRAY_SIZE(cs47l15_dsp1_regions); + + if (arizona->pdata.num_fw_defs[0]) { + cs47l15->core.adsp[0].firmwares + = arizona->pdata.fw_defs[0]; + + cs47l15->core.adsp[0].num_firmwares + = arizona->pdata.num_fw_defs[0]; + } + + cs47l15->core.adsp[0].rate_put_cb = + cs47l15_adsp_rate_put_cb; + + cs47l15->core.adsp[0].lock_regions = WM_ADSP2_REGION_1_3; + + cs47l15->core.adsp[0].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&cs47l15->core.adsp[0], &cs47l15->fw_lock); + if (ret != 0) + return ret; + + cs47l15_init_compr_info(cs47l15); + + for (i = 0; i < ARRAY_SIZE(cs47l15->fll); i++) { + cs47l15->fll[i].vco_mult = 3; + cs47l15->fll[i].min_outdiv = 3; + cs47l15->fll[i].max_outdiv = 3; + } + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &cs47l15->fll[0]); + arizona_init_fll(arizona, 4, MOON_FLLAO_CONTROL_1 - 1, + MOON_IRQ_FLLAO_CLOCK_OK, MOON_IRQ_FLLAO_CLOCK_OK, + &cs47l15->fll[1]); + + for (i = 0; i < ARRAY_SIZE(cs47l15_dai); i++) + arizona_init_dai(&cs47l15->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(cs47l15_digital_vu); i++) + regmap_update_bits(arizona->regmap, cs47l15_digital_vu[i], + CS47L15_DIG_VU, CS47L15_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = snd_soc_register_platform(&pdev->dev, &cs47l15_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_cs47l15, + cs47l15_dai, ARRAY_SIZE(cs47l15_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + cs47l15_destroy_compr_info(cs47l15); + mutex_destroy(&cs47l15->fw_lock); + + return ret; +} + +static int cs47l15_remove(struct platform_device *pdev) +{ + struct cs47l15_priv *cs47l15 = platform_get_drvdata(pdev); + + snd_soc_unregister_platform(&pdev->dev); + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + cs47l15_destroy_compr_info(cs47l15); + + wm_adsp2_remove(&cs47l15->core.adsp[0]); + + mutex_destroy(&cs47l15->fw_lock); + + return 0; +} + +static struct platform_driver cs47l15_codec_driver = { + .driver = { + .name = "cs47l15-codec", + .owner = THIS_MODULE, + }, + .probe = cs47l15_probe, + .remove = cs47l15_remove, +}; + +module_platform_driver(cs47l15_codec_driver); + +MODULE_DESCRIPTION("ASoC CS47L15 driver"); +MODULE_AUTHOR("Jaswinder Jassal "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cs47l15-codec"); diff --git a/sound/soc/codecs/cs47l15.h b/sound/soc/codecs/cs47l15.h new file mode 100644 index 00000000000..8e27dfb0056 --- /dev/null +++ b/sound/soc/codecs/cs47l15.h @@ -0,0 +1,22 @@ +/* + * cs47l15.h -- ALSA SoC Audio driver for CS47L15 + * + * Copyright 2016 Cirrus Logic + * + * Author: Jaswinder Jassal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _CS47L15_H +#define _CS47L15_H + +#include "arizona.h" + +#define CS47L15_FLL1 1 +#define CS47L15_FLL1_REFCLK 3 +#define CS47L15_FLLAO 5 + +#endif diff --git a/sound/soc/codecs/da7210.c b/sound/soc/codecs/da7210.c index 9c123145650..c134cdcdd79 100644 --- a/sound/soc/codecs/da7210.c +++ b/sound/soc/codecs/da7210.c @@ -1190,7 +1190,7 @@ static struct snd_soc_codec_driver soc_codec_dev_da7210 = { #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) -static struct reg_default da7210_regmap_i2c_patch[] = { +static struct reg_sequence da7210_regmap_i2c_patch[] = { /* System controller master disable */ { DA7210_STARTUP1, 0x00 }, @@ -1277,7 +1277,7 @@ static struct i2c_driver da7210_i2c_driver = { #if defined(CONFIG_SPI_MASTER) -static struct reg_default da7210_regmap_spi_patch[] = { +static struct reg_sequence da7210_regmap_spi_patch[] = { /* Dummy read to give two pulses over nCS for SPI */ { DA7210_AUX2, 0x00 }, { DA7210_AUX2, 0x00 }, diff --git a/sound/soc/codecs/florida.c b/sound/soc/codecs/florida.c new file mode 100644 index 00000000000..16c1ad0a303 --- /dev/null +++ b/sound/soc/codecs/florida.c @@ -0,0 +1,2612 @@ +/* + * florida.c -- ALSA SoC Audio driver for Florida-class codecs + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "wm_adsp.h" +#include "florida.h" + +#define FLORIDA_NUM_ADSP 4 + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU + * are counted as one DAI + */ +#define FLORIDA_NUM_COMPR_DAI 2 + +struct florida_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; + bool trig; + struct mutex trig_lock; +}; + +struct florida_priv { + struct arizona_priv core; + struct arizona_fll fll[2]; + struct florida_compr compr_info[FLORIDA_NUM_COMPR_DAI]; + + struct mutex fw_lock; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[FLORIDA_NUM_COMPR_DAI] = { + { + .dai_name = "florida-dsp-voicectrl", + .adsp_num = 2, + }, + { + .dai_name = "florida-dsp-trace", + .adsp_num = 0, + }, +}; + +static const struct wm_adsp_region florida_dsp1_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x100000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x180000 }, + { .type = WMFW_ADSP2_XM, .base = 0x190000 }, + { .type = WMFW_ADSP2_YM, .base = 0x1a8000 }, +}; + +static const struct wm_adsp_region florida_dsp2_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x200000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x280000 }, + { .type = WMFW_ADSP2_XM, .base = 0x290000 }, + { .type = WMFW_ADSP2_YM, .base = 0x2a8000 }, +}; + +static const struct wm_adsp_region florida_dsp3_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x300000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x380000 }, + { .type = WMFW_ADSP2_XM, .base = 0x390000 }, + { .type = WMFW_ADSP2_YM, .base = 0x3a8000 }, +}; + +static const struct wm_adsp_region florida_dsp4_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x400000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x480000 }, + { .type = WMFW_ADSP2_XM, .base = 0x490000 }, + { .type = WMFW_ADSP2_YM, .base = 0x4a8000 }, +}; + +static const struct wm_adsp_region *florida_dsp_regions[] = { + florida_dsp1_regions, + florida_dsp2_regions, + florida_dsp3_regions, + florida_dsp4_regions, +}; + +static const struct reg_default florida_sysclk_revd_patch[] = { + { 0x3093, 0x1001 }, + { 0x30E3, 0x1301 }, + { 0x3133, 0x1201 }, + { 0x3183, 0x1501 }, + { 0x31D3, 0x1401 }, + { 0x0049, 0x01ea }, + { 0x004a, 0x01f2 }, + { 0x0057, 0x01e7 }, + { 0x0058, 0x01fb }, + { 0x33ce, 0xc4f5 }, + { 0x33cf, 0x1361 }, + { 0x33d0, 0x0402 }, + { 0x33d1, 0x4700 }, + { 0x33d2, 0x026d }, + { 0x33d3, 0xff00 }, + { 0x33d4, 0x026d }, + { 0x33d5, 0x0101 }, + { 0x33d6, 0xc4f5 }, + { 0x33d7, 0x0361 }, + { 0x33d8, 0x0402 }, + { 0x33d9, 0x6701 }, + { 0x33da, 0xc4f5 }, + { 0x33db, 0x136f }, + { 0x33dc, 0xc4f5 }, + { 0x33dd, 0x134f }, + { 0x33de, 0xc4f5 }, + { 0x33df, 0x131f }, + { 0x33e0, 0x026d }, + { 0x33e1, 0x4f01 }, + { 0x33e2, 0x026d }, + { 0x33e3, 0xf100 }, + { 0x33e4, 0x026d }, + { 0x33e5, 0x0001 }, + { 0x33e6, 0xc4f5 }, + { 0x33e7, 0x0361 }, + { 0x33e8, 0x0402 }, + { 0x33e9, 0x6601 }, + { 0x33ea, 0xc4f5 }, + { 0x33eb, 0x136f }, + { 0x33ec, 0xc4f5 }, + { 0x33ed, 0x134f }, + { 0x33ee, 0xc4f5 }, + { 0x33ef, 0x131f }, + { 0x33f0, 0x026d }, + { 0x33f1, 0x4e01 }, + { 0x33f2, 0x026d }, + { 0x33f3, 0xf000 }, + { 0x33f6, 0xc4f5 }, + { 0x33f7, 0x1361 }, + { 0x33f8, 0x0402 }, + { 0x33f9, 0x4600 }, + { 0x33fa, 0x026d }, + { 0x33fb, 0xfe00 }, +}; + +static const struct reg_default florida_sysclk_reve_patch[] = { + { 0x3270, 0xE410 }, + { 0x3271, 0x3078 }, + { 0x3272, 0xE410 }, + { 0x3273, 0x3070 }, + { 0x3274, 0xE410 }, + { 0x3275, 0x3066 }, + { 0x3276, 0xE410 }, + { 0x3277, 0x3056 }, + { 0x327A, 0xE414 }, + { 0x327B, 0x3078 }, + { 0x327C, 0xE414 }, + { 0x327D, 0x3070 }, + { 0x327E, 0xE414 }, + { 0x327F, 0x3066 }, + { 0x3280, 0xE414 }, + { 0x3281, 0x3056 }, +}; + +static int florida_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct regmap *regmap = codec->control_data; + const struct reg_default *patch = NULL; + int i, patch_size; + + switch (arizona->rev) { + case 3: + patch = florida_sysclk_revd_patch; + patch_size = ARRAY_SIZE(florida_sysclk_revd_patch); + break; + default: + patch = florida_sysclk_reve_patch; + patch_size = ARRAY_SIZE(florida_sysclk_reve_patch); + break; + } + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (patch) + for (i = 0; i < patch_size; i++) + regmap_write(regmap, patch[i].reg, + patch[i].def); + break; + + default: + break; + } + + udelay(1000); + + return 0; +} + +static int florida_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct florida_priv *florida = snd_soc_codec_get_drvdata(w->codec); + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + unsigned int v; + int ret; + int i; + + ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v); + if (ret != 0) { + dev_err(codec->dev, + "Failed to read SYSCLK state: %d\n", ret); + return -EIO; + } + + v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + for (i = 0; i < ARRAY_SIZE(florida->compr_info); ++i) { + if (florida->compr_info[i].adsp_compr.dsp->num != + w->shift + 1) + continue; + + mutex_lock(&florida->compr_info[i].trig_lock); + florida->compr_info[i].trig = false; + mutex_unlock(&florida->compr_info[i].trig_lock); + } + break; + default: + break; + } + + return wm_adsp2_early_event(w, kcontrol, event, v); +} + +static const struct reg_sequence florida_no_dre_left_enable[] = { + { 0x3024, 0xE410 }, + { 0x3025, 0x0056 }, + { 0x301B, 0x0224 }, + { 0x301F, 0x4263 }, + { 0x3021, 0x5291 }, + { 0x3030, 0xE410 }, + { 0x3031, 0x3066 }, + { 0x3032, 0xE410 }, + { 0x3033, 0x3070 }, + { 0x3034, 0xE410 }, + { 0x3035, 0x3078 }, + { 0x3036, 0xE410 }, + { 0x3037, 0x3080 }, + { 0x3038, 0xE410 }, + { 0x3039, 0x3080 }, +}; + +static const struct reg_sequence florida_dre_left_enable[] = { + { 0x3024, 0x0231 }, + { 0x3025, 0x0B00 }, + { 0x301B, 0x0227 }, + { 0x301F, 0x4266 }, + { 0x3021, 0x5294 }, + { 0x3030, 0xE231 }, + { 0x3031, 0x0266 }, + { 0x3032, 0x8231 }, + { 0x3033, 0x4B15 }, + { 0x3034, 0x8231 }, + { 0x3035, 0x0B15 }, + { 0x3036, 0xE231 }, + { 0x3037, 0x5294 }, + { 0x3038, 0x0231 }, + { 0x3039, 0x0B00 }, +}; + +static const struct reg_sequence florida_no_dre_right_enable[] = { + { 0x3074, 0xE414 }, + { 0x3075, 0x0056 }, + { 0x306B, 0x0224 }, + { 0x306F, 0x4263 }, + { 0x3071, 0x5291 }, + { 0x3080, 0xE414 }, + { 0x3081, 0x3066 }, + { 0x3082, 0xE414 }, + { 0x3083, 0x3070 }, + { 0x3084, 0xE414 }, + { 0x3085, 0x3078 }, + { 0x3086, 0xE414 }, + { 0x3087, 0x3080 }, + { 0x3088, 0xE414 }, + { 0x3089, 0x3080 }, +}; + +static const struct reg_sequence florida_dre_right_enable[] = { + { 0x3074, 0x0231 }, + { 0x3075, 0x0B00 }, + { 0x306B, 0x0227 }, + { 0x306F, 0x4266 }, + { 0x3071, 0x5294 }, + { 0x3080, 0xE231 }, + { 0x3081, 0x0266 }, + { 0x3082, 0x8231 }, + { 0x3083, 0x4B17 }, + { 0x3084, 0x8231 }, + { 0x3085, 0x0B17 }, + { 0x3086, 0xE231 }, + { 0x3087, 0x5294 }, + { 0x3088, 0x0231 }, + { 0x3089, 0x0B00 }, +}; + +static int florida_hp_pre_enable(struct snd_soc_dapm_widget *w) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + struct arizona *arizona = priv->arizona; + unsigned int val = snd_soc_read(w->codec, ARIZONA_DRE_ENABLE); + const struct reg_sequence *wseq; + int nregs; + int ret; + + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + if (val & ARIZONA_DRE1L_ENA_MASK) { + wseq = florida_dre_left_enable; + nregs = ARRAY_SIZE(florida_dre_left_enable); + } else { + wseq = florida_no_dre_left_enable; + nregs = ARRAY_SIZE(florida_no_dre_left_enable); + priv->out_up_delay += 10; + } + break; + case ARIZONA_OUT1R_ENA_SHIFT: + if (val & ARIZONA_DRE1R_ENA_MASK) { + wseq = florida_dre_right_enable; + nregs = ARRAY_SIZE(florida_dre_right_enable); + } else { + wseq = florida_no_dre_right_enable; + nregs = ARRAY_SIZE(florida_no_dre_right_enable); + priv->out_up_delay += 10; + } + break; + default: + return 0; + } + + ret = regmap_multi_reg_write(arizona->regmap, wseq, nregs); + udelay(1000); + return ret; +} + +static int florida_hp_pre_disable(struct snd_soc_dapm_widget *w) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + unsigned int val = snd_soc_read(w->codec, ARIZONA_DRE_ENABLE); + + switch (w->shift) { + case ARIZONA_OUT1L_ENA_SHIFT: + if (!(val & ARIZONA_DRE1L_ENA_MASK)) { + snd_soc_update_bits(w->codec, ARIZONA_SPARE_TRIGGERS, + ARIZONA_WS_TRG1, ARIZONA_WS_TRG1); + snd_soc_update_bits(w->codec, ARIZONA_SPARE_TRIGGERS, + ARIZONA_WS_TRG1, 0); + priv->out_down_delay += 27; + } + break; + case ARIZONA_OUT1R_ENA_SHIFT: + if (!(val & ARIZONA_DRE1R_ENA_MASK)) { + snd_soc_update_bits(w->codec, ARIZONA_SPARE_TRIGGERS, + ARIZONA_WS_TRG2, ARIZONA_WS_TRG2); + snd_soc_update_bits(w->codec, ARIZONA_SPARE_TRIGGERS, + ARIZONA_WS_TRG2, 0); + priv->out_down_delay += 27; + } + break; + + default: + break; + } + + return 0; +} + +static int florida_hp_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec); + + switch (priv->arizona->rev) { + case 0 ... 3: + break; + default: + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + florida_hp_pre_enable(w); + break; + case SND_SOC_DAPM_PRE_PMD: + florida_hp_pre_disable(w); + break; + default: + break; + } + break; + } + + return arizona_hp_ev(w, kcontrol, event); +} + +static int florida_clear_pga_volume(struct arizona *arizona, int output) +{ + struct reg_sequence clear_pga = { + ARIZONA_OUTPUT_PATH_CONFIG_1L + output * 4, 0x80 + }; + int ret; + + ret = regmap_multi_reg_write_bypassed(arizona->regmap, &clear_pga, 1); + if (ret) + dev_err(arizona->dev, "Failed to clear PGA (0x%x): %d\n", + clear_pga.reg, ret); + + return ret; +} + +static int florida_set_dre(struct arizona *arizona, unsigned int shift, + bool enable) +{ + unsigned int mask = 1 << shift; + unsigned int val = 0; + const struct reg_sequence *wseq; + int nregs; + bool change; + + if (enable) { + regmap_update_bits_check(arizona->regmap, ARIZONA_DRE_ENABLE, + mask, mask, &change); + if (!change) + return 0; + + switch (shift) { + case ARIZONA_DRE1L_ENA_SHIFT: + mask = ARIZONA_OUT1L_ENA; + wseq = florida_dre_left_enable; + nregs = ARRAY_SIZE(florida_dre_left_enable); + break; + case ARIZONA_DRE1R_ENA_SHIFT: + mask = ARIZONA_OUT1R_ENA; + wseq = florida_dre_right_enable; + nregs = ARRAY_SIZE(florida_dre_right_enable); + break; + default: + return 0; + } + } else { + regmap_update_bits_check(arizona->regmap, ARIZONA_DRE_ENABLE, + mask, 0, &change); + if (!change) + return 0; + + /* Force reset of PGA Vol */ + florida_clear_pga_volume(arizona, shift); + + switch (shift) { + case ARIZONA_DRE1L_ENA_SHIFT: + mask = ARIZONA_OUT1L_ENA; + wseq = florida_no_dre_left_enable; + nregs = ARRAY_SIZE(florida_no_dre_left_enable); + break; + case ARIZONA_DRE1R_ENA_SHIFT: + mask = ARIZONA_OUT1R_ENA; + wseq = florida_no_dre_right_enable; + nregs = ARRAY_SIZE(florida_no_dre_right_enable); + break; + default: + return 0; + } + } + + /* If the output is on we need to update the disable sequence */ + regmap_read(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1, &val); + + if (val & mask) { + regmap_multi_reg_write(arizona->regmap, wseq, nregs); + udelay(1000); + } + + return 0; +} + +static int florida_put_dre(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; + unsigned int lshift = mc->shift; + unsigned int rshift = mc->rshift; + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + florida_set_dre(arizona, lshift, !!ucontrol->value.integer.value[0]); + florida_set_dre(arizona, rshift, !!ucontrol->value.integer.value[1]); + + mutex_unlock(&codec->card->dapm_mutex); + + return 0; +} + +static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(vol_limit_tlv, -600, 50, 116); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); + +#define FLORIDA_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0) + +#define FLORIDA_RXANC_INPUT_ROUTES(widget, name) \ + { widget, NULL, name " NG Mux" }, \ + { name " NG Internal", NULL, "RXANC NG Clock" }, \ + { name " NG Internal", NULL, name " Channel" }, \ + { name " NG External", NULL, "RXANC NG External Clock" }, \ + { name " NG External", NULL, name " Channel" }, \ + { name " NG Mux", "None", name " Channel" }, \ + { name " NG Mux", "Internal", name " NG Internal" }, \ + { name " NG Mux", "External", name " NG External" }, \ + { name " Channel", "Left", name " Left Input" }, \ + { name " Channel", "Combine", name " Left Input" }, \ + { name " Channel", "Right", name " Right Input" }, \ + { name " Channel", "Combine", name " Right Input" }, \ + { name " Left Input", "IN1", "IN1L PGA" }, \ + { name " Right Input", "IN1", "IN1R PGA" }, \ + { name " Left Input", "IN2", "IN2L PGA" }, \ + { name " Right Input", "IN2", "IN2R PGA" }, \ + { name " Left Input", "IN3", "IN3L PGA" }, \ + { name " Right Input", "IN3", "IN3R PGA" }, \ + { name " Left Input", "IN4", "IN4L PGA" }, \ + { name " Right Input", "IN4", "IN4R PGA" } + +#define FLORIDA_RXANC_OUTPUT_ROUTES(widget, name) \ + { widget, NULL, name " ANC Source" }, \ + { name " ANC Source", "RXANCL", "RXANCL" }, \ + { name " ANC Source", "RXANCR", "RXANCR" } + +static const struct snd_kcontrol_new florida_snd_controls[] = { +SOC_ENUM("IN1 OSR", arizona_in_dmic_osr[0]), +SOC_ENUM("IN2 OSR", arizona_in_dmic_osr[1]), +SOC_ENUM("IN3 OSR", arizona_in_dmic_osr[2]), +SOC_ENUM("IN4 OSR", arizona_in_dmic_osr[3]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN3L HPF Switch", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN3R HPF Switch", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN4L HPF Switch", ARIZONA_IN4L_CONTROL, + ARIZONA_IN4L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN4R HPF Switch", ARIZONA_IN4R_CONTROL, + ARIZONA_IN4R_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, + ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R, + ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +SND_SOC_BYTES("RXANC Coefficients", ARIZONA_ANC_COEFF_START, + ARIZONA_ANC_COEFF_END - ARIZONA_ANC_COEFF_START + 1), +SND_SOC_BYTES("RXANCL Config", ARIZONA_FCL_FILTER_CONTROL, 1), +SND_SOC_BYTES("RXANCL Coefficients", ARIZONA_FCL_COEFF_START, + ARIZONA_FCL_COEFF_END - ARIZONA_FCL_COEFF_START + 1), +SND_SOC_BYTES("RXANCR Config", ARIZONA_FCR_FILTER_CONTROL, 1), +SND_SOC_BYTES("RXANCR Coefficients", ARIZONA_FCR_COEFF_START, + ARIZONA_FCR_COEFF_END - ARIZONA_FCR_COEFF_START + 1), + +ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), +SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), +SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), +SND_SOC_BYTES_MASK("DRC2", ARIZONA_DRC2_CTRL1, 5, + ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +ARIZONA_SAMPLE_RATE_CONTROL("Sample Rate 2", 2), +ARIZONA_SAMPLE_RATE_CONTROL("Sample Rate 3", 3), + +SOC_VALUE_ENUM("FX Rate", arizona_fx_rate), + +SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +SOC_VALUE_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]), +SOC_VALUE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +SOC_VALUE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), +SOC_VALUE_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]), +SOC_VALUE_ENUM("ASRC RATE 1", arizona_asrc_rate1), +SOC_VALUE_ENUM("ASRC RATE 2", arizona_asrc_rate2), + +ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP4L", ARIZONA_DSP4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP4R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE), + +SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR, + ARIZONA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv), + +ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT2L", ARIZONA_OUT2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT2R", ARIZONA_OUT2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT3L", ARIZONA_OUT3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT3R", ARIZONA_OUT3RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT2L", ARIZONA_OUT6LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT2R", ARIZONA_OUT6RMIX_INPUT_1_SOURCE), + +SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_SHIFT, 1, 0), +SOC_SINGLE("HPOUT2 SC Protect Switch", ARIZONA_HP2_SHORT_CIRCUIT_CTRL, + ARIZONA_HP2_SC_ENA_SHIFT, 1, 0), +SOC_SINGLE("HPOUT3 SC Protect Switch", ARIZONA_HP3_SHORT_CIRCUIT_CTRL, + ARIZONA_HP3_SC_ENA_SHIFT, 1, 0), + +SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L, + ARIZONA_OUT5_OSR_SHIFT, 1, 0), +SOC_SINGLE("SPKDAT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_6L, + ARIZONA_OUT6_OSR_SHIFT, 1, 0), + +SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("HPOUT3 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_6L, + ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_6L, + ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_DOUBLE_R_RANGE_TLV("HPOUT1 Volume Limit", ARIZONA_DAC_VOLUME_LIMIT_1L, + ARIZONA_DAC_VOLUME_LIMIT_1R, ARIZONA_OUT1L_VOL_LIM_SHIFT, + 0x74, 0x8C, 0, vol_limit_tlv), +SOC_DOUBLE_R_RANGE_TLV("HPOUT2 Volume Limit", ARIZONA_DAC_VOLUME_LIMIT_2L, + ARIZONA_DAC_VOLUME_LIMIT_2R, ARIZONA_OUT1L_VOL_LIM_SHIFT, + 0x74, 0x8C, 0, vol_limit_tlv), +SOC_DOUBLE_R_RANGE_TLV("HPOUT3 Volume Limit", ARIZONA_DAC_VOLUME_LIMIT_3L, + ARIZONA_DAC_VOLUME_LIMIT_3R, ARIZONA_OUT1L_VOL_LIM_SHIFT, + 0x74, 0x8C, 0, vol_limit_tlv), +SOC_DOUBLE_R_RANGE_TLV("Speaker Volume Limit", ARIZONA_OUT_VOLUME_4L, + ARIZONA_OUT_VOLUME_4R, ARIZONA_OUT1L_VOL_LIM_SHIFT, + 0x74, 0x8C, 0, vol_limit_tlv), +SOC_DOUBLE_R_RANGE_TLV("SPKDAT1 Volume Limit", ARIZONA_DAC_VOLUME_LIMIT_5L, + ARIZONA_DAC_VOLUME_LIMIT_5R, ARIZONA_OUT1L_VOL_LIM_SHIFT, + 0x74, 0x8C, 0, vol_limit_tlv), +SOC_DOUBLE_R_RANGE_TLV("SPKDAT2 Volume Limit", ARIZONA_DAC_VOLUME_LIMIT_6L, + ARIZONA_DAC_VOLUME_LIMIT_6R, ARIZONA_OUT1L_VOL_LIM_SHIFT, + 0x74, 0x8C, 0, vol_limit_tlv), + +SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), +SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT, + ARIZONA_SPK2R_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_EXT("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, florida_put_dre), +SOC_DOUBLE_EXT("HPOUT2 DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE2L_ENA_SHIFT, ARIZONA_DRE2R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, florida_put_dre), +SOC_DOUBLE_EXT("HPOUT3 DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE3L_ENA_SHIFT, ARIZONA_DRE3R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, florida_put_dre), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +SOC_VALUE_ENUM("Output Rate 1", arizona_output_rate), +SOC_VALUE_ENUM("In Rate", arizona_input_rate), + +FLORIDA_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +FLORIDA_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +FLORIDA_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), +FLORIDA_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R), +FLORIDA_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L), +FLORIDA_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R), +FLORIDA_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), +FLORIDA_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R), +FLORIDA_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +FLORIDA_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), +FLORIDA_NG_SRC("SPKDAT2L", ARIZONA_NOISE_GATE_SELECT_6L), +FLORIDA_NG_SRC("SPKDAT2R", ARIZONA_NOISE_GATE_SELECT_6R), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE), +}; + +ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); +ARIZONA_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE); +ARIZONA_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE); +ARIZONA_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DSP4L, ARIZONA_DSP4LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DSP4R, ARIZONA_DSP4RMIX_INPUT_1_SOURCE); +ARIZONA_DSP_AUX_ENUMS(DSP4, ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(Mic, ARIZONA_MICMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(Noise, ARIZONA_NOISEMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT3L, ARIZONA_OUT3LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT3R, ARIZONA_OUT3RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKDAT2L, ARIZONA_OUT6LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKDAT2R, ARIZONA_OUT6RMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC3INT1, ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3INT2, ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3INT3, ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3INT4, ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC3DEC1, ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3DEC2, ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3DEC3, ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3DEC4, ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE); + +static const char * const florida_dsp_output_texts[] = { + "None", + "DSP3", +}; + +static const struct soc_enum florida_dsp_output_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(florida_dsp_output_texts), + florida_dsp_output_texts); + +static const struct snd_kcontrol_new florida_dsp_output_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", florida_dsp_output_enum), +}; + +static const char * const florida_memory_mux_texts[] = { + "None", + "Shared Memory", +}; + +static const struct soc_enum florida_memory_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(florida_memory_mux_texts), + florida_memory_mux_texts); + +static const struct snd_kcontrol_new florida_memory_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP2 Virtual Input", florida_memory_enum), + SOC_DAPM_ENUM_VIRT("DSP3 Virtual Input", florida_memory_enum), +}; + +static const char * const florida_aec_loopback_texts[] = { + "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R", + "SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", "SPKDAT2L", "SPKDAT2R", +}; + +static const unsigned int florida_aec_loopback_values[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, +}; + +static const struct soc_enum florida_aec_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(florida_aec_loopback_texts), + florida_aec_loopback_texts, + florida_aec_loopback_values); + +static const struct snd_kcontrol_new florida_aec_loopback_mux = + SOC_DAPM_VALUE_ENUM("AEC Loopback", florida_aec_loopback); + +static const struct snd_kcontrol_new florida_anc_input_mux[] = { + SOC_DAPM_ENUM("RXANCL Input", arizona_anc_input_src[0]), + SOC_DAPM_ENUM("RXANCL Channel", arizona_anc_input_src[1]), + SOC_DAPM_ENUM("RXANCR Input", arizona_anc_input_src[2]), + SOC_DAPM_ENUM("RXANCR Channel", arizona_anc_input_src[3]), +}; + +static const struct snd_kcontrol_new florida_anc_ng_mux = + SOC_DAPM_ENUM_VIRT("RXANC NG Source", arizona_anc_ng_enum); + +static const struct snd_kcontrol_new florida_output_anc_src[] = { + SOC_DAPM_ENUM("HPOUT1L ANC Source", arizona_output_anc_src[0]), + SOC_DAPM_ENUM("HPOUT1R ANC Source", arizona_output_anc_src[1]), + SOC_DAPM_ENUM("HPOUT2L ANC Source", arizona_output_anc_src[2]), + SOC_DAPM_ENUM("HPOUT2R ANC Source", arizona_output_anc_src[3]), + SOC_DAPM_ENUM("HPOUT3L ANC Source", arizona_output_anc_src[4]), + SOC_DAPM_ENUM("HPOUT3R ANC Source", arizona_output_anc_src[5]), + SOC_DAPM_ENUM("SPKOUTL ANC Source", arizona_output_anc_src[6]), + SOC_DAPM_ENUM("SPKOUTR ANC Source", arizona_output_anc_src[7]), + SOC_DAPM_ENUM("SPKDAT1L ANC Source", arizona_output_anc_src[8]), + SOC_DAPM_ENUM("SPKDAT1R ANC Source", arizona_output_anc_src[9]), + SOC_DAPM_ENUM("SPKDAT2L ANC Source", arizona_output_anc_src[10]), + SOC_DAPM_ENUM("SPKDAT2R ANC Source", arizona_output_anc_src[11]), +}; + +static const struct snd_soc_dapm_widget florida_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, + 0, florida_sysclk_ev, SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, + ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK, + ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_INPUT("IN1L"), +SND_SOC_DAPM_INPUT("IN1R"), +SND_SOC_DAPM_INPUT("IN2L"), +SND_SOC_DAPM_INPUT("IN2R"), +SND_SOC_DAPM_INPUT("IN3L"), +SND_SOC_DAPM_INPUT("IN3R"), +SND_SOC_DAPM_INPUT("IN4L"), +SND_SOC_DAPM_INPUT("IN4R"), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN3L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN3R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN4L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN4R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR, + ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Mic Mute Mixer", ARIZONA_MIC_NOISE_MIX_CONTROL_1, + ARIZONA_MICMUTE_MIX_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_PGA("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0, + NULL, 0), + +WM_ADSP2("DSP1", 0, florida_adsp_power_ev), +WM_ADSP2("DSP2", 1, florida_adsp_power_ev), +WM_ADSP2("DSP3", 2, florida_adsp_power_ev), +WM_ADSP2("DSP4", 3, florida_adsp_power_ev), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3INT1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT3", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT4", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3DEC1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC3", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC4", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &florida_aec_loopback_mux), + +SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM, + ARIZONA_EXT_NG_SEL_SET_SHIFT, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM, + ARIZONA_CLK_NG_ENA_SET_SHIFT, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0, + &florida_anc_input_mux[0]), +SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0, + &florida_anc_input_mux[0]), +SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0, + &florida_anc_input_mux[1]), +SND_SOC_DAPM_VIRT_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &florida_anc_ng_mux), +SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0, + &florida_anc_input_mux[2]), +SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0, + &florida_anc_input_mux[2]), +SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0, + &florida_anc_input_mux[3]), +SND_SOC_DAPM_VIRT_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &florida_anc_ng_mux), + +SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, ARIZONA_CLK_L_ENA_SET_SHIFT, + 0, NULL, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, ARIZONA_CLK_R_ENA_SET_SHIFT, + 0, NULL, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[0]), +SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[1]), +SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[2]), +SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[3]), +SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[4]), +SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[5]), +SND_SOC_DAPM_MUX("SPKOUTL ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[6]), +SND_SOC_DAPM_MUX("SPKOUTR ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[7]), +SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[8]), +SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[9]), +SND_SOC_DAPM_MUX("SPKDAT2L ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[10]), +SND_SOC_DAPM_MUX("SPKDAT2R ANC Source", SND_SOC_NOPM, 0, 0, + &florida_output_anc_src[11]), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, florida_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, florida_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT6L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT6L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT6R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT6R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + +ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), +ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), +ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"), +ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), + +ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), +ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), +ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(Mic, "Mic"), +ARIZONA_MIXER_WIDGETS(Noise, "Noise"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"), +ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"), +ARIZONA_MIXER_WIDGETS(OUT2L, "HPOUT2L"), +ARIZONA_MIXER_WIDGETS(OUT2R, "HPOUT2R"), +ARIZONA_MIXER_WIDGETS(OUT3L, "HPOUT3L"), +ARIZONA_MIXER_WIDGETS(OUT3R, "HPOUT3R"), +ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"), +ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"), +ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"), +ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"), +ARIZONA_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"), +ARIZONA_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), +ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"), +ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), +ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"), +ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"), +ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"), +ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"), +ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"), +ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"), + +ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"), +ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"), +ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), +ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"), + +ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), +ARIZONA_DSP_WIDGETS(DSP2, "DSP2"), +ARIZONA_DSP_WIDGETS(DSP3, "DSP3"), +ARIZONA_DSP_WIDGETS(DSP4, "DSP4"), + +SND_SOC_DAPM_VIRT_MUX("DSP2 Virtual Input", SND_SOC_NOPM, 0, 0, + &florida_memory_mux[0]), +SND_SOC_DAPM_VIRT_MUX("DSP3 Virtual Input", SND_SOC_NOPM, 0, 0, + &florida_memory_mux[1]), + +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &florida_dsp_output_mux[0]), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), +ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"), +ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), +ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"), +ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"), + +ARIZONA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), +ARIZONA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), +ARIZONA_MUX_WIDGETS(ISRC3DEC3, "ISRC3DEC3"), +ARIZONA_MUX_WIDGETS(ISRC3DEC4, "ISRC3DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), +ARIZONA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), +ARIZONA_MUX_WIDGETS(ISRC3INT3, "ISRC3INT3"), +ARIZONA_MUX_WIDGETS(ISRC3INT4, "ISRC3INT4"), + +SND_SOC_DAPM_OUTPUT("HPOUT1L"), +SND_SOC_DAPM_OUTPUT("HPOUT1R"), +SND_SOC_DAPM_OUTPUT("HPOUT2L"), +SND_SOC_DAPM_OUTPUT("HPOUT2R"), +SND_SOC_DAPM_OUTPUT("HPOUT3L"), +SND_SOC_DAPM_OUTPUT("HPOUT3R"), +SND_SOC_DAPM_OUTPUT("SPKOUTLN"), +SND_SOC_DAPM_OUTPUT("SPKOUTLP"), +SND_SOC_DAPM_OUTPUT("SPKOUTRN"), +SND_SOC_DAPM_OUTPUT("SPKOUTRP"), +SND_SOC_DAPM_OUTPUT("SPKDAT1L"), +SND_SOC_DAPM_OUTPUT("SPKDAT1R"), +SND_SOC_DAPM_OUTPUT("SPKDAT2L"), +SND_SOC_DAPM_OUTPUT("SPKDAT2R"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "IN3L", "IN3L PGA" }, \ + { name, "IN3R", "IN3R PGA" }, \ + { name, "IN4L", "IN4L PGA" }, \ + { name, "IN4R", "IN4R PGA" }, \ + { name, "Mic Mute Mixer", "Mic Mute Mixer" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF1RX7", "AIF1RX7" }, \ + { name, "AIF1RX8", "AIF1RX8" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF2RX3", "AIF2RX3" }, \ + { name, "AIF2RX4", "AIF2RX4" }, \ + { name, "AIF2RX5", "AIF2RX5" }, \ + { name, "AIF2RX6", "AIF2RX6" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "SLIMRX5", "SLIMRX5" }, \ + { name, "SLIMRX6", "SLIMRX6" }, \ + { name, "SLIMRX7", "SLIMRX7" }, \ + { name, "SLIMRX8", "SLIMRX8" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ASRC1L", "ASRC1L" }, \ + { name, "ASRC1R", "ASRC1R" }, \ + { name, "ASRC2L", "ASRC2L" }, \ + { name, "ASRC2R", "ASRC2R" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2DEC3", "ISRC2DEC3" }, \ + { name, "ISRC2DEC4", "ISRC2DEC4" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC2INT3", "ISRC2INT3" }, \ + { name, "ISRC2INT4", "ISRC2INT4" }, \ + { name, "ISRC3DEC1", "ISRC3DEC1" }, \ + { name, "ISRC3DEC2", "ISRC3DEC2" }, \ + { name, "ISRC3DEC3", "ISRC3DEC3" }, \ + { name, "ISRC3DEC4", "ISRC3DEC4" }, \ + { name, "ISRC3INT1", "ISRC3INT1" }, \ + { name, "ISRC3INT2", "ISRC3INT2" }, \ + { name, "ISRC3INT3", "ISRC3INT3" }, \ + { name, "ISRC3INT4", "ISRC3INT4" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" }, \ + { name, "DSP2.1", "DSP2" }, \ + { name, "DSP2.2", "DSP2" }, \ + { name, "DSP2.3", "DSP2" }, \ + { name, "DSP2.4", "DSP2" }, \ + { name, "DSP2.5", "DSP2" }, \ + { name, "DSP2.6", "DSP2" }, \ + { name, "DSP3.1", "DSP3" }, \ + { name, "DSP3.2", "DSP3" }, \ + { name, "DSP3.3", "DSP3" }, \ + { name, "DSP3.4", "DSP3" }, \ + { name, "DSP3.5", "DSP3" }, \ + { name, "DSP3.6", "DSP3" }, \ + { name, "DSP4.1", "DSP4" }, \ + { name, "DSP4.2", "DSP4" }, \ + { name, "DSP4.3", "DSP4" }, \ + { name, "DSP4.4", "DSP4" }, \ + { name, "DSP4.5", "DSP4" }, \ + { name, "DSP4.6", "DSP4" } + +static const struct snd_soc_dapm_route florida_dapm_routes[] = { + { "AIF2 Capture", NULL, "DBVDD2" }, + { "AIF2 Playback", NULL, "DBVDD2" }, + + { "AIF3 Capture", NULL, "DBVDD3" }, + { "AIF3 Playback", NULL, "DBVDD3" }, + + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + { "OUT2L", NULL, "CPVDD" }, + { "OUT2R", NULL, "CPVDD" }, + { "OUT3L", NULL, "CPVDD" }, + { "OUT3R", NULL, "CPVDD" }, + + { "OUT4L", NULL, "SPKVDDL" }, + { "OUT4R", NULL, "SPKVDDR" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT2L", NULL, "SYSCLK" }, + { "OUT2R", NULL, "SYSCLK" }, + { "OUT3L", NULL, "SYSCLK" }, + { "OUT3R", NULL, "SYSCLK" }, + { "OUT4L", NULL, "SYSCLK" }, + { "OUT4R", NULL, "SYSCLK" }, + { "OUT5L", NULL, "SYSCLK" }, + { "OUT5R", NULL, "SYSCLK" }, + { "OUT6L", NULL, "SYSCLK" }, + { "OUT6R", NULL, "SYSCLK" }, + + { "IN1L", NULL, "SYSCLK" }, + { "IN1R", NULL, "SYSCLK" }, + { "IN2L", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, + { "IN3L", NULL, "SYSCLK" }, + { "IN3R", NULL, "SYSCLK" }, + { "IN4L", NULL, "SYSCLK" }, + { "IN4R", NULL, "SYSCLK" }, + + { "MICBIAS1", NULL, "MICVDD" }, + { "MICBIAS2", NULL, "MICVDD" }, + { "MICBIAS3", NULL, "MICVDD" }, + + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Noise Generator", NULL, "NOISE" }, + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + { "AIF1 Capture", NULL, "AIF1TX7" }, + { "AIF1 Capture", NULL, "AIF1TX8" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + { "AIF1RX7", NULL, "AIF1 Playback" }, + { "AIF1RX8", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + { "AIF2 Capture", NULL, "AIF2TX3" }, + { "AIF2 Capture", NULL, "AIF2TX4" }, + { "AIF2 Capture", NULL, "AIF2TX5" }, + { "AIF2 Capture", NULL, "AIF2TX6" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + { "AIF2RX3", NULL, "AIF2 Playback" }, + { "AIF2RX4", NULL, "AIF2 Playback" }, + { "AIF2RX5", NULL, "AIF2 Playback" }, + { "AIF2RX6", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + { "SLIMRX3", NULL, "Slim1 Playback" }, + { "SLIMRX4", NULL, "Slim1 Playback" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX5", NULL, "Slim2 Playback" }, + { "SLIMRX6", NULL, "Slim2 Playback" }, + + { "Slim3 Capture", NULL, "SLIMTX7" }, + { "Slim3 Capture", NULL, "SLIMTX8" }, + + { "SLIMRX7", NULL, "Slim3 Playback" }, + { "SLIMRX8", NULL, "Slim3 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + { "Slim3 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + { "Slim3 Capture", NULL, "SYSCLK" }, + + { "Voice Control CPU", NULL, "Voice Control DSP" }, + { "Voice Control DSP", NULL, "DSP3" }, + { "Voice Control CPU", NULL, "SYSCLK" }, + { "Voice Control DSP", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP1" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, + + { "IN1L PGA", NULL, "IN1L" }, + { "IN1R PGA", NULL, "IN1R" }, + + { "IN2L PGA", NULL, "IN2L" }, + { "IN2R PGA", NULL, "IN2R" }, + + { "IN3L PGA", NULL, "IN3L" }, + { "IN3R PGA", NULL, "IN3R" }, + + { "IN4L PGA", NULL, "IN4L" }, + { "IN4R PGA", NULL, "IN4R" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), + ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), + ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), + ARIZONA_MIXER_ROUTES("OUT2R", "HPOUT2R"), + ARIZONA_MIXER_ROUTES("OUT3L", "HPOUT3L"), + ARIZONA_MIXER_ROUTES("OUT3R", "HPOUT3R"), + + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"), + ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"), + ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"), + ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"), + ARIZONA_MIXER_ROUTES("OUT6L", "SPKDAT2L"), + ARIZONA_MIXER_ROUTES("OUT6R", "SPKDAT2R"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"), + ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"), + ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"), + ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"), + ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"), + ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"), + ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"), + + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), + ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), + ARIZONA_MIXER_ROUTES("EQ3", "EQ3"), + ARIZONA_MIXER_ROUTES("EQ4", "EQ4"), + + ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), + ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), + ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Noise"), + ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"), + + ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"), + ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"), + ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"), + ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"), + + ARIZONA_DSP_ROUTES("DSP1"), + ARIZONA_DSP_ROUTES("DSP2"), + ARIZONA_DSP_ROUTES("DSP3"), + ARIZONA_DSP_ROUTES("DSP4"), + + { "DSP2 Preloader", NULL, "DSP2 Virtual Input" }, + { "DSP2 Virtual Input", "Shared Memory", "DSP3" }, + { "DSP3 Preloader", NULL, "DSP3 Virtual Input" }, + { "DSP3 Virtual Input", "Shared Memory", "DSP2" }, + + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP3", "DSP3" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"), + ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + ARIZONA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), + ARIZONA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), + ARIZONA_MUX_ROUTES("ISRC3INT3", "ISRC3INT3"), + ARIZONA_MUX_ROUTES("ISRC3INT4", "ISRC3INT4"), + + ARIZONA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), + ARIZONA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), + ARIZONA_MUX_ROUTES("ISRC3DEC3", "ISRC3DEC3"), + ARIZONA_MUX_ROUTES("ISRC3DEC4", "ISRC3DEC4"), + + { "AEC Loopback", "HPOUT1L", "OUT1L" }, + { "AEC Loopback", "HPOUT1R", "OUT1R" }, + { "HPOUT1L", NULL, "OUT1L" }, + { "HPOUT1R", NULL, "OUT1R" }, + + { "AEC Loopback", "HPOUT2L", "OUT2L" }, + { "AEC Loopback", "HPOUT2R", "OUT2R" }, + { "HPOUT2L", NULL, "OUT2L" }, + { "HPOUT2R", NULL, "OUT2R" }, + + { "AEC Loopback", "HPOUT3L", "OUT3L" }, + { "AEC Loopback", "HPOUT3R", "OUT3R" }, + { "HPOUT3L", NULL, "OUT3L" }, + { "HPOUT3R", NULL, "OUT3R" }, + + { "AEC Loopback", "SPKOUTL", "OUT4L" }, + { "SPKOUTLN", NULL, "OUT4L" }, + { "SPKOUTLP", NULL, "OUT4L" }, + + { "AEC Loopback", "SPKOUTR", "OUT4R" }, + { "SPKOUTRN", NULL, "OUT4R" }, + { "SPKOUTRP", NULL, "OUT4R" }, + + { "AEC Loopback", "SPKDAT1L", "OUT5L" }, + { "AEC Loopback", "SPKDAT1R", "OUT5R" }, + { "SPKDAT1L", NULL, "OUT5L" }, + { "SPKDAT1R", NULL, "OUT5R" }, + + { "AEC Loopback", "SPKDAT2L", "OUT6L" }, + { "AEC Loopback", "SPKDAT2R", "OUT6R" }, + { "SPKDAT2L", NULL, "OUT6L" }, + { "SPKDAT2R", NULL, "OUT6R" }, + + FLORIDA_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"), + FLORIDA_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"), + + FLORIDA_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT4L", "SPKOUTL"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT4R", "SPKOUTR"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT6L", "SPKDAT2L"), + FLORIDA_RXANC_OUTPUT_ROUTES("OUT6R", "SPKDAT2R"), + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, + { "DRC2 Signal Activity", NULL, "DRC2L" }, + { "DRC2 Signal Activity", NULL, "DRC2R" }, +}; + +static int florida_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct florida_priv *florida = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case FLORIDA_FLL1: + return arizona_set_fll(&florida->fll[0], source, Fref, Fout); + case FLORIDA_FLL2: + return arizona_set_fll(&florida->fll[1], source, Fref, Fout); + case FLORIDA_FLL1_REFCLK: + return arizona_set_fll_refclk(&florida->fll[0], source, Fref, + Fout); + case FLORIDA_FLL2_REFCLK: + return arizona_set_fll_refclk(&florida->fll[1], source, Fref, + Fout); + default: + return -EINVAL; + } +} + +#define FLORIDA_RATES SNDRV_PCM_RATE_KNOT + +#define FLORIDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver florida_dai[] = { + { + .name = "florida-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "florida-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "florida-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "florida-slim1", + .id = 4, + .playback = { + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "florida-slim2", + .id = 5, + .playback = { + .stream_name = "Slim2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .capture = { + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "florida-slim3", + .id = 6, + .playback = { + .stream_name = "Slim3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .capture = { + .stream_name = "Slim3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "florida-cpu-voicectrl", + .capture = { + .stream_name = "Voice Control CPU", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "florida-dsp-voicectrl", + .capture = { + .stream_name = "Voice Control DSP", + .channels_min = 1, + .channels_max = 2, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + }, + { + .name = "florida-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 2, + .channels_max = 8, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "florida-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 2, + .channels_max = 8, + .rates = FLORIDA_RATES, + .formats = FLORIDA_FORMATS, + }, + }, +}; + +static void florida_compr_irq(struct florida_priv *florida, + struct florida_compr *compr) +{ + struct arizona *arizona = florida->core.arizona; + bool trigger = false; + int ret; + + ret = wm_adsp_compr_irq(&compr->adsp_compr, &trigger); + if (ret < 0) + return; + + if (trigger && arizona->pdata.ez2ctrl_trigger) { + mutex_lock(&compr->trig_lock); + if (!compr->trig) { + compr->trig = true; + + if (wm_adsp_fw_has_voice_trig(compr->adsp_compr.dsp)) + arizona->pdata.ez2ctrl_trigger(); + } + mutex_unlock(&compr->trig_lock); + } +} + +static irqreturn_t florida_adsp2_irq(int irq, void *data) +{ + struct florida_priv *florida = data; + int i; + + for (i = 0; i < ARRAY_SIZE(florida->compr_info); ++i) { + if (!florida->compr_info[i].adsp_compr.dsp->running) + continue; + + florida_compr_irq(florida, &florida->compr_info[i]); + } + + return IRQ_HANDLED; +} + +static struct florida_compr *florida_get_compr(struct snd_soc_pcm_runtime *rtd, + struct florida_priv *florida) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(florida->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + florida->compr_info[i].dai_name) == 0) + return &florida->compr_info[i]; + } + + return NULL; +} + +static int florida_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct florida_priv *florida = snd_soc_codec_get_drvdata(rtd->codec); + struct arizona *arizona = florida->core.arizona; + struct florida_compr *compr; + + /* Find a compr_info for this DAI */ + compr = florida_get_compr(rtd, florida); + if (!compr) { + dev_err(arizona->dev, + "No suitable compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int florida_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *adsp_compr = + (struct wm_adsp_compr *)stream->runtime->private_data; + struct florida_compr *compr = container_of(adsp_compr, + struct florida_compr, + adsp_compr); + bool dummy; + int ret; + + ret = wm_adsp_compr_trigger(stream, cmd); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /** + * If the firmware already triggered before the stream + * was opened process any outstanding data + */ + if (compr->trig) + wm_adsp_compr_irq(&compr->adsp_compr, &dummy); + break; + default: + break; + } + + return ret; +} + +static int florida_codec_probe(struct snd_soc_codec *codec) +{ + struct florida_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int i, ret; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_spk(codec); + arizona_init_gpio(codec); + arizona_init_mono(codec); + arizona_init_input(codec); + + for (i = 0; i < FLORIDA_NUM_ADSP; ++i) { + ret = wm_adsp2_codec_probe(&priv->core.adsp[i], codec); + if (ret) + return ret; + } + + ret = snd_soc_add_codec_controls(codec, + arizona_adsp2_rate_controls, + FLORIDA_NUM_ADSP); + if (ret) + return ret; + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + mutex_unlock(&codec->card->dapm_mutex); + + priv->core.arizona->dapm = &codec->dapm; + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", + florida_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_enable_pin(&codec->dapm, "DRC2 Signal Activity"); + mutex_unlock(&codec->card->dapm_mutex); + + ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ2_STATUS_3_MASK, + ARIZONA_IM_DRC2_SIG_DET_EINT2, + 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC2 IRQ for DSP: %d\n", + ret); + return ret; + } + + return 0; +} + +static int florida_codec_remove(struct snd_soc_codec *codec) +{ + struct florida_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int i; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + regmap_update_bits(arizona->regmap, ARIZONA_IRQ2_STATUS_3_MASK, + ARIZONA_IM_DRC2_SIG_DET_EINT2, + ARIZONA_IM_DRC2_SIG_DET_EINT2); + + for (i = 0; i < FLORIDA_NUM_ADSP; ++i) + wm_adsp2_codec_remove(&priv->core.adsp[i], codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define FLORIDA_DIG_VU 0x0200 + +static unsigned int florida_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, + ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, + ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, + ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, + ARIZONA_DAC_DIGITAL_VOLUME_6L, + ARIZONA_DAC_DIGITAL_VOLUME_6R, +}; + +static struct snd_soc_codec_driver soc_codec_dev_florida = { + .probe = florida_codec_probe, + .remove = florida_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = florida_set_fll, + + .controls = florida_snd_controls, + .num_controls = ARRAY_SIZE(florida_snd_controls), + .dapm_widgets = florida_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(florida_dapm_widgets), + .dapm_routes = florida_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(florida_dapm_routes), +}; + +static struct snd_compr_ops florida_compr_ops = { + .open = florida_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = florida_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver florida_compr_platform = { + .compr_ops = &florida_compr_ops, +}; + +static void florida_init_compr_info(struct florida_priv *florida) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(florida->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(florida->compr_info); ++i) { + florida->compr_info[i].dai_name = compr_dai_mapping[i].dai_name; + + dsp = &florida->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &florida->compr_info[i].adsp_compr); + + mutex_init(&florida->compr_info[i].trig_lock); + } +} + +static void florida_destroy_compr_info(struct florida_priv *florida) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(florida->compr_info); ++i) + wm_adsp_compr_destroy(&florida->compr_info[i].adsp_compr); +} + +static int florida_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct florida_priv *florida; + int i, ret; + + BUILD_BUG_ON(ARRAY_SIZE(florida_dai) > ARIZONA_MAX_DAI); + + florida = devm_kzalloc(&pdev->dev, sizeof(struct florida_priv), + GFP_KERNEL); + if (florida == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, florida); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&florida->fw_lock); + + florida->core.arizona = arizona; + florida->core.num_inputs = 8; + + for (i = 0; i < FLORIDA_NUM_ADSP; i++) { + florida->core.adsp[i].part = "florida"; + florida->core.adsp[i].num = i + 1; + florida->core.adsp[i].type = WMFW_ADSP2; + florida->core.adsp[i].dev = arizona->dev; + florida->core.adsp[i].regmap = arizona->regmap; + + florida->core.adsp[i].base = ARIZONA_DSP1_CONTROL_1 + + (0x100 * i); + florida->core.adsp[i].mem = florida_dsp_regions[i]; + florida->core.adsp[i].num_mems + = ARRAY_SIZE(florida_dsp1_regions); + + if (arizona->pdata.num_fw_defs[i]) { + florida->core.adsp[i].firmwares + = arizona->pdata.fw_defs[i]; + + florida->core.adsp[i].num_firmwares + = arizona->pdata.num_fw_defs[i]; + } + + florida->core.adsp[i].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&florida->core.adsp[i], &florida->fw_lock); + if (ret != 0) + goto error; + } + + florida_init_compr_info(florida); + + for (i = 0; i < ARRAY_SIZE(florida->fll); i++) + florida->fll[i].vco_mult = 3; + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &florida->fll[0]); + arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1, + ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, + &florida->fll[1]); + + for (i = 0; i < ARRAY_SIZE(florida_dai); i++) + arizona_init_dai(&florida->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(florida_digital_vu); i++) + regmap_update_bits(arizona->regmap, florida_digital_vu[i], + FLORIDA_DIG_VU, FLORIDA_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = snd_soc_register_platform(&pdev->dev, &florida_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_florida, + florida_dai, ARRAY_SIZE(florida_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + florida_destroy_compr_info(florida); + mutex_destroy(&florida->fw_lock); + + return ret; +} + +static int florida_remove(struct platform_device *pdev) +{ + struct florida_priv *florida = platform_get_drvdata(pdev); + int i; + + snd_soc_unregister_platform(&pdev->dev); + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + florida_destroy_compr_info(florida); + + for (i = 0; i < FLORIDA_NUM_ADSP; i++) + wm_adsp2_remove(&florida->core.adsp[i]); + + mutex_destroy(&florida->fw_lock); + + return 0; +} + +static struct platform_driver florida_codec_driver = { + .driver = { + .name = "florida-codec", + .owner = THIS_MODULE, + }, + .probe = florida_probe, + .remove = florida_remove, +}; + +module_platform_driver(florida_codec_driver); + +MODULE_DESCRIPTION("ASoC Florida driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:florida-codec"); diff --git a/sound/soc/codecs/florida.h b/sound/soc/codecs/florida.h new file mode 100644 index 00000000000..6855d9dbd0e --- /dev/null +++ b/sound/soc/codecs/florida.h @@ -0,0 +1,23 @@ +/* + * florida.h -- ALSA SoC Audio driver for Florida-class codecs + * + * Copyright 2012 Wolfson Microelectronics plc + * + * Author: Mark Brown + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _FLORIDA_H +#define _FLORIDA_H + +#include "arizona.h" + +#define FLORIDA_FLL1 1 +#define FLORIDA_FLL2 2 +#define FLORIDA_FLL1_REFCLK 3 +#define FLORIDA_FLL2_REFCLK 4 + +#endif diff --git a/sound/soc/codecs/largo.c b/sound/soc/codecs/largo.c new file mode 100644 index 00000000000..0e4d1d0d537 --- /dev/null +++ b/sound/soc/codecs/largo.c @@ -0,0 +1,1531 @@ +/* + * largo.c -- ALSA SoC Audio driver for Largo codec + * + * Copyright 2014 CirrusLogic, Inc. + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "wm_adsp.h" +#include "largo.h" + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU + * are counted as one DAI + */ +#define LARGO_NUM_COMPR_DAI 2 + +struct largo_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; + bool trig; + struct mutex trig_lock; +}; + +struct largo_priv { + struct arizona_priv core; + struct arizona_fll fll[2]; + struct largo_compr compr_info[LARGO_NUM_COMPR_DAI]; + + struct mutex fw_lock; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[LARGO_NUM_COMPR_DAI] = { + { + .dai_name = "largo-dsp-voicectrl", + .adsp_num = 2, + }, + { + .dai_name = "largo-dsp-trace", + .adsp_num = 1, + }, +}; + +static const struct wm_adsp_region largo_dsp2_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x200000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x280000 }, + { .type = WMFW_ADSP2_XM, .base = 0x290000 }, + { .type = WMFW_ADSP2_YM, .base = 0x2a8000 }, +}; + +static const struct wm_adsp_region largo_dsp3_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x300000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x380000 }, + { .type = WMFW_ADSP2_XM, .base = 0x390000 }, + { .type = WMFW_ADSP2_YM, .base = 0x3a8000 }, +}; + +static const struct wm_adsp_region *largo_dsp_regions[] = { + largo_dsp2_regions, + largo_dsp3_regions, +}; + +static int largo_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct largo_priv *largo = snd_soc_codec_get_drvdata(w->codec); + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + unsigned int v; + int ret; + int i; + + ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v); + if (ret != 0) { + dev_err(codec->dev, + "Failed to read SYSCLK state: %d\n", ret); + return -EIO; + } + + v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + for (i = 0; i < ARRAY_SIZE(largo->compr_info); ++i) { + if (largo->compr_info[i].adsp_compr.dsp->num != + w->shift + 1) + continue; + + mutex_lock(&largo->compr_info[i].trig_lock); + largo->compr_info[i].trig = false; + mutex_unlock(&largo->compr_info[i].trig_lock); + } + break; + default: + break; + } + + return wm_adsp2_early_event(w, kcontrol, event, v); +} + +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); + +#define LARGO_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0) + +static const struct snd_kcontrol_new largo_snd_controls[] = { +SOC_ENUM("IN1 OSR", arizona_in_dmic_osr[0]), +SOC_ENUM("IN2 OSR", arizona_in_dmic_osr[1]), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), +SND_SOC_BYTES_MASK("DRC2", ARIZONA_DRC2_CTRL1, 5, + ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +ARIZONA_SAMPLE_RATE_CONTROL("Sample Rate 2", 2), +ARIZONA_SAMPLE_RATE_CONTROL("Sample Rate 3", 3), + +SOC_VALUE_ENUM("FX Rate", arizona_fx_rate), + +SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +SOC_VALUE_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]), +SOC_VALUE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +SOC_VALUE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), +SOC_VALUE_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]), +SOC_VALUE_ENUM("ASRC RATE 1", arizona_asrc_rate1), +SOC_VALUE_ENUM("ASRC RATE 2", arizona_asrc_rate2), + +ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE), + +SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR, + ARIZONA_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv), + +ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUT", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), + +SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_SHIFT, 1, 0), + +SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +SOC_VALUE_ENUM("Output Rate 1", arizona_output_rate), +SOC_VALUE_ENUM("In Rate", arizona_input_rate), + +LARGO_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +LARGO_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +LARGO_NG_SRC("SPKOUT", ARIZONA_NOISE_GATE_SELECT_4L), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), +}; + +ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE); +ARIZONA_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE); +ARIZONA_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKOUT, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC3INT1, ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3INT2, ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3INT3, ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3INT4, ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC3DEC1, ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3DEC2, ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3DEC3, ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC3DEC4, ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE); + +static const char * const largo_dsp_output_texts[] = { + "None", + "DSP3", +}; + +static const struct soc_enum largo_dsp_output_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(largo_dsp_output_texts), + largo_dsp_output_texts); + +static const struct snd_kcontrol_new largo_dsp_output_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", largo_dsp_output_enum), +}; + +static const char * const largo_memory_mux_texts[] = { + "None", + "Shared Memory", +}; + +static const struct soc_enum largo_memory_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(largo_memory_mux_texts), + largo_memory_mux_texts); + +static const struct snd_kcontrol_new largo_memory_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP2 Virtual Input", largo_memory_enum), + SOC_DAPM_ENUM_VIRT("DSP3 Virtual Input", largo_memory_enum), +}; + +static const char * const largo_aec_loopback_texts[] = { + "HPOUT1L", "HPOUT1R", "SPKOUT", +}; + +static const unsigned int largo_aec_loopback_values[] = { + 0, 1, 6, +}; + +static const struct soc_enum largo_aec_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(largo_aec_loopback_texts), + largo_aec_loopback_texts, + largo_aec_loopback_values); + +static const struct snd_kcontrol_new largo_aec_loopback_mux = + SOC_DAPM_VALUE_ENUM("AEC Loopback", largo_aec_loopback); + +static const struct snd_soc_dapm_widget largo_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, + ARIZONA_SYSCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, + ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK, + ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_INPUT("IN1L"), +SND_SOC_DAPM_INPUT("IN1R"), +SND_SOC_DAPM_INPUT("IN2L"), +SND_SOC_DAPM_INPUT("IN2R"), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR, + ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_PGA("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0, + NULL, 0), + +WM_ADSP2("DSP2", 1, largo_adsp_power_ev), +WM_ADSP2("DSP3", 2, largo_adsp_power_ev), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3INT1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT3", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT4", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3DEC1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC3", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC4", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &largo_aec_loopback_mux), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), +ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), + +ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), +ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), +ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"), +ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"), +ARIZONA_MIXER_WIDGETS(SPKOUT, "SPKOUT"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), +ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"), +ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), +ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"), +ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"), +ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"), +ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"), +ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"), +ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), +ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"), + +ARIZONA_DSP_WIDGETS(DSP2, "DSP2"), +ARIZONA_DSP_WIDGETS(DSP3, "DSP3"), + +SND_SOC_DAPM_VIRT_MUX("DSP2 Virtual Input", SND_SOC_NOPM, 0, 0, + &largo_memory_mux[0]), +SND_SOC_DAPM_VIRT_MUX("DSP3 Virtual Input", SND_SOC_NOPM, 0, 0, + &largo_memory_mux[1]), + +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &largo_dsp_output_mux[0]), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), +ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"), +ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), +ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"), +ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"), + +ARIZONA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), +ARIZONA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), +ARIZONA_MUX_WIDGETS(ISRC3DEC3, "ISRC3DEC3"), +ARIZONA_MUX_WIDGETS(ISRC3DEC4, "ISRC3DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), +ARIZONA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), +ARIZONA_MUX_WIDGETS(ISRC3INT3, "ISRC3INT3"), +ARIZONA_MUX_WIDGETS(ISRC3INT4, "ISRC3INT4"), + +SND_SOC_DAPM_OUTPUT("HPOUT1L"), +SND_SOC_DAPM_OUTPUT("HPOUT1R"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF1RX7", "AIF1RX7" }, \ + { name, "AIF1RX8", "AIF1RX8" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF2RX3", "AIF2RX3" }, \ + { name, "AIF2RX4", "AIF2RX4" }, \ + { name, "AIF2RX5", "AIF2RX5" }, \ + { name, "AIF2RX6", "AIF2RX6" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ASRC1L", "ASRC1L" }, \ + { name, "ASRC1R", "ASRC1R" }, \ + { name, "ASRC2L", "ASRC2L" }, \ + { name, "ASRC2R", "ASRC2R" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2DEC3", "ISRC2DEC3" }, \ + { name, "ISRC2DEC4", "ISRC2DEC4" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC2INT3", "ISRC2INT3" }, \ + { name, "ISRC2INT4", "ISRC2INT4" }, \ + { name, "ISRC3DEC1", "ISRC3DEC1" }, \ + { name, "ISRC3DEC2", "ISRC3DEC2" }, \ + { name, "ISRC3DEC3", "ISRC3DEC3" }, \ + { name, "ISRC3DEC4", "ISRC3DEC4" }, \ + { name, "ISRC3INT1", "ISRC3INT1" }, \ + { name, "ISRC3INT2", "ISRC3INT2" }, \ + { name, "ISRC3INT3", "ISRC3INT3" }, \ + { name, "ISRC3INT4", "ISRC3INT4" }, \ + { name, "DSP2.1", "DSP2" }, \ + { name, "DSP2.2", "DSP2" }, \ + { name, "DSP2.3", "DSP2" }, \ + { name, "DSP2.4", "DSP2" }, \ + { name, "DSP2.5", "DSP2" }, \ + { name, "DSP2.6", "DSP2" }, \ + { name, "DSP3.1", "DSP3" }, \ + { name, "DSP3.2", "DSP3" }, \ + { name, "DSP3.3", "DSP3" }, \ + { name, "DSP3.4", "DSP3" }, \ + { name, "DSP3.5", "DSP3" }, \ + { name, "DSP3.6", "DSP3" } + +static const struct snd_soc_dapm_route largo_dapm_routes[] = { + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + + { "OUT4L", NULL, "SPKVDD" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT4L", NULL, "SYSCLK" }, + + { "IN1L", NULL, "SYSCLK" }, + { "IN1R", NULL, "SYSCLK" }, + { "IN2L", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, + + { "MICBIAS1", NULL, "MICVDD" }, + { "MICBIAS2", NULL, "MICVDD" }, + + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Noise Generator", NULL, "NOISE" }, + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + { "AIF1 Capture", NULL, "AIF1TX7" }, + { "AIF1 Capture", NULL, "AIF1TX8" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + { "AIF1RX7", NULL, "AIF1 Playback" }, + { "AIF1RX8", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + { "AIF2 Capture", NULL, "AIF2TX3" }, + { "AIF2 Capture", NULL, "AIF2TX4" }, + { "AIF2 Capture", NULL, "AIF2TX5" }, + { "AIF2 Capture", NULL, "AIF2TX6" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + { "AIF2RX3", NULL, "AIF2 Playback" }, + { "AIF2RX4", NULL, "AIF2 Playback" }, + { "AIF2RX5", NULL, "AIF2 Playback" }, + { "AIF2RX6", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + + { "Voice Control CPU", NULL, "Voice Control DSP" }, + { "Voice Control DSP", NULL, "DSP3" }, + { "Voice Control CPU", NULL, "SYSCLK" }, + { "Voice Control DSP", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP2" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, + + { "IN1L PGA", NULL, "IN1L" }, + { "IN1R PGA", NULL, "IN1R" }, + + { "IN2L PGA", NULL, "IN2L" }, + { "IN2R PGA", NULL, "IN2R" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), + ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), + + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUT"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"), + ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"), + ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"), + ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"), + ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), + ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), + + ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), + ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), + ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"), + ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"), + ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"), + ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"), + + ARIZONA_DSP_ROUTES("DSP2"), + ARIZONA_DSP_ROUTES("DSP3"), + + { "DSP2 Preloader", NULL, "DSP2 Virtual Input" }, + { "DSP2 Virtual Input", "Shared Memory", "DSP3" }, + { "DSP3 Preloader", NULL, "DSP3 Virtual Input" }, + { "DSP3 Virtual Input", "Shared Memory", "DSP2" }, + + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP3", "DSP3" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"), + ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + ARIZONA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), + ARIZONA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), + ARIZONA_MUX_ROUTES("ISRC3INT3", "ISRC3INT3"), + ARIZONA_MUX_ROUTES("ISRC3INT4", "ISRC3INT4"), + + ARIZONA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), + ARIZONA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), + ARIZONA_MUX_ROUTES("ISRC3DEC3", "ISRC3DEC3"), + ARIZONA_MUX_ROUTES("ISRC3DEC4", "ISRC3DEC4"), + + { "AEC Loopback", "HPOUT1L", "OUT1L" }, + { "AEC Loopback", "HPOUT1R", "OUT1R" }, + { "HPOUT1L", NULL, "OUT1L" }, + { "HPOUT1R", NULL, "OUT1R" }, + + { "AEC Loopback", "SPKOUT", "OUT4L" }, + { "SPKOUTN", NULL, "OUT4L" }, + { "SPKOUTP", NULL, "OUT4L" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, + { "DRC2 Signal Activity", NULL, "DRC2L" }, + { "DRC2 Signal Activity", NULL, "DRC2R" }, +}; + +static int largo_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct largo_priv *largo = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case LARGO_FLL1: + return arizona_set_fll(&largo->fll[0], source, Fref, Fout); + case LARGO_FLL2: + return arizona_set_fll(&largo->fll[1], source, Fref, Fout); + case LARGO_FLL1_REFCLK: + return arizona_set_fll_refclk(&largo->fll[0], source, Fref, + Fout); + case LARGO_FLL2_REFCLK: + return arizona_set_fll_refclk(&largo->fll[1], source, Fref, + Fout); + default: + return -EINVAL; + } +} + +#define LARGO_RATES SNDRV_PCM_RATE_KNOT + +#define LARGO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver largo_dai[] = { + { + .name = "largo-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "largo-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "largo-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "largo-cpu-voicectrl", + .capture = { + .stream_name = "Voice Control CPU", + .channels_min = 1, + .channels_max = 2, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "largo-dsp-voicectrl", + .capture = { + .stream_name = "Voice Control DSP", + .channels_min = 1, + .channels_max = 2, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + }, + { + .name = "largo-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 1, + .channels_max = 6, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "largo-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 1, + .channels_max = 6, + .rates = LARGO_RATES, + .formats = LARGO_FORMATS, + }, + }, +}; + +static void largo_compr_irq(struct largo_priv *largo, struct largo_compr *compr) +{ + struct arizona *arizona = largo->core.arizona; + bool trigger = false; + int ret; + + ret = wm_adsp_compr_irq(&compr->adsp_compr, &trigger); + if (ret < 0) + return; + + if (trigger && arizona->pdata.ez2ctrl_trigger) { + mutex_lock(&compr->trig_lock); + if (!compr->trig) { + compr->trig = true; + + if (wm_adsp_fw_has_voice_trig(compr->adsp_compr.dsp)) + arizona->pdata.ez2ctrl_trigger(); + } + mutex_unlock(&compr->trig_lock); + } +} + +static irqreturn_t largo_adsp2_irq(int irq, void *data) +{ + struct largo_priv *largo = data; + int i; + + for (i = 0; i < ARRAY_SIZE(largo->compr_info); ++i) { + if (!largo->compr_info[i].adsp_compr.dsp->running) + continue; + + largo_compr_irq(largo, &largo->compr_info[i]); + } + + return IRQ_HANDLED; +} + +static struct largo_compr *largo_get_compr(struct snd_soc_pcm_runtime *rtd, + struct largo_priv *largo) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(largo->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + largo->compr_info[i].dai_name) == 0) + return &largo->compr_info[i]; + } + + return NULL; +} + +static int largo_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct largo_priv *largo = snd_soc_codec_get_drvdata(rtd->codec); + struct arizona *arizona = largo->core.arizona; + struct largo_compr *compr; + + /* Find a compr_info for this DAI */ + compr = largo_get_compr(rtd, largo); + if (!compr) { + dev_err(arizona->dev, + "No suitable compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int largo_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *adsp_compr = + (struct wm_adsp_compr *)stream->runtime->private_data; + struct largo_compr *compr = container_of(adsp_compr, + struct largo_compr, + adsp_compr); + bool dummy; + int ret; + + ret = wm_adsp_compr_trigger(stream, cmd); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + /** + * If the firmware already triggered before the stream + * was opened process any outstanding data + */ + if (compr->trig) + wm_adsp_compr_irq(&compr->adsp_compr, &dummy); + break; + default: + break; + } + + return ret; +} + +static int largo_codec_probe(struct snd_soc_codec *codec) +{ + struct largo_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int ret; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_spk(codec); + arizona_init_gpio(codec); + arizona_init_mono(codec); + arizona_init_input(codec); + + ret = wm_adsp2_codec_probe(&priv->core.adsp[1], codec); + if (ret) + return ret; + + ret = wm_adsp2_codec_probe(&priv->core.adsp[2], codec); + if (ret) + return ret; + + ret = snd_soc_add_codec_controls(codec, + &arizona_adsp2_rate_controls[1], 2); + if (ret) + return ret; + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + mutex_unlock(&codec->card->dapm_mutex); + + priv->core.arizona->dapm = &codec->dapm; + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", largo_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_enable_pin(&codec->dapm, "DRC2 Signal Activity"); + mutex_unlock(&codec->card->dapm_mutex); + + ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ2_STATUS_3_MASK, + ARIZONA_IM_DRC2_SIG_DET_EINT2, + 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC2 IRQ for DSP: %d\n", + ret); + return ret; + } + + return 0; +} + +static int largo_codec_remove(struct snd_soc_codec *codec) +{ + struct largo_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + regmap_update_bits(arizona->regmap, ARIZONA_IRQ2_STATUS_3_MASK, + ARIZONA_IM_DRC2_SIG_DET_EINT2, + ARIZONA_IM_DRC2_SIG_DET_EINT2); + + wm_adsp2_codec_remove(&priv->core.adsp[1], codec); + wm_adsp2_codec_remove(&priv->core.adsp[2], codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define LARGO_DIG_VU 0x0200 + +static unsigned int largo_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_4L, +}; + +static struct snd_soc_codec_driver soc_codec_dev_largo = { + .probe = largo_codec_probe, + .remove = largo_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = largo_set_fll, + + .controls = largo_snd_controls, + .num_controls = ARRAY_SIZE(largo_snd_controls), + .dapm_widgets = largo_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(largo_dapm_widgets), + .dapm_routes = largo_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(largo_dapm_routes), +}; + +static struct snd_compr_ops largo_compr_ops = { + .open = largo_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = largo_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver largo_compr_platform = { + .compr_ops = &largo_compr_ops, +}; + +static void largo_init_compr_info(struct largo_priv *largo) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(largo->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(largo->compr_info); ++i) { + largo->compr_info[i].dai_name = compr_dai_mapping[i].dai_name; + + dsp = &largo->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &largo->compr_info[i].adsp_compr); + + mutex_init(&largo->compr_info[i].trig_lock); + } +} + +static void largo_destroy_compr_info(struct largo_priv *largo) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(largo->compr_info); ++i) + wm_adsp_compr_destroy(&largo->compr_info[i].adsp_compr); +} + +static int largo_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct largo_priv *largo; + int i, ret; + + BUILD_BUG_ON(ARRAY_SIZE(largo_dai) > ARIZONA_MAX_DAI); + + largo = devm_kzalloc(&pdev->dev, sizeof(struct largo_priv), + GFP_KERNEL); + if (largo == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, largo); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&largo->fw_lock); + + largo->core.arizona = arizona; + largo->core.num_inputs = 4; + + for (i = 1; i <= 2; i++) { + largo->core.adsp[i].part = "largo"; + largo->core.adsp[i].num = i + 1; + largo->core.adsp[i].type = WMFW_ADSP2; + largo->core.adsp[i].dev = arizona->dev; + largo->core.adsp[i].regmap = arizona->regmap; + + largo->core.adsp[i].base = ARIZONA_DSP1_CONTROL_1 + + (0x100 * i); + largo->core.adsp[i].mem = largo_dsp_regions[i - 1]; + largo->core.adsp[i].num_mems + = ARRAY_SIZE(largo_dsp2_regions); + + if (arizona->pdata.num_fw_defs[i]) { + largo->core.adsp[i].firmwares + = arizona->pdata.fw_defs[i]; + + largo->core.adsp[i].num_firmwares + = arizona->pdata.num_fw_defs[i]; + } + + largo->core.adsp[i].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&largo->core.adsp[i], &largo->fw_lock); + if (ret != 0) + goto error; + } + + largo_init_compr_info(largo); + + for (i = 0; i < ARRAY_SIZE(largo->fll); i++) + largo->fll[i].vco_mult = 3; + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &largo->fll[0]); + arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1, + ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, + &largo->fll[1]); + + for (i = 0; i < ARRAY_SIZE(largo_dai); i++) + arizona_init_dai(&largo->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(largo_digital_vu); i++) + regmap_update_bits(arizona->regmap, largo_digital_vu[i], + LARGO_DIG_VU, LARGO_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = snd_soc_register_platform(&pdev->dev, &largo_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_largo, + largo_dai, ARRAY_SIZE(largo_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + largo_destroy_compr_info(largo); + mutex_destroy(&largo->fw_lock); + + return ret; +} + +static int largo_remove(struct platform_device *pdev) +{ + struct largo_priv *largo = platform_get_drvdata(pdev); + + snd_soc_unregister_platform(&pdev->dev); + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + largo_destroy_compr_info(largo); + + wm_adsp2_remove(&largo->core.adsp[1]); + wm_adsp2_remove(&largo->core.adsp[2]); + + mutex_destroy(&largo->fw_lock); + + return 0; +} + +static struct platform_driver largo_codec_driver = { + .driver = { + .name = "largo-codec", + .owner = THIS_MODULE, + }, + .probe = largo_probe, + .remove = largo_remove, +}; + +module_platform_driver(largo_codec_driver); + +MODULE_DESCRIPTION("ASoC Largo driver"); +MODULE_AUTHOR("Richard Fitzgerald "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:largo-codec"); diff --git a/sound/soc/codecs/largo.h b/sound/soc/codecs/largo.h new file mode 100644 index 00000000000..10f49cf9a5c --- /dev/null +++ b/sound/soc/codecs/largo.h @@ -0,0 +1,23 @@ +/* + * largo.h -- ALSA SoC Audio driver for Largo + * + * Copyright 2014 Cirrus Logic + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LARGO_H +#define _LARGO_H + +#include "arizona.h" + +#define LARGO_FLL1 1 +#define LARGO_FLL2 2 +#define LARGO_FLL1_REFCLK 3 +#define LARGO_FLL2_REFCLK 4 + +#endif diff --git a/sound/soc/codecs/marley.c b/sound/soc/codecs/marley.c new file mode 100644 index 00000000000..035286f912f --- /dev/null +++ b/sound/soc/codecs/marley.c @@ -0,0 +1,2355 @@ +/* + * marley.c -- ALSA SoC Audio driver for Marley class devices + * + * Copyright 2015 Cirrus Logic + * + * Author: Piotr Stankiewicz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "wm_adsp.h" +#include "marley.h" + +#define MARLEY_NUM_ADSP 3 + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU + * are counted as one DAI + */ +#define MARLEY_NUM_COMPR_DAI 2 + +#define MARLEY_FRF_COEFFICIENT_LEN 4 + +#define MARLEY_FLL_COUNT 1 + +static int marley_frf_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define MARLEY_FRF_BYTES(xname, xbase, xregs) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = marley_frf_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } + +/* 2 mixer inputs with a stride of n in the register address */ +#define MARLEY_MIXER_INPUTS_2_N(_reg, n) \ + (_reg), \ + (_reg) + (1 * (n)) + +/* 4 mixer inputs with a stride of n in the register address */ +#define MARLEY_MIXER_INPUTS_4_N(_reg, n) \ + MARLEY_MIXER_INPUTS_2_N(_reg, n), \ + MARLEY_MIXER_INPUTS_2_N(_reg + (2 * n), n) + +#define MARLEY_DSP_MIXER_INPUTS(_reg) \ + MARLEY_MIXER_INPUTS_4_N(_reg, 2), \ + MARLEY_MIXER_INPUTS_4_N(_reg + 8, 2), \ + MARLEY_MIXER_INPUTS_4_N(_reg + 16, 8), \ + MARLEY_MIXER_INPUTS_2_N(_reg + 48, 8) + +static const int marley_fx_inputs[] = { + MARLEY_MIXER_INPUTS_4_N(ARIZONA_EQ1MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_EQ2MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_EQ3MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_EQ4MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_DRC1LMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_DRC1RMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_DRC2LMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_DRC2RMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_HPLP1MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_HPLP2MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_HPLP3MIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_HPLP4MIX_INPUT_1_SOURCE, 2), +}; + +static const int marley_isrc1_fsl_inputs[] = { + MARLEY_MIXER_INPUTS_4_N(ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int marley_isrc1_fsh_inputs[] = { + MARLEY_MIXER_INPUTS_4_N(ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int marley_isrc2_fsl_inputs[] = { + MARLEY_MIXER_INPUTS_4_N(ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int marley_isrc2_fsh_inputs[] = { + MARLEY_MIXER_INPUTS_4_N(ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int marley_out_inputs[] = { + MARLEY_MIXER_INPUTS_4_N(ARIZONA_OUT1LMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_OUT1RMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_OUT4LMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_OUT5LMIX_INPUT_1_SOURCE, 2), + MARLEY_MIXER_INPUTS_4_N(ARIZONA_OUT5RMIX_INPUT_1_SOURCE, 2), +}; + +static const int marley_spd1_inputs[] = { + MARLEY_MIXER_INPUTS_2_N(ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE, 8), +}; + +static const int marley_dsp1_inputs[] = { + MARLEY_DSP_MIXER_INPUTS(ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +}; + +static const int marley_dsp2_inputs[] = { + MARLEY_DSP_MIXER_INPUTS(ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +}; + +static const int marley_dsp3_inputs[] = { + MARLEY_DSP_MIXER_INPUTS(ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +}; + +static int marley_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define MARLEY_RATE_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_get_value_enum_double, .put = marley_rate_put, \ + .private_value = (unsigned long)&xenum } + +struct marley_priv; + +struct marley_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; + bool trig; + struct mutex trig_lock; + struct marley_priv *priv; +}; + +struct marley_priv { + struct arizona_priv core; + struct arizona_fll fll[MARLEY_FLL_COUNT]; + struct marley_compr compr_info[MARLEY_NUM_COMPR_DAI]; + + struct mutex fw_lock; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[MARLEY_NUM_COMPR_DAI] = { + { + .dai_name = "marley-dsp-voicectrl", + .adsp_num = 2, + }, + { + .dai_name = "marley-dsp-trace", + .adsp_num = 0, + }, +}; + +static const struct wm_adsp_region marley_dsp1_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x080000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, +}; + +static const struct wm_adsp_region marley_dsp2_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x100000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x160000 }, + { .type = WMFW_ADSP2_XM, .base = 0x120000 }, + { .type = WMFW_ADSP2_YM, .base = 0x140000 }, +}; + +static const struct wm_adsp_region marley_dsp3_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x180000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x1a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x1c0000 }, +}; + +static const struct wm_adsp_region *marley_dsp_regions[] = { + marley_dsp1_regions, + marley_dsp2_regions, + marley_dsp3_regions, +}; + +static const int wm_adsp2_control_bases[] = { + CLEARWATER_DSP1_CONFIG, + CLEARWATER_DSP2_CONFIG, + CLEARWATER_DSP3_CONFIG, +}; + +static const char * const marley_inmux_texts[] = { + "A", + "B", +}; + +static int marley_in1mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct marley_priv *marley = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = marley->core.arizona; + struct soc_enum *e = (struct soc_enum *) kcontrol->private_value; + unsigned int mux, inmode; + unsigned int mode_val, src_val; + bool changed = false; + int ret; + + mux = ucontrol->value.enumerated.item[0]; + if (mux > 1) + return -EINVAL; + + /* L and R registers have same shift and mask */ + inmode = arizona->pdata.inmode[2 * mux]; + src_val = mux << ARIZONA_IN1L_SRC_SHIFT; + if (inmode & ARIZONA_INMODE_SE) + src_val |= 1 << ARIZONA_IN1L_SRC_SE_SHIFT; + + switch (arizona->pdata.inmode[0]) { + case ARIZONA_INMODE_DMIC: + if (mux) + mode_val = 0; /* B always analogue */ + else + mode_val = 1 << ARIZONA_IN1_MODE_SHIFT; + + ret = snd_soc_update_bits(codec, ARIZONA_IN1L_CONTROL, + ARIZONA_IN1_MODE_MASK, + mode_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + /* IN1A is digital so L and R must change together */ + /* src_val setting same for both registers */ + + ret = snd_soc_update_bits(codec, ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_MASK | + ARIZONA_IN1L_SRC_SE_MASK, + src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + ret = snd_soc_update_bits(codec, ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_MASK | + ARIZONA_IN1R_SRC_SE_MASK, + src_val); + + if (ret < 0) + return ret; + else if (ret) + changed = true; + break; + default: + /* both analogue */ + ret = snd_soc_update_bits(codec, e->reg, + ARIZONA_IN1L_SRC_MASK | + ARIZONA_IN1L_SRC_SE_MASK, + src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + break; + } + + if (changed) + return snd_soc_dapm_mux_update_power(widget, kcontrol, + mux, e); + else + return 0; +} + +static const SOC_ENUM_SINGLE_DECL(marley_in1muxl_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_SHIFT, + marley_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(marley_in1muxr_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_SHIFT, + marley_inmux_texts); + +static const struct snd_kcontrol_new marley_in1mux[2] = { + SOC_DAPM_ENUM_EXT("IN1L Mux", marley_in1muxl_enum, + snd_soc_dapm_get_enum_double, marley_in1mux_put), + SOC_DAPM_ENUM_EXT("IN1R Mux", marley_in1muxr_enum, + snd_soc_dapm_get_enum_double, marley_in1mux_put), +}; + +static const char * const marley_outdemux_texts[] = { + "HPOUT", + "EPOUT", +}; + +static int marley_put_demux(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct snd_soc_card *card = codec->card; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int ep_sel, mux, change; + unsigned int mask; + int ret, demux_change_ret; + bool restore_out = true, out_mono; + + if (ucontrol->value.enumerated.item[0] > e->max - 1) + return -EINVAL; + mux = ucontrol->value.enumerated.item[0]; + ep_sel = mux << e->shift_l; + mask = e->mask << e->shift_l; + + mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + change = snd_soc_test_bits(codec, e->reg, mask, ep_sel); + /* if no change is required, skip */ + if (!change) + goto end; + + /* EP_SEL and OUT1_MONO should not be modified while HP or EP driver + * is enabled + */ + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret) + dev_warn(arizona->dev, + "Failed to disable outputs: %d\n", ret); + + usleep_range(2000, 3000); /* wait for wseq to complete */ + + /* [1] if HP detection clamp is applied while switching to HPOUT, OUT1 + * should remain disabled and EDRE should be set to Manual + */ + if (!ep_sel && (arizona->hpdet_clamp || + (arizona->hp_impedance_x100 <= + OHM_TO_HOHM(arizona->pdata.hpdet_short_circuit_imp)))) + restore_out = false; + + if (!ep_sel && arizona->hpdet_clamp) { + ret = regmap_write(arizona->regmap, CLEARWATER_EDRE_MANUAL, + 0x3); + if (ret) + dev_warn(arizona->dev, + "Failed to set EDRE Manual: %d\n", ret); + } + + /* change demux setting */ + demux_change_ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_EP_SEL, ep_sel); + if (demux_change_ret) { + dev_err(arizona->dev, "Failed to set EP_SEL: %d\n", + demux_change_ret); + } else { /* provided the switch to HP/EP was successful, update output + mode accordingly */ + /* when switching to stereo headphone */ + if (!ep_sel && !arizona->pdata.out_mono[0]) + out_mono = false; + /* when switching to mono headphone, or any earpiece */ + else + out_mono = true; + + ret = arizona_set_output_mode(codec, 1, out_mono); + if (ret < 0) + dev_warn(arizona->dev, + "Failed to set output mode: %d\n", ret); + } + + /* restore outputs to the desired state, or keep them disabled provided + * condition [1] arose + */ + if (restore_out) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, + arizona->hp_ena); + if (ret) { + dev_warn(arizona->dev, + "Failed to restore outputs: %d\n", ret); + } else { + /* wait for wseq */ + if (arizona->hp_ena) + msleep(34); /* enable delay */ + else + usleep_range(2000, 3000); /* disable delay */ + } + } + + /* provided a switch to EPOUT occured and succeded, set EDRE Manual + * to the proper value + */ + if (ep_sel && !demux_change_ret) { + ret = regmap_write(arizona->regmap, CLEARWATER_EDRE_MANUAL, 0); + if (ret) + dev_warn(arizona->dev, + "Failed to restore EDRE Manual: %d\n", ret); + } + +end: + mutex_unlock(&card->dapm_mutex); + + return snd_soc_dapm_put_enum_virt(kcontrol, ucontrol); +} + +static const SOC_ENUM_SINGLE_DECL(marley_outdemux_enum, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_EP_SEL_SHIFT, + marley_outdemux_texts); + +static const struct snd_kcontrol_new marley_outdemux = + SOC_DAPM_ENUM_EXT("OUT1 Demux", marley_outdemux_enum, + snd_soc_dapm_get_enum_double, marley_put_demux); + +static int marley_frf_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes *params = (void *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int ret, len; + void *data; + + len = params->num_regs * codec->val_bytes; + + data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA); + if (!data) { + ret = -ENOMEM; + goto out; + } + + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + + ret = regmap_raw_write(codec->control_data, params->base, + data, len); + + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + +out: + kfree(data); + return ret; +} + +/* Allow the worst case number of sources (FX Rate currently) */ +static unsigned int mixer_sources_cache[ARRAY_SIZE(marley_fx_inputs)]; + +static int marley_get_sources(unsigned int reg, const int **cur_sources, + int *lim) +{ + int ret = 0; + + switch (reg) { + case ARIZONA_FX_CTRL1: + *cur_sources = marley_fx_inputs; + *lim = ARRAY_SIZE(marley_fx_inputs); + break; + case ARIZONA_ISRC_1_CTRL_1: + *cur_sources = marley_isrc1_fsh_inputs; + *lim = ARRAY_SIZE(marley_isrc1_fsh_inputs); + break; + case ARIZONA_ISRC_1_CTRL_2: + *cur_sources = marley_isrc1_fsl_inputs; + *lim = ARRAY_SIZE(marley_isrc1_fsl_inputs); + break; + case ARIZONA_ISRC_2_CTRL_1: + *cur_sources = marley_isrc2_fsh_inputs; + *lim = ARRAY_SIZE(marley_isrc2_fsh_inputs); + break; + case ARIZONA_ISRC_2_CTRL_2: + *cur_sources = marley_isrc2_fsl_inputs; + *lim = ARRAY_SIZE(marley_isrc2_fsl_inputs); + break; + case ARIZONA_OUTPUT_RATE_1: + *cur_sources = marley_out_inputs; + *lim = ARRAY_SIZE(marley_out_inputs); + break; + case ARIZONA_SPD1_TX_CONTROL: + *cur_sources = marley_spd1_inputs; + *lim = ARRAY_SIZE(marley_spd1_inputs); + break; + case CLEARWATER_DSP1_CONFIG: + *cur_sources = marley_dsp1_inputs; + *lim = ARRAY_SIZE(marley_dsp1_inputs); + break; + case CLEARWATER_DSP2_CONFIG: + *cur_sources = marley_dsp2_inputs; + *lim = ARRAY_SIZE(marley_dsp2_inputs); + break; + case CLEARWATER_DSP3_CONFIG: + *cur_sources = marley_dsp3_inputs; + *lim = ARRAY_SIZE(marley_dsp3_inputs); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int marley_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret, err; + int lim; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + struct marley_priv *marley = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &marley->core; + struct arizona *arizona = priv->arizona; + + const int *cur_sources; + + unsigned int val, cur; + unsigned int mask; + + if (ucontrol->value.enumerated.item[0] > e->max - 1) + return -EINVAL; + + val = e->values[ucontrol->value.enumerated.item[0]] << e->shift_l; + mask = e->mask << e->shift_l; + + ret = regmap_read(arizona->regmap, e->reg, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current reg: %d\n", ret); + return ret; + } + + if ((cur & mask) == (val & mask)) + return 0; + + ret = marley_get_sources((int)e->reg, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + e->reg, + ret); + return ret; + } + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + /* Apply the rate through the original callback */ + clearwater_spin_sysclk(arizona); + ret = snd_soc_update_bits_locked(codec, e->reg, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int marley_adsp_rate_put_cb(struct wm_adsp *adsp, unsigned int mask, + unsigned int val) +{ + int ret, err; + int lim; + const int *cur_sources; + struct arizona *arizona = dev_get_drvdata(adsp->dev); + unsigned int cur; + + ret = regmap_read(adsp->regmap, adsp->base, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current: %d\n", ret); + return ret; + } + + if ((val & mask) == (cur & mask)) + return 0; + + ret = marley_get_sources(adsp->base, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + adsp->base, + ret); + return ret; + } + + dev_dbg(arizona->dev, "%s for DSP%d\n", __func__, adsp->num); + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + clearwater_spin_sysclk(arizona); + /* Apply the rate */ + ret = regmap_update_bits(adsp->regmap, adsp->base, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int marley_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct marley_priv *marley = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &marley->core; + struct arizona *arizona = priv->arizona; + + clearwater_spin_sysclk(arizona); + + return 0; +} + +static int marley_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct marley_priv *marley = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &marley->core; + struct arizona *arizona = priv->arizona; + unsigned int freq; + int i, ret; + + ret = regmap_read(arizona->regmap, CLEARWATER_DSP_CLOCK_1, &freq); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read CLEARWATER_DSP_CLOCK_1: %d\n", ret); + return ret; + } + + freq &= CLEARWATER_DSP_CLK_FREQ_LEGACY_MASK; + freq >>= CLEARWATER_DSP_CLK_FREQ_LEGACY_SHIFT; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + for (i = 0; i < ARRAY_SIZE(marley->compr_info); ++i) { + if (marley->compr_info[i].adsp_compr.dsp->num != + w->shift + 1) + continue; + + mutex_lock(&marley->compr_info[i].trig_lock); + marley->compr_info[i].trig = false; + mutex_unlock(&marley->compr_info[i].trig_lock); + } + break; + default: + break; + } + + return wm_adsp2_early_event(w, kcontrol, event, freq); +} + +static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -12000, 600, 0); + +#define MARLEY_NG_SRC(name, base) \ + SOC_SINGLE(name " NG OUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG OUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKDATL Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDATR Switch", base, 9, 1, 0) + +static int marley_cp_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + unsigned int val; + + regmap_read(arizona->regmap, CLEARWATER_CP_MODE, &val); + if (val == 0x400) + ucontrol->value.enumerated.item[0] = 0; + else + ucontrol->value.enumerated.item[0] = 1; + + return 0; +} + +static int marley_cp_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int val = ucontrol->value.enumerated.item[0]; + + if (val > e->max - 1) + return -EINVAL; + + mutex_lock(&arizona->reg_setting_lock); + if (val == 0) { /* Default */ + regmap_write(arizona->regmap, 0x80, 0x1); + regmap_write(arizona->regmap, CLEARWATER_CP_MODE, 0x400); + regmap_write(arizona->regmap, 0x80, 0x0); + } else {/* Inverting */ + regmap_write(arizona->regmap, 0x80, 0x1); + regmap_write(arizona->regmap, CLEARWATER_CP_MODE, 0x407); + regmap_write(arizona->regmap, 0x80, 0x0); + } + mutex_unlock(&arizona->reg_setting_lock); + + return 0; +} + +static const char * const marley_cp_mode_text[2] = { + "Default", "Inverting", +}; + +static const struct soc_enum marley_cp_mode[] = { + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(marley_cp_mode_text), + marley_cp_mode_text), +}; + +static const struct snd_kcontrol_new marley_snd_controls[] = { +SOC_VALUE_ENUM("IN1 OSR", clearwater_in_dmic_osr[0]), +SOC_VALUE_ENUM("IN2 OSR", clearwater_in_dmic_osr[1]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM_EXT("CP Mode", marley_cp_mode[0], + marley_cp_mode_get, marley_cp_mode_put), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +MARLEY_FRF_BYTES("FRF COEFF 1L", CLEARWATER_FRF_COEFFICIENT_1L_1, + MARLEY_FRF_COEFFICIENT_LEN), +MARLEY_FRF_BYTES("FRF COEFF 1R", CLEARWATER_FRF_COEFFICIENT_1R_1, + MARLEY_FRF_COEFFICIENT_LEN), +MARLEY_FRF_BYTES("FRF COEFF 4L", MARLEY_FRF_COEFFICIENT_4L_1, + MARLEY_FRF_COEFFICIENT_LEN), +MARLEY_FRF_BYTES("FRF COEFF 5L", MARLEY_FRF_COEFFICIENT_5L_1, + MARLEY_FRF_COEFFICIENT_LEN), +MARLEY_FRF_BYTES("FRF COEFF 5R", MARLEY_FRF_COEFFICIENT_5R_1, + MARLEY_FRF_COEFFICIENT_LEN), + +SND_SOC_BYTES("DAC COMP 1", CLEARWATER_DAC_COMP_1, 1), +SND_SOC_BYTES("DAC COMP 2", CLEARWATER_DAC_COMP_2, 1), + +ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), +SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), +SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), +SND_SOC_BYTES_MASK("DRC2", CLEARWATER_DRC2_CTRL1, 5, + ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +SOC_VALUE_ENUM("Sample Rate 2", arizona_sample_rate[0]), +SOC_VALUE_ENUM("Sample Rate 3", arizona_sample_rate[1]), + +MARLEY_RATE_ENUM("FX Rate", arizona_fx_rate), + +MARLEY_RATE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +MARLEY_RATE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +MARLEY_RATE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +MARLEY_RATE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), + +ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE), + +SOC_SINGLE_TLV("Noise Generator Volume", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv), + +ARIZONA_MIXER_CONTROLS("OUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("OUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUT", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDATL", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDATR", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), + +SOC_SINGLE("OUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_SHIFT, 1, 0), + +SOC_SINGLE("OUT1L ONEFLT Switch", ARIZONA_HP_TEST_CTRL_5, + ARIZONA_HP1L_ONEFLT_SHIFT, 1, 0), +SOC_SINGLE("OUT1R ONEFLT Switch", ARIZONA_HP_TEST_CTRL_6, + ARIZONA_HP1R_ONEFLT_SHIFT, 1, 0), + +SOC_SINGLE("SPKDAT High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L, + ARIZONA_OUT5_OSR_SHIFT, 1, 0), + +SOC_DOUBLE_R("OUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("OUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_DOUBLE("SPKDAT Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_EXT("OUT1 DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), + +SOC_DOUBLE("OUT1 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT1L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT1R_THR1_ENA_SHIFT, 1, 0), + +SOC_SINGLE("Speaker THR1 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT4L_THR1_ENA_SHIFT, 1, 0), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +MARLEY_RATE_ENUM("SPDIF Rate", arizona_spdif_rate), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +MARLEY_RATE_ENUM("Output Rate 1", arizona_output_rate), +SOC_VALUE_ENUM("In Rate", arizona_input_rate), + +MARLEY_NG_SRC("OUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +MARLEY_NG_SRC("OUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +MARLEY_NG_SRC("SPKOUT", ARIZONA_NOISE_GATE_SELECT_4L), +MARLEY_NG_SRC("SPKDATL", ARIZONA_NOISE_GATE_SELECT_5L), +MARLEY_NG_SRC("SPKDATR", ARIZONA_NOISE_GATE_SELECT_5R), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), + +ARIZONA_GAINMUX_CONTROLS("SPDIFTX1", ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SPDIFTX2", ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE), +}; + +CLEARWATER_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKOUT, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(SPD1TX1, ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(SPD1TX2, ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE); + +static const char * const marley_dsp_output_texts[] = { + "None", + "DSP3", +}; + +static const struct soc_enum marley_dsp_output_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(marley_dsp_output_texts), + marley_dsp_output_texts); + +static const struct snd_kcontrol_new marley_dsp_output_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", marley_dsp_output_enum), +}; + +static const char * const marley_memory_mux_texts[] = { + "None", + "Shared Memory", +}; + +static const struct soc_enum marley_memory_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(marley_memory_mux_texts), + marley_memory_mux_texts); + +static const struct snd_kcontrol_new marley_memory_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP2 Virtual Input", marley_memory_enum), + SOC_DAPM_ENUM_VIRT("DSP3 Virtual Input", marley_memory_enum), +}; + +static const char * const marley_aec_loopback_texts[] = { + "OUT1L", "OUT1R", "SPKOUT", "SPKDATL", "SPKDATR", +}; + +static const unsigned int marley_aec_loopback_values[] = { + 0, 1, 6, 8, 9, +}; + +static const struct soc_enum marley_aec_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(marley_aec_loopback_texts), + marley_aec_loopback_texts, + marley_aec_loopback_values); + +static const struct snd_kcontrol_new marley_aec_loopback_mux = + SOC_DAPM_VALUE_ENUM("AEC Loopback", marley_aec_loopback); + +static const struct snd_soc_dapm_widget marley_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, + 0, marley_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("DSPCLK", CLEARWATER_DSP_CLOCK_1, 6, + 0, NULL, 0), + + +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_INPUT("IN1AL"), +SND_SOC_DAPM_INPUT("IN1AR"), +SND_SOC_DAPM_INPUT("IN1BL"), +SND_SOC_DAPM_INPUT("IN1BR"), +SND_SOC_DAPM_INPUT("IN2L"), +SND_SOC_DAPM_INPUT("IN2R"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &marley_in1mux[0]), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &marley_in1mux[1]), + +SND_SOC_DAPM_DEMUX("OUT1 Demux", SND_SOC_NOPM, 0, 0, &marley_outdemux), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("MICBIAS1A", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1A_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1B", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1B_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2A", ARIZONA_MIC_BIAS_CTRL_6, + ARIZONA_MICB2A_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2B", ARIZONA_MIC_BIAS_CTRL_6, + ARIZONA_MICB2B_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Noise Generator", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +WM_ADSP2("DSP1", 0, marley_adsp_power_ev), +WM_ADSP2("DSP2", 1, marley_adsp_power_ev), +WM_ADSP2("DSP3", 2, marley_adsp_power_ev), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &marley_aec_loopback_mux), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, clearwater_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, clearwater_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_PGA("SPD1TX1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL1_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("SPD1TX2", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL2_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_OUT_DRV("SPD1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_ENA_SHIFT, 0, NULL, 0), + +ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), +ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), +ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"), +ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), + +ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), +ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), +ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "OUT1L"), +ARIZONA_MIXER_WIDGETS(OUT1R, "OUT1R"), +ARIZONA_MIXER_WIDGETS(SPKOUT, "SPKOUT"), +ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDATL"), +ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDATR"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"), + +ARIZONA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"), +ARIZONA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"), + +ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), +ARIZONA_DSP_WIDGETS(DSP2, "DSP2"), +ARIZONA_DSP_WIDGETS(DSP3, "DSP3"), + +SND_SOC_DAPM_VIRT_MUX("DSP2 Virtual Input", SND_SOC_NOPM, 0, 0, + &marley_memory_mux[0]), +SND_SOC_DAPM_VIRT_MUX("DSP3 Virtual Input", SND_SOC_NOPM, 0, 0, + &marley_memory_mux[1]), + +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &marley_dsp_output_mux[0]), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), +ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"), +ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), +ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"), +ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"), + +SND_SOC_DAPM_OUTPUT("HPOUTL"), +SND_SOC_DAPM_OUTPUT("HPOUTR"), +SND_SOC_DAPM_OUTPUT("EPOUTP"), +SND_SOC_DAPM_OUTPUT("EPOUTN"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), +SND_SOC_DAPM_OUTPUT("SPKDATL"), +SND_SOC_DAPM_OUTPUT("SPKDATR"), +SND_SOC_DAPM_OUTPUT("SPDIF"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "SLIMRX5", "SLIMRX5" }, \ + { name, "SLIMRX6", "SLIMRX6" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2DEC3", "ISRC2DEC3" }, \ + { name, "ISRC2DEC4", "ISRC2DEC4" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC2INT3", "ISRC2INT3" }, \ + { name, "ISRC2INT4", "ISRC2INT4" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" }, \ + { name, "DSP2.1", "DSP2" }, \ + { name, "DSP2.2", "DSP2" }, \ + { name, "DSP2.3", "DSP2" }, \ + { name, "DSP2.4", "DSP2" }, \ + { name, "DSP2.5", "DSP2" }, \ + { name, "DSP2.6", "DSP2" }, \ + { name, "DSP3.1", "DSP3" }, \ + { name, "DSP3.2", "DSP3" }, \ + { name, "DSP3.3", "DSP3" }, \ + { name, "DSP3.4", "DSP3" }, \ + { name, "DSP3.5", "DSP3" }, \ + { name, "DSP3.6", "DSP3" } + +static const struct snd_soc_dapm_route marley_dapm_routes[] = { + { "AIF2 Capture", NULL, "DBVDD2" }, + { "AIF2 Playback", NULL, "DBVDD2" }, + + { "AIF3 Capture", NULL, "DBVDD2" }, + { "AIF3 Playback", NULL, "DBVDD2" }, + + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + + { "OUT4L", NULL, "SPKVDD" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT4L", NULL, "SYSCLK" }, + { "OUT5L", NULL, "SYSCLK" }, + { "OUT5R", NULL, "SYSCLK" }, + + { "SPD1", NULL, "SYSCLK" }, + { "SPD1", NULL, "SPD1TX1" }, + { "SPD1", NULL, "SPD1TX2" }, + + { "IN1AL", NULL, "SYSCLK" }, + { "IN1AR", NULL, "SYSCLK" }, + { "IN1BL", NULL, "SYSCLK" }, + { "IN1BR", NULL, "SYSCLK" }, + { "IN2L", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, + + { "DSP1", NULL, "DSPCLK"}, + { "DSP2", NULL, "DSPCLK"}, + { "DSP3", NULL, "DSPCLK"}, + + { "MICBIAS1", NULL, "MICVDD" }, + { "MICBIAS2", NULL, "MICVDD" }, + + { "MICBIAS1A", NULL, "MICBIAS1" }, + { "MICBIAS1B", NULL, "MICBIAS1" }, + { "MICBIAS2A", NULL, "MICBIAS2" }, + { "MICBIAS2B", NULL, "MICBIAS2" }, + + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Noise Generator", NULL, "NOISE" }, + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + { "SLIMRX3", NULL, "Slim1 Playback" }, + { "SLIMRX4", NULL, "Slim1 Playback" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX5", NULL, "Slim2 Playback" }, + { "SLIMRX6", NULL, "Slim2 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + + { "Voice Control CPU", NULL, "Voice Control DSP" }, + { "Voice Control DSP", NULL, "DSP3" }, + { "Voice Control CPU", NULL, "SYSCLK" }, + { "Voice Control DSP", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP1" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, + + { "IN1L Mux", "A", "IN1AL" }, + { "IN1L Mux", "B", "IN1BL" }, + { "IN1R Mux", "A", "IN1AR" }, + { "IN1R Mux", "B", "IN1BR" }, + + { "IN1L PGA", NULL, "IN1L Mux" }, + { "IN1R PGA", NULL, "IN1R Mux" }, + + { "IN2L PGA", NULL, "IN2L" }, + { "IN2R PGA", NULL, "IN2R" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "OUT1L"), + ARIZONA_MIXER_ROUTES("OUT1R", "OUT1R"), + + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUT"), + + ARIZONA_MIXER_ROUTES("OUT5L", "SPKDATL"), + ARIZONA_MIXER_ROUTES("OUT5R", "SPKDATR"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"), + + ARIZONA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"), + ARIZONA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"), + + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), + ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), + ARIZONA_MIXER_ROUTES("EQ3", "EQ3"), + ARIZONA_MIXER_ROUTES("EQ4", "EQ4"), + + ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), + ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), + ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_DSP_ROUTES("DSP1"), + ARIZONA_DSP_ROUTES("DSP2"), + ARIZONA_DSP_ROUTES("DSP3"), + + { "DSP2 Preloader", NULL, "DSP2 Virtual Input" }, + { "DSP2 Virtual Input", "Shared Memory", "DSP3" }, + { "DSP3 Preloader", NULL, "DSP3 Virtual Input" }, + { "DSP3 Virtual Input", "Shared Memory", "DSP2" }, + + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP3", "DSP3" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"), + ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + { "AEC Loopback", "OUT1L", "OUT1L" }, + { "AEC Loopback", "OUT1R", "OUT1R" }, + { "OUT1 Demux", NULL, "OUT1L" }, + { "OUT1 Demux", NULL, "OUT1R" }, + + { "AEC Loopback", "SPKOUT", "OUT4L" }, + { "SPKOUTN", NULL, "OUT4L" }, + { "SPKOUTP", NULL, "OUT4L" }, + + { "HPOUTL", "HPOUT", "OUT1 Demux" }, + { "HPOUTR", "HPOUT", "OUT1 Demux" }, + { "EPOUTP", "EPOUT", "OUT1 Demux" }, + { "EPOUTN", "EPOUT", "OUT1 Demux" }, + + { "AEC Loopback", "SPKDATL", "OUT5L" }, + { "AEC Loopback", "SPKDATR", "OUT5R" }, + { "SPKDATL", NULL, "OUT5L" }, + { "SPKDATR", NULL, "OUT5R" }, + + { "SPDIF", NULL, "SPD1" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, + { "DRC2 Signal Activity", NULL, "DRC2L" }, + { "DRC2 Signal Activity", NULL, "DRC2R" }, +}; + +static int marley_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int fref, unsigned int fout) +{ + struct marley_priv *marley = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case MARLEY_FLL1: + return arizona_set_fll(&marley->fll[0], source, fref, fout); + case MARLEY_FLL1_REFCLK: + return arizona_set_fll_refclk(&marley->fll[0], source, fref, + fout); + default: + return -EINVAL; + } +} + +#define MARLEY_RATES SNDRV_PCM_RATE_KNOT + +#define MARLEY_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver marley_dai[] = { + { + .name = "marley-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "marley-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "marley-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "marley-slim1", + .id = 5, + .playback = { + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "marley-slim2", + .id = 6, + .playback = { + .stream_name = "Slim2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .capture = { + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "marley-cpu-voicectrl", + .capture = { + .stream_name = "Voice Control CPU", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "marley-dsp-voicectrl", + .capture = { + .stream_name = "Voice Control DSP", + .channels_min = 1, + .channels_max = 2, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + }, + { + .name = "marley-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 2, + .channels_max = 8, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "marley-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 2, + .channels_max = 8, + .rates = MARLEY_RATES, + .formats = MARLEY_FORMATS, + }, + }, +}; + +static void marley_compr_irq(struct marley_priv *marley, + struct marley_compr *compr) +{ + struct arizona *arizona = marley->core.arizona; + bool trigger = false; + int ret; + + ret = wm_adsp_compr_irq(&compr->adsp_compr, &trigger); + if (ret < 0) + return; + + if (trigger && arizona->pdata.ez2ctrl_trigger) { + mutex_lock(&compr->trig_lock); + if (!compr->trig) { + compr->trig = true; + + if (wm_adsp_fw_has_voice_trig(compr->adsp_compr.dsp)) + arizona->pdata.ez2ctrl_trigger(); + } + mutex_unlock(&compr->trig_lock); + } +} + +static irqreturn_t marley_adsp2_irq(int irq, void *data) +{ + struct marley_priv *marley = data; + int i; + + for (i = 0; i < ARRAY_SIZE(marley->compr_info); ++i) { + if (!marley->compr_info[i].adsp_compr.dsp->running) + continue; + + marley_compr_irq(marley, &marley->compr_info[i]); + } + return IRQ_HANDLED; +} + +static struct marley_compr *marley_get_compr(struct snd_soc_pcm_runtime *rtd, + struct marley_priv *marley) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(marley->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + marley->compr_info[i].dai_name) == 0) + return &marley->compr_info[i]; + } + + return NULL; +} + +static int marley_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct marley_priv *marley = snd_soc_codec_get_drvdata(rtd->codec); + struct marley_compr *compr; + + compr = marley_get_compr(rtd, marley); + if (!compr) { + dev_err(marley->core.arizona->dev, + "No compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int marley_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *adsp_compr = + (struct wm_adsp_compr *)stream->runtime->private_data; + struct marley_compr *compr = container_of(adsp_compr, + struct marley_compr, + adsp_compr); + struct arizona *arizona = compr->priv->core.arizona; + int ret; + + ret = wm_adsp_compr_trigger(stream, cmd); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (compr->trig) + /* + * If the firmware already triggered before the stream + * was opened trigger another interrupt so irq handler + * will run and process any outstanding data + */ + regmap_write(arizona->regmap, + CLEARWATER_ADSP2_IRQ0, 0x01); + break; + default: + break; + } + + return ret; +} + +static int marley_codec_probe(struct snd_soc_codec *codec) +{ + struct marley_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int i, ret; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_spk(codec); + arizona_init_gpio(codec); + arizona_init_mono(codec); + arizona_init_input(codec); + + /* Update Sample Rate 1 to 48kHz for cases when no AIF1 hw_params */ + regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_1, + ARIZONA_SAMPLE_RATE_1_MASK, 0x03); + + for (i = 0; i < MARLEY_NUM_ADSP; ++i) { + ret = wm_adsp2_codec_probe(&priv->core.adsp[i], codec); + if (ret) + return ret; + } + + ret = snd_soc_add_codec_controls(codec, + arizona_adsp2v2_rate_controls, + MARLEY_NUM_ADSP); + if (ret) + return ret; + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + mutex_unlock(&codec->card->dapm_mutex); + + priv->core.arizona->dapm = &codec->dapm; + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", marley_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_enable_pin(&codec->dapm, "DRC2 Signal Activity"); + mutex_unlock(&codec->card->dapm_mutex); + + ret = regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC2 IRQ for DSP: %d\n", + ret); + return ret; + } + + return 0; +} + +static int marley_codec_remove(struct snd_soc_codec *codec) +{ + struct marley_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int i; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + CLEARWATER_DRC2_SIG_DET_EINT2); + + for (i = 0; i < MARLEY_NUM_ADSP; ++i) + wm_adsp2_codec_remove(&priv->core.adsp[i], codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define MARLEY_DIG_VU 0x0200 + +static unsigned int marley_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, +}; + +static struct snd_soc_codec_driver soc_codec_dev_marley = { + .probe = marley_codec_probe, + .remove = marley_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = marley_set_fll, + + .controls = marley_snd_controls, + .num_controls = ARRAY_SIZE(marley_snd_controls), + .dapm_widgets = marley_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(marley_dapm_widgets), + .dapm_routes = marley_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(marley_dapm_routes), +}; + +static struct snd_compr_ops marley_compr_ops = { + .open = marley_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = marley_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver marley_compr_platform = { + .compr_ops = &marley_compr_ops, +}; + +static void marley_init_compr_info(struct marley_priv *marley) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(marley->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(marley->compr_info); ++i) { + marley->compr_info[i].priv = marley; + marley->compr_info[i].dai_name = + compr_dai_mapping[i].dai_name; + + dsp = &marley->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &marley->compr_info[i].adsp_compr); + + mutex_init(&marley->compr_info[i].trig_lock); + } +} + +static void marley_destroy_compr_info(struct marley_priv *marley) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(marley->compr_info); ++i) + wm_adsp_compr_destroy(&marley->compr_info[i].adsp_compr); +} + +static int marley_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct marley_priv *marley; + int i, ret; + + BUILD_BUG_ON(ARRAY_SIZE(marley_dai) > ARIZONA_MAX_DAI); + + marley = devm_kzalloc(&pdev->dev, sizeof(struct marley_priv), + GFP_KERNEL); + if (marley == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, marley); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&marley->fw_lock); + + marley->core.arizona = arizona; + marley->core.num_inputs = 4; + + for (i = 0; i < MARLEY_NUM_ADSP; i++) { + marley->core.adsp[i].part = "marley"; + if (arizona->pdata.rev_specific_fw) + marley->core.adsp[i].part_rev = 'a' + arizona->rev; + marley->core.adsp[i].num = i + 1; + marley->core.adsp[i].type = WMFW_ADSP2; + marley->core.adsp[i].rev = 1; + marley->core.adsp[i].dev = arizona->dev; + marley->core.adsp[i].regmap = arizona->regmap_32bit; + + marley->core.adsp[i].base = wm_adsp2_control_bases[i]; + marley->core.adsp[i].mem = marley_dsp_regions[i]; + marley->core.adsp[i].num_mems + = ARRAY_SIZE(marley_dsp1_regions); + + if (arizona->pdata.num_fw_defs[i]) { + marley->core.adsp[i].firmwares + = arizona->pdata.fw_defs[i]; + + marley->core.adsp[i].num_firmwares + = arizona->pdata.num_fw_defs[i]; + } + + marley->core.adsp[i].rate_put_cb = marley_adsp_rate_put_cb; + + marley->core.adsp[i].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&marley->core.adsp[i], &marley->fw_lock); + if (ret != 0) + return ret; + } + + marley_init_compr_info(marley); + + for (i = 0; i < ARRAY_SIZE(marley->fll); i++) { + marley->fll[i].vco_mult = 3; + marley->fll[i].min_outdiv = 3; + marley->fll[i].max_outdiv = 3; + marley->fll[i].sync_offset = 0xE; + } + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &marley->fll[0]); + + for (i = 0; i < ARRAY_SIZE(marley_dai); i++) + arizona_init_dai(&marley->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(marley_digital_vu); i++) + regmap_update_bits(arizona->regmap, marley_digital_vu[i], + MARLEY_DIG_VU, MARLEY_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = snd_soc_register_platform(&pdev->dev, &marley_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_marley, + marley_dai, ARRAY_SIZE(marley_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + marley_destroy_compr_info(marley); + mutex_destroy(&marley->fw_lock); + + return ret; +} + +static int marley_remove(struct platform_device *pdev) +{ + struct marley_priv *marley = platform_get_drvdata(pdev); + int i; + + snd_soc_unregister_platform(&pdev->dev); + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + marley_destroy_compr_info(marley); + + for (i = 0; i < MARLEY_NUM_ADSP; i++) + wm_adsp2_remove(&marley->core.adsp[i]); + + mutex_destroy(&marley->fw_lock); + + return 0; +} + +static struct platform_driver marley_codec_driver = { + .driver = { + .name = "marley-codec", + .owner = THIS_MODULE, + }, + .probe = marley_probe, + .remove = marley_remove, +}; + +module_platform_driver(marley_codec_driver); + +MODULE_DESCRIPTION("ASoC Marley driver"); +MODULE_AUTHOR("Piotr Stankiewicz "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:marley-codec"); diff --git a/sound/soc/codecs/marley.h b/sound/soc/codecs/marley.h new file mode 100644 index 00000000000..972f3bd6cc5 --- /dev/null +++ b/sound/soc/codecs/marley.h @@ -0,0 +1,21 @@ +/* + * marley.h -- ALSA SoC Audio driver for Marley class codecs + * + * Copyright 2015 Cirrus Logic + * + * Author: Piotr Stankiewicz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MARLEY_H +#define _MARLEY_H + +#include "arizona.h" + +#define MARLEY_FLL1 1 +#define MARLEY_FLL1_REFCLK 3 + +#endif diff --git a/sound/soc/codecs/moon.c b/sound/soc/codecs/moon.c new file mode 100644 index 00000000000..1ebc0453715 --- /dev/null +++ b/sound/soc/codecs/moon.c @@ -0,0 +1,3110 @@ +/* + * moon.c -- ALSA SoC Audio driver for MOON-class devices + * + * Copyright 2015 Cirrus Logic + * + * Author: Nikesh Oswal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "wm_adsp.h" +#include "moon.h" + +#define MOON_NUM_ADSP 7 + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU + * are counted as one DAI + */ +#define MOON_NUM_COMPR_DAI 2 + +#define MOON_FRF_COEFFICIENT_LEN 4 + +static int moon_frf_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define MOON_FRF_BYTES(xname, xbase, xregs) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = moon_frf_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } + +/* 2 mixer inputs with a stride of n in the register address */ +#define MOON_MIXER_INPUTS_2_N(_reg, n) \ + (_reg), \ + (_reg) + (1 * (n)) + +/* 4 mixer inputs with a stride of n in the register address */ +#define MOON_MIXER_INPUTS_4_N(_reg, n) \ + MOON_MIXER_INPUTS_2_N(_reg, n), \ + MOON_MIXER_INPUTS_2_N(_reg + (2 * n), n) + +#define MOON_DSP_MIXER_INPUTS(_reg) \ + MOON_MIXER_INPUTS_4_N(_reg, 2), \ + MOON_MIXER_INPUTS_4_N(_reg + 8, 2), \ + MOON_MIXER_INPUTS_4_N(_reg + 16, 8), \ + MOON_MIXER_INPUTS_2_N(_reg + 48, 8) + +static const int moon_fx_inputs[] = { + MOON_MIXER_INPUTS_4_N(ARIZONA_EQ1MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_EQ2MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_EQ3MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_EQ4MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_DRC1LMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_DRC1RMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_DRC2LMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_DRC2RMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_HPLP1MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_HPLP2MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_HPLP3MIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_HPLP4MIX_INPUT_1_SOURCE, 2), +}; + +static const int moon_asrc1_1_inputs[] = { + MOON_MIXER_INPUTS_2_N(CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_asrc1_2_inputs[] = { + MOON_MIXER_INPUTS_2_N(CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_asrc2_1_inputs[] = { + MOON_MIXER_INPUTS_2_N(CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_asrc2_2_inputs[] = { + MOON_MIXER_INPUTS_2_N(CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc1_fsl_inputs[] = { + MOON_MIXER_INPUTS_4_N(ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc1_fsh_inputs[] = { + MOON_MIXER_INPUTS_4_N(ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc2_fsl_inputs[] = { + MOON_MIXER_INPUTS_4_N(ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc2_fsh_inputs[] = { + MOON_MIXER_INPUTS_4_N(ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc3_fsl_inputs[] = { + MOON_MIXER_INPUTS_2_N(ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc3_fsh_inputs[] = { + MOON_MIXER_INPUTS_2_N(ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc4_fsl_inputs[] = { + MOON_MIXER_INPUTS_2_N(ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_isrc4_fsh_inputs[] = { + MOON_MIXER_INPUTS_2_N(ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_out_inputs[] = { + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT1LMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT1RMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT2LMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT2RMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT3LMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT3RMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT5LMIX_INPUT_1_SOURCE, 2), + MOON_MIXER_INPUTS_4_N(ARIZONA_OUT5RMIX_INPUT_1_SOURCE, 2), +}; + +static const int moon_spd1_inputs[] = { + MOON_MIXER_INPUTS_2_N(ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE, 8), +}; + +static const int moon_dsp1_inputs[] = { + MOON_DSP_MIXER_INPUTS(ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +}; + +static const int moon_dsp2_inputs[] = { + MOON_DSP_MIXER_INPUTS(ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +}; + +static const int moon_dsp3_inputs[] = { + MOON_DSP_MIXER_INPUTS(ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +}; + +static const int moon_dsp4_inputs[] = { + MOON_DSP_MIXER_INPUTS(ARIZONA_DSP4LMIX_INPUT_1_SOURCE), +}; + +static const int moon_dsp5_inputs[] = { + MOON_DSP_MIXER_INPUTS(CLEARWATER_DSP5LMIX_INPUT_1_SOURCE), +}; + +static const int moon_dsp6_inputs[] = { + MOON_DSP_MIXER_INPUTS(CLEARWATER_DSP6LMIX_INPUT_1_SOURCE), +}; + +static const int moon_dsp7_inputs[] = { + MOON_DSP_MIXER_INPUTS(CLEARWATER_DSP7LMIX_INPUT_1_SOURCE), +}; + +static int moon_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define MOON_RATE_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_get_value_enum_double, .put = moon_rate_put, \ + .private_value = (unsigned long)&xenum } + +struct moon_priv; + +struct moon_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; + bool trig; + struct mutex trig_lock; + struct moon_priv *priv; +}; + +struct moon_priv { + struct arizona_priv core; + struct arizona_fll fll[3]; + struct moon_compr compr_info[MOON_NUM_COMPR_DAI]; + + struct mutex fw_lock; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[MOON_NUM_COMPR_DAI] = { + { + .dai_name = "moon-dsp6-voicectrl", + .adsp_num = 5, + }, + { + .dai_name = "moon-dsp-trace", + .adsp_num = 0, + }, +}; + +static const struct wm_adsp_region moon_dsp1_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x080000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x0a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x0c0000 }, +}; + +static const struct wm_adsp_region moon_dsp2_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x100000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x160000 }, + { .type = WMFW_ADSP2_XM, .base = 0x120000 }, + { .type = WMFW_ADSP2_YM, .base = 0x140000 }, +}; + +static const struct wm_adsp_region moon_dsp3_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x180000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x1a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x1c0000 }, +}; + +static const struct wm_adsp_region moon_dsp4_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x200000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x260000 }, + { .type = WMFW_ADSP2_XM, .base = 0x220000 }, + { .type = WMFW_ADSP2_YM, .base = 0x240000 }, +}; + +static const struct wm_adsp_region moon_dsp5_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x280000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x2e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x2a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x2c0000 }, +}; + +static const struct wm_adsp_region moon_dsp6_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x300000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x360000 }, + { .type = WMFW_ADSP2_XM, .base = 0x320000 }, + { .type = WMFW_ADSP2_YM, .base = 0x340000 }, +}; + +static const struct wm_adsp_region moon_dsp7_regions[] = { + { .type = WMFW_ADSP2_PM, .base = 0x380000 }, + { .type = WMFW_ADSP2_ZM, .base = 0x3e0000 }, + { .type = WMFW_ADSP2_XM, .base = 0x3a0000 }, + { .type = WMFW_ADSP2_YM, .base = 0x3c0000 }, +}; + +static const struct wm_adsp_region *moon_dsp_regions[] = { + moon_dsp1_regions, + moon_dsp2_regions, + moon_dsp3_regions, + moon_dsp4_regions, + moon_dsp5_regions, + moon_dsp6_regions, + moon_dsp7_regions, +}; + +static const int wm_adsp2_control_bases[] = { + CLEARWATER_DSP1_CONFIG, + CLEARWATER_DSP2_CONFIG, + CLEARWATER_DSP3_CONFIG, + CLEARWATER_DSP4_CONFIG, + CLEARWATER_DSP5_CONFIG, + CLEARWATER_DSP6_CONFIG, + CLEARWATER_DSP7_CONFIG, +}; + +static const int moon_adsp_bus_error_irqs[MOON_NUM_ADSP] = { + MOON_IRQ_DSP1_BUS_ERROR, + MOON_IRQ_DSP2_BUS_ERROR, + MOON_IRQ_DSP3_BUS_ERROR, + MOON_IRQ_DSP4_BUS_ERROR, + MOON_IRQ_DSP5_BUS_ERROR, + MOON_IRQ_DSP6_BUS_ERROR, + MOON_IRQ_DSP7_BUS_ERROR, +}; + +static const char * const moon_inmux_texts[] = { + "A", + "B", +}; + +static const SOC_ENUM_SINGLE_DECL(moon_in1muxl_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_SHIFT, + moon_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(moon_in1muxr_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_SHIFT, + moon_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(moon_in2muxl_enum, + ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_SRC_SHIFT, + moon_inmux_texts); + +static const struct snd_kcontrol_new moon_in1mux[2] = { + SOC_DAPM_ENUM("IN1L Mux", moon_in1muxl_enum), + SOC_DAPM_ENUM("IN1R Mux", moon_in1muxr_enum), +}; + +static const struct snd_kcontrol_new moon_in2mux = + SOC_DAPM_ENUM("IN2L Mux", moon_in2muxl_enum); + +static int moon_frf_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct soc_bytes *params = (void *)kcontrol->private_value; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->arizona; + int ret, len; + void *data; + + len = params->num_regs * codec->val_bytes; + + data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA); + if (!data) { + ret = -ENOMEM; + goto out; + } + + mutex_lock(&arizona->reg_setting_lock); + regmap_write(arizona->regmap, 0x80, 0x3); + + ret = regmap_raw_write(codec->control_data, params->base, + data, len); + + regmap_write(arizona->regmap, 0x80, 0x0); + mutex_unlock(&arizona->reg_setting_lock); + +out: + kfree(data); + return ret; +} + +/* Allow the worst case number of sources (FX Rate currently) */ +static unsigned int mixer_sources_cache[ARRAY_SIZE(moon_fx_inputs)]; + +static int moon_get_sources(unsigned int reg, + const int **cur_sources, int *lim) +{ + int ret = 0; + + switch (reg) { + case ARIZONA_FX_CTRL1: + *cur_sources = moon_fx_inputs; + *lim = ARRAY_SIZE(moon_fx_inputs); + break; + case CLEARWATER_ASRC1_RATE1: + *cur_sources = moon_asrc1_1_inputs; + *lim = ARRAY_SIZE(moon_asrc1_1_inputs); + break; + case CLEARWATER_ASRC1_RATE2: + *cur_sources = moon_asrc1_2_inputs; + *lim = ARRAY_SIZE(moon_asrc1_2_inputs); + break; + case CLEARWATER_ASRC2_RATE1: + *cur_sources = moon_asrc2_1_inputs; + *lim = ARRAY_SIZE(moon_asrc2_1_inputs); + break; + case CLEARWATER_ASRC2_RATE2: + *cur_sources = moon_asrc2_2_inputs; + *lim = ARRAY_SIZE(moon_asrc2_2_inputs); + break; + case ARIZONA_ISRC_1_CTRL_1: + *cur_sources = moon_isrc1_fsh_inputs; + *lim = ARRAY_SIZE(moon_isrc1_fsh_inputs); + break; + case ARIZONA_ISRC_1_CTRL_2: + *cur_sources = moon_isrc1_fsl_inputs; + *lim = ARRAY_SIZE(moon_isrc1_fsl_inputs); + break; + case ARIZONA_ISRC_2_CTRL_1: + *cur_sources = moon_isrc2_fsh_inputs; + *lim = ARRAY_SIZE(moon_isrc2_fsh_inputs); + break; + case ARIZONA_ISRC_2_CTRL_2: + *cur_sources = moon_isrc2_fsl_inputs; + *lim = ARRAY_SIZE(moon_isrc2_fsl_inputs); + break; + case ARIZONA_ISRC_3_CTRL_1: + *cur_sources = moon_isrc3_fsh_inputs; + *lim = ARRAY_SIZE(moon_isrc3_fsh_inputs); + break; + case ARIZONA_ISRC_3_CTRL_2: + *cur_sources = moon_isrc3_fsl_inputs; + *lim = ARRAY_SIZE(moon_isrc3_fsl_inputs); + break; + case ARIZONA_ISRC_4_CTRL_1: + *cur_sources = moon_isrc4_fsh_inputs; + *lim = ARRAY_SIZE(moon_isrc4_fsh_inputs); + break; + case ARIZONA_ISRC_4_CTRL_2: + *cur_sources = moon_isrc4_fsl_inputs; + *lim = ARRAY_SIZE(moon_isrc4_fsl_inputs); + break; + case ARIZONA_OUTPUT_RATE_1: + *cur_sources = moon_out_inputs; + *lim = ARRAY_SIZE(moon_out_inputs); + break; + case ARIZONA_SPD1_TX_CONTROL: + *cur_sources = moon_spd1_inputs; + *lim = ARRAY_SIZE(moon_spd1_inputs); + break; + case CLEARWATER_DSP1_CONFIG: + *cur_sources = moon_dsp1_inputs; + *lim = ARRAY_SIZE(moon_dsp1_inputs); + break; + case CLEARWATER_DSP2_CONFIG: + *cur_sources = moon_dsp2_inputs; + *lim = ARRAY_SIZE(moon_dsp2_inputs); + break; + case CLEARWATER_DSP3_CONFIG: + *cur_sources = moon_dsp3_inputs; + *lim = ARRAY_SIZE(moon_dsp3_inputs); + break; + case CLEARWATER_DSP4_CONFIG: + *cur_sources = moon_dsp4_inputs; + *lim = ARRAY_SIZE(moon_dsp4_inputs); + break; + case CLEARWATER_DSP5_CONFIG: + *cur_sources = moon_dsp5_inputs; + *lim = ARRAY_SIZE(moon_dsp5_inputs); + break; + case CLEARWATER_DSP6_CONFIG: + *cur_sources = moon_dsp6_inputs; + *lim = ARRAY_SIZE(moon_dsp6_inputs); + break; + case CLEARWATER_DSP7_CONFIG: + *cur_sources = moon_dsp7_inputs; + *lim = ARRAY_SIZE(moon_dsp7_inputs); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int moon_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret, err; + int lim; + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + struct moon_priv *moon = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &moon->core; + struct arizona *arizona = priv->arizona; + + const int *cur_sources; + + unsigned int val, cur; + unsigned int mask; + + if (ucontrol->value.enumerated.item[0] > e->max - 1) + return -EINVAL; + + val = e->values[ucontrol->value.enumerated.item[0]] << e->shift_l; + mask = e->mask << e->shift_l; + + ret = regmap_read(arizona->regmap, e->reg, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current reg: %d\n", ret); + return ret; + } + + if ((cur & mask) == (val & mask)) + return 0; + + ret = moon_get_sources((int)e->reg, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + e->reg, + ret); + return ret; + } + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + /* Apply the rate through the original callback */ + clearwater_spin_sysclk(arizona); + ret = snd_soc_update_bits_locked(codec, e->reg, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int moon_adsp_rate_put_cb(struct wm_adsp *adsp, + unsigned int mask, + unsigned int val) +{ + int ret, err; + int lim; + const int *cur_sources; + struct arizona *arizona = dev_get_drvdata(adsp->dev); + unsigned int cur; + + ret = regmap_read(adsp->regmap, adsp->base, &cur); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read current: %d\n", ret); + return ret; + } + + if ((val & mask) == (cur & mask)) + return 0; + + ret = moon_get_sources(adsp->base, &cur_sources, &lim); + if (ret != 0) { + dev_err(arizona->dev, "Failed to get sources for 0x%08x: %d\n", + adsp->base, + ret); + return ret; + } + + dev_dbg(arizona->dev, "%s for DSP%d\n", __func__, adsp->num); + + mutex_lock(&arizona->rate_lock); + + ret = arizona_cache_and_clear_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (ret != 0) { + dev_err(arizona->dev, + "%s Failed to cache and clear sources %d\n", + __func__, + ret); + goto out; + } + + clearwater_spin_sysclk(arizona); + /* Apply the rate */ + ret = regmap_update_bits(adsp->regmap, adsp->base, mask, val); + clearwater_spin_sysclk(arizona); + +out: + err = arizona_restore_sources(arizona, cur_sources, + mixer_sources_cache, lim); + + if (err != 0) { + dev_err(arizona->dev, + "%s Failed to restore sources %d\n", + __func__, + err); + } + + mutex_unlock(&arizona->rate_lock); + return ret; +} + +static int moon_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct moon_priv *moon = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &moon->core; + struct arizona *arizona = priv->arizona; + + clearwater_spin_sysclk(arizona); + + return 0; +} + +static int moon_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct moon_priv *moon = snd_soc_codec_get_drvdata(codec); + struct arizona_priv *priv = &moon->core; + struct arizona *arizona = priv->arizona; + unsigned int freq; + int i, ret; + + ret = regmap_read(arizona->regmap, CLEARWATER_DSP_CLOCK_2, &freq); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read CLEARWATER_DSP_CLOCK_2: %d\n", ret); + return ret; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + for (i = 0; i < ARRAY_SIZE(moon->compr_info); ++i) { + if (moon->compr_info[i].adsp_compr.dsp->num != + w->shift + 1) + continue; + + mutex_lock(&moon->compr_info[i].trig_lock); + moon->compr_info[i].trig = false; + mutex_unlock(&moon->compr_info[i].trig_lock); + } + break; + default: + break; + } + + return wm_adsp2_early_event(w, kcontrol, event, freq); +} + +static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -12000, 600, 0); + +#define MOON_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ + SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) + +#define MOON_RXANC_INPUT_ROUTES(widget, name) \ + { widget, NULL, name " NG Mux" }, \ + { name " NG Internal", NULL, "RXANC NG Clock" }, \ + { name " NG Internal", NULL, name " Channel" }, \ + { name " NG External", NULL, "RXANC NG External Clock" }, \ + { name " NG External", NULL, name " Channel" }, \ + { name " NG Mux", "None", name " Channel" }, \ + { name " NG Mux", "Internal", name " NG Internal" }, \ + { name " NG Mux", "External", name " NG External" }, \ + { name " Channel", "Left", name " Left Input" }, \ + { name " Channel", "Combine", name " Left Input" }, \ + { name " Channel", "Right", name " Right Input" }, \ + { name " Channel", "Combine", name " Right Input" }, \ + { name " Left Input", "IN1", "IN1L PGA" }, \ + { name " Right Input", "IN1", "IN1R PGA" }, \ + { name " Left Input", "IN2", "IN2L PGA" }, \ + { name " Right Input", "IN2", "IN2R PGA" }, \ + { name " Left Input", "IN3", "IN3L PGA" }, \ + { name " Right Input", "IN3", "IN3R PGA" }, \ + { name " Left Input", "IN4", "IN4L PGA" }, \ + { name " Right Input", "IN4", "IN4R PGA" }, \ + { name " Left Input", "IN5", "IN5L PGA" }, \ + { name " Right Input", "IN5", "IN5R PGA" } + +#define MOON_RXANC_OUTPUT_ROUTES(widget, name) \ + { widget, NULL, name " ANC Source" }, \ + { name " ANC Source", "RXANCL", "RXANCL" }, \ + { name " ANC Source", "RXANCR", "RXANCR" } + +static const struct snd_kcontrol_new moon_snd_controls[] = { +SOC_VALUE_ENUM("IN1 OSR", clearwater_in_dmic_osr[0]), +SOC_VALUE_ENUM("IN2 OSR", clearwater_in_dmic_osr[1]), +SOC_VALUE_ENUM("IN3 OSR", clearwater_in_dmic_osr[2]), +SOC_VALUE_ENUM("IN4 OSR", clearwater_in_dmic_osr[3]), +SOC_VALUE_ENUM("IN5 OSR", clearwater_in_dmic_osr[4]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE_EXT("IN1L LP Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, + MOON_IN1L_LP_MODE_SHIFT, 1, 0, + snd_soc_get_volsw, moon_lp_mode_put), +SOC_SINGLE_EXT("IN1R LP Switch", ARIZONA_ADC_DIGITAL_VOLUME_1R, + MOON_IN1L_LP_MODE_SHIFT, 1, 0, + snd_soc_get_volsw, moon_lp_mode_put), +SOC_SINGLE_EXT("IN2L LP Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, + MOON_IN1L_LP_MODE_SHIFT, 1, 0, + snd_soc_get_volsw, moon_lp_mode_put), +SOC_SINGLE_EXT("IN2R LP Switch", ARIZONA_ADC_DIGITAL_VOLUME_2R, + MOON_IN1L_LP_MODE_SHIFT, 1, 0, + snd_soc_get_volsw, moon_lp_mode_put), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2L HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2R HPF Switch", ARIZONA_IN2R_CONTROL, + ARIZONA_IN2R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN3L HPF Switch", ARIZONA_IN3L_CONTROL, + ARIZONA_IN3L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN3R HPF Switch", ARIZONA_IN3R_CONTROL, + ARIZONA_IN3R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN4L HPF Switch", ARIZONA_IN4L_CONTROL, + ARIZONA_IN4L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN4R HPF Switch", ARIZONA_IN4R_CONTROL, + ARIZONA_IN4R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN5L HPF Switch", ARIZONA_IN5L_CONTROL, + ARIZONA_IN5L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN5R HPF Switch", ARIZONA_IN5R_CONTROL, + ARIZONA_IN5R_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, + ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, + ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R, + ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, + ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R, + ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN5L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_5L, + ARIZONA_IN5L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN5R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_5R, + ARIZONA_IN5R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +SND_SOC_BYTES("RXANC Coefficients", ARIZONA_ANC_COEFF_START, + ARIZONA_ANC_COEFF_END - ARIZONA_ANC_COEFF_START + 1), +SND_SOC_BYTES("RXANCL Config", ARIZONA_FCL_FILTER_CONTROL, 1), +SND_SOC_BYTES("RXANCL Coefficients", ARIZONA_FCL_COEFF_START, + ARIZONA_FCL_COEFF_END - ARIZONA_FCL_COEFF_START + 1), +SND_SOC_BYTES("RXANCR Config", CLEARWATER_FCR_FILTER_CONTROL, 1), +SND_SOC_BYTES("RXANCR Coefficients", CLEARWATER_FCR_COEFF_START, + CLEARWATER_FCR_COEFF_END - CLEARWATER_FCR_COEFF_START + 1), + +MOON_FRF_BYTES("FRF COEFF 1L", CLEARWATER_FRF_COEFFICIENT_1L_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 1R", CLEARWATER_FRF_COEFFICIENT_1R_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 2L", CLEARWATER_FRF_COEFFICIENT_2L_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 2R", CLEARWATER_FRF_COEFFICIENT_2R_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 3L", CLEARWATER_FRF_COEFFICIENT_3L_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 3R", CLEARWATER_FRF_COEFFICIENT_3R_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 5L", CLEARWATER_FRF_COEFFICIENT_5L_1, + MOON_FRF_COEFFICIENT_LEN), +MOON_FRF_BYTES("FRF COEFF 5R", CLEARWATER_FRF_COEFFICIENT_5R_1, + MOON_FRF_COEFFICIENT_LEN), + +SND_SOC_BYTES("DAC COMP 1", CLEARWATER_DAC_COMP_1, 1), +SND_SOC_BYTES("DAC COMP 2", CLEARWATER_DAC_COMP_2, 1), + +ARIZONA_MIXER_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), +SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), +SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), +SND_SOC_BYTES_MASK("DRC2", CLEARWATER_DRC2_CTRL1, 5, + ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +SND_SOC_BYTES("LHPF1 Coefficients", ARIZONA_HPLPF1_2, 1), +SND_SOC_BYTES("LHPF2 Coefficients", ARIZONA_HPLPF2_2, 1), +SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1), +SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +SOC_VALUE_ENUM("Sample Rate 2", arizona_sample_rate[0]), +SOC_VALUE_ENUM("Sample Rate 3", arizona_sample_rate[1]), +SOC_VALUE_ENUM("ASYNC Sample Rate 2", arizona_sample_rate[2]), + +MOON_RATE_ENUM("FX Rate", arizona_fx_rate), + +MOON_RATE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +MOON_RATE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +MOON_RATE_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]), +MOON_RATE_ENUM("ISRC4 FSL", arizona_isrc_fsl[3]), +MOON_RATE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +MOON_RATE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), +MOON_RATE_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]), +MOON_RATE_ENUM("ISRC4 FSH", arizona_isrc_fsh[3]), +MOON_RATE_ENUM("ASRC1 Rate 1", clearwater_asrc1_rate[0]), +MOON_RATE_ENUM("ASRC1 Rate 2", clearwater_asrc1_rate[1]), +MOON_RATE_ENUM("ASRC2 Rate 1", clearwater_asrc2_rate[0]), +MOON_RATE_ENUM("ASRC2 Rate 2", clearwater_asrc2_rate[1]), + +ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP4L", ARIZONA_DSP4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP4R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP5L", CLEARWATER_DSP5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP5R", CLEARWATER_DSP5RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP6L", CLEARWATER_DSP6LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP6R", CLEARWATER_DSP6RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP7L", CLEARWATER_DSP7LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("DSP7R", CLEARWATER_DSP7RMIX_INPUT_1_SOURCE), + +SOC_SINGLE_TLV("Noise Generator Volume", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_GAIN_SHIFT, 0x16, 0, noise_tlv), + +ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT2L", ARIZONA_OUT2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT2R", ARIZONA_OUT2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT3L", ARIZONA_OUT3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUT3R", ARIZONA_OUT3RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), + +SOC_SINGLE("HPOUT1 SC Protect Switch", ARIZONA_HP1_SHORT_CIRCUIT_CTRL, + ARIZONA_HP1_SC_ENA_SHIFT, 1, 0), +SOC_SINGLE("HPOUT2 SC Protect Switch", ARIZONA_HP2_SHORT_CIRCUIT_CTRL, + ARIZONA_HP2_SC_ENA_SHIFT, 1, 0), +SOC_SINGLE("HPOUT3 SC Protect Switch", ARIZONA_HP3_SHORT_CIRCUIT_CTRL, + ARIZONA_HP3_SC_ENA_SHIFT, 1, 0), + +SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L, + ARIZONA_OUT5_OSR_SHIFT, 1, 0), + +SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("HPOUT3 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_EXT("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE1L_ENA_SHIFT, VEGAS_DRE1R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), +SOC_DOUBLE_EXT("HPOUT2 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE2L_ENA_SHIFT, VEGAS_DRE2R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), +SOC_DOUBLE_EXT("HPOUT3 DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE3L_ENA_SHIFT, VEGAS_DRE3R_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, clearwater_put_dre), + +SOC_DOUBLE("HPOUT1 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT1L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT1R_THR1_ENA_SHIFT, 1, 0), +SOC_DOUBLE("HPOUT2 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT2L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT2R_THR1_ENA_SHIFT, 1, 0), +SOC_DOUBLE("HPOUT3 EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT3L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT3R_THR1_ENA_SHIFT, 1, 0), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +MOON_RATE_ENUM("SPDIF Rate", arizona_spdif_rate), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +MOON_RATE_ENUM("Output Rate 1", arizona_output_rate), + +SOC_VALUE_ENUM_EXT("IN1L Rate", moon_input_rate[0], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN1R Rate", moon_input_rate[1], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN2L Rate", moon_input_rate[2], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN2R Rate", moon_input_rate[3], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN3L Rate", moon_input_rate[4], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN3R Rate", moon_input_rate[5], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN4L Rate", moon_input_rate[6], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN4R Rate", moon_input_rate[7], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN5L Rate", moon_input_rate[8], + snd_soc_get_value_enum_double, moon_in_rate_put), +SOC_VALUE_ENUM_EXT("IN5R Rate", moon_input_rate[9], + snd_soc_get_value_enum_double, moon_in_rate_put), + +SOC_VALUE_ENUM_EXT("DFC1RX Width", moon_dfc_width[0], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC1RX Type", moon_dfc_type[0], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC1TX Width", moon_dfc_width[1], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC1TX Type", moon_dfc_type[1], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC2RX Width", moon_dfc_width[2], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC2RX Type", moon_dfc_type[2], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC2TX Width", moon_dfc_width[3], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC2TX Type", moon_dfc_type[3], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC3RX Width", moon_dfc_width[4], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC3RX Type", moon_dfc_type[4], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC3TX Width", moon_dfc_width[5], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC3TX Type", moon_dfc_type[5], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC4RX Width", moon_dfc_width[6], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC4RX Type", moon_dfc_type[6], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC4TX Width", moon_dfc_width[7], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC4TX Type", moon_dfc_type[7], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC5RX Width", moon_dfc_width[8], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC5RX Type", moon_dfc_type[8], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC5TX Width", moon_dfc_width[9], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC5TX Type", moon_dfc_type[9], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC6RX Width", moon_dfc_width[10], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC6RX Type", moon_dfc_type[10], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC6TX Width", moon_dfc_width[11], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC6TX Type", moon_dfc_type[11], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC7RX Width", moon_dfc_width[12], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC7RX Type", moon_dfc_type[12], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC7TX Width", moon_dfc_width[13], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC7TX Type", moon_dfc_type[13], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC8RX Width", moon_dfc_width[14], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC8RX Type", moon_dfc_type[14], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC8TX Width", moon_dfc_width[15], + snd_soc_get_value_enum_double, moon_dfc_put), +SOC_VALUE_ENUM_EXT("DFC8TX Type", moon_dfc_type[15], + snd_soc_get_value_enum_double, moon_dfc_put), + +MOON_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +MOON_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +MOON_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), +MOON_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R), +MOON_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L), +MOON_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R), +MOON_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +MOON_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX7", ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX7", ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX8", ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF4TX1", ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF4TX2", ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE), + +ARIZONA_GAINMUX_CONTROLS("SPDIFTX1", ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SPDIFTX2", ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE), +}; + +CLEARWATER_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP2L, ARIZONA_DSP2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP2R, ARIZONA_DSP2RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP2, ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP3L, ARIZONA_DSP3LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP3R, ARIZONA_DSP3RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP3, ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP4L, ARIZONA_DSP4LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP4R, ARIZONA_DSP4RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP4, ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP5L, CLEARWATER_DSP5LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP5R, CLEARWATER_DSP5RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP5, CLEARWATER_DSP5AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP6L, CLEARWATER_DSP6LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP6R, CLEARWATER_DSP6RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP6, CLEARWATER_DSP6AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(DSP7L, CLEARWATER_DSP7LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(DSP7R, CLEARWATER_DSP7RMIX_INPUT_1_SOURCE); +CLEARWATER_DSP_AUX_ENUMS(DSP7, CLEARWATER_DSP7AUX1MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT3L, ARIZONA_OUT3LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(OUT3R, ARIZONA_OUT3RMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX7, ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX7, ARIZONA_AIF2TX7MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF2TX8, ARIZONA_AIF2TX8MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(AIF4TX1, ARIZONA_AIF4TX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(AIF4TX2, ARIZONA_AIF4TX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE); +CLEARWATER_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(SPD1TX1, ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(SPD1TX2, ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ASRC1IN1L, CLEARWATER_ASRC1_1LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC1IN1R, CLEARWATER_ASRC1_1RMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC1IN2L, CLEARWATER_ASRC1_2LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC1IN2R, CLEARWATER_ASRC1_2RMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN1L, CLEARWATER_ASRC2_1LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN1R, CLEARWATER_ASRC2_1RMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN2L, CLEARWATER_ASRC2_2LMIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ASRC2IN2R, CLEARWATER_ASRC2_2RMIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT3, ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2INT4, ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC3, ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC2DEC4, ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC3INT1, ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC3INT2, ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC3DEC1, ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC3DEC2, ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC4INT1, ARIZONA_ISRC4INT1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC4INT2, ARIZONA_ISRC4INT2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(ISRC4DEC1, ARIZONA_ISRC4DEC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(ISRC4DEC2, ARIZONA_ISRC4DEC2MIX_INPUT_1_SOURCE); + +CLEARWATER_MUX_ENUMS(DFC1, MOON_DFC1MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC2, MOON_DFC2MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC3, MOON_DFC3MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC4, MOON_DFC4MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC5, MOON_DFC5MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC6, MOON_DFC6MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC7, MOON_DFC7MIX_INPUT_1_SOURCE); +CLEARWATER_MUX_ENUMS(DFC8, MOON_DFC8MIX_INPUT_1_SOURCE); + +static const char * const moon_dsp_output_texts[] = { + "None", + "DSP6", +}; + +static const struct soc_enum moon_dsp_output_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(moon_dsp_output_texts), + moon_dsp_output_texts); + +static const struct snd_kcontrol_new moon_dsp_output_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", moon_dsp_output_enum), +}; + +static const char * const moon_memory_mux_texts[] = { + "None", + "Shared Memory", +}; + +static const struct soc_enum moon_memory_enum = + SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(moon_memory_mux_texts), + moon_memory_mux_texts); + +static const struct snd_kcontrol_new moon_memory_mux[] = { + SOC_DAPM_ENUM_VIRT("DSP2 Virtual Input", moon_memory_enum), + SOC_DAPM_ENUM_VIRT("DSP3 Virtual Input", moon_memory_enum), +}; + +static const char * const moon_aec_loopback_texts[] = { + "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R", + "SPKDAT1L", "SPKDAT1R", +}; + +static const unsigned int moon_aec_loopback_values[] = { + 0, 1, 2, 3, 4, 5, 8, 9, +}; + +static const struct soc_enum moon_aec_loopback = + SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + ARRAY_SIZE(moon_aec_loopback_texts), + moon_aec_loopback_texts, + moon_aec_loopback_values); + +static const struct snd_kcontrol_new moon_aec_loopback_mux = + SOC_DAPM_VALUE_ENUM("AEC Loopback", moon_aec_loopback); + +static const struct snd_kcontrol_new moon_anc_input_mux[] = { + SOC_DAPM_ENUM("RXANCL Input", clearwater_anc_input_src[0]), + SOC_DAPM_ENUM("RXANCL Channel", clearwater_anc_input_src[1]), + SOC_DAPM_ENUM("RXANCR Input", clearwater_anc_input_src[2]), + SOC_DAPM_ENUM("RXANCR Channel", clearwater_anc_input_src[3]), +}; + +static const struct snd_kcontrol_new moon_anc_ng_mux = + SOC_DAPM_ENUM_VIRT("RXANC NG Source", arizona_anc_ng_enum); + +static const struct snd_kcontrol_new moon_output_anc_src[] = { + SOC_DAPM_ENUM("HPOUT1L ANC Source", arizona_output_anc_src[0]), + SOC_DAPM_ENUM("HPOUT1R ANC Source", arizona_output_anc_src[1]), + SOC_DAPM_ENUM("HPOUT2L ANC Source", arizona_output_anc_src[2]), + SOC_DAPM_ENUM("HPOUT2R ANC Source", arizona_output_anc_src[3]), + SOC_DAPM_ENUM("HPOUT3L ANC Source", arizona_output_anc_src[4]), + SOC_DAPM_ENUM("HPOUT3R ANC Source", clearwater_output_anc_src_defs[0]), + SOC_DAPM_ENUM("SPKDAT1L ANC Source", arizona_output_anc_src[8]), + SOC_DAPM_ENUM("SPKDAT1R ANC Source", arizona_output_anc_src[9]), +}; + +static const struct snd_soc_dapm_widget moon_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, + 0, moon_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, + ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK, + ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("DSPCLK", CLEARWATER_DSP_CLOCK_1, 6, + 0, NULL, 0), + + +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD4", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_SIGGEN("NOISE"), + +SND_SOC_DAPM_INPUT("IN1AL"), +SND_SOC_DAPM_INPUT("IN1BL"), +SND_SOC_DAPM_INPUT("IN1AR"), +SND_SOC_DAPM_INPUT("IN1BR"), +SND_SOC_DAPM_INPUT("IN2AL"), +SND_SOC_DAPM_INPUT("IN2BL"), +SND_SOC_DAPM_INPUT("IN2R"), +SND_SOC_DAPM_INPUT("IN3L"), +SND_SOC_DAPM_INPUT("IN3R"), +SND_SOC_DAPM_INPUT("IN4L"), +SND_SOC_DAPM_INPUT("IN4R"), +SND_SOC_DAPM_INPUT("IN5L"), +SND_SOC_DAPM_INPUT("IN5R"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &moon_in1mux[0]), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &moon_in1mux[1]), +SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &moon_in2mux), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), +SND_SOC_DAPM_OUTPUT("DRC2 Signal Activity"), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("MICBIAS1A", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1A_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1B", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1B_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1C", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1C_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS1D", ARIZONA_MIC_BIAS_CTRL_5, + ARIZONA_MICB1D_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("MICBIAS2A", ARIZONA_MIC_BIAS_CTRL_6, + ARIZONA_MICB2A_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2B", ARIZONA_MIC_BIAS_CTRL_6, + ARIZONA_MICB2B_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2C", ARIZONA_MIC_BIAS_CTRL_6, + ARIZONA_MICB2C_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2D", ARIZONA_MIC_BIAS_CTRL_6, + ARIZONA_MICB2D_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("RXANC NG External Clock", SND_SOC_NOPM, + ARIZONA_EXT_NG_SEL_SET_SHIFT, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA("RXANCL NG External", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("RXANCR NG External", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_SUPPLY("RXANC NG Clock", SND_SOC_NOPM, + ARIZONA_CLK_NG_ENA_SET_SHIFT, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA("RXANCL NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0), +SND_SOC_DAPM_PGA("RXANCR NG Internal", SND_SOC_NOPM, 0, 0, NULL, 0), + +SND_SOC_DAPM_MUX("RXANCL Left Input", SND_SOC_NOPM, 0, 0, + &moon_anc_input_mux[0]), +SND_SOC_DAPM_MUX("RXANCL Right Input", SND_SOC_NOPM, 0, 0, + &moon_anc_input_mux[0]), +SND_SOC_DAPM_MUX("RXANCL Channel", SND_SOC_NOPM, 0, 0, &moon_anc_input_mux[1]), +SND_SOC_DAPM_VIRT_MUX("RXANCL NG Mux", SND_SOC_NOPM, 0, 0, &moon_anc_ng_mux), +SND_SOC_DAPM_MUX("RXANCR Left Input", SND_SOC_NOPM, 0, 0, + &moon_anc_input_mux[2]), +SND_SOC_DAPM_MUX("RXANCR Right Input", SND_SOC_NOPM, 0, 0, + &moon_anc_input_mux[2]), +SND_SOC_DAPM_MUX("RXANCR Channel", SND_SOC_NOPM, 0, 0, &moon_anc_input_mux[3]), +SND_SOC_DAPM_VIRT_MUX("RXANCR NG Mux", SND_SOC_NOPM, 0, 0, &moon_anc_ng_mux), + +SND_SOC_DAPM_PGA_E("RXANCL", SND_SOC_NOPM, ARIZONA_CLK_L_ENA_SET_SHIFT, + 0, NULL, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_PGA_E("RXANCR", SND_SOC_NOPM, ARIZONA_CLK_R_ENA_SET_SHIFT, + 0, NULL, 0, arizona_anc_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + +SND_SOC_DAPM_MUX("HPOUT1L ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[0]), +SND_SOC_DAPM_MUX("HPOUT1R ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[1]), +SND_SOC_DAPM_MUX("HPOUT2L ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[2]), +SND_SOC_DAPM_MUX("HPOUT2R ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[3]), +SND_SOC_DAPM_MUX("HPOUT3L ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[4]), +SND_SOC_DAPM_MUX("HPOUT3R ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[5]), +SND_SOC_DAPM_MUX("SPKDAT1L ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[6]), +SND_SOC_DAPM_MUX("SPKDAT1R ANC Source", SND_SOC_NOPM, 0, 0, + &moon_output_anc_src[7]), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX7", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX8", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX7", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX8", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF4TX1", NULL, 0, + ARIZONA_AIF4_TX_ENABLES, ARIZONA_AIF4TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF4TX2", NULL, 0, + ARIZONA_AIF4_TX_ENABLES, ARIZONA_AIF4TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_PGA("SPD1TX1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL1_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("SPD1TX2", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL2_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_OUT_DRV("SPD1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_ENA_SHIFT, 0, NULL, 0), + +/* mux_in widgets : arranged in the order of sources + specified in ARIZONA_MIXER_INPUT_ROUTES */ + +SND_SOC_DAPM_PGA("Noise Generator", CLEARWATER_COMFORT_NOISE_GENERATOR, + CLEARWATER_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &moon_aec_loopback_mux), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN3L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN3R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN4L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN4R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN5L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN5L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN5R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN5R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX7", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX8", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX7", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX8", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF4RX1", NULL, 0, + ARIZONA_AIF4_RX_ENABLES, ARIZONA_AIF4RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF4RX2", NULL, 0, + ARIZONA_AIF4_RX_ENABLES, ARIZONA_AIF4RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2L", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC2R", CLEARWATER_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("ASRC1IN1L", CLEARWATER_ASRC1_ENABLE, + CLEARWATER_ASRC1_IN1L_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC1IN1R", CLEARWATER_ASRC1_ENABLE, + CLEARWATER_ASRC1_IN1R_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC1IN2L", CLEARWATER_ASRC1_ENABLE, + CLEARWATER_ASRC1_IN2L_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC1IN2R", CLEARWATER_ASRC1_ENABLE, + CLEARWATER_ASRC1_IN2R_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ASRC2IN1L", CLEARWATER_ASRC2_ENABLE, + CLEARWATER_ASRC2_IN1L_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC2IN1R", CLEARWATER_ASRC2_ENABLE, + CLEARWATER_ASRC2_IN1R_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC2IN2L", CLEARWATER_ASRC2_ENABLE, + CLEARWATER_ASRC2_IN2L_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ASRC2IN2R", CLEARWATER_ASRC2_ENABLE, + CLEARWATER_ASRC2_IN2R_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT3", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT4", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3DEC1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3DEC2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC3INT1", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC3INT2", ARIZONA_ISRC_3_CTRL_3, + ARIZONA_ISRC3_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC4DEC1", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC4DEC2", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC4INT1", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC4INT2", ARIZONA_ISRC_4_CTRL_3, + ARIZONA_ISRC4_INT1_ENA_SHIFT, 0, NULL, 0), + +WM_ADSP2("DSP1", 0, moon_adsp_power_ev), +WM_ADSP2("DSP2", 1, moon_adsp_power_ev), +WM_ADSP2("DSP3", 2, moon_adsp_power_ev), +WM_ADSP2("DSP4", 3, moon_adsp_power_ev), +WM_ADSP2("DSP5", 4, moon_adsp_power_ev), +WM_ADSP2("DSP6", 5, moon_adsp_power_ev), +WM_ADSP2("DSP7", 6, moon_adsp_power_ev), + +SND_SOC_DAPM_PGA("DFC1", MOON_DFC1_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC2", MOON_DFC2_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC3", MOON_DFC3_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC4", MOON_DFC4_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC5", MOON_DFC5_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC6", MOON_DFC6_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC7", MOON_DFC7_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("DFC8", MOON_DFC8_CTRL, + MOON_DFC1_ENA_SHIFT, 0, NULL, 0), + +ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), +ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), +ARIZONA_MIXER_WIDGETS(EQ3, "EQ3"), +ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), + +ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), +ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), +ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"), +ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"), +ARIZONA_MIXER_WIDGETS(OUT2L, "HPOUT2L"), +ARIZONA_MIXER_WIDGETS(OUT2R, "HPOUT2R"), +ARIZONA_MIXER_WIDGETS(OUT3L, "HPOUT3L"), +ARIZONA_MIXER_WIDGETS(OUT3R, "HPOUT3R"), +ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"), +ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), +ARIZONA_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"), +ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), +ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"), +ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"), +ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"), +ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"), +ARIZONA_MIXER_WIDGETS(AIF2TX7, "AIF2TX7"), +ARIZONA_MIXER_WIDGETS(AIF2TX8, "AIF2TX8"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MIXER_WIDGETS(AIF4TX1, "AIF4TX1"), +ARIZONA_MIXER_WIDGETS(AIF4TX2, "AIF4TX2"), + +ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"), +ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"), +ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"), + +ARIZONA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"), +ARIZONA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"), + +ARIZONA_MUX_WIDGETS(ASRC1IN1L, "ASRC1IN1L"), +ARIZONA_MUX_WIDGETS(ASRC1IN1R, "ASRC1IN1R"), +ARIZONA_MUX_WIDGETS(ASRC1IN2L, "ASRC1IN2L"), +ARIZONA_MUX_WIDGETS(ASRC1IN2R, "ASRC1IN2R"), +ARIZONA_MUX_WIDGETS(ASRC2IN1L, "ASRC2IN1L"), +ARIZONA_MUX_WIDGETS(ASRC2IN1R, "ASRC2IN1R"), +ARIZONA_MUX_WIDGETS(ASRC2IN2L, "ASRC2IN2L"), +ARIZONA_MUX_WIDGETS(ASRC2IN2R, "ASRC2IN2R"), + + +ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), +ARIZONA_DSP_WIDGETS(DSP2, "DSP2"), +ARIZONA_DSP_WIDGETS(DSP3, "DSP3"), +ARIZONA_DSP_WIDGETS(DSP4, "DSP4"), +ARIZONA_DSP_WIDGETS(DSP5, "DSP5"), +ARIZONA_DSP_WIDGETS(DSP6, "DSP6"), +ARIZONA_DSP_WIDGETS(DSP7, "DSP7"), + +SND_SOC_DAPM_VIRT_MUX("DSP2 Virtual Input", SND_SOC_NOPM, 0, 0, + &moon_memory_mux[0]), +SND_SOC_DAPM_VIRT_MUX("DSP3 Virtual Input", SND_SOC_NOPM, 0, 0, + &moon_memory_mux[1]), + +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &moon_dsp_output_mux[0]), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), +ARIZONA_MUX_WIDGETS(ISRC2DEC3, "ISRC2DEC3"), +ARIZONA_MUX_WIDGETS(ISRC2DEC4, "ISRC2DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), +ARIZONA_MUX_WIDGETS(ISRC2INT3, "ISRC2INT3"), +ARIZONA_MUX_WIDGETS(ISRC2INT4, "ISRC2INT4"), + +ARIZONA_MUX_WIDGETS(ISRC3DEC1, "ISRC3DEC1"), +ARIZONA_MUX_WIDGETS(ISRC3DEC2, "ISRC3DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC3INT1, "ISRC3INT1"), +ARIZONA_MUX_WIDGETS(ISRC3INT2, "ISRC3INT2"), + +ARIZONA_MUX_WIDGETS(ISRC4DEC1, "ISRC4DEC1"), +ARIZONA_MUX_WIDGETS(ISRC4DEC2, "ISRC4DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC4INT1, "ISRC4INT1"), +ARIZONA_MUX_WIDGETS(ISRC4INT2, "ISRC4INT2"), + +ARIZONA_MUX_WIDGETS(DFC1, "DFC1"), +ARIZONA_MUX_WIDGETS(DFC2, "DFC2"), +ARIZONA_MUX_WIDGETS(DFC3, "DFC3"), +ARIZONA_MUX_WIDGETS(DFC4, "DFC4"), +ARIZONA_MUX_WIDGETS(DFC5, "DFC5"), +ARIZONA_MUX_WIDGETS(DFC6, "DFC6"), +ARIZONA_MUX_WIDGETS(DFC7, "DFC7"), +ARIZONA_MUX_WIDGETS(DFC8, "DFC8"), + +SND_SOC_DAPM_OUTPUT("HPOUT1L"), +SND_SOC_DAPM_OUTPUT("HPOUT1R"), +SND_SOC_DAPM_OUTPUT("HPOUT2L"), +SND_SOC_DAPM_OUTPUT("HPOUT2R"), +SND_SOC_DAPM_OUTPUT("HPOUT3L"), +SND_SOC_DAPM_OUTPUT("HPOUT3R"), +SND_SOC_DAPM_OUTPUT("SPKDAT1L"), +SND_SOC_DAPM_OUTPUT("SPKDAT1R"), +SND_SOC_DAPM_OUTPUT("SPDIF"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Noise Generator", "Noise Generator" }, \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2L PGA" }, \ + { name, "IN2R", "IN2R PGA" }, \ + { name, "IN3L", "IN3L PGA" }, \ + { name, "IN3R", "IN3R PGA" }, \ + { name, "IN4L", "IN4L PGA" }, \ + { name, "IN4R", "IN4R PGA" }, \ + { name, "IN5L", "IN5L PGA" }, \ + { name, "IN5R", "IN5R PGA" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF1RX7", "AIF1RX7" }, \ + { name, "AIF1RX8", "AIF1RX8" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF2RX3", "AIF2RX3" }, \ + { name, "AIF2RX4", "AIF2RX4" }, \ + { name, "AIF2RX5", "AIF2RX5" }, \ + { name, "AIF2RX6", "AIF2RX6" }, \ + { name, "AIF2RX7", "AIF2RX7" }, \ + { name, "AIF2RX8", "AIF2RX8" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "AIF4RX1", "AIF4RX1" }, \ + { name, "AIF4RX2", "AIF4RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "SLIMRX5", "SLIMRX5" }, \ + { name, "SLIMRX6", "SLIMRX6" }, \ + { name, "SLIMRX7", "SLIMRX7" }, \ + { name, "SLIMRX8", "SLIMRX8" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "DRC2L", "DRC2L" }, \ + { name, "DRC2R", "DRC2R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ASRC1IN1L", "ASRC1IN1L" }, \ + { name, "ASRC1IN1R", "ASRC1IN1R" }, \ + { name, "ASRC1IN2L", "ASRC1IN2L" }, \ + { name, "ASRC1IN2R", "ASRC1IN2R" }, \ + { name, "ASRC2IN1L", "ASRC2IN1L" }, \ + { name, "ASRC2IN1R", "ASRC2IN1R" }, \ + { name, "ASRC2IN2L", "ASRC2IN2L" }, \ + { name, "ASRC2IN2R", "ASRC2IN2R" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2DEC3", "ISRC2DEC3" }, \ + { name, "ISRC2DEC4", "ISRC2DEC4" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" }, \ + { name, "ISRC2INT3", "ISRC2INT3" }, \ + { name, "ISRC2INT4", "ISRC2INT4" }, \ + { name, "ISRC3DEC1", "ISRC3DEC1" }, \ + { name, "ISRC3DEC2", "ISRC3DEC2" }, \ + { name, "ISRC3INT1", "ISRC3INT1" }, \ + { name, "ISRC3INT2", "ISRC3INT2" }, \ + { name, "ISRC4DEC1", "ISRC4DEC1" }, \ + { name, "ISRC4DEC2", "ISRC4DEC2" }, \ + { name, "ISRC4INT1", "ISRC4INT1" }, \ + { name, "ISRC4INT2", "ISRC4INT2" }, \ + { name, "DSP1.1", "DSP1" }, \ + { name, "DSP1.2", "DSP1" }, \ + { name, "DSP1.3", "DSP1" }, \ + { name, "DSP1.4", "DSP1" }, \ + { name, "DSP1.5", "DSP1" }, \ + { name, "DSP1.6", "DSP1" }, \ + { name, "DSP2.1", "DSP2" }, \ + { name, "DSP2.2", "DSP2" }, \ + { name, "DSP2.3", "DSP2" }, \ + { name, "DSP2.4", "DSP2" }, \ + { name, "DSP2.5", "DSP2" }, \ + { name, "DSP2.6", "DSP2" }, \ + { name, "DSP3.1", "DSP3" }, \ + { name, "DSP3.2", "DSP3" }, \ + { name, "DSP3.3", "DSP3" }, \ + { name, "DSP3.4", "DSP3" }, \ + { name, "DSP3.5", "DSP3" }, \ + { name, "DSP3.6", "DSP3" }, \ + { name, "DSP4.1", "DSP4" }, \ + { name, "DSP4.2", "DSP4" }, \ + { name, "DSP4.3", "DSP4" }, \ + { name, "DSP4.4", "DSP4" }, \ + { name, "DSP4.5", "DSP4" }, \ + { name, "DSP4.6", "DSP4" }, \ + { name, "DSP5.1", "DSP5" }, \ + { name, "DSP5.2", "DSP5" }, \ + { name, "DSP5.3", "DSP5" }, \ + { name, "DSP5.4", "DSP5" }, \ + { name, "DSP5.5", "DSP5" }, \ + { name, "DSP5.6", "DSP5" }, \ + { name, "DSP6.1", "DSP6" }, \ + { name, "DSP6.2", "DSP6" }, \ + { name, "DSP6.3", "DSP6" }, \ + { name, "DSP6.4", "DSP6" }, \ + { name, "DSP6.5", "DSP6" }, \ + { name, "DSP6.6", "DSP6" }, \ + { name, "DSP7.1", "DSP7" }, \ + { name, "DSP7.2", "DSP7" }, \ + { name, "DSP7.3", "DSP7" }, \ + { name, "DSP7.4", "DSP7" }, \ + { name, "DSP7.5", "DSP7" }, \ + { name, "DSP7.6", "DSP7" }, \ + { name, "DFC1", "DFC1" }, \ + { name, "DFC2", "DFC2" }, \ + { name, "DFC3", "DFC3" }, \ + { name, "DFC4", "DFC4" }, \ + { name, "DFC5", "DFC5" }, \ + { name, "DFC6", "DFC6" }, \ + { name, "DFC7", "DFC7" }, \ + { name, "DFC8", "DFC8" } + +static const struct snd_soc_dapm_route moon_dapm_routes[] = { + { "AIF2 Capture", NULL, "DBVDD2" }, + { "AIF2 Playback", NULL, "DBVDD2" }, + + { "AIF3 Capture", NULL, "DBVDD3" }, + { "AIF3 Playback", NULL, "DBVDD3" }, + + { "AIF4 Capture", NULL, "DBVDD3" }, + { "AIF4 Playback", NULL, "DBVDD3" }, + + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + { "OUT2L", NULL, "CPVDD" }, + { "OUT2R", NULL, "CPVDD" }, + { "OUT3L", NULL, "CPVDD" }, + { "OUT3R", NULL, "CPVDD" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT2L", NULL, "SYSCLK" }, + { "OUT2R", NULL, "SYSCLK" }, + { "OUT3L", NULL, "SYSCLK" }, + { "OUT3R", NULL, "SYSCLK" }, + { "OUT5L", NULL, "SYSCLK" }, + { "OUT5R", NULL, "SYSCLK" }, + + { "SPD1", NULL, "SYSCLK" }, + { "SPD1", NULL, "SPD1TX1" }, + { "SPD1", NULL, "SPD1TX2" }, + + { "IN1AL", NULL, "SYSCLK" }, + { "IN1BL", NULL, "SYSCLK" }, + { "IN1AR", NULL, "SYSCLK" }, + { "IN1BR", NULL, "SYSCLK" }, + { "IN2AL", NULL, "SYSCLK" }, + { "IN2BL", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, + { "IN3L", NULL, "SYSCLK" }, + { "IN3R", NULL, "SYSCLK" }, + { "IN4L", NULL, "SYSCLK" }, + { "IN4R", NULL, "SYSCLK" }, + { "IN5L", NULL, "SYSCLK" }, + { "IN5R", NULL, "SYSCLK" }, + + { "IN3L", NULL, "DBVDD4" }, + { "IN3R", NULL, "DBVDD4" }, + { "IN4L", NULL, "DBVDD4" }, + { "IN4R", NULL, "DBVDD4" }, + { "IN5L", NULL, "DBVDD4" }, + { "IN5R", NULL, "DBVDD4" }, + + { "DSP1", NULL, "DSPCLK"}, + { "DSP2", NULL, "DSPCLK"}, + { "DSP3", NULL, "DSPCLK"}, + { "DSP4", NULL, "DSPCLK"}, + { "DSP5", NULL, "DSPCLK"}, + { "DSP6", NULL, "DSPCLK"}, + { "DSP7", NULL, "DSPCLK"}, + + { "MICBIAS1", NULL, "MICVDD" }, + { "MICBIAS2", NULL, "MICVDD" }, + + { "MICBIAS1A", NULL, "MICBIAS1" }, + { "MICBIAS1B", NULL, "MICBIAS1" }, + { "MICBIAS1C", NULL, "MICBIAS1" }, + { "MICBIAS1D", NULL, "MICBIAS1" }, + + { "MICBIAS2A", NULL, "MICBIAS2" }, + { "MICBIAS2B", NULL, "MICBIAS2" }, + { "MICBIAS2C", NULL, "MICBIAS2" }, + { "MICBIAS2D", NULL, "MICBIAS2" }, + + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Noise Generator", NULL, "NOISE" }, + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + { "AIF1 Capture", NULL, "AIF1TX7" }, + { "AIF1 Capture", NULL, "AIF1TX8" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + { "AIF1RX7", NULL, "AIF1 Playback" }, + { "AIF1RX8", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + { "AIF2 Capture", NULL, "AIF2TX3" }, + { "AIF2 Capture", NULL, "AIF2TX4" }, + { "AIF2 Capture", NULL, "AIF2TX5" }, + { "AIF2 Capture", NULL, "AIF2TX6" }, + { "AIF2 Capture", NULL, "AIF2TX7" }, + { "AIF2 Capture", NULL, "AIF2TX8" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + { "AIF2RX3", NULL, "AIF2 Playback" }, + { "AIF2RX4", NULL, "AIF2 Playback" }, + { "AIF2RX5", NULL, "AIF2 Playback" }, + { "AIF2RX6", NULL, "AIF2 Playback" }, + { "AIF2RX7", NULL, "AIF2 Playback" }, + { "AIF2RX8", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "AIF4 Capture", NULL, "AIF4TX1" }, + { "AIF4 Capture", NULL, "AIF4TX2" }, + + { "AIF4RX1", NULL, "AIF4 Playback" }, + { "AIF4RX2", NULL, "AIF4 Playback" }, + + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + { "SLIMRX3", NULL, "Slim1 Playback" }, + { "SLIMRX4", NULL, "Slim1 Playback" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX5", NULL, "Slim2 Playback" }, + { "SLIMRX6", NULL, "Slim2 Playback" }, + + { "Slim3 Capture", NULL, "SLIMTX7" }, + { "Slim3 Capture", NULL, "SLIMTX8" }, + + { "SLIMRX7", NULL, "Slim3 Playback" }, + { "SLIMRX8", NULL, "Slim3 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + { "AIF4 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + { "Slim3 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + { "AIF4 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + { "Slim3 Capture", NULL, "SYSCLK" }, + + { "Voice Control CPU", NULL, "Voice Control DSP" }, + { "Voice Control DSP", NULL, "DSP6" }, + { "Voice Control CPU", NULL, "SYSCLK" }, + { "Voice Control DSP", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP1" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, + + { "IN1L Mux", "A", "IN1AL" }, + { "IN1L Mux", "B", "IN1BL" }, + { "IN1R Mux", "A", "IN1AR" }, + { "IN1R Mux", "B", "IN1BR" }, + + { "IN2L Mux", "A", "IN2AL" }, + { "IN2L Mux", "B", "IN2BL" }, + + { "IN1L PGA", NULL, "IN1L Mux" }, + { "IN1R PGA", NULL, "IN1R Mux" }, + + { "IN2L PGA", NULL, "IN2L Mux" }, + { "IN2R PGA", NULL, "IN2R" }, + + { "IN3L PGA", NULL, "IN3L" }, + { "IN3R PGA", NULL, "IN3R" }, + + { "IN4L PGA", NULL, "IN4L" }, + { "IN4R PGA", NULL, "IN4R" }, + + { "IN5L PGA", NULL, "IN5L" }, + { "IN5R PGA", NULL, "IN5R" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), + ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), + ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), + ARIZONA_MIXER_ROUTES("OUT2R", "HPOUT2R"), + ARIZONA_MIXER_ROUTES("OUT3L", "HPOUT3L"), + ARIZONA_MIXER_ROUTES("OUT3R", "HPOUT3R"), + + ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"), + ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + ARIZONA_MIXER_ROUTES("AIF1TX7", "AIF1TX7"), + ARIZONA_MIXER_ROUTES("AIF1TX8", "AIF1TX8"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"), + ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"), + ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"), + ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"), + ARIZONA_MIXER_ROUTES("AIF2TX7", "AIF2TX7"), + ARIZONA_MIXER_ROUTES("AIF2TX8", "AIF2TX8"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MIXER_ROUTES("AIF4TX1", "AIF4TX1"), + ARIZONA_MIXER_ROUTES("AIF4TX2", "AIF4TX2"), + + ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"), + ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"), + ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"), + + ARIZONA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"), + ARIZONA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"), + + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), + ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), + ARIZONA_MIXER_ROUTES("EQ3", "EQ3"), + ARIZONA_MIXER_ROUTES("EQ4", "EQ4"), + + ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), + ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), + ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_MUX_ROUTES("ASRC1IN1L", "ASRC1IN1L"), + ARIZONA_MUX_ROUTES("ASRC1IN1R", "ASRC1IN1R"), + ARIZONA_MUX_ROUTES("ASRC1IN2L", "ASRC1IN2L"), + ARIZONA_MUX_ROUTES("ASRC1IN2R", "ASRC1IN2R"), + ARIZONA_MUX_ROUTES("ASRC2IN1L", "ASRC2IN1L"), + ARIZONA_MUX_ROUTES("ASRC2IN1R", "ASRC2IN1R"), + ARIZONA_MUX_ROUTES("ASRC2IN2L", "ASRC2IN2L"), + ARIZONA_MUX_ROUTES("ASRC2IN2R", "ASRC2IN2R"), + + ARIZONA_DSP_ROUTES("DSP1"), + ARIZONA_DSP_ROUTES("DSP2"), + ARIZONA_DSP_ROUTES("DSP3"), + ARIZONA_DSP_ROUTES("DSP4"), + ARIZONA_DSP_ROUTES("DSP5"), + ARIZONA_DSP_ROUTES("DSP6"), + ARIZONA_DSP_ROUTES("DSP7"), + + { "DSP2 Preloader", NULL, "DSP2 Virtual Input" }, + { "DSP2 Virtual Input", "Shared Memory", "DSP3" }, + { "DSP3 Preloader", NULL, "DSP3 Virtual Input" }, + { "DSP3 Virtual Input", "Shared Memory", "DSP2" }, + + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP6", "DSP6" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT3", "ISRC2INT3"), + ARIZONA_MUX_ROUTES("ISRC2INT4", "ISRC2INT4"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC3", "ISRC2DEC3"), + ARIZONA_MUX_ROUTES("ISRC2DEC4", "ISRC2DEC4"), + + ARIZONA_MUX_ROUTES("ISRC3INT1", "ISRC3INT1"), + ARIZONA_MUX_ROUTES("ISRC3INT2", "ISRC3INT2"), + + ARIZONA_MUX_ROUTES("ISRC3DEC1", "ISRC3DEC1"), + ARIZONA_MUX_ROUTES("ISRC3DEC2", "ISRC3DEC2"), + + ARIZONA_MUX_ROUTES("ISRC4INT1", "ISRC4INT1"), + ARIZONA_MUX_ROUTES("ISRC4INT2", "ISRC4INT2"), + + ARIZONA_MUX_ROUTES("ISRC4DEC1", "ISRC4DEC1"), + ARIZONA_MUX_ROUTES("ISRC4DEC2", "ISRC4DEC2"), + + { "AEC Loopback", "HPOUT1L", "OUT1L" }, + { "AEC Loopback", "HPOUT1R", "OUT1R" }, + { "HPOUT1L", NULL, "OUT1L" }, + { "HPOUT1R", NULL, "OUT1R" }, + + { "AEC Loopback", "HPOUT2L", "OUT2L" }, + { "AEC Loopback", "HPOUT2R", "OUT2R" }, + { "HPOUT2L", NULL, "OUT2L" }, + { "HPOUT2R", NULL, "OUT2R" }, + + { "AEC Loopback", "HPOUT3L", "OUT3L" }, + { "AEC Loopback", "HPOUT3R", "OUT3R" }, + { "HPOUT3L", NULL, "OUT3L" }, + { "HPOUT3R", NULL, "OUT3R" }, + + { "AEC Loopback", "SPKDAT1L", "OUT5L" }, + { "AEC Loopback", "SPKDAT1R", "OUT5R" }, + { "SPKDAT1L", NULL, "OUT5L" }, + { "SPKDAT1R", NULL, "OUT5R" }, + + MOON_RXANC_INPUT_ROUTES("RXANCL", "RXANCL"), + MOON_RXANC_INPUT_ROUTES("RXANCR", "RXANCR"), + + MOON_RXANC_OUTPUT_ROUTES("OUT1L", "HPOUT1L"), + MOON_RXANC_OUTPUT_ROUTES("OUT1R", "HPOUT1R"), + MOON_RXANC_OUTPUT_ROUTES("OUT2L", "HPOUT2L"), + MOON_RXANC_OUTPUT_ROUTES("OUT2R", "HPOUT2R"), + MOON_RXANC_OUTPUT_ROUTES("OUT3L", "HPOUT3L"), + MOON_RXANC_OUTPUT_ROUTES("OUT3R", "HPOUT3R"), + MOON_RXANC_OUTPUT_ROUTES("OUT5L", "SPKDAT1L"), + MOON_RXANC_OUTPUT_ROUTES("OUT5R", "SPKDAT1R"), + + { "SPDIF", NULL, "SPD1" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, + { "DRC2 Signal Activity", NULL, "DRC2L" }, + { "DRC2 Signal Activity", NULL, "DRC2R" }, + + ARIZONA_MUX_ROUTES("DFC1", "DFC1"), + ARIZONA_MUX_ROUTES("DFC2", "DFC2"), + ARIZONA_MUX_ROUTES("DFC3", "DFC3"), + ARIZONA_MUX_ROUTES("DFC4", "DFC4"), + ARIZONA_MUX_ROUTES("DFC5", "DFC5"), + ARIZONA_MUX_ROUTES("DFC6", "DFC6"), + ARIZONA_MUX_ROUTES("DFC7", "DFC7"), + ARIZONA_MUX_ROUTES("DFC8", "DFC8"), +}; + +static int moon_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct moon_priv *moon = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case MOON_FLL1: + return arizona_set_fll(&moon->fll[0], source, Fref, Fout); + case MOON_FLL2: + return arizona_set_fll(&moon->fll[1], source, Fref, Fout); + case MOON_FLLAO: + return arizona_set_fll_ao(&moon->fll[2], source, Fref, Fout); + case MOON_FLL1_REFCLK: + return arizona_set_fll_refclk(&moon->fll[0], source, Fref, + Fout); + case MOON_FLL2_REFCLK: + return arizona_set_fll_refclk(&moon->fll[1], source, Fref, + Fout); + default: + return -EINVAL; + } +} + +#define MOON_RATES SNDRV_PCM_RATE_KNOT + +#define MOON_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver moon_dai[] = { + { + .name = "moon-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "moon-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 8, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 8, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "moon-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "moon-aif4", + .id = 4, + .base = ARIZONA_AIF4_BCLK_CTRL, + .playback = { + .stream_name = "AIF4 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "AIF4 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "moon-slim1", + .id = 5, + .playback = { + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "moon-slim2", + .id = 6, + .playback = { + .stream_name = "Slim2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "moon-slim3", + .id = 7, + .playback = { + .stream_name = "Slim3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .capture = { + .stream_name = "Slim3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "moon-cpu6-voicectrl", + .capture = { + .stream_name = "Voice Control CPU", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "moon-dsp6-voicectrl", + .capture = { + .stream_name = "Voice Control DSP", + .channels_min = 1, + .channels_max = 2, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + }, + { + .name = "moon-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 2, + .channels_max = 8, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "moon-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 2, + .channels_max = 8, + .rates = MOON_RATES, + .formats = MOON_FORMATS, + }, + }, +}; + +static irqreturn_t moon_adsp_bus_error(int irq, void *data) +{ + struct wm_adsp *adsp = (struct wm_adsp *)data; + return wm_adsp2_bus_error(adsp); +} + +static void moon_compr_irq(struct moon_priv *moon, + struct moon_compr *compr) +{ + struct arizona *arizona = moon->core.arizona; + bool trigger = false; + int ret; + + ret = wm_adsp_compr_irq(&compr->adsp_compr, &trigger); + if (ret < 0) + return; + + if (trigger && arizona->pdata.ez2ctrl_trigger) { + mutex_lock(&compr->trig_lock); + if (!compr->trig) { + compr->trig = true; + + if (wm_adsp_fw_has_voice_trig(compr->adsp_compr.dsp)) + arizona->pdata.ez2ctrl_trigger(); + } + mutex_unlock(&compr->trig_lock); + } +} + +static irqreturn_t moon_adsp2_irq(int irq, void *data) +{ + struct moon_priv *moon = data; + int i; + + for (i = 0; i < ARRAY_SIZE(moon->compr_info); ++i) { + if (!moon->compr_info[i].adsp_compr.dsp->running) + continue; + + moon_compr_irq(moon, &moon->compr_info[i]); + } + return IRQ_HANDLED; +} + +static struct moon_compr *moon_get_compr(struct snd_soc_pcm_runtime *rtd, + struct moon_priv *moon) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(moon->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + moon->compr_info[i].dai_name) == 0) + return &moon->compr_info[i]; + } + + return NULL; +} + +static int moon_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct moon_priv *moon = snd_soc_codec_get_drvdata(rtd->codec); + struct moon_compr *compr; + + compr = moon_get_compr(rtd, moon); + if (!compr) { + dev_err(moon->core.arizona->dev, + "No compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int moon_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *adsp_compr = + (struct wm_adsp_compr *)stream->runtime->private_data; + struct moon_compr *compr = container_of(adsp_compr, + struct moon_compr, + adsp_compr); + struct arizona *arizona = compr->priv->core.arizona; + int ret; + + ret = wm_adsp_compr_trigger(stream, cmd); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + if (compr->trig) + /* + * If the firmware already triggered before the stream + * was opened trigger another interrupt so irq handler + * will run and process any outstanding data + */ + regmap_write(arizona->regmap, + CLEARWATER_ADSP2_IRQ0, 0x01); + break; + default: + break; + } + + return ret; +} + +static int moon_codec_probe(struct snd_soc_codec *codec) +{ + struct moon_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + int ret, i, j; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_gpio(codec); + arizona_init_mono(codec); + arizona_init_input(codec); + + for (i = 0; i < MOON_NUM_ADSP; ++i) { + ret = wm_adsp2_codec_probe(&priv->core.adsp[i], codec); + if (ret) + return ret; + } + + ret = snd_soc_add_codec_controls(codec, + arizona_adsp2v2_rate_controls, + MOON_NUM_ADSP); + if (ret) + return ret; + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + mutex_unlock(&codec->card->dapm_mutex); + + priv->core.arizona->dapm = &codec->dapm; + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", moon_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + for (i = 0; i < MOON_NUM_ADSP; i++) { + ret = arizona_request_irq(arizona, + moon_adsp_bus_error_irqs[i], + "ADSP2 bus error", + moon_adsp_bus_error, + &priv->core.adsp[i]); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to request DSP Lock region IRQ: %d\n", + ret); + for (j = 0; j < i; j++) + arizona_free_irq(arizona, + moon_adsp_bus_error_irqs[j], + &priv->core.adsp[j]); + return ret; + } + } + + mutex_lock(&codec->card->dapm_mutex); + snd_soc_dapm_enable_pin(&codec->dapm, "DRC2 Signal Activity"); + mutex_unlock(&codec->card->dapm_mutex); + + ret = regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC2 IRQ for DSP: %d\n", + ret); + goto err_drc; + } + + return 0; + +err_drc: + for (i = 0; i < MOON_NUM_ADSP; i++) + arizona_free_irq(arizona, moon_adsp_bus_error_irqs[i], + &priv->core.adsp[i]); + + return ret; +} + +static int moon_codec_remove(struct snd_soc_codec *codec) +{ + int i; + struct moon_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + for (i = 0; i < MOON_NUM_ADSP; i++) + arizona_free_irq(arizona, moon_adsp_bus_error_irqs[i], + &priv->core.adsp[i]); + regmap_update_bits(arizona->regmap, CLEARWATER_IRQ2_MASK_9, + CLEARWATER_DRC2_SIG_DET_EINT2, + CLEARWATER_DRC2_SIG_DET_EINT2); + + for (i = 0; i < MOON_NUM_ADSP; ++i) + wm_adsp2_codec_remove(&priv->core.adsp[i], codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define MOON_DIG_VU 0x0200 + +static unsigned int moon_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, + ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_3R, + ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, +}; + +static struct snd_soc_codec_driver soc_codec_dev_moon = { + .probe = moon_codec_probe, + .remove = moon_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = moon_set_fll, + + .controls = moon_snd_controls, + .num_controls = ARRAY_SIZE(moon_snd_controls), + .dapm_widgets = moon_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(moon_dapm_widgets), + .dapm_routes = moon_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(moon_dapm_routes), +}; + +static struct snd_compr_ops moon_compr_ops = { + .open = moon_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = moon_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver moon_compr_platform = { + .compr_ops = &moon_compr_ops, +}; + +static void moon_init_compr_info(struct moon_priv *moon) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(moon->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(moon->compr_info); ++i) { + moon->compr_info[i].priv = moon; + + moon->compr_info[i].dai_name = + compr_dai_mapping[i].dai_name; + + dsp = &moon->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &moon->compr_info[i].adsp_compr); + + mutex_init(&moon->compr_info[i].trig_lock); + } +} + +static void moon_destroy_compr_info(struct moon_priv *moon) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(moon->compr_info); ++i) + wm_adsp_compr_destroy(&moon->compr_info[i].adsp_compr); +} + +static int moon_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct moon_priv *moon; + int i, ret; + + BUILD_BUG_ON(ARRAY_SIZE(moon_dai) > ARIZONA_MAX_DAI); + + moon = devm_kzalloc(&pdev->dev, sizeof(struct moon_priv), + GFP_KERNEL); + if (moon == NULL) + return -ENOMEM; + platform_set_drvdata(pdev, moon); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&moon->fw_lock); + + moon->core.arizona = arizona; + moon->core.num_inputs = 10; + + for (i = 0; i < MOON_NUM_ADSP; i++) { + moon->core.adsp[i].part = "moon"; + if (arizona->pdata.rev_specific_fw) + moon->core.adsp[i].part_rev = 'a' + arizona->rev; + moon->core.adsp[i].num = i + 1; + moon->core.adsp[i].type = WMFW_ADSP2; + moon->core.adsp[i].rev = 2; + moon->core.adsp[i].dev = arizona->dev; + moon->core.adsp[i].regmap = arizona->regmap_32bit; + + moon->core.adsp[i].base = wm_adsp2_control_bases[i]; + moon->core.adsp[i].mem = moon_dsp_regions[i]; + moon->core.adsp[i].num_mems + = ARRAY_SIZE(moon_dsp1_regions); + + if (arizona->pdata.num_fw_defs[i]) { + moon->core.adsp[i].firmwares + = arizona->pdata.fw_defs[i]; + + moon->core.adsp[i].num_firmwares + = arizona->pdata.num_fw_defs[i]; + } + + moon->core.adsp[i].rate_put_cb = + moon_adsp_rate_put_cb; + + moon->core.adsp[i].lock_regions = WM_ADSP2_REGION_1_9; + + moon->core.adsp[i].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&moon->core.adsp[i], &moon->fw_lock); + if (ret != 0) + return ret; + } + + moon_init_compr_info(moon); + + for (i = 0; i < ARRAY_SIZE(moon->fll); i++) { + moon->fll[i].vco_mult = 3; + moon->fll[i].min_outdiv = 3; + moon->fll[i].max_outdiv = 3; + } + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &moon->fll[0]); + arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1, + ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, + &moon->fll[1]); + arizona_init_fll(arizona, 4, MOON_FLLAO_CONTROL_1 - 1, + MOON_IRQ_FLLAO_CLOCK_OK, MOON_IRQ_FLLAO_CLOCK_OK, + &moon->fll[2]); + + for (i = 0; i < ARRAY_SIZE(moon_dai); i++) + arizona_init_dai(&moon->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(moon_digital_vu); i++) + regmap_update_bits(arizona->regmap, moon_digital_vu[i], + MOON_DIG_VU, MOON_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + ret = snd_soc_register_platform(&pdev->dev, &moon_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_moon, + moon_dai, ARRAY_SIZE(moon_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + moon_destroy_compr_info(moon); + mutex_destroy(&moon->fw_lock); + + return ret; +} + +static int moon_remove(struct platform_device *pdev) +{ + struct moon_priv *moon = platform_get_drvdata(pdev); + int i; + + snd_soc_unregister_platform(&pdev->dev); + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + moon_destroy_compr_info(moon); + + for (i = 0; i < MOON_NUM_ADSP; i++) + wm_adsp2_remove(&moon->core.adsp[i]); + + mutex_destroy(&moon->fw_lock); + + return 0; +} + +static struct platform_driver moon_codec_driver = { + .driver = { + .name = "moon-codec", + .owner = THIS_MODULE, + }, + .probe = moon_probe, + .remove = moon_remove, +}; + +module_platform_driver(moon_codec_driver); + +MODULE_DESCRIPTION("ASoC MOON driver"); +MODULE_AUTHOR("Nikesh Oswal "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:moon-codec"); diff --git a/sound/soc/codecs/moon.h b/sound/soc/codecs/moon.h new file mode 100644 index 00000000000..81140951407 --- /dev/null +++ b/sound/soc/codecs/moon.h @@ -0,0 +1,24 @@ +/* + * moon.h -- ALSA SoC Audio driver for Moon-class codecs + * + * Copyright 2015 Cirrus Logic + * + * Author: Nikesh Oswal + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MOON_H +#define _MOON_H + +#include "arizona.h" + +#define MOON_FLL1 1 +#define MOON_FLL2 2 +#define MOON_FLL1_REFCLK 3 +#define MOON_FLL2_REFCLK 4 +#define MOON_FLLAO 5 + +#endif diff --git a/sound/soc/codecs/vegas.c b/sound/soc/codecs/vegas.c new file mode 100644 index 00000000000..a073104af7c --- /dev/null +++ b/sound/soc/codecs/vegas.c @@ -0,0 +1,1602 @@ +/* + * vegas.c -- ALSA SoC Audio driver for Vegas codecs + * + * Copyright 2014-2015 Cirrus Logic + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arizona.h" +#include "vegas.h" + +struct vegas_priv { + struct arizona_priv core; + struct arizona_fll fll[2]; +}; + +static int vegas_put_volsw_locked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + int ret; + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + ret = snd_soc_put_volsw(kcontrol, ucontrol); + + mutex_unlock(&codec->card->dapm_mutex); + + return ret; +} + +static int vegas_put_spk_edre(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + unsigned int val = 0; + + + mutex_lock_nested(&codec->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); + + if (ucontrol->value.integer.value[0] != 0) + val |= CLEARWATER_EDRE_OUT4L_THR1_ENA_MASK | + CLEARWATER_EDRE_OUT4L_THR2_ENA_MASK; + + if (ucontrol->value.integer.value[1] != 0) + val |= CLEARWATER_EDRE_OUT4R_THR1_ENA_MASK | + CLEARWATER_EDRE_OUT4R_THR2_ENA_MASK; + + snd_soc_update_bits(codec, CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT4L_THR1_ENA_MASK | + CLEARWATER_EDRE_OUT4R_THR1_ENA_MASK | + CLEARWATER_EDRE_OUT4L_THR2_ENA_MASK | + CLEARWATER_EDRE_OUT4R_THR2_ENA_MASK, + val); + + mutex_unlock(&codec->card->dapm_mutex); + + return 0; +} + +static int vegas_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + break; + case SND_SOC_DAPM_PRE_PMD: + break; + default: + return 0; + } + + return arizona_dvfs_sysclk_ev(w, kcontrol, event); +} +static int vegas_asrc_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + unsigned int val; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + val = snd_soc_read(w->codec, ARIZONA_ASRC_RATE1); + val &= ARIZONA_ASRC_RATE1_MASK; + val >>= ARIZONA_ASRC_RATE1_SHIFT; + + switch (val) { + case 0: + case 1: + case 2: + val = snd_soc_read(w->codec, + ARIZONA_SAMPLE_RATE_1 + val); + if (val >= 0x11) { + dev_warn(w->codec->dev, + "Unsupported ASRC rate1 (%s)\n", + arizona_sample_rate_val_to_name(val)); + return -EINVAL; + } + break; + default: + dev_err(w->codec->dev, + "Illegal ASRC rate1 selector (0x%x)\n", + val); + return -EINVAL; + } + + val = snd_soc_read(w->codec, ARIZONA_ASRC_RATE2); + val &= ARIZONA_ASRC_RATE2_MASK; + val >>= ARIZONA_ASRC_RATE2_SHIFT; + + switch (val) { + case 8: + case 9: + val -= 0x8; + val = snd_soc_read(w->codec, + ARIZONA_ASYNC_SAMPLE_RATE_1 + val); + if (val >= 0x11) { + dev_warn(w->codec->dev, + "Unsupported ASRC rate2 (%s)\n", + arizona_sample_rate_val_to_name(val)); + return -EINVAL; + } + break; + default: + dev_err(w->codec->dev, + "Illegal ASRC rate2 selector (0x%x)\n", + val); + return -EINVAL; + } + + break; + default: + return -EINVAL; + } + + return 0; +} + +static int vegas_in1mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct vegas_priv *vegas = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = vegas->core.arizona; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int mux, inmode; + unsigned int mode_val, src_val; + bool changed = false; + int ret; + + mux = ucontrol->value.enumerated.item[0]; + if (mux > 1) + return -EINVAL; + + /* L and R registers have same shift and mask */ + inmode = arizona->pdata.inmode[2 * mux]; + src_val = mux << ARIZONA_IN1L_SRC_SHIFT; + if (inmode & ARIZONA_INMODE_SE) + src_val |= 1 << ARIZONA_IN1L_SRC_SE_SHIFT; + + switch (arizona->pdata.inmode[0]) { + case ARIZONA_INMODE_DMIC: + if (mux) + mode_val = 0; /* B always analogue */ + else + mode_val = 1 << ARIZONA_IN1_MODE_SHIFT; + + ret = snd_soc_update_bits(codec, ARIZONA_IN1L_CONTROL, + ARIZONA_IN1_MODE_MASK, mode_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + /* IN1A is digital so L and R must change together */ + /* src_val setting same for both registers */ + ret = snd_soc_update_bits(codec, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_MASK | + ARIZONA_IN1L_SRC_SE_MASK, src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + ret = snd_soc_update_bits(codec, + ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_MASK | + ARIZONA_IN1R_SRC_SE_MASK, src_val); + + if (ret < 0) + return ret; + else if (ret) + changed = true; + break; + default: + /* both analogue */ + ret = snd_soc_update_bits(codec, + e->reg, + ARIZONA_IN1L_SRC_MASK | + ARIZONA_IN1L_SRC_SE_MASK, + src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + break; + } + + if (changed) + return snd_soc_dapm_mux_update_power(widget, kcontrol, + mux, e); + else + return 0; +} + +static int vegas_in2mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); + struct snd_soc_dapm_widget *widget = wlist->widgets[0]; + struct snd_soc_codec *codec = widget->codec; + struct vegas_priv *vegas = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = vegas->core.arizona; + unsigned int mux, inmode, src_val, mode_val; + bool changed = false; + int ret; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + mux = ucontrol->value.enumerated.item[0]; + if (mux > 1) + return -EINVAL; + + inmode = arizona->pdata.inmode[1 + (2 * mux)]; + if (inmode & ARIZONA_INMODE_DMIC) + mode_val = 1 << ARIZONA_IN2_MODE_SHIFT; + else + mode_val = 0; + + src_val = mux << ARIZONA_IN2L_SRC_SHIFT; + if (inmode & ARIZONA_INMODE_SE) + src_val |= 1 << ARIZONA_IN2L_SRC_SE_SHIFT; + + ret = snd_soc_update_bits(codec, ARIZONA_IN2L_CONTROL, + ARIZONA_IN2_MODE_MASK, mode_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + ret = snd_soc_update_bits(codec, ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_SRC_MASK | ARIZONA_IN2L_SRC_SE_MASK, + src_val); + if (ret < 0) + return ret; + else if (ret) + changed = true; + + + + if (changed) + return snd_soc_dapm_mux_update_power(widget, kcontrol, + mux, e); + else + return 0; +} + +static const char * const vegas_inmux_texts[] = { + "A", + "B", +}; + +static const SOC_ENUM_SINGLE_DECL(vegas_in1muxl_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_SRC_SHIFT, + vegas_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(vegas_in1muxr_enum, + ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_SRC_SHIFT, + vegas_inmux_texts); + +static const SOC_ENUM_SINGLE_DECL(vegas_in2mux_enum, + ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_SRC_SHIFT, + vegas_inmux_texts); + +static const struct snd_kcontrol_new vegas_in1mux[2] = { + SOC_DAPM_ENUM_EXT("IN1L Mux", vegas_in1muxl_enum, + snd_soc_dapm_get_enum_double, vegas_in1mux_put), + SOC_DAPM_ENUM_EXT("IN1R Mux", vegas_in1muxr_enum, + snd_soc_dapm_get_enum_double, vegas_in1mux_put), +}; + +static const struct snd_kcontrol_new vegas_in2mux = + SOC_DAPM_ENUM_EXT("IN2 Mux", vegas_in2mux_enum, + snd_soc_dapm_get_enum_double, vegas_in2mux_put); + +static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); +static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); +static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); +static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); + +#define VEGAS_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUTL Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUTR Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG LINEOUTL Switch", base, 2, 1, 0), \ + SOC_SINGLE(name " NG LINEOUTR Switch", base, 3, 1, 0), \ + SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0) + +static const struct snd_kcontrol_new vegas_snd_controls[] = { +SOC_ENUM("IN1 OSR", arizona_in_dmic_osr[0]), +SOC_ENUM("IN2 OSR", arizona_in_dmic_osr[1]), + +SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), +SOC_SINGLE_RANGE_TLV("IN2 Volume", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), + +SOC_ENUM("IN HPF Cutoff Frequency", arizona_in_hpf_cut_enum), + +SOC_SINGLE("IN1L HPF Switch", ARIZONA_IN1L_CONTROL, + ARIZONA_IN1L_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN1R HPF Switch", ARIZONA_IN1R_CONTROL, + ARIZONA_IN1R_HPF_SHIFT, 1, 0), +SOC_SINGLE("IN2 HPF Switch", ARIZONA_IN2L_CONTROL, + ARIZONA_IN2L_HPF_SHIFT, 1, 0), + +SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, + ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R, + ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("IN2 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, + ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), + +SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), +SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), + +ARIZONA_GAINMUX_CONTROLS("EQ1", ARIZONA_EQ1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), + +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), +SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B3 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), +SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B3 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), +SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B3 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), +SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B3 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B3_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B4 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B4_GAIN_SHIFT, + 24, 0, eq_tlv), +SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, + 24, 0, eq_tlv), + +ARIZONA_GAINMUX_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), + +SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, + ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), + +ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), + +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), + +SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), +SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), +SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), +SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), + +ARIZONA_SAMPLE_RATE_CONTROL_DVFS("Sample Rate 2", 2), +ARIZONA_SAMPLE_RATE_CONTROL_DVFS("Sample Rate 3", 3), +ARIZONA_SAMPLE_RATE_CONTROL_DVFS("ASYNC Sample Rate 2", 4), + +SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +SOC_VALUE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), +SOC_VALUE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), +SOC_VALUE_ENUM("ASRC RATE 1", arizona_asrc_rate1), +SOC_VALUE_ENUM("ASRC RATE 2", arizona_asrc_rate2), + +ARIZONA_MIXER_CONTROLS("HPOUTL", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("HPOUTR", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LINEOUTL", ARIZONA_OUT2LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("LINEOUTR", ARIZONA_OUT2RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EPOUT", ARIZONA_OUT3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDATL", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKDATR", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), + +SOC_DOUBLE_R("HPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), +SOC_DOUBLE_R("LINEOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("EPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_OUT3L_MUTE_SHIFT, 1, 1), + +/* There isn't a SOC_DOUBLE_R_EXT macro that we can use for this */ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Speaker Digital Switch", + .info = snd_soc_info_volsw, + .get = snd_soc_get_volsw, .put = vegas_put_volsw_locked, + .private_value = SOC_DOUBLE_R_VALUE(ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, + ARIZONA_OUT4L_MUTE_SHIFT, + 1, 1) +}, + +SOC_DOUBLE_R("SPKDAT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE_R_TLV("HPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("LINEOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("EPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_OUT3L_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT, + 0xbf, 0, digital_tlv), +SOC_DOUBLE_R_TLV("SPKDAT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, + 0xbf, 0, digital_tlv), + +SOC_DOUBLE("SPKDAT Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), + +SOC_DOUBLE("HPOUT DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE1L_ENA_SHIFT, VEGAS_DRE1R_ENA_SHIFT, 1, 0), +SOC_DOUBLE("LINEOUT DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE2L_ENA_SHIFT, VEGAS_DRE2R_ENA_SHIFT, 1, 0), +SOC_SINGLE("EPOUT DRE Switch", ARIZONA_DRE_ENABLE, + VEGAS_DRE3L_ENA_SHIFT, 1, 0), + +SOC_SINGLE("DRE Threshold", ARIZONA_DRE_CONTROL_2, + ARIZONA_DRE_T_LOW_SHIFT, 63, 0), + +SOC_SINGLE("DRE Low Level ABS", ARIZONA_DRE_CONTROL_3, + ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT, 15, 0), + +SOC_SINGLE("DRE TC Fast", ARIZONA_DRE_CONTROL_1, + ARIZONA_DRE_ENV_TC_FAST_SHIFT, 15, 0), + +SOC_SINGLE("DRE Analogue Volume Delay", ARIZONA_DRE_CONTROL_2, + ARIZONA_DRE_ALOG_VOL_DELAY_SHIFT, 15, 0), + +SOC_DOUBLE_EXT("HPOUT EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT1L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT1R_THR1_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, vegas_put_volsw_locked), +SOC_DOUBLE_EXT("LINEOUT EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT2L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT2R_THR1_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, vegas_put_volsw_locked), +SOC_SINGLE_EXT("EPOUT EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT3L_THR1_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, vegas_put_volsw_locked), +SOC_DOUBLE_EXT("SPKOUT EDRE Switch", CLEARWATER_EDRE_ENABLE, + CLEARWATER_EDRE_OUT4L_THR1_ENA_SHIFT, + CLEARWATER_EDRE_OUT4R_THR1_ENA_SHIFT, 1, 0, + snd_soc_get_volsw, vegas_put_spk_edre), + +SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), +SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), + +SOC_ENUM("SPDIF Rate", arizona_spdif_rate), + +SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_ENA_SHIFT, 1, 0), +SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, + ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), +SOC_ENUM("Noise Gate Hold", arizona_ng_hold), + +VEGAS_NG_SRC("HPOUTL", ARIZONA_NOISE_GATE_SELECT_1L), +VEGAS_NG_SRC("HPOUTR", ARIZONA_NOISE_GATE_SELECT_1R), +VEGAS_NG_SRC("LINEOUTL", ARIZONA_NOISE_GATE_SELECT_2L), +VEGAS_NG_SRC("LINEOUTR", ARIZONA_NOISE_GATE_SELECT_2R), +VEGAS_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L), +VEGAS_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), +VEGAS_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R), +VEGAS_NG_SRC("SPKDATL", ARIZONA_NOISE_GATE_SELECT_5L), +VEGAS_NG_SRC("SPKDATR", ARIZONA_NOISE_GATE_SELECT_5R), + +ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX4", ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX5", ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF1TX6", ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX3", ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX4", ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX5", ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF2TX6", ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_GAINMUX_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), + +ARIZONA_GAINMUX_CONTROLS("SPDIFTX1", ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE), +ARIZONA_GAINMUX_CONTROLS("SPDIFTX2", ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE), +}; + +static const struct snd_kcontrol_new wm1814_snd_controls[] = { +SND_SOC_BYTES("FRF Coefficients", ARIZONA_FRF_COEFF_1, 4), +SND_SOC_BYTES("DAC Comp", ARIZONA_V2_DAC_COMP_1, 2), +SND_SOC_BYTES_MASK("HP1 Bias", ARIZONA_HP_TEST_CTRL_13, 1, 0x3FFF), +}; + +ARIZONA_MUX_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(EQ2, ARIZONA_EQ2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(EQ3, ARIZONA_EQ3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF3, ARIZONA_HPLP3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(LHPF4, ARIZONA_HPLP4MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(PWM1, ARIZONA_PWM1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT3, ARIZONA_OUT3LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKDATL, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKDATR, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX3, ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX4, ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX5, ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF1TX6, ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX3, ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX4, ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX5, ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF2TX6, ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE); + +ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(SPD1TX1, ARIZONA_SPDIFTX1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(SPD1TX2, ARIZONA_SPDIFTX2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT3, ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT4, ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC3, ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC4, ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); + +static const char * const vegas_aec_loopback_texts[] = { + "HPOUTL", "HPOUTR", "LINEOUTL", "LINEOUTR", "EPOUT", + "SPKOUTL", "SPKOUTR", "SPKDATL", "SPKDATR", +}; + +static const unsigned int vegas_aec_loopback_values[] = { + 0, 1, 2, 3, 4, 6, 7, 8, 9, +}; + +static const SOC_VALUE_ENUM_SINGLE_DECL(vegas_aec1_loopback, + ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + vegas_aec_loopback_texts, + vegas_aec_loopback_values); + +static const SOC_VALUE_ENUM_SINGLE_DECL(vegas_aec2_loopback, + ARIZONA_DAC_AEC_CONTROL_2, + ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, + vegas_aec_loopback_texts, + vegas_aec_loopback_values); + +static const struct snd_kcontrol_new vegas_aec_loopback_mux[] = { + SOC_DAPM_VALUE_ENUM("AEC1 Loopback", vegas_aec1_loopback), + SOC_DAPM_VALUE_ENUM("AEC2 Loopback", vegas_aec2_loopback), +}; + +static const struct snd_soc_dapm_widget vegas_dapm_widgets[] = { +SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, + ARIZONA_SYSCLK_ENA_SHIFT, 0, + vegas_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), +SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, + ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, + ARIZONA_OPCLK_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK, + ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0), + +SND_SOC_DAPM_SIGGEN("TONE"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), + +SND_SOC_DAPM_INPUT("IN1AL"), +SND_SOC_DAPM_INPUT("IN1AR"), +SND_SOC_DAPM_INPUT("IN1BL"), +SND_SOC_DAPM_INPUT("IN1BR"), +SND_SOC_DAPM_INPUT("IN2A"), +SND_SOC_DAPM_INPUT("IN2B"), + +SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &vegas_in1mux[0]), +SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &vegas_in1mux[1]), +SND_SOC_DAPM_MUX("IN2 Mux", SND_SOC_NOPM, 0, 0, &vegas_in2mux), + +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), + +SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN1R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1R_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("IN2 PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2L_ENA_SHIFT, + 0, NULL, 0, arizona_in_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3, + ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1, + ARIZONA_TONE2_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("EQ1", ARIZONA_EQ1_1, ARIZONA_EQ1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ2", ARIZONA_EQ2_1, ARIZONA_EQ2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ3", ARIZONA_EQ3_1, ARIZONA_EQ3_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("EQ4", ARIZONA_EQ4_1, ARIZONA_EQ4_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF2", ARIZONA_HPLPF2_1, ARIZONA_LHPF2_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF3", ARIZONA_HPLPF3_1, ARIZONA_LHPF3_ENA_SHIFT, 0, + NULL, 0), +SND_SOC_DAPM_PGA("LHPF4", ARIZONA_HPLPF4_1, ARIZONA_LHPF4_ENA_SHIFT, 0, + NULL, 0), + +SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, + 0, NULL, 0), +SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, + 0, NULL, 0), + +SND_SOC_DAPM_PGA_E("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0, + NULL, 0, vegas_asrc_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0, + NULL, 0, vegas_asrc_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0, + NULL, 0, vegas_asrc_ev, SND_SOC_DAPM_PRE_PMU), +SND_SOC_DAPM_PGA_E("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0, + NULL, 0, vegas_asrc_ev, SND_SOC_DAPM_PRE_PMU), + +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC3", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC2_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC4", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC3_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_VALUE_MUX("AEC1 Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &vegas_aec_loopback_mux[0]), + +SND_SOC_DAPM_VALUE_MUX("AEC2 Loopback", ARIZONA_DAC_AEC_CONTROL_2, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &vegas_aec_loopback_mux[1]), + +SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF1TX6", NULL, 0, + ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF1RX6", NULL, 0, + ARIZONA_AIF1_RX_ENABLES, ARIZONA_AIF1RX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX2", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX3", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX4", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX5", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF2TX6", NULL, 0, + ARIZONA_AIF2_TX_ENABLES, ARIZONA_AIF2TX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX3", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX4", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX5", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF2RX6", NULL, 0, + ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, + ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, + ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), + +SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, + ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, + ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT3", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), +SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + +SND_SOC_DAPM_PGA("SPD1TX1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL1_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("SPD1TX2", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_VAL2_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_OUT_DRV("SPD1", ARIZONA_SPD1_TX_CONTROL, + ARIZONA_SPD1_ENA_SHIFT, 0, NULL, 0), + +ARIZONA_MUX_WIDGETS(EQ1, "EQ1"), +ARIZONA_MUX_WIDGETS(EQ2, "EQ2"), +ARIZONA_MUX_WIDGETS(EQ3, "EQ3"), +ARIZONA_MUX_WIDGETS(EQ4, "EQ4"), + +ARIZONA_MUX_WIDGETS(DRC1L, "DRC1L"), +ARIZONA_MUX_WIDGETS(DRC1R, "DRC1R"), + +ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), +ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), +ARIZONA_MIXER_WIDGETS(LHPF3, "LHPF3"), +ARIZONA_MIXER_WIDGETS(LHPF4, "LHPF4"), + +ARIZONA_MIXER_WIDGETS(PWM1, "PWM1"), +ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), + +ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUTL"), +ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUTR"), +ARIZONA_MIXER_WIDGETS(OUT2L, "LINEOUTL"), +ARIZONA_MIXER_WIDGETS(OUT2R, "LINEOUTR"), +ARIZONA_MIXER_WIDGETS(OUT3, "EPOUT"), +ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"), +ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"), +ARIZONA_MIXER_WIDGETS(SPKDATL, "SPKDATL"), +ARIZONA_MIXER_WIDGETS(SPKDATR, "SPKDATR"), + +ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), +ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), +ARIZONA_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"), +ARIZONA_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"), +ARIZONA_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"), +ARIZONA_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"), + +ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), +ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), +ARIZONA_MIXER_WIDGETS(AIF2TX3, "AIF2TX3"), +ARIZONA_MIXER_WIDGETS(AIF2TX4, "AIF2TX4"), +ARIZONA_MIXER_WIDGETS(AIF2TX5, "AIF2TX5"), +ARIZONA_MIXER_WIDGETS(AIF2TX6, "AIF2TX6"), + +ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), +ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), + +ARIZONA_MUX_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MUX_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MUX_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MUX_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MUX_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MUX_WIDGETS(SLIMTX6, "SLIMTX6"), + +ARIZONA_MUX_WIDGETS(SPD1TX1, "SPDIFTX1"), +ARIZONA_MUX_WIDGETS(SPD1TX2, "SPDIFTX2"), + +ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"), +ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"), +ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), +ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), +ARIZONA_MUX_WIDGETS(ISRC1DEC3, "ISRC1DEC3"), +ARIZONA_MUX_WIDGETS(ISRC1DEC4, "ISRC1DEC4"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), +ARIZONA_MUX_WIDGETS(ISRC1INT3, "ISRC1INT3"), +ARIZONA_MUX_WIDGETS(ISRC1INT4, "ISRC1INT4"), + +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), + +SND_SOC_DAPM_OUTPUT("HPOUTL"), +SND_SOC_DAPM_OUTPUT("HPOUTR"), +SND_SOC_DAPM_OUTPUT("LINEOUTL"), +SND_SOC_DAPM_OUTPUT("LINEOUTR"), +SND_SOC_DAPM_OUTPUT("EPOUT"), +SND_SOC_DAPM_OUTPUT("SPKOUTLN"), +SND_SOC_DAPM_OUTPUT("SPKOUTLP"), +SND_SOC_DAPM_OUTPUT("SPKOUTRN"), +SND_SOC_DAPM_OUTPUT("SPKOUTRP"), +SND_SOC_DAPM_OUTPUT("SPKDATL"), +SND_SOC_DAPM_OUTPUT("SPKDATR"), +SND_SOC_DAPM_OUTPUT("SPDIF"), + +SND_SOC_DAPM_OUTPUT("MICSUPP"), +}; + +#define ARIZONA_MIXER_INPUT_ROUTES(name) \ + { name, "Tone Generator 1", "Tone Generator 1" }, \ + { name, "Tone Generator 2", "Tone Generator 2" }, \ + { name, "Haptics", "HAPTICS" }, \ + { name, "AEC", "AEC1 Loopback" }, \ + { name, "AEC2", "AEC2 Loopback" }, \ + { name, "IN1L", "IN1L PGA" }, \ + { name, "IN1R", "IN1R PGA" }, \ + { name, "IN2L", "IN2 PGA" }, \ + { name, "AIF1RX1", "AIF1RX1" }, \ + { name, "AIF1RX2", "AIF1RX2" }, \ + { name, "AIF1RX3", "AIF1RX3" }, \ + { name, "AIF1RX4", "AIF1RX4" }, \ + { name, "AIF1RX5", "AIF1RX5" }, \ + { name, "AIF1RX6", "AIF1RX6" }, \ + { name, "AIF2RX1", "AIF2RX1" }, \ + { name, "AIF2RX2", "AIF2RX2" }, \ + { name, "AIF2RX3", "AIF2RX3" }, \ + { name, "AIF2RX4", "AIF2RX4" }, \ + { name, "AIF2RX5", "AIF2RX5" }, \ + { name, "AIF2RX6", "AIF2RX6" }, \ + { name, "AIF3RX1", "AIF3RX1" }, \ + { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "EQ1", "EQ1" }, \ + { name, "EQ2", "EQ2" }, \ + { name, "EQ3", "EQ3" }, \ + { name, "EQ4", "EQ4" }, \ + { name, "DRC1L", "DRC1L" }, \ + { name, "DRC1R", "DRC1R" }, \ + { name, "LHPF1", "LHPF1" }, \ + { name, "LHPF2", "LHPF2" }, \ + { name, "LHPF3", "LHPF3" }, \ + { name, "LHPF4", "LHPF4" }, \ + { name, "ASRC1L", "ASRC1L" }, \ + { name, "ASRC1R", "ASRC1R" }, \ + { name, "ASRC2L", "ASRC2L" }, \ + { name, "ASRC2R", "ASRC2R" }, \ + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1DEC3", "ISRC1DEC3" }, \ + { name, "ISRC1DEC4", "ISRC1DEC4" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC1INT3", "ISRC1INT3" }, \ + { name, "ISRC1INT4", "ISRC1INT4" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" } + +static const struct snd_soc_dapm_route vegas_dapm_routes[] = { + { "AIF2 Capture", NULL, "DBVDD2" }, + { "AIF2 Playback", NULL, "DBVDD2" }, + + { "AIF3 Capture", NULL, "DBVDD3" }, + { "AIF3 Playback", NULL, "DBVDD3" }, + + { "OUT1L", NULL, "CPVDD" }, + { "OUT1R", NULL, "CPVDD" }, + { "OUT2L", NULL, "CPVDD" }, + { "OUT2R", NULL, "CPVDD" }, + { "OUT3", NULL, "CPVDD" }, + + { "OUT4L", NULL, "SPKVDDL" }, + { "OUT4R", NULL, "SPKVDDR" }, + + { "OUT1L", NULL, "SYSCLK" }, + { "OUT1R", NULL, "SYSCLK" }, + { "OUT2L", NULL, "SYSCLK" }, + { "OUT2R", NULL, "SYSCLK" }, + { "OUT3", NULL, "SYSCLK" }, + { "OUT4L", NULL, "SYSCLK" }, + { "OUT4R", NULL, "SYSCLK" }, + { "OUT5L", NULL, "SYSCLK" }, + { "OUT5R", NULL, "SYSCLK" }, + + { "IN1AL", NULL, "SYSCLK" }, + { "IN1AR", NULL, "SYSCLK" }, + { "IN1BL", NULL, "SYSCLK" }, + { "IN1BR", NULL, "SYSCLK" }, + { "IN2A", NULL, "SYSCLK" }, + { "IN2B", NULL, "SYSCLK" }, + + { "SPD1", NULL, "SYSCLK" }, + { "SPD1", NULL, "SPD1TX1" }, + { "SPD1", NULL, "SPD1TX2" }, + + { "MICBIAS1", NULL, "MICVDD" }, + { "MICBIAS2", NULL, "MICVDD" }, + { "MICBIAS3", NULL, "MICVDD" }, + + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + + { "Tone Generator 1", NULL, "TONE" }, + { "Tone Generator 2", NULL, "TONE" }, + + { "AIF1 Capture", NULL, "AIF1TX1" }, + { "AIF1 Capture", NULL, "AIF1TX2" }, + { "AIF1 Capture", NULL, "AIF1TX3" }, + { "AIF1 Capture", NULL, "AIF1TX4" }, + { "AIF1 Capture", NULL, "AIF1TX5" }, + { "AIF1 Capture", NULL, "AIF1TX6" }, + + { "AIF1RX1", NULL, "AIF1 Playback" }, + { "AIF1RX2", NULL, "AIF1 Playback" }, + { "AIF1RX3", NULL, "AIF1 Playback" }, + { "AIF1RX4", NULL, "AIF1 Playback" }, + { "AIF1RX5", NULL, "AIF1 Playback" }, + { "AIF1RX6", NULL, "AIF1 Playback" }, + + { "AIF2 Capture", NULL, "AIF2TX1" }, + { "AIF2 Capture", NULL, "AIF2TX2" }, + { "AIF2 Capture", NULL, "AIF2TX3" }, + { "AIF2 Capture", NULL, "AIF2TX4" }, + { "AIF2 Capture", NULL, "AIF2TX5" }, + { "AIF2 Capture", NULL, "AIF2TX6" }, + + { "AIF2RX1", NULL, "AIF2 Playback" }, + { "AIF2RX2", NULL, "AIF2 Playback" }, + { "AIF2RX3", NULL, "AIF2 Playback" }, + { "AIF2RX4", NULL, "AIF2 Playback" }, + { "AIF2RX5", NULL, "AIF2 Playback" }, + { "AIF2RX6", NULL, "AIF2 Playback" }, + + { "AIF3 Capture", NULL, "AIF3TX1" }, + { "AIF3 Capture", NULL, "AIF3TX2" }, + + { "AIF3RX1", NULL, "AIF3 Playback" }, + { "AIF3RX2", NULL, "AIF3 Playback" }, + + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + + { "SLIMRX3", NULL, "Slim2 Playback" }, + { "SLIMRX4", NULL, "Slim2 Playback" }, + + { "AIF1 Playback", NULL, "SYSCLK" }, + { "AIF2 Playback", NULL, "SYSCLK" }, + { "AIF3 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + + { "AIF1 Capture", NULL, "SYSCLK" }, + { "AIF2 Capture", NULL, "SYSCLK" }, + { "AIF3 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + + { "IN1L Mux", "A", "IN1AL" }, + { "IN1R Mux", "A", "IN1AR" }, + { "IN1L Mux", "B", "IN1BL" }, + { "IN1R Mux", "B", "IN1BR" }, + + { "IN2 Mux", "A", "IN2A" }, + { "IN2 Mux", "B", "IN2B" }, + + { "IN1L PGA", NULL, "IN1L Mux" }, + { "IN1R PGA", NULL, "IN1R Mux" }, + { "IN2 PGA", NULL, "IN2 Mux" }, + + ARIZONA_MIXER_ROUTES("OUT1L", "HPOUTL"), + ARIZONA_MIXER_ROUTES("OUT1R", "HPOUTR"), + ARIZONA_MIXER_ROUTES("OUT2L", "LINEOUTL"), + ARIZONA_MIXER_ROUTES("OUT2R", "LINEOUTR"), + ARIZONA_MIXER_ROUTES("OUT3", "EPOUT"), + + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"), + ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"), + ARIZONA_MIXER_ROUTES("OUT5L", "SPKDATL"), + ARIZONA_MIXER_ROUTES("OUT5R", "SPKDATR"), + + ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), + ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), + + ARIZONA_MIXER_ROUTES("AIF1TX1", "AIF1TX1"), + ARIZONA_MIXER_ROUTES("AIF1TX2", "AIF1TX2"), + ARIZONA_MIXER_ROUTES("AIF1TX3", "AIF1TX3"), + ARIZONA_MIXER_ROUTES("AIF1TX4", "AIF1TX4"), + ARIZONA_MIXER_ROUTES("AIF1TX5", "AIF1TX5"), + ARIZONA_MIXER_ROUTES("AIF1TX6", "AIF1TX6"), + + ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), + ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), + ARIZONA_MIXER_ROUTES("AIF2TX3", "AIF2TX3"), + ARIZONA_MIXER_ROUTES("AIF2TX4", "AIF2TX4"), + ARIZONA_MIXER_ROUTES("AIF2TX5", "AIF2TX5"), + ARIZONA_MIXER_ROUTES("AIF2TX6", "AIF2TX6"), + + ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), + ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + + ARIZONA_MUX_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MUX_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MUX_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MUX_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MUX_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MUX_ROUTES("SLIMTX6", "SLIMTX6"), + + ARIZONA_MUX_ROUTES("SPD1TX1", "SPDIFTX1"), + ARIZONA_MUX_ROUTES("SPD1TX2", "SPDIFTX2"), + + ARIZONA_MUX_ROUTES("EQ1", "EQ1"), + ARIZONA_MUX_ROUTES("EQ2", "EQ2"), + ARIZONA_MUX_ROUTES("EQ3", "EQ3"), + ARIZONA_MUX_ROUTES("EQ4", "EQ4"), + + ARIZONA_MUX_ROUTES("DRC1L", "DRC1L"), + ARIZONA_MUX_ROUTES("DRC1R", "DRC1R"), + + ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), + ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), + ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), + ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), + + ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"), + ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"), + ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"), + ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"), + + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT3", "ISRC1INT3"), + ARIZONA_MUX_ROUTES("ISRC1INT4", "ISRC1INT4"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC3", "ISRC1DEC3"), + ARIZONA_MUX_ROUTES("ISRC1DEC4", "ISRC1DEC4"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), + + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), + + { "AEC1 Loopback", "HPOUTL", "OUT1L" }, + { "AEC1 Loopback", "HPOUTR", "OUT1R" }, + { "AEC2 Loopback", "HPOUTL", "OUT1L" }, + { "AEC2 Loopback", "HPOUTR", "OUT1R" }, + { "HPOUTL", NULL, "OUT1L" }, + { "HPOUTR", NULL, "OUT1R" }, + + { "AEC1 Loopback", "LINEOUTL", "OUT2L" }, + { "AEC1 Loopback", "LINEOUTR", "OUT2R" }, + { "AEC2 Loopback", "LINEOUTL", "OUT2L" }, + { "AEC2 Loopback", "LINEOUTR", "OUT2R" }, + { "LINEOUTL", NULL, "OUT2L" }, + { "LINEOUTR", NULL, "OUT2R" }, + + { "AEC1 Loopback", "EPOUT", "OUT3" }, + { "AEC2 Loopback", "EPOUT", "OUT3" }, + { "EPOUT", NULL, "OUT3" }, + + { "AEC1 Loopback", "SPKOUTL", "OUT4L" }, + { "AEC2 Loopback", "SPKOUTL", "OUT4L" }, + { "SPKOUTLN", NULL, "OUT4L" }, + { "SPKOUTLP", NULL, "OUT4L" }, + + { "AEC1 Loopback", "SPKOUTR", "OUT4R" }, + { "AEC2 Loopback", "SPKOUTR", "OUT4R" }, + { "SPKOUTRN", NULL, "OUT4R" }, + { "SPKOUTRP", NULL, "OUT4R" }, + + { "SPDIF", NULL, "SPD1" }, + + { "AEC1 Loopback", "SPKDATL", "OUT5L" }, + { "AEC1 Loopback", "SPKDATR", "OUT5R" }, + { "AEC2 Loopback", "SPKDATL", "OUT5L" }, + { "AEC2 Loopback", "SPKDATR", "OUT5R" }, + { "SPKDATL", NULL, "OUT5L" }, + { "SPKDATR", NULL, "OUT5R" }, + + { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, +}; + +#define VEGAS_RATES SNDRV_PCM_RATE_KNOT + +#define VEGAS_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver vegas_dai[] = { + { + .name = "vegas-aif1", + .id = 1, + .base = ARIZONA_AIF1_BCLK_CTRL, + .playback = { + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .capture = { + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "vegas-aif2", + .id = 2, + .base = ARIZONA_AIF2_BCLK_CTRL, + .playback = { + .stream_name = "AIF2 Playback", + .channels_min = 1, + .channels_max = 6, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .capture = { + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 6, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "vegas-aif3", + .id = 3, + .base = ARIZONA_AIF3_BCLK_CTRL, + .playback = { + .stream_name = "AIF3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .capture = { + .stream_name = "AIF3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .ops = &arizona_dai_ops, + .symmetric_rates = 1, + }, + { + .name = "vegas-slim1", + .id = 4, + .playback = { + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "vegas-slim2", + .id = 5, + .playback = { + .stream_name = "Slim2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .capture = { + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = VEGAS_RATES, + .formats = VEGAS_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, +}; + +static int vegas_set_fll(struct snd_soc_codec *codec, int fll_id, int source, + unsigned int Fref, unsigned int Fout) +{ + struct vegas_priv *vegas = snd_soc_codec_get_drvdata(codec); + + switch (fll_id) { + case VEGAS_FLL1: + return arizona_set_fll(&vegas->fll[0], source, Fref, Fout); + case VEGAS_FLL2: + return arizona_set_fll(&vegas->fll[1], source, Fref, Fout); + case VEGAS_FLL1_REFCLK: + return arizona_set_fll_refclk(&vegas->fll[0], source, Fref, + Fout); + case VEGAS_FLL2_REFCLK: + return arizona_set_fll_refclk(&vegas->fll[1], source, Fref, + Fout); + default: + return -EINVAL; + } +} + +static int vegas_codec_probe(struct snd_soc_codec *codec) +{ + struct vegas_priv *priv = snd_soc_codec_get_drvdata(codec); + int ret; + + codec->control_data = priv->core.arizona->regmap; + priv->core.arizona->dapm = &codec->dapm; + + ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); + if (ret != 0) + return ret; + + arizona_init_spk(codec); + arizona_init_gpio(codec); + + switch (priv->core.arizona->type) { + case WM1814: + ret = snd_soc_add_codec_controls(codec, + wm1814_snd_controls, + ARRAY_SIZE(wm1814_snd_controls)); + if (ret != 0) + return ret; + break; + default: + break; + } + + snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); + + priv->core.arizona->dapm = &codec->dapm; + + return 0; +} + +static int vegas_codec_remove(struct snd_soc_codec *codec) +{ + struct vegas_priv *priv = snd_soc_codec_get_drvdata(codec); + + priv->core.arizona->dapm = NULL; + + return 0; +} + +#define VEGAS_DIG_VU 0x0200 + +static unsigned int vegas_digital_vu[] = { + ARIZONA_DAC_DIGITAL_VOLUME_1L, + ARIZONA_DAC_DIGITAL_VOLUME_1R, + ARIZONA_DAC_DIGITAL_VOLUME_2L, + ARIZONA_DAC_DIGITAL_VOLUME_2R, + ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_DAC_DIGITAL_VOLUME_4R, + ARIZONA_DAC_DIGITAL_VOLUME_5L, + ARIZONA_DAC_DIGITAL_VOLUME_5R, +}; + +static struct snd_soc_codec_driver soc_codec_dev_vegas = { + .probe = vegas_codec_probe, + .remove = vegas_codec_remove, + + .idle_bias_off = true, + + .set_sysclk = arizona_set_sysclk, + .set_pll = vegas_set_fll, + + .controls = vegas_snd_controls, + .num_controls = ARRAY_SIZE(vegas_snd_controls), + .dapm_widgets = vegas_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(vegas_dapm_widgets), + .dapm_routes = vegas_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(vegas_dapm_routes), +}; + +static int vegas_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct vegas_priv *vegas; + int i; + + vegas = devm_kzalloc(&pdev->dev, sizeof(struct vegas_priv), + GFP_KERNEL); + if (!vegas) + return -ENOMEM; + platform_set_drvdata(pdev, vegas); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + vegas->core.arizona = arizona; + vegas->core.num_inputs = 3; /* IN1L, IN1R, IN2 */ + + arizona_init_dvfs(&vegas->core); + + for (i = 0; i < ARRAY_SIZE(vegas->fll); i++) + vegas->fll[i].vco_mult = 1; + + arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, + ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, + &vegas->fll[0]); + arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1, + ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, + &vegas->fll[1]); + + for (i = 0; i < ARRAY_SIZE(vegas_dai); i++) + arizona_init_dai(&vegas->core, i); + + /* Latch volume update bits */ + for (i = 0; i < ARRAY_SIZE(vegas_digital_vu); i++) + regmap_update_bits(arizona->regmap, vegas_digital_vu[i], + VEGAS_DIG_VU, VEGAS_DIG_VU); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + + return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_vegas, + vegas_dai, ARRAY_SIZE(vegas_dai)); +} + +static int vegas_remove(struct platform_device *pdev) +{ + snd_soc_unregister_codec(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static struct platform_driver vegas_codec_driver = { + .driver = { + .name = "vegas-codec", + .owner = THIS_MODULE, + }, + .probe = vegas_probe, + .remove = vegas_remove, +}; + +module_platform_driver(vegas_codec_driver); + +MODULE_DESCRIPTION("ASoC Vegas driver"); +MODULE_AUTHOR("Richard Fitzgerald "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:vegas-codec"); diff --git a/sound/soc/codecs/vegas.h b/sound/soc/codecs/vegas.h new file mode 100644 index 00000000000..38b41e8e5ec --- /dev/null +++ b/sound/soc/codecs/vegas.h @@ -0,0 +1,23 @@ +/* + * vegas.h -- ALSA SoC Audio driver for Vegas codecs + * + * Copyright 2014-2015 Cirrus Logic + * + * Author: Richard Fitzgerald + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _VEGAS_H +#define _VEGAS_H + +#include "arizona.h" + +#define VEGAS_FLL1 1 +#define VEGAS_FLL2 2 +#define VEGAS_FLL1_REFCLK 3 +#define VEGAS_FLL2_REFCLK 4 + +#endif diff --git a/sound/soc/codecs/wm2200.c b/sound/soc/codecs/wm2200.c index 57ba315d0c8..51ea08e3e39 100644 --- a/sound/soc/codecs/wm2200.c +++ b/sound/soc/codecs/wm2200.c @@ -897,7 +897,7 @@ static bool wm2200_readable_register(struct device *dev, unsigned int reg) } } -static const struct reg_default wm2200_reva_patch[] = { +static const struct reg_sequence wm2200_reva_patch[] = { { 0x07, 0x0003 }, { 0x102, 0x0200 }, { 0x203, 0x0084 }, @@ -1565,7 +1565,7 @@ static int wm2200_probe(struct snd_soc_codec *codec) return ret; } - ret = snd_soc_add_codec_controls(codec, wm_adsp1_fw_controls, 2); + ret = snd_soc_add_codec_controls(codec, wm_adsp_fw_controls, 2); if (ret != 0) return ret; diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c index ac1745d030d..16aa093f6d8 100644 --- a/sound/soc/codecs/wm5100.c +++ b/sound/soc/codecs/wm5100.c @@ -1246,7 +1246,7 @@ static const struct snd_soc_dapm_route wm5100_dapm_routes[] = { { "PWM2", NULL, "PWM2 Driver" }, }; -static const struct reg_default wm5100_reva_patches[] = { +static const struct reg_sequence wm5100_reva_patches[] = { { WM5100_AUDIO_IF_1_10, 0 }, { WM5100_AUDIO_IF_1_11, 1 }, { WM5100_AUDIO_IF_1_12, 2 }, diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c index 100fdadda56..156e85a442d 100644 --- a/sound/soc/codecs/wm5102.c +++ b/sound/soc/codecs/wm5102.c @@ -33,15 +33,40 @@ #include "wm5102.h" #include "wm_adsp.h" +#define WM5102_NUM_ADSP 1 + +/* Number of compressed DAI hookups, each pair of DSP and dummy CPU +* are counted as one DAI +*/ +#define WM5102_NUM_COMPR_DAI 1 + +struct wm5102_compr { + struct wm_adsp_compr adsp_compr; + const char *dai_name; +}; + struct wm5102_priv { struct arizona_priv core; struct arizona_fll fll[2]; + struct wm5102_compr compr_info[WM5102_NUM_COMPR_DAI]; + + struct mutex fw_lock; +}; + +static const struct { + const char *dai_name; + int adsp_num; +} compr_dai_mapping[WM5102_NUM_COMPR_DAI] = { + { + .dai_name = "wm5102-dsp-trace", + .adsp_num = 0, + }, }; static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0); static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); -static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0); +static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0); static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); static const struct wm_adsp_region wm5102_dsp1_regions[] = { @@ -577,6 +602,12 @@ static const struct reg_default wm5102_sysclk_revb_patch[] = { { 0x30C3, 0x00ED }, }; +static const struct reg_default wm5102t_sysclk_pwr[] = { + { 0x3125, 0x0A03 }, + { 0x3127, 0x0A03 }, + { 0x3129, 0x0A03 }, +}; + static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -603,16 +634,122 @@ static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w, for (i = 0; i < patch_size; i++) regmap_write(regmap, patch[i].reg, patch[i].def); + + if (arizona->pdata.wm5102t_output_pwr) + for (i = 0; i < ARRAY_SIZE(wm5102t_sysclk_pwr); i++) + regmap_write(regmap, + wm5102t_sysclk_pwr[i].reg, + wm5102t_sysclk_pwr[i].def); + break; + case SND_SOC_DAPM_PRE_PMD: + break; + default: + return 0; + } + + return arizona_dvfs_sysclk_ev(w, kcontrol, event); +} + +static int wm5102_adsp_power_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + unsigned int v; + int ret; + + ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &v); + if (ret != 0) { + dev_err(codec->dev, + "Failed to read SYSCLK state: %d\n", ret); + return -EIO; + } + + v = (v & ARIZONA_SYSCLK_FREQ_MASK) >> ARIZONA_SYSCLK_FREQ_SHIFT; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (v >= 3) { + ret = arizona_dvfs_up(codec, ARIZONA_DVFS_ADSP1_RQ); + if (ret != 0) { + dev_err(codec->dev, + "Failed to raise DVFS: %d\n", ret); + return ret; + } + } + break; + + case SND_SOC_DAPM_POST_PMD: + ret = arizona_dvfs_down(codec, ARIZONA_DVFS_ADSP1_RQ); + if (ret != 0) + dev_warn(codec->dev, + "Failed to lower DVFS: %d\n", ret); break; default: break; } + return wm_adsp2_early_event(w, kcontrol, event, v); +} + +static int wm5102_out_comp_coeff_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + uint16_t data; + + mutex_lock(&codec->mutex); + data = cpu_to_be16(arizona->out_comp_coeff); + memcpy(ucontrol->value.bytes.data, &data, sizeof(data)); + mutex_unlock(&codec->mutex); + return 0; } -static const char *wm5102_osr_text[] = { +static int wm5102_out_comp_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + mutex_lock(&codec->mutex); + memcpy(&arizona->out_comp_coeff, ucontrol->value.bytes.data, + sizeof(arizona->out_comp_coeff)); + arizona->out_comp_coeff = be16_to_cpu(arizona->out_comp_coeff); + mutex_unlock(&codec->mutex); + + return 0; +} + +static int wm5102_out_comp_switch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + mutex_lock(&codec->mutex); + ucontrol->value.integer.value[0] = arizona->out_comp_enabled; + mutex_unlock(&codec->mutex); + + return 0; +} + +static int wm5102_out_comp_switch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + + mutex_lock(&codec->mutex); + arizona->out_comp_enabled = ucontrol->value.integer.value[0]; + mutex_unlock(&codec->mutex); + + return 0; +} + +static const char * const wm5102_osr_text[] = { "Low power", "Normal", "High performance", }; @@ -685,15 +822,7 @@ ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), -SND_SOC_BYTES_MASK("EQ1 Coefficeints", ARIZONA_EQ1_1, 21, - ARIZONA_EQ1_ENA_MASK), -SND_SOC_BYTES_MASK("EQ2 Coefficeints", ARIZONA_EQ2_1, 21, - ARIZONA_EQ2_ENA_MASK), -SND_SOC_BYTES_MASK("EQ3 Coefficeints", ARIZONA_EQ3_1, 21, - ARIZONA_EQ3_ENA_MASK), -SND_SOC_BYTES_MASK("EQ4 Coefficeints", ARIZONA_EQ4_1, 21, - ARIZONA_EQ4_ENA_MASK), - +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, @@ -705,6 +834,7 @@ SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, 24, 0, eq_tlv), +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, @@ -716,6 +846,7 @@ SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, 24, 0, eq_tlv), +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, @@ -727,6 +858,7 @@ SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, 24, 0, eq_tlv), +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, @@ -749,10 +881,10 @@ ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), -SND_SOC_BYTES("LHPF1 Coefficients", ARIZONA_HPLPF1_2, 1), -SND_SOC_BYTES("LHPF2 Coefficients", ARIZONA_HPLPF2_2, 1), -SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1), -SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1), +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), @@ -762,8 +894,15 @@ SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), +ARIZONA_SAMPLE_RATE_CONTROL_DVFS("Sample Rate 2", 2), +ARIZONA_SAMPLE_RATE_CONTROL_DVFS("Sample Rate 3", 3), + +SOC_VALUE_ENUM("FX Rate", arizona_fx_rate), + SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), +SOC_VALUE_ENUM("ASRC RATE 1", arizona_asrc_rate1), +SOC_VALUE_ENUM("ASRC RATE 2", arizona_asrc_rate2), ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE), @@ -814,7 +953,20 @@ SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, SOC_VALUE_ENUM("HPOUT1 OSR", wm5102_hpout_osr[0]), SOC_VALUE_ENUM("HPOUT2 OSR", wm5102_hpout_osr[1]), -SOC_VALUE_ENUM("HPOUT3 OSR", wm5102_hpout_osr[2]), +SOC_VALUE_ENUM("EPOUT OSR", wm5102_hpout_osr[2]), + +SOC_DOUBLE("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0), +SOC_DOUBLE("HPOUT2 DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE2L_ENA_SHIFT, ARIZONA_DRE2R_ENA_SHIFT, 1, 0), +SOC_SINGLE("EPOUT DRE Switch", ARIZONA_DRE_ENABLE, + ARIZONA_DRE3L_ENA_SHIFT, 1, 0), + +SOC_SINGLE("DRE Threshold", ARIZONA_DRE_CONTROL_2, + ARIZONA_DRE_T_LOW_SHIFT, 63, 0), + +SOC_SINGLE("DRE Low Level ABS", ARIZONA_DRE_CONTROL_3, + ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT, 15, 0), SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), @@ -828,6 +980,15 @@ SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), SOC_ENUM("Noise Gate Hold", arizona_ng_hold), +SND_SOC_BYTES_EXT("Output Compensation Coefficient", 2, + wm5102_out_comp_coeff_get, wm5102_out_comp_coeff_put), + +SOC_SINGLE_EXT("Output Compensation Switch", 0, 0, 1, 0, + wm5102_out_comp_switch_get, wm5102_out_comp_switch_put), + +SOC_VALUE_ENUM("Output Rate 1", arizona_output_rate), +SOC_VALUE_ENUM("In Rate", arizona_input_rate), + WM5102_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), WM5102_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), WM5102_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), @@ -852,6 +1013,15 @@ ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), + +ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE), }; ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); @@ -898,6 +1068,15 @@ ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE); + ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE); ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE); ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); @@ -920,7 +1099,17 @@ ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); ARIZONA_DSP_AUX_ENUMS(DSP1, ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE); -static const char *wm5102_aec_loopback_texts[] = { +static const char * const wm5102_dsp_output_texts[] = { + "None", + "DSP1", +}; + +static const SOC_ENUM_SINGLE_DECL(wm5102_dsp_output_enum, 0, 0, wm5102_dsp_output_texts); + +static const struct snd_kcontrol_new wm5102_dsp_output_mux = + SOC_DAPM_ENUM_VIRT("DSP Virtual Output Mux", wm5102_dsp_output_enum); + +static const char * const wm5102_aec_loopback_texts[] = { "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "EPOUT", "SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", }; @@ -941,7 +1130,8 @@ static const struct snd_kcontrol_new wm5102_aec_loopback_mux = static const struct snd_soc_dapm_widget wm5102_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, - 0, wm5102_sysclk_ev, SND_SOC_DAPM_POST_PMU), + 0, wm5102_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, @@ -958,7 +1148,7 @@ SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0), SND_SOC_DAPM_SIGGEN("TONE"), SND_SOC_DAPM_SIGGEN("NOISE"), -SND_SOC_DAPM_SIGGEN("HAPTICS"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), SND_SOC_DAPM_INPUT("IN1L"), SND_SOC_DAPM_INPUT("IN1R"), @@ -967,6 +1157,8 @@ SND_SOC_DAPM_INPUT("IN2R"), SND_SOC_DAPM_INPUT("IN3L"), SND_SOC_DAPM_INPUT("IN3R"), +SND_SOC_DAPM_OUTPUT("DRC1 Signal Activity"), + SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, 0, NULL, 0, arizona_in_ev, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | @@ -1117,27 +1309,85 @@ SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX8_ENA_SHIFT, 0), + ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), +SND_SOC_DAPM_VIRT_MUX("DSP Virtual Output Mux", SND_SOC_NOPM, 0, 0, + &wm5102_dsp_output_mux), + SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, &wm5102_aec_loopback_mux), SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), @@ -1189,6 +1439,15 @@ ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"), +ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"), +ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"), + ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"), ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"), ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), @@ -1206,7 +1465,9 @@ ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), -WM_ADSP2("DSP1", 0), +WM_ADSP2("DSP1", 0, wm5102_adsp_power_ev), + +SND_SOC_DAPM_OUTPUT("DSP Virtual Output"), SND_SOC_DAPM_OUTPUT("HPOUT1L"), SND_SOC_DAPM_OUTPUT("HPOUT1R"), @@ -1249,6 +1510,14 @@ SND_SOC_DAPM_OUTPUT("MICSUPP"), { name, "AIF2RX2", "AIF2RX2" }, \ { name, "AIF3RX1", "AIF3RX1" }, \ { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "SLIMRX5", "SLIMRX5" }, \ + { name, "SLIMRX6", "SLIMRX6" }, \ + { name, "SLIMRX7", "SLIMRX7" }, \ + { name, "SLIMRX8", "SLIMRX8" }, \ { name, "EQ1", "EQ1" }, \ { name, "EQ2", "EQ2" }, \ { name, "EQ3", "EQ3" }, \ @@ -1304,17 +1573,25 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { { "OUT5L", NULL, "SYSCLK" }, { "OUT5R", NULL, "SYSCLK" }, + { "IN1L", NULL, "SYSCLK" }, + { "IN1R", NULL, "SYSCLK" }, + { "IN2L", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, + { "IN3L", NULL, "SYSCLK" }, + { "IN3R", NULL, "SYSCLK" }, + { "MICBIAS1", NULL, "MICVDD" }, { "MICBIAS2", NULL, "MICVDD" }, { "MICBIAS3", NULL, "MICVDD" }, + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + { "Noise Generator", NULL, "NOISE" }, { "Tone Generator 1", NULL, "TONE" }, { "Tone Generator 2", NULL, "TONE" }, - { "Mic Mute Mixer", NULL, "Noise Mixer" }, - { "Mic Mute Mixer", NULL, "Mic Mixer" }, - { "AIF1 Capture", NULL, "AIF1TX1" }, { "AIF1 Capture", NULL, "AIF1TX2" }, { "AIF1 Capture", NULL, "AIF1TX3" }, @@ -1345,13 +1622,46 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { { "AIF3RX1", NULL, "AIF3 Playback" }, { "AIF3RX2", NULL, "AIF3 Playback" }, + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + { "SLIMRX3", NULL, "Slim1 Playback" }, + { "SLIMRX4", NULL, "Slim1 Playback" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX5", NULL, "Slim2 Playback" }, + { "SLIMRX6", NULL, "Slim2 Playback" }, + + { "Slim3 Capture", NULL, "SLIMTX7" }, + { "Slim3 Capture", NULL, "SLIMTX8" }, + + { "SLIMRX7", NULL, "Slim3 Playback" }, + { "SLIMRX8", NULL, "Slim3 Playback" }, + { "AIF1 Playback", NULL, "SYSCLK" }, { "AIF2 Playback", NULL, "SYSCLK" }, { "AIF3 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + { "Slim3 Playback", NULL, "SYSCLK" }, { "AIF1 Capture", NULL, "SYSCLK" }, { "AIF2 Capture", NULL, "SYSCLK" }, { "AIF3 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + { "Slim3 Capture", NULL, "SYSCLK" }, + + { "Trace CPU", NULL, "Trace DSP" }, + { "Trace DSP", NULL, "DSP1" }, + { "Trace CPU", NULL, "SYSCLK" }, + { "Trace DSP", NULL, "SYSCLK" }, { "IN1L PGA", NULL, "IN1L" }, { "IN1R PGA", NULL, "IN1R" }, @@ -1362,23 +1672,6 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { { "IN3L PGA", NULL, "IN3L" }, { "IN3R PGA", NULL, "IN3R" }, - { "ASRC1L", NULL, "ASRC1L Input" }, - { "ASRC1R", NULL, "ASRC1R Input" }, - { "ASRC2L", NULL, "ASRC2L Input" }, - { "ASRC2R", NULL, "ASRC2R Input" }, - - { "ISRC1DEC1", NULL, "ISRC1DEC1 Input" }, - { "ISRC1DEC2", NULL, "ISRC1DEC2 Input" }, - - { "ISRC1INT1", NULL, "ISRC1INT1 Input" }, - { "ISRC1INT2", NULL, "ISRC1INT2 Input" }, - - { "ISRC2DEC1", NULL, "ISRC2DEC1 Input" }, - { "ISRC2DEC2", NULL, "ISRC2DEC2 Input" }, - - { "ISRC2INT1", NULL, "ISRC2INT1 Input" }, - { "ISRC2INT2", NULL, "ISRC2INT2 Input" }, - ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), @@ -1408,6 +1701,15 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"), + ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"), + ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"), + ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), ARIZONA_MIXER_ROUTES("EQ3", "EQ3"), @@ -1421,25 +1723,32 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), - ARIZONA_MUX_ROUTES("ASRC1L"), - ARIZONA_MUX_ROUTES("ASRC1R"), - ARIZONA_MUX_ROUTES("ASRC2L"), - ARIZONA_MUX_ROUTES("ASRC2R"), + ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Noise"), + ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"), + + ARIZONA_MUX_ROUTES("ASRC1L", "ASRC1L"), + ARIZONA_MUX_ROUTES("ASRC1R", "ASRC1R"), + ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"), + ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"), - ARIZONA_MUX_ROUTES("ISRC1INT1"), - ARIZONA_MUX_ROUTES("ISRC1INT2"), + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), - ARIZONA_MUX_ROUTES("ISRC1DEC1"), - ARIZONA_MUX_ROUTES("ISRC1DEC2"), + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), - ARIZONA_MUX_ROUTES("ISRC2INT1"), - ARIZONA_MUX_ROUTES("ISRC2INT2"), + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), - ARIZONA_MUX_ROUTES("ISRC2DEC1"), - ARIZONA_MUX_ROUTES("ISRC2DEC2"), + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), ARIZONA_DSP_ROUTES("DSP1"), + { "DSP Virtual Output", NULL, "DSP Virtual Output Mux" }, + { "DSP Virtual Output Mux", "DSP1", "DSP1" }, + { "DSP Virtual Output", NULL, "SYSCLK" }, + { "AEC Loopback", "HPOUT1L", "OUT1L" }, { "AEC Loopback", "HPOUT1R", "OUT1R" }, { "HPOUT1L", NULL, "OUT1L" }, @@ -1468,6 +1777,9 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = { { "SPKDAT1R", NULL, "OUT5R" }, { "MICSUPP", NULL, "SYSCLK" }, + + { "DRC1 Signal Activity", NULL, "DRC1L" }, + { "DRC1 Signal Activity", NULL, "DRC1R" }, }; static int wm5102_set_fll(struct snd_soc_codec *codec, int fll_id, int source, @@ -1491,7 +1803,7 @@ static int wm5102_set_fll(struct snd_soc_codec *codec, int fll_id, int source, } } -#define WM5102_RATES SNDRV_PCM_RATE_8000_192000 +#define WM5102_RATES SNDRV_PCM_RATE_KNOT #define WM5102_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) @@ -1560,11 +1872,143 @@ static struct snd_soc_dai_driver wm5102_dai[] = { .ops = &arizona_dai_ops, .symmetric_rates = 1, }, + { + .name = "wm5102-slim1", + .id = 4, + .playback = { + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "wm5102-slim2", + .id = 5, + .playback = { + .stream_name = "Slim2 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .capture = { + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "wm5102-slim3", + .id = 6, + .playback = { + .stream_name = "Slim3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .capture = { + .stream_name = "Slim3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "wm5102-cpu-trace", + .capture = { + .stream_name = "Trace CPU", + .channels_min = 1, + .channels_max = 4, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + .compress_dai = 1, + }, + { + .name = "wm5102-dsp-trace", + .capture = { + .stream_name = "Trace DSP", + .channels_min = 1, + .channels_max = 4, + .rates = WM5102_RATES, + .formats = WM5102_FORMATS, + }, + }, }; +static irqreturn_t wm5102_adsp2_irq(int irq, void *data) +{ + struct wm5102_priv *wm5102 = data; + int i; + + for (i = 0; i < ARRAY_SIZE(wm5102->compr_info); ++i) { + if (!wm5102->compr_info[i].adsp_compr.dsp->running) + continue; + + wm_adsp_compr_irq(&wm5102->compr_info[i].adsp_compr, NULL); + } + + return IRQ_HANDLED; +} + +static struct wm5102_compr *wm5102_get_compr(struct snd_soc_pcm_runtime *rtd, + struct wm5102_priv *wm5102) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(wm5102->compr_info); ++i) { + if (strcmp(rtd->codec_dai->name, + wm5102->compr_info[i].dai_name) == 0) + return &wm5102->compr_info[i]; + } + + return NULL; +} + +static int wm5102_compr_open(struct snd_compr_stream *stream) +{ + struct snd_soc_pcm_runtime *rtd = stream->private_data; + struct wm5102_priv *wm5102 = snd_soc_codec_get_drvdata(rtd->codec); + struct arizona *arizona = wm5102->core.arizona; + struct wm5102_compr *compr; + + /* Find a compr_info for this DAI */ + compr = wm5102_get_compr(rtd, wm5102); + if (!compr) { + dev_err(arizona->dev, + "No suitable compressed stream for dai '%s'\n", + rtd->codec_dai->name); + return -EINVAL; + } + + return wm_adsp_compr_open(&compr->adsp_compr, stream); +} + +static int wm5102_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + return wm_adsp_compr_trigger(stream, cmd); +} + static int wm5102_codec_probe(struct snd_soc_codec *codec) { struct wm5102_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; int ret; codec->control_data = priv->core.arizona->regmap; @@ -1573,22 +2017,60 @@ static int wm5102_codec_probe(struct snd_soc_codec *codec) if (ret != 0) return ret; - ret = snd_soc_add_codec_controls(codec, wm_adsp2_fw_controls, 2); - if (ret != 0) + ret = wm_adsp2_codec_probe(&priv->core.adsp[0], codec); + if (ret) + return ret; + + ret = snd_soc_add_codec_controls(codec, + arizona_adsp2_rate_controls, 1); + if (ret) return ret; arizona_init_spk(codec); + arizona_init_gpio(codec); snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); priv->core.arizona->dapm = &codec->dapm; + ret = arizona_request_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, + "ADSP2 interrupt 1", wm5102_adsp2_irq, priv); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request DSP IRQ: %d\n", ret); + return ret; + } + + ret = irq_set_irq_wake(arizona->irq, 1); + if (ret) + dev_err(arizona->dev, + "Failed to set DSP IRQ to wake source: %d\n", + ret); + + snd_soc_dapm_enable_pin(&codec->dapm, "DRC1 Signal Activity"); + ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ2_STATUS_3_MASK, + ARIZONA_IM_DRC1_SIG_DET_EINT2, 0); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to unmask DRC1 IRQ for DSP: %d\n", + ret); + return ret; + } + return 0; } static int wm5102_codec_remove(struct snd_soc_codec *codec) { struct wm5102_priv *priv = snd_soc_codec_get_drvdata(codec); + struct arizona *arizona = priv->core.arizona; + + irq_set_irq_wake(arizona->irq, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_DSP_IRQ1, priv); + regmap_update_bits(arizona->regmap, ARIZONA_IRQ2_STATUS_3_MASK, + ARIZONA_IM_DRC1_SIG_DET_EINT2, + ARIZONA_IM_DRC1_SIG_DET_EINT2); + + wm_adsp2_codec_remove(&priv->core.adsp[0], codec); priv->core.arizona->dapm = NULL; @@ -1603,7 +2085,6 @@ static unsigned int wm5102_digital_vu[] = { ARIZONA_DAC_DIGITAL_VOLUME_2L, ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_DAC_DIGITAL_VOLUME_3L, - ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_DAC_DIGITAL_VOLUME_4L, ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_DAC_DIGITAL_VOLUME_5L, @@ -1627,6 +2108,44 @@ static struct snd_soc_codec_driver soc_codec_dev_wm5102 = { .num_dapm_routes = ARRAY_SIZE(wm5102_dapm_routes), }; +static struct snd_compr_ops wm5102_compr_ops = { + .open = wm5102_compr_open, + .free = wm_adsp_compr_free, + .set_params = wm_adsp_compr_set_params, + .trigger = wm5102_compr_trigger, + .pointer = wm_adsp_compr_pointer, + .copy = wm_adsp_compr_copy, + .get_caps = wm_adsp_compr_get_caps, +}; + +static struct snd_soc_platform_driver wm5102_compr_platform = { + .compr_ops = &wm5102_compr_ops, +}; + +static void wm5102_init_compr_info(struct wm5102_priv *wm5102) +{ + struct wm_adsp *dsp; + int i; + + BUILD_BUG_ON(ARRAY_SIZE(wm5102->compr_info) != + ARRAY_SIZE(compr_dai_mapping)); + + for (i = 0; i < ARRAY_SIZE(wm5102->compr_info); ++i) { + wm5102->compr_info[i].dai_name = compr_dai_mapping[i].dai_name; + + dsp = &wm5102->core.adsp[compr_dai_mapping[i].adsp_num], + wm_adsp_compr_init(dsp, &wm5102->compr_info[i].adsp_compr); + } +} + +static void wm5102_destroy_compr_info(struct wm5102_priv *wm5102) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(wm5102->compr_info); ++i) + wm_adsp_compr_destroy(&wm5102->compr_info[i].adsp_compr); +} + static int wm5102_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); @@ -1639,9 +2158,17 @@ static int wm5102_probe(struct platform_device *pdev) return -ENOMEM; platform_set_drvdata(pdev, wm5102); + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; + + mutex_init(&wm5102->fw_lock); + wm5102->core.arizona = arizona; wm5102->core.num_inputs = 6; + arizona_init_dvfs(&wm5102->core); + wm5102->core.adsp[0].part = "wm5102"; wm5102->core.adsp[0].num = 1; wm5102->core.adsp[0].type = WMFW_ADSP2; @@ -1651,10 +2178,22 @@ static int wm5102_probe(struct platform_device *pdev) wm5102->core.adsp[0].mem = wm5102_dsp1_regions; wm5102->core.adsp[0].num_mems = ARRAY_SIZE(wm5102_dsp1_regions); - ret = wm_adsp2_init(&wm5102->core.adsp[0], true); + if (arizona->pdata.num_fw_defs[0]) { + wm5102->core.adsp[0].firmwares + = arizona->pdata.fw_defs[0]; + + wm5102->core.adsp[0].num_firmwares + = arizona->pdata.num_fw_defs[0]; + } + + wm5102->core.adsp[0].hpimp_cb = arizona_hpimp_cb; + + ret = wm_adsp2_init(&wm5102->core.adsp[0], &wm5102->fw_lock); if (ret != 0) return ret; + wm5102_init_compr_info(wm5102); + for (i = 0; i < ARRAY_SIZE(wm5102->fll); i++) wm5102->fll[i].vco_mult = 1; @@ -1665,12 +2204,6 @@ static int wm5102_probe(struct platform_device *pdev) ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, &wm5102->fll[1]); - /* SR2 fixed at 8kHz, SR3 fixed at 16kHz */ - regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_2, - ARIZONA_SAMPLE_RATE_2_MASK, 0x11); - regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_3, - ARIZONA_SAMPLE_RATE_3_MASK, 0x12); - for (i = 0; i < ARRAY_SIZE(wm5102_dai); i++) arizona_init_dai(&wm5102->core, i); @@ -1682,15 +2215,44 @@ static int wm5102_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); pm_runtime_idle(&pdev->dev); - return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm5102, + ret = snd_soc_register_platform(&pdev->dev, &wm5102_compr_platform); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register platform: %d\n", + ret); + goto error; + } + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm5102, wm5102_dai, ARRAY_SIZE(wm5102_dai)); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to register codec: %d\n", + ret); + snd_soc_unregister_platform(&pdev->dev); + goto error; + } + + return ret; + +error: + wm5102_destroy_compr_info(wm5102); + mutex_destroy(&wm5102->fw_lock); + + return ret; } static int wm5102_remove(struct platform_device *pdev) { + struct wm5102_priv *wm5102 = platform_get_drvdata(pdev); + snd_soc_unregister_codec(&pdev->dev); pm_runtime_disable(&pdev->dev); + wm5102_destroy_compr_info(wm5102); + + wm_adsp2_remove(&wm5102->core.adsp[0]); + return 0; } diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 305d28dec66..5dd271084e9 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3577,7 +3577,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8962 = { }; /* Improve power consumption for IN4 DC measurement mode */ -static const struct reg_default wm8962_dc_measure[] = { +static const struct reg_sequence wm8962_dc_measure[] = { { 0xfd, 0x1 }, { 0xcc, 0x40 }, { 0xfd, 0 }, diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c index 433d59a0f3e..4fdde53e651 100644 --- a/sound/soc/codecs/wm8993.c +++ b/sound/soc/codecs/wm8993.c @@ -1618,7 +1618,7 @@ static int wm8993_resume(struct snd_soc_codec *codec) #endif /* Tune DC servo configuration */ -static struct reg_default wm8993_regmap_patch[] = { +static struct reg_sequence wm8993_regmap_patch[] = { { 0x44, 3 }, { 0x56, 3 }, { 0x44, 0 }, diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm8997.c similarity index 58% rename from sound/soc/codecs/wm5110.c rename to sound/soc/codecs/wm8997.c index 3775394c9c8..de851c1a238 100644 --- a/sound/soc/codecs/wm5110.c +++ b/sound/soc/codecs/wm8997.c @@ -1,9 +1,9 @@ /* - * wm5110.c -- WM5110 ALSA SoC Audio driver + * wm8997.c -- WM8997 ALSA SoC Audio driver * * Copyright 2012 Wolfson Microelectronics plc * - * Author: Mark Brown + * Author: Charles Keepax * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -30,9 +30,9 @@ #include #include "arizona.h" -#include "wm5110.h" +#include "wm8997.h" -struct wm5110_priv { +struct wm8997_priv { struct arizona_priv core; struct arizona_fll fll[2]; }; @@ -132,29 +132,108 @@ static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0); static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); -#define WM5110_NG_SRC(name, base) \ - SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ - SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ - SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \ - SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \ - SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \ - SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \ - SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \ - SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \ - SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ - SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \ - SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \ - SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0) - -static const struct snd_kcontrol_new wm5110_snd_controls[] = { +static const struct reg_default wm8997_sysclk_reva_patch[] = { + { 0x301D, 0x7B15 }, + { 0x301B, 0x0050 }, + { 0x305D, 0x7B17 }, + { 0x305B, 0x0050 }, + { 0x3001, 0x08FE }, + { 0x3003, 0x00F4 }, + { 0x3041, 0x08FF }, + { 0x3043, 0x0005 }, + { 0x3020, 0x0225 }, + { 0x3021, 0x0A00 }, + { 0x3022, 0xE24D }, + { 0x3023, 0x0800 }, + { 0x3024, 0xE24D }, + { 0x3025, 0xF000 }, + { 0x3060, 0x0226 }, + { 0x3061, 0x0A00 }, + { 0x3062, 0xE252 }, + { 0x3063, 0x0800 }, + { 0x3064, 0xE252 }, + { 0x3065, 0xF000 }, + { 0x3116, 0x022B }, + { 0x3117, 0xFA00 }, + { 0x3110, 0x246C }, + { 0x3111, 0x0A03 }, + { 0x3112, 0x246E }, + { 0x3113, 0x0A03 }, + { 0x3114, 0x2470 }, + { 0x3115, 0x0A03 }, + { 0x3126, 0x246C }, + { 0x3127, 0x0A02 }, + { 0x3128, 0x246E }, + { 0x3129, 0x0A02 }, + { 0x312A, 0x2470 }, + { 0x312B, 0xFA02 }, + { 0x3125, 0x0800 }, +}; + +static int wm8997_sysclk_ev(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct arizona *arizona = dev_get_drvdata(codec->dev->parent); + struct regmap *regmap = codec->control_data; + const struct reg_default *patch = NULL; + int i, patch_size; + + switch (arizona->rev) { + case 0: + patch = wm8997_sysclk_reva_patch; + patch_size = ARRAY_SIZE(wm8997_sysclk_reva_patch); + break; + default: + break; + } + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (patch) + for (i = 0; i < patch_size; i++) + regmap_write(regmap, patch[i].reg, + patch[i].def); + break; + case SND_SOC_DAPM_PRE_PMD: + break; + default: + return 0; + } + + return arizona_dvfs_sysclk_ev(w, kcontrol, event); +} + +static const char * const wm8997_osr_text[] = { + "Low power", "Normal", "High performance", +}; + +static const unsigned int wm8997_osr_val[] = { + 0x0, 0x3, 0x5, +}; + +static const struct soc_enum wm8997_hpout_osr[] = { + SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_1L, + ARIZONA_OUT1_OSR_SHIFT, 0x7, 3, + wm8997_osr_text, wm8997_osr_val), + SOC_VALUE_ENUM_SINGLE(ARIZONA_OUTPUT_PATH_CONFIG_3L, + ARIZONA_OUT3_OSR_SHIFT, 0x7, 3, + wm8997_osr_text, wm8997_osr_val), +}; + +#define WM8997_NG_SRC(name, base) \ + SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \ + SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \ + SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \ + SOC_SINGLE(name " NG SPKOUT Switch", base, 6, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \ + SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0) + +static const struct snd_kcontrol_new wm8997_snd_controls[] = { SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT, 1, 0), SOC_SINGLE("IN2 High Performance Switch", ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT, 1, 0), -SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL, - ARIZONA_IN3_OSR_SHIFT, 1, 0), -SOC_SINGLE("IN4 High Performance Switch", ARIZONA_IN4L_CONTROL, - ARIZONA_IN4_OSR_SHIFT, 1, 0), SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL, ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), @@ -164,10 +243,6 @@ SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL, ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL, ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), -SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL, - ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), -SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL, - ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), @@ -177,14 +252,6 @@ SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), -SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, - ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), -SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R, - ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), -SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, - ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), -SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R, - ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv), SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), @@ -194,15 +261,7 @@ ARIZONA_MIXER_CONTROLS("EQ2", ARIZONA_EQ2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("EQ3", ARIZONA_EQ3MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("EQ4", ARIZONA_EQ4MIX_INPUT_1_SOURCE), -SND_SOC_BYTES_MASK("EQ1 Coefficeints", ARIZONA_EQ1_1, 21, - ARIZONA_EQ1_ENA_MASK), -SND_SOC_BYTES_MASK("EQ2 Coefficeints", ARIZONA_EQ2_1, 21, - ARIZONA_EQ2_ENA_MASK), -SND_SOC_BYTES_MASK("EQ3 Coefficeints", ARIZONA_EQ3_1, 21, - ARIZONA_EQ3_ENA_MASK), -SND_SOC_BYTES_MASK("EQ4 Coefficeints", ARIZONA_EQ4_1, 21, - ARIZONA_EQ4_ENA_MASK), - +ARIZONA_EQ_CONTROL("EQ1 Coefficients", ARIZONA_EQ1_2), SOC_SINGLE_TLV("EQ1 B1 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ1 B2 Volume", ARIZONA_EQ1_1, ARIZONA_EQ1_B2_GAIN_SHIFT, @@ -214,6 +273,7 @@ SOC_SINGLE_TLV("EQ1 B4 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B4_GAIN_SHIFT, SOC_SINGLE_TLV("EQ1 B5 Volume", ARIZONA_EQ1_2, ARIZONA_EQ1_B5_GAIN_SHIFT, 24, 0, eq_tlv), +ARIZONA_EQ_CONTROL("EQ2 Coefficients", ARIZONA_EQ2_2), SOC_SINGLE_TLV("EQ2 B1 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ2 B2 Volume", ARIZONA_EQ2_1, ARIZONA_EQ2_B2_GAIN_SHIFT, @@ -225,6 +285,7 @@ SOC_SINGLE_TLV("EQ2 B4 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B4_GAIN_SHIFT, SOC_SINGLE_TLV("EQ2 B5 Volume", ARIZONA_EQ2_2, ARIZONA_EQ2_B5_GAIN_SHIFT, 24, 0, eq_tlv), +ARIZONA_EQ_CONTROL("EQ3 Coefficients", ARIZONA_EQ3_2), SOC_SINGLE_TLV("EQ3 B1 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ3 B2 Volume", ARIZONA_EQ3_1, ARIZONA_EQ3_B2_GAIN_SHIFT, @@ -236,6 +297,7 @@ SOC_SINGLE_TLV("EQ3 B4 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B4_GAIN_SHIFT, SOC_SINGLE_TLV("EQ3 B5 Volume", ARIZONA_EQ3_2, ARIZONA_EQ3_B5_GAIN_SHIFT, 24, 0, eq_tlv), +ARIZONA_EQ_CONTROL("EQ4 Coefficients", ARIZONA_EQ4_2), SOC_SINGLE_TLV("EQ4 B1 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B1_GAIN_SHIFT, 24, 0, eq_tlv), SOC_SINGLE_TLV("EQ4 B2 Volume", ARIZONA_EQ4_1, ARIZONA_EQ4_B2_GAIN_SHIFT, @@ -249,37 +311,27 @@ SOC_SINGLE_TLV("EQ4 B5 Volume", ARIZONA_EQ4_2, ARIZONA_EQ4_B5_GAIN_SHIFT, ARIZONA_MIXER_CONTROLS("DRC1L", ARIZONA_DRC1LMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("DRC1R", ARIZONA_DRC1RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DRC2L", ARIZONA_DRC2LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DRC2R", ARIZONA_DRC2RMIX_INPUT_1_SOURCE), SND_SOC_BYTES_MASK("DRC1", ARIZONA_DRC1_CTRL1, 5, ARIZONA_DRC1R_ENA | ARIZONA_DRC1L_ENA), -SND_SOC_BYTES_MASK("DRC2", ARIZONA_DRC2_CTRL1, 5, - ARIZONA_DRC2R_ENA | ARIZONA_DRC2L_ENA), ARIZONA_MIXER_CONTROLS("LHPF1", ARIZONA_HPLP1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("LHPF2", ARIZONA_HPLP2MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("LHPF3", ARIZONA_HPLP3MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("LHPF4", ARIZONA_HPLP4MIX_INPUT_1_SOURCE), -SND_SOC_BYTES("LHPF1 Coefficients", ARIZONA_HPLPF1_2, 1), -SND_SOC_BYTES("LHPF2 Coefficients", ARIZONA_HPLPF2_2, 1), -SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1), -SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1), - SOC_ENUM("LHPF1 Mode", arizona_lhpf1_mode), SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode), SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), -ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP2L", ARIZONA_DSP2LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP2R", ARIZONA_DSP2RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP3L", ARIZONA_DSP3LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP3R", ARIZONA_DSP3RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP4L", ARIZONA_DSP4LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("DSP4R", ARIZONA_DSP4RMIX_INPUT_1_SOURCE), +ARIZONA_LHPF_CONTROL("LHPF1 Coefficients", ARIZONA_HPLPF1_2), +ARIZONA_LHPF_CONTROL("LHPF2 Coefficients", ARIZONA_HPLPF2_2), +ARIZONA_LHPF_CONTROL("LHPF3 Coefficients", ARIZONA_HPLPF3_2), +ARIZONA_LHPF_CONTROL("LHPF4 Coefficients", ARIZONA_HPLPF4_2), + +SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), +SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE), @@ -289,100 +341,57 @@ SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR, ARIZONA_MIXER_CONTROLS("HPOUT1L", ARIZONA_OUT1LMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("HPOUT1R", ARIZONA_OUT1RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("HPOUT2L", ARIZONA_OUT2LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("HPOUT2R", ARIZONA_OUT2RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("HPOUT3L", ARIZONA_OUT3LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("HPOUT3R", ARIZONA_OUT3RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("SPKOUTL", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("SPKOUTR", ARIZONA_OUT4RMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("EPOUT", ARIZONA_OUT3LMIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SPKOUT", ARIZONA_OUT4LMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("SPKDAT1L", ARIZONA_OUT5LMIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("SPKDAT2L", ARIZONA_OUT6LMIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("SPKDAT2R", ARIZONA_OUT6RMIX_INPUT_1_SOURCE), - -SOC_SINGLE("HPOUT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_1L, - ARIZONA_OUT1_OSR_SHIFT, 1, 0), -SOC_SINGLE("HPOUT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_2L, - ARIZONA_OUT2_OSR_SHIFT, 1, 0), -SOC_SINGLE("HPOUT3 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_3L, - ARIZONA_OUT3_OSR_SHIFT, 1, 0), + SOC_SINGLE("Speaker High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_4L, ARIZONA_OUT4_OSR_SHIFT, 1, 0), SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L, ARIZONA_OUT5_OSR_SHIFT, 1, 0), -SOC_SINGLE("SPKDAT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_6L, - ARIZONA_OUT6_OSR_SHIFT, 1, 0), SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, - ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("HPOUT3 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L, - ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, - ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("EPOUT Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_OUT3L_MUTE_SHIFT, 1, 1), +SOC_SINGLE("Speaker Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_MUTE_SHIFT, 1, 1), SOC_DOUBLE_R("SPKDAT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_5L, ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_MUTE_SHIFT, 1, 1), -SOC_DOUBLE_R("SPKDAT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_6L, - ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_MUTE_SHIFT, 1, 1), SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_1L, ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_VOL_SHIFT, 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_2L, - ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_OUT2L_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L, - ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_OUT3L_VOL_SHIFT, - 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, - ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_OUT4L_VOL_SHIFT, - 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("EPOUT Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_3L, + ARIZONA_OUT3L_VOL_SHIFT, 0xbf, 0, digital_tlv), +SOC_SINGLE_TLV("Speaker Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_4L, + ARIZONA_OUT4L_VOL_SHIFT, 0xbf, 0, digital_tlv), SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L, ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, 0xbf, 0, digital_tlv), -SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_6L, - ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_VOL_SHIFT, - 0xbf, 0, digital_tlv), - -SOC_DOUBLE_R_RANGE_TLV("HPOUT1 Volume", ARIZONA_OUTPUT_PATH_CONFIG_1L, - ARIZONA_OUTPUT_PATH_CONFIG_1R, - ARIZONA_OUT1L_PGA_VOL_SHIFT, - 0x34, 0x40, 0, ana_tlv), -SOC_DOUBLE_R_RANGE_TLV("HPOUT2 Volume", ARIZONA_OUTPUT_PATH_CONFIG_2L, - ARIZONA_OUTPUT_PATH_CONFIG_2R, - ARIZONA_OUT2L_PGA_VOL_SHIFT, - 0x34, 0x40, 0, ana_tlv), -SOC_DOUBLE_R_RANGE_TLV("HPOUT3 Volume", ARIZONA_OUTPUT_PATH_CONFIG_3L, - ARIZONA_OUTPUT_PATH_CONFIG_3R, - ARIZONA_OUT3L_PGA_VOL_SHIFT, 0x34, 0x40, 0, ana_tlv), -SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, - ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), -SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT, - ARIZONA_SPK2R_MUTE_SHIFT, 1, 1), +SOC_VALUE_ENUM("HPOUT1 OSR", wm8997_hpout_osr[0]), +SOC_VALUE_ENUM("EPOUT OSR", wm8997_hpout_osr[1]), SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), +SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, + ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), + SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_ENA_SHIFT, 1, 0), SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv), SOC_ENUM("Noise Gate Hold", arizona_ng_hold), -WM5110_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), -WM5110_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), -WM5110_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L), -WM5110_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R), -WM5110_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L), -WM5110_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R), -WM5110_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L), -WM5110_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R), -WM5110_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), -WM5110_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), -WM5110_NG_SRC("SPKDAT2L", ARIZONA_NOISE_GATE_SELECT_6L), -WM5110_NG_SRC("SPKDAT2R", ARIZONA_NOISE_GATE_SELECT_6R), +WM8997_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L), +WM8997_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R), +WM8997_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L), +WM8997_NG_SRC("SPKOUT", ARIZONA_NOISE_GATE_SELECT_4L), +WM8997_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L), +WM8997_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R), ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), @@ -396,8 +405,14 @@ ARIZONA_MIXER_CONTROLS("AIF1TX8", ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF2TX1", ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE), ARIZONA_MIXER_CONTROLS("AIF2TX2", ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("AIF3TX1", ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE), -ARIZONA_MIXER_CONTROLS("AIF3TX2", ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX1", ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX2", ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX3", ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX4", ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX5", ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX6", ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX7", ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE), +ARIZONA_MIXER_CONTROLS("SLIMTX8", ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE), }; ARIZONA_MIXER_ENUMS(EQ1, ARIZONA_EQ1MIX_INPUT_1_SOURCE); @@ -407,8 +422,6 @@ ARIZONA_MIXER_ENUMS(EQ4, ARIZONA_EQ4MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(DRC1L, ARIZONA_DRC1LMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(DRC1R, ARIZONA_DRC1RMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(DRC2L, ARIZONA_DRC2LMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(DRC2R, ARIZONA_DRC2RMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(LHPF1, ARIZONA_HPLP1MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(LHPF2, ARIZONA_HPLP2MIX_INPUT_1_SOURCE); @@ -423,16 +436,10 @@ ARIZONA_MIXER_ENUMS(PWM2, ARIZONA_PWM2MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(OUT1L, ARIZONA_OUT1LMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(OUT1R, ARIZONA_OUT1RMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(OUT2L, ARIZONA_OUT2LMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(OUT2R, ARIZONA_OUT2RMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(OUT3L, ARIZONA_OUT3LMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(OUT3R, ARIZONA_OUT3RMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(SPKOUTL, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(SPKOUTR, ARIZONA_OUT4RMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(OUT3, ARIZONA_OUT3LMIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SPKOUT, ARIZONA_OUT4LMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(SPKDAT1L, ARIZONA_OUT5LMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(SPKDAT1R, ARIZONA_OUT5RMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(SPKDAT2L, ARIZONA_OUT6LMIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(SPKDAT2R, ARIZONA_OUT6RMIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(AIF1TX1, ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(AIF1TX2, ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE); @@ -446,36 +453,49 @@ ARIZONA_MIXER_ENUMS(AIF1TX8, ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(AIF2TX1, ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE); ARIZONA_MIXER_ENUMS(AIF2TX2, ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(AIF3TX1, ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE); -ARIZONA_MIXER_ENUMS(AIF3TX2, ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX1, ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX2, ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX3, ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX4, ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX5, ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX6, ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX7, ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE); +ARIZONA_MIXER_ENUMS(SLIMTX8, ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE); -ARIZONA_MUX_ENUMS(ASRC1L, ARIZONA_ASRC1LMIX_INPUT_1_SOURCE); -ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE); -ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); -ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE); -static const char *wm5110_aec_loopback_texts[] = { - "HPOUT1L", "HPOUT1R", "HPOUT2L", "HPOUT2R", "HPOUT3L", "HPOUT3R", - "SPKOUTL", "SPKOUTR", "SPKDAT1L", "SPKDAT1R", "SPKDAT2L", "SPKDAT2R", +ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE); + +ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE); +ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE); + +static const char * const wm8997_aec_loopback_texts[] = { + "HPOUT1L", "HPOUT1R", "EPOUT", "SPKOUT", "SPKDAT1L", "SPKDAT1R", }; -static const unsigned int wm5110_aec_loopback_values[] = { - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, +static const unsigned int wm8997_aec_loopback_values[] = { + 0, 1, 4, 6, 8, 9, }; -static const struct soc_enum wm5110_aec_loopback = +static const struct soc_enum wm8997_aec_loopback = SOC_VALUE_ENUM_SINGLE(ARIZONA_DAC_AEC_CONTROL_1, ARIZONA_AEC_LOOPBACK_SRC_SHIFT, 0xf, - ARRAY_SIZE(wm5110_aec_loopback_texts), - wm5110_aec_loopback_texts, - wm5110_aec_loopback_values); + ARRAY_SIZE(wm8997_aec_loopback_texts), + wm8997_aec_loopback_texts, + wm8997_aec_loopback_values); -static const struct snd_kcontrol_new wm5110_aec_loopback_mux = - SOC_DAPM_VALUE_ENUM("AEC Loopback", wm5110_aec_loopback); +static const struct snd_kcontrol_new wm8997_aec_loopback_mux = + SOC_DAPM_VALUE_ENUM("AEC Loopback", wm8997_aec_loopback); -static const struct snd_soc_dapm_widget wm5110_dapm_widgets[] = { +static const struct snd_soc_dapm_widget wm8997_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, - 0, wm5110_sysclk_ev, SND_SOC_DAPM_POST_PMU), + 0, wm8997_sysclk_ev, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), SND_SOC_DAPM_SUPPLY("ASYNCCLK", ARIZONA_ASYNC_CLOCK_1, ARIZONA_ASYNC_CLK_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("OPCLK", ARIZONA_OUTPUT_SYSTEM_CLOCK, @@ -484,24 +504,18 @@ SND_SOC_DAPM_SUPPLY("ASYNCOPCLK", ARIZONA_OUTPUT_ASYNC_CLOCK, ARIZONA_OPCLK_ASYNC_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0), -SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0), SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), SND_SOC_DAPM_REGULATOR_SUPPLY("MICVDD", 0, SND_SOC_DAPM_REGULATOR_BYPASS), -SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDL", 0, 0), -SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDDR", 0, 0), +SND_SOC_DAPM_REGULATOR_SUPPLY("SPKVDD", 0, 0), SND_SOC_DAPM_SIGGEN("TONE"), SND_SOC_DAPM_SIGGEN("NOISE"), -SND_SOC_DAPM_SIGGEN("HAPTICS"), +SND_SOC_DAPM_MIC("HAPTICS", NULL), SND_SOC_DAPM_INPUT("IN1L"), SND_SOC_DAPM_INPUT("IN1R"), SND_SOC_DAPM_INPUT("IN2L"), SND_SOC_DAPM_INPUT("IN2R"), -SND_SOC_DAPM_INPUT("IN3L"), -SND_SOC_DAPM_INPUT("IN3R"), -SND_SOC_DAPM_INPUT("IN4L"), -SND_SOC_DAPM_INPUT("IN4R"), SND_SOC_DAPM_PGA_E("IN1L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN1L_ENA_SHIFT, 0, NULL, 0, arizona_in_ev, @@ -519,29 +533,13 @@ SND_SOC_DAPM_PGA_E("IN2R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN2R_ENA_SHIFT, 0, NULL, 0, arizona_in_ev, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("IN3L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3L_ENA_SHIFT, - 0, NULL, 0, arizona_in_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("IN3R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN3R_ENA_SHIFT, - 0, NULL, 0, arizona_in_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("IN4L PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4L_ENA_SHIFT, - 0, NULL, 0, arizona_in_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("IN4R PGA", ARIZONA_INPUT_ENABLES, ARIZONA_IN4R_ENA_SHIFT, - 0, NULL, 0, arizona_in_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_SUPPLY("MICBIAS1", ARIZONA_MIC_BIAS_CTRL_1, ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS2", ARIZONA_MIC_BIAS_CTRL_2, - ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + ARIZONA_MICB2_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS3", ARIZONA_MIC_BIAS_CTRL_3, - ARIZONA_MICB1_ENA_SHIFT, 0, NULL, 0), + ARIZONA_MICB3_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR, ARIZONA_NOISE_GEN_ENA_SHIFT, 0, NULL, 0), @@ -563,10 +561,6 @@ SND_SOC_DAPM_PGA("DRC1L", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1L_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_PGA("DRC1R", ARIZONA_DRC1_CTRL1, ARIZONA_DRC1R_ENA_SHIFT, 0, NULL, 0), -SND_SOC_DAPM_PGA("DRC2L", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2L_ENA_SHIFT, 0, - NULL, 0), -SND_SOC_DAPM_PGA("DRC2R", ARIZONA_DRC2_CTRL1, ARIZONA_DRC2R_ENA_SHIFT, 0, - NULL, 0), SND_SOC_DAPM_PGA("LHPF1", ARIZONA_HPLPF1_1, ARIZONA_LHPF1_ENA_SHIFT, 0, NULL, 0), @@ -582,18 +576,25 @@ SND_SOC_DAPM_PGA("PWM1 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM1_ENA_SHIFT, SND_SOC_DAPM_PGA("PWM2 Driver", ARIZONA_PWM_DRIVE_1, ARIZONA_PWM2_ENA_SHIFT, 0, NULL, 0), -SND_SOC_DAPM_PGA("ASRC1L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1L_ENA_SHIFT, 0, - NULL, 0), -SND_SOC_DAPM_PGA("ASRC1R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC1R_ENA_SHIFT, 0, - NULL, 0), -SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0, - NULL, 0), -SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0, - NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0), -SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, - ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, - &wm5110_aec_loopback_mux), +SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3, + ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0), + +SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0), +SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3, + ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0), SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), @@ -639,46 +640,78 @@ SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, SND_SOC_DAPM_AIF_IN("AIF2RX2", NULL, 0, ARIZONA_AIF2_RX_ENABLES, ARIZONA_AIF2RX2_ENA_SHIFT, 0), -SND_SOC_DAPM_AIF_OUT("AIF3TX1", NULL, 0, - ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX1_ENA_SHIFT, 0), -SND_SOC_DAPM_AIF_OUT("AIF3TX2", NULL, 0, - ARIZONA_AIF3_TX_ENABLES, ARIZONA_AIF3TX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX1", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX2", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX3", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX4", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX5", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX6", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX7", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_OUT("SLIMTX8", NULL, 0, + ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE, + ARIZONA_SLIMTX8_ENA_SHIFT, 0), + +SND_SOC_DAPM_AIF_IN("SLIMRX1", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX1_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX2", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX2_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX3", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX3_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX4", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX4_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX5", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX5_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX6", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX6_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX7", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX7_ENA_SHIFT, 0), +SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0, + ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, + ARIZONA_SLIMRX8_ENA_SHIFT, 0), -SND_SOC_DAPM_AIF_IN("AIF3RX1", NULL, 0, - ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX1_ENA_SHIFT, 0), -SND_SOC_DAPM_AIF_IN("AIF3RX2", NULL, 0, - ARIZONA_AIF3_RX_ENABLES, ARIZONA_AIF3RX2_ENA_SHIFT, 0), +SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, + ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, + &wm8997_aec_loopback_mux), SND_SOC_DAPM_PGA_E("OUT1L", SND_SOC_NOPM, ARIZONA_OUT1L_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT1R", SND_SOC_NOPM, ARIZONA_OUT1R_ENA_SHIFT, 0, NULL, 0, arizona_hp_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("OUT2L", ARIZONA_OUTPUT_ENABLES_1, - ARIZONA_OUT2L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("OUT2R", ARIZONA_OUTPUT_ENABLES_1, - ARIZONA_OUT2R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT3L", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT3L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("OUT3R", ARIZONA_OUTPUT_ENABLES_1, - ARIZONA_OUT3R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD | + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT5L", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT5L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), SND_SOC_DAPM_PGA_E("OUT5R", ARIZONA_OUTPUT_ENABLES_1, ARIZONA_OUT5R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("OUT6L", ARIZONA_OUTPUT_ENABLES_1, - ARIZONA_OUT6L_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), -SND_SOC_DAPM_PGA_E("OUT6R", ARIZONA_OUTPUT_ENABLES_1, - ARIZONA_OUT6R_ENA_SHIFT, 0, NULL, 0, arizona_out_ev, - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), ARIZONA_MIXER_WIDGETS(EQ1, "EQ1"), ARIZONA_MIXER_WIDGETS(EQ2, "EQ2"), @@ -687,8 +720,6 @@ ARIZONA_MIXER_WIDGETS(EQ4, "EQ4"), ARIZONA_MIXER_WIDGETS(DRC1L, "DRC1L"), ARIZONA_MIXER_WIDGETS(DRC1R, "DRC1R"), -ARIZONA_MIXER_WIDGETS(DRC2L, "DRC2L"), -ARIZONA_MIXER_WIDGETS(DRC2R, "DRC2R"), ARIZONA_MIXER_WIDGETS(LHPF1, "LHPF1"), ARIZONA_MIXER_WIDGETS(LHPF2, "LHPF2"), @@ -703,16 +734,10 @@ ARIZONA_MIXER_WIDGETS(PWM2, "PWM2"), ARIZONA_MIXER_WIDGETS(OUT1L, "HPOUT1L"), ARIZONA_MIXER_WIDGETS(OUT1R, "HPOUT1R"), -ARIZONA_MIXER_WIDGETS(OUT2L, "HPOUT2L"), -ARIZONA_MIXER_WIDGETS(OUT2R, "HPOUT2R"), -ARIZONA_MIXER_WIDGETS(OUT3L, "HPOUT3L"), -ARIZONA_MIXER_WIDGETS(OUT3R, "HPOUT3R"), -ARIZONA_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"), -ARIZONA_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"), +ARIZONA_MIXER_WIDGETS(OUT3, "EPOUT"), +ARIZONA_MIXER_WIDGETS(SPKOUT, "SPKOUT"), ARIZONA_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"), ARIZONA_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"), -ARIZONA_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"), -ARIZONA_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"), ARIZONA_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"), ARIZONA_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"), @@ -726,28 +751,35 @@ ARIZONA_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"), ARIZONA_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"), ARIZONA_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"), -ARIZONA_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"), -ARIZONA_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX1, "SLIMTX1"), +ARIZONA_MIXER_WIDGETS(SLIMTX2, "SLIMTX2"), +ARIZONA_MIXER_WIDGETS(SLIMTX3, "SLIMTX3"), +ARIZONA_MIXER_WIDGETS(SLIMTX4, "SLIMTX4"), +ARIZONA_MIXER_WIDGETS(SLIMTX5, "SLIMTX5"), +ARIZONA_MIXER_WIDGETS(SLIMTX6, "SLIMTX6"), +ARIZONA_MIXER_WIDGETS(SLIMTX7, "SLIMTX7"), +ARIZONA_MIXER_WIDGETS(SLIMTX8, "SLIMTX8"), + +ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"), +ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"), +ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"), -ARIZONA_MUX_WIDGETS(ASRC1L, "ASRC1L"), -ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"), -ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), -ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"), +ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"), +ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"), + +ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"), +ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"), SND_SOC_DAPM_OUTPUT("HPOUT1L"), SND_SOC_DAPM_OUTPUT("HPOUT1R"), -SND_SOC_DAPM_OUTPUT("HPOUT2L"), -SND_SOC_DAPM_OUTPUT("HPOUT2R"), -SND_SOC_DAPM_OUTPUT("HPOUT3L"), -SND_SOC_DAPM_OUTPUT("HPOUT3R"), -SND_SOC_DAPM_OUTPUT("SPKOUTLN"), -SND_SOC_DAPM_OUTPUT("SPKOUTLP"), -SND_SOC_DAPM_OUTPUT("SPKOUTRN"), -SND_SOC_DAPM_OUTPUT("SPKOUTRP"), +SND_SOC_DAPM_OUTPUT("EPOUTN"), +SND_SOC_DAPM_OUTPUT("EPOUTP"), +SND_SOC_DAPM_OUTPUT("SPKOUTN"), +SND_SOC_DAPM_OUTPUT("SPKOUTP"), SND_SOC_DAPM_OUTPUT("SPKDAT1L"), SND_SOC_DAPM_OUTPUT("SPKDAT1R"), -SND_SOC_DAPM_OUTPUT("SPKDAT2L"), -SND_SOC_DAPM_OUTPUT("SPKDAT2R"), SND_SOC_DAPM_OUTPUT("MICSUPP"), }; @@ -762,10 +794,6 @@ SND_SOC_DAPM_OUTPUT("MICSUPP"), { name, "IN1R", "IN1R PGA" }, \ { name, "IN2L", "IN2L PGA" }, \ { name, "IN2R", "IN2R PGA" }, \ - { name, "IN3L", "IN3L PGA" }, \ - { name, "IN3R", "IN3R PGA" }, \ - { name, "IN4L", "IN4L PGA" }, \ - { name, "IN4R", "IN4R PGA" }, \ { name, "Mic Mute Mixer", "Mic Mute Mixer" }, \ { name, "AIF1RX1", "AIF1RX1" }, \ { name, "AIF1RX2", "AIF1RX2" }, \ @@ -777,65 +805,65 @@ SND_SOC_DAPM_OUTPUT("MICSUPP"), { name, "AIF1RX8", "AIF1RX8" }, \ { name, "AIF2RX1", "AIF2RX1" }, \ { name, "AIF2RX2", "AIF2RX2" }, \ - { name, "AIF3RX1", "AIF3RX1" }, \ - { name, "AIF3RX2", "AIF3RX2" }, \ + { name, "SLIMRX1", "SLIMRX1" }, \ + { name, "SLIMRX2", "SLIMRX2" }, \ + { name, "SLIMRX3", "SLIMRX3" }, \ + { name, "SLIMRX4", "SLIMRX4" }, \ + { name, "SLIMRX5", "SLIMRX5" }, \ + { name, "SLIMRX6", "SLIMRX6" }, \ + { name, "SLIMRX7", "SLIMRX7" }, \ + { name, "SLIMRX8", "SLIMRX8" }, \ { name, "EQ1", "EQ1" }, \ { name, "EQ2", "EQ2" }, \ { name, "EQ3", "EQ3" }, \ { name, "EQ4", "EQ4" }, \ { name, "DRC1L", "DRC1L" }, \ { name, "DRC1R", "DRC1R" }, \ - { name, "DRC2L", "DRC2L" }, \ - { name, "DRC2R", "DRC2R" }, \ { name, "LHPF1", "LHPF1" }, \ { name, "LHPF2", "LHPF2" }, \ { name, "LHPF3", "LHPF3" }, \ { name, "LHPF4", "LHPF4" }, \ - { name, "ASRC1L", "ASRC1L" }, \ - { name, "ASRC1R", "ASRC1R" }, \ - { name, "ASRC2L", "ASRC2L" }, \ - { name, "ASRC2R", "ASRC2R" } - -static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { + { name, "ISRC1DEC1", "ISRC1DEC1" }, \ + { name, "ISRC1DEC2", "ISRC1DEC2" }, \ + { name, "ISRC1INT1", "ISRC1INT1" }, \ + { name, "ISRC1INT2", "ISRC1INT2" }, \ + { name, "ISRC2DEC1", "ISRC2DEC1" }, \ + { name, "ISRC2DEC2", "ISRC2DEC2" }, \ + { name, "ISRC2INT1", "ISRC2INT1" }, \ + { name, "ISRC2INT2", "ISRC2INT2" } + +static const struct snd_soc_dapm_route wm8997_dapm_routes[] = { { "AIF2 Capture", NULL, "DBVDD2" }, { "AIF2 Playback", NULL, "DBVDD2" }, - { "AIF3 Capture", NULL, "DBVDD3" }, - { "AIF3 Playback", NULL, "DBVDD3" }, - { "OUT1L", NULL, "CPVDD" }, { "OUT1R", NULL, "CPVDD" }, - { "OUT2L", NULL, "CPVDD" }, - { "OUT2R", NULL, "CPVDD" }, { "OUT3L", NULL, "CPVDD" }, - { "OUT3R", NULL, "CPVDD" }, - { "OUT4L", NULL, "SPKVDDL" }, - { "OUT4R", NULL, "SPKVDDR" }, + { "OUT4L", NULL, "SPKVDD" }, { "OUT1L", NULL, "SYSCLK" }, { "OUT1R", NULL, "SYSCLK" }, - { "OUT2L", NULL, "SYSCLK" }, - { "OUT2R", NULL, "SYSCLK" }, { "OUT3L", NULL, "SYSCLK" }, { "OUT4L", NULL, "SYSCLK" }, - { "OUT4R", NULL, "SYSCLK" }, - { "OUT5L", NULL, "SYSCLK" }, - { "OUT5R", NULL, "SYSCLK" }, - { "OUT6L", NULL, "SYSCLK" }, - { "OUT6R", NULL, "SYSCLK" }, + + { "IN1L", NULL, "SYSCLK" }, + { "IN1R", NULL, "SYSCLK" }, + { "IN2L", NULL, "SYSCLK" }, + { "IN2R", NULL, "SYSCLK" }, { "MICBIAS1", NULL, "MICVDD" }, { "MICBIAS2", NULL, "MICVDD" }, { "MICBIAS3", NULL, "MICVDD" }, + { "Noise Generator", NULL, "SYSCLK" }, + { "Tone Generator 1", NULL, "SYSCLK" }, + { "Tone Generator 2", NULL, "SYSCLK" }, + { "Noise Generator", NULL, "NOISE" }, { "Tone Generator 1", NULL, "TONE" }, { "Tone Generator 2", NULL, "TONE" }, - { "Mic Mute Mixer", NULL, "Noise Mixer" }, - { "Mic Mute Mixer", NULL, "Mic Mixer" }, - { "AIF1 Capture", NULL, "AIF1TX1" }, { "AIF1 Capture", NULL, "AIF1TX2" }, { "AIF1 Capture", NULL, "AIF1TX3" }, @@ -860,19 +888,39 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { { "AIF2RX1", NULL, "AIF2 Playback" }, { "AIF2RX2", NULL, "AIF2 Playback" }, - { "AIF3 Capture", NULL, "AIF3TX1" }, - { "AIF3 Capture", NULL, "AIF3TX2" }, + { "Slim1 Capture", NULL, "SLIMTX1" }, + { "Slim1 Capture", NULL, "SLIMTX2" }, + { "Slim1 Capture", NULL, "SLIMTX3" }, + { "Slim1 Capture", NULL, "SLIMTX4" }, + + { "SLIMRX1", NULL, "Slim1 Playback" }, + { "SLIMRX2", NULL, "Slim1 Playback" }, + { "SLIMRX3", NULL, "Slim1 Playback" }, + { "SLIMRX4", NULL, "Slim1 Playback" }, + + { "Slim2 Capture", NULL, "SLIMTX5" }, + { "Slim2 Capture", NULL, "SLIMTX6" }, + + { "SLIMRX5", NULL, "Slim2 Playback" }, + { "SLIMRX6", NULL, "Slim2 Playback" }, - { "AIF3RX1", NULL, "AIF3 Playback" }, - { "AIF3RX2", NULL, "AIF3 Playback" }, + { "Slim3 Capture", NULL, "SLIMTX7" }, + { "Slim3 Capture", NULL, "SLIMTX8" }, + + { "SLIMRX7", NULL, "Slim3 Playback" }, + { "SLIMRX8", NULL, "Slim3 Playback" }, { "AIF1 Playback", NULL, "SYSCLK" }, { "AIF2 Playback", NULL, "SYSCLK" }, - { "AIF3 Playback", NULL, "SYSCLK" }, + { "Slim1 Playback", NULL, "SYSCLK" }, + { "Slim2 Playback", NULL, "SYSCLK" }, + { "Slim3 Playback", NULL, "SYSCLK" }, { "AIF1 Capture", NULL, "SYSCLK" }, { "AIF2 Capture", NULL, "SYSCLK" }, - { "AIF3 Capture", NULL, "SYSCLK" }, + { "Slim1 Capture", NULL, "SYSCLK" }, + { "Slim2 Capture", NULL, "SYSCLK" }, + { "Slim3 Capture", NULL, "SYSCLK" }, { "IN1L PGA", NULL, "IN1L" }, { "IN1R PGA", NULL, "IN1R" }, @@ -880,25 +928,13 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { { "IN2L PGA", NULL, "IN2L" }, { "IN2R PGA", NULL, "IN2R" }, - { "IN3L PGA", NULL, "IN3L" }, - { "IN3R PGA", NULL, "IN3R" }, - - { "IN4L PGA", NULL, "IN4L" }, - { "IN4R PGA", NULL, "IN4R" }, - ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), - ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), - ARIZONA_MIXER_ROUTES("OUT2R", "HPOUT2R"), - ARIZONA_MIXER_ROUTES("OUT3L", "HPOUT3L"), - ARIZONA_MIXER_ROUTES("OUT3R", "HPOUT3R"), + ARIZONA_MIXER_ROUTES("OUT3L", "EPOUT"), - ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUTL"), - ARIZONA_MIXER_ROUTES("OUT4R", "SPKOUTR"), + ARIZONA_MIXER_ROUTES("OUT4L", "SPKOUT"), ARIZONA_MIXER_ROUTES("OUT5L", "SPKDAT1L"), ARIZONA_MIXER_ROUTES("OUT5R", "SPKDAT1R"), - ARIZONA_MIXER_ROUTES("OUT6L", "SPKDAT2L"), - ARIZONA_MIXER_ROUTES("OUT6R", "SPKDAT2R"), ARIZONA_MIXER_ROUTES("PWM1 Driver", "PWM1"), ARIZONA_MIXER_ROUTES("PWM2 Driver", "PWM2"), @@ -915,8 +951,14 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { ARIZONA_MIXER_ROUTES("AIF2TX1", "AIF2TX1"), ARIZONA_MIXER_ROUTES("AIF2TX2", "AIF2TX2"), - ARIZONA_MIXER_ROUTES("AIF3TX1", "AIF3TX1"), - ARIZONA_MIXER_ROUTES("AIF3TX2", "AIF3TX2"), + ARIZONA_MIXER_ROUTES("SLIMTX1", "SLIMTX1"), + ARIZONA_MIXER_ROUTES("SLIMTX2", "SLIMTX2"), + ARIZONA_MIXER_ROUTES("SLIMTX3", "SLIMTX3"), + ARIZONA_MIXER_ROUTES("SLIMTX4", "SLIMTX4"), + ARIZONA_MIXER_ROUTES("SLIMTX5", "SLIMTX5"), + ARIZONA_MIXER_ROUTES("SLIMTX6", "SLIMTX6"), + ARIZONA_MIXER_ROUTES("SLIMTX7", "SLIMTX7"), + ARIZONA_MIXER_ROUTES("SLIMTX8", "SLIMTX8"), ARIZONA_MIXER_ROUTES("EQ1", "EQ1"), ARIZONA_MIXER_ROUTES("EQ2", "EQ2"), @@ -925,142 +967,182 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = { ARIZONA_MIXER_ROUTES("DRC1L", "DRC1L"), ARIZONA_MIXER_ROUTES("DRC1R", "DRC1R"), - ARIZONA_MIXER_ROUTES("DRC2L", "DRC2L"), - ARIZONA_MIXER_ROUTES("DRC2R", "DRC2R"), ARIZONA_MIXER_ROUTES("LHPF1", "LHPF1"), ARIZONA_MIXER_ROUTES("LHPF2", "LHPF2"), ARIZONA_MIXER_ROUTES("LHPF3", "LHPF3"), ARIZONA_MIXER_ROUTES("LHPF4", "LHPF4"), - ARIZONA_MUX_ROUTES("ASRC1L"), - ARIZONA_MUX_ROUTES("ASRC1R"), - ARIZONA_MUX_ROUTES("ASRC2L"), - ARIZONA_MUX_ROUTES("ASRC2R"), + ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Noise"), + ARIZONA_MIXER_ROUTES("Mic Mute Mixer", "Mic"), - { "HPOUT1L", NULL, "OUT1L" }, - { "HPOUT1R", NULL, "OUT1R" }, + ARIZONA_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), + ARIZONA_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), + + ARIZONA_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), + ARIZONA_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), + + ARIZONA_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), + ARIZONA_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), - { "HPOUT2L", NULL, "OUT2L" }, - { "HPOUT2R", NULL, "OUT2R" }, + ARIZONA_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), + ARIZONA_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), - { "HPOUT3L", NULL, "OUT3L" }, - { "HPOUT3R", NULL, "OUT3R" }, + { "AEC Loopback", "HPOUT1L", "OUT1L" }, + { "AEC Loopback", "HPOUT1R", "OUT1R" }, + { "HPOUT1L", NULL, "OUT1L" }, + { "HPOUT1R", NULL, "OUT1R" }, - { "SPKOUTLN", NULL, "OUT4L" }, - { "SPKOUTLP", NULL, "OUT4L" }, + { "AEC Loopback", "EPOUT", "OUT3L" }, + { "EPOUTN", NULL, "OUT3L" }, + { "EPOUTP", NULL, "OUT3L" }, - { "SPKOUTRN", NULL, "OUT4R" }, - { "SPKOUTRP", NULL, "OUT4R" }, + { "AEC Loopback", "SPKOUT", "OUT4L" }, + { "SPKOUTN", NULL, "OUT4L" }, + { "SPKOUTP", NULL, "OUT4L" }, + { "AEC Loopback", "SPKDAT1L", "OUT5L" }, + { "AEC Loopback", "SPKDAT1R", "OUT5R" }, { "SPKDAT1L", NULL, "OUT5L" }, { "SPKDAT1R", NULL, "OUT5R" }, - { "SPKDAT2L", NULL, "OUT6L" }, - { "SPKDAT2R", NULL, "OUT6R" }, - { "MICSUPP", NULL, "SYSCLK" }, }; -static int wm5110_set_fll(struct snd_soc_codec *codec, int fll_id, int source, +static int wm8997_set_fll(struct snd_soc_codec *codec, int fll_id, int source, unsigned int Fref, unsigned int Fout) { - struct wm5110_priv *wm5110 = snd_soc_codec_get_drvdata(codec); + struct wm8997_priv *wm8997 = snd_soc_codec_get_drvdata(codec); switch (fll_id) { - case WM5110_FLL1: - return arizona_set_fll(&wm5110->fll[0], source, Fref, Fout); - case WM5110_FLL2: - return arizona_set_fll(&wm5110->fll[1], source, Fref, Fout); - case WM5110_FLL1_REFCLK: - return arizona_set_fll_refclk(&wm5110->fll[0], source, Fref, + case WM8997_FLL1: + return arizona_set_fll(&wm8997->fll[0], source, Fref, Fout); + case WM8997_FLL2: + return arizona_set_fll(&wm8997->fll[1], source, Fref, Fout); + case WM8997_FLL1_REFCLK: + return arizona_set_fll_refclk(&wm8997->fll[0], source, Fref, Fout); - case WM5110_FLL2_REFCLK: - return arizona_set_fll_refclk(&wm5110->fll[1], source, Fref, + case WM8997_FLL2_REFCLK: + return arizona_set_fll_refclk(&wm8997->fll[1], source, Fref, Fout); default: return -EINVAL; } } -#define WM5110_RATES SNDRV_PCM_RATE_8000_192000 +#define WM8997_RATES SNDRV_PCM_RATE_KNOT -#define WM5110_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ +#define WM8997_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) -static struct snd_soc_dai_driver wm5110_dai[] = { +static struct snd_soc_dai_driver wm8997_dai[] = { { - .name = "wm5110-aif1", + .name = "wm8997-aif1", .id = 1, .base = ARIZONA_AIF1_BCLK_CTRL, .playback = { .stream_name = "AIF1 Playback", .channels_min = 1, .channels_max = 8, - .rates = WM5110_RATES, - .formats = WM5110_FORMATS, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, }, .capture = { .stream_name = "AIF1 Capture", .channels_min = 1, .channels_max = 8, - .rates = WM5110_RATES, - .formats = WM5110_FORMATS, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, }, .ops = &arizona_dai_ops, .symmetric_rates = 1, }, { - .name = "wm5110-aif2", + .name = "wm8997-aif2", .id = 2, .base = ARIZONA_AIF2_BCLK_CTRL, .playback = { .stream_name = "AIF2 Playback", .channels_min = 1, .channels_max = 2, - .rates = WM5110_RATES, - .formats = WM5110_FORMATS, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, }, .capture = { .stream_name = "AIF2 Capture", .channels_min = 1, .channels_max = 2, - .rates = WM5110_RATES, - .formats = WM5110_FORMATS, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, }, .ops = &arizona_dai_ops, .symmetric_rates = 1, }, { - .name = "wm5110-aif3", + .name = "wm8997-slim1", .id = 3, - .base = ARIZONA_AIF3_BCLK_CTRL, .playback = { - .stream_name = "AIF3 Playback", + .stream_name = "Slim1 Playback", + .channels_min = 1, + .channels_max = 4, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, + }, + .capture = { + .stream_name = "Slim1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "wm8997-slim2", + .id = 4, + .playback = { + .stream_name = "Slim2 Playback", .channels_min = 1, .channels_max = 2, - .rates = WM5110_RATES, - .formats = WM5110_FORMATS, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, }, .capture = { - .stream_name = "AIF3 Capture", - .channels_min = 1, - .channels_max = 2, - .rates = WM5110_RATES, - .formats = WM5110_FORMATS, - }, - .ops = &arizona_dai_ops, - .symmetric_rates = 1, + .stream_name = "Slim2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, + }, + .ops = &arizona_simple_dai_ops, + }, + { + .name = "wm8997-slim3", + .id = 5, + .playback = { + .stream_name = "Slim3 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, + }, + .capture = { + .stream_name = "Slim3 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = WM8997_RATES, + .formats = WM8997_FORMATS, + }, + .ops = &arizona_simple_dai_ops, }, }; -static int wm5110_codec_probe(struct snd_soc_codec *codec) +static int wm8997_codec_probe(struct snd_soc_codec *codec) { - struct wm5110_priv *priv = snd_soc_codec_get_drvdata(codec); + struct wm8997_priv *priv = snd_soc_codec_get_drvdata(codec); int ret; codec->control_data = priv->core.arizona->regmap; - priv->core.arizona->dapm = &codec->dapm; ret = snd_soc_codec_set_cache_io(codec, 32, 16, SND_SOC_REGMAP); if (ret != 0) @@ -1075,90 +1157,96 @@ static int wm5110_codec_probe(struct snd_soc_codec *codec) return 0; } -static int wm5110_codec_remove(struct snd_soc_codec *codec) +static int wm8997_codec_remove(struct snd_soc_codec *codec) { - struct wm5110_priv *priv = snd_soc_codec_get_drvdata(codec); + struct wm8997_priv *priv = snd_soc_codec_get_drvdata(codec); priv->core.arizona->dapm = NULL; return 0; } -#define WM5110_DIG_VU 0x0200 +#define WM8997_DIG_VU 0x0200 -static unsigned int wm5110_digital_vu[] = { +static unsigned int wm8997_digital_vu[] = { ARIZONA_DAC_DIGITAL_VOLUME_1L, ARIZONA_DAC_DIGITAL_VOLUME_1R, - ARIZONA_DAC_DIGITAL_VOLUME_2L, - ARIZONA_DAC_DIGITAL_VOLUME_2R, ARIZONA_DAC_DIGITAL_VOLUME_3L, - ARIZONA_DAC_DIGITAL_VOLUME_3R, ARIZONA_DAC_DIGITAL_VOLUME_4L, - ARIZONA_DAC_DIGITAL_VOLUME_4R, ARIZONA_DAC_DIGITAL_VOLUME_5L, ARIZONA_DAC_DIGITAL_VOLUME_5R, - ARIZONA_DAC_DIGITAL_VOLUME_6L, - ARIZONA_DAC_DIGITAL_VOLUME_6R, }; -static struct snd_soc_codec_driver soc_codec_dev_wm5110 = { - .probe = wm5110_codec_probe, - .remove = wm5110_codec_remove, +static struct snd_soc_codec_driver soc_codec_dev_wm8997 = { + .probe = wm8997_codec_probe, + .remove = wm8997_codec_remove, .idle_bias_off = true, .set_sysclk = arizona_set_sysclk, - .set_pll = wm5110_set_fll, - - .controls = wm5110_snd_controls, - .num_controls = ARRAY_SIZE(wm5110_snd_controls), - .dapm_widgets = wm5110_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(wm5110_dapm_widgets), - .dapm_routes = wm5110_dapm_routes, - .num_dapm_routes = ARRAY_SIZE(wm5110_dapm_routes), + .set_pll = wm8997_set_fll, + + .controls = wm8997_snd_controls, + .num_controls = ARRAY_SIZE(wm8997_snd_controls), + .dapm_widgets = wm8997_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(wm8997_dapm_widgets), + .dapm_routes = wm8997_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(wm8997_dapm_routes), }; -static int wm5110_probe(struct platform_device *pdev) +static int wm8997_probe(struct platform_device *pdev) { struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); - struct wm5110_priv *wm5110; + struct wm8997_priv *wm8997; int i; - wm5110 = devm_kzalloc(&pdev->dev, sizeof(struct wm5110_priv), + wm8997 = devm_kzalloc(&pdev->dev, sizeof(struct wm8997_priv), GFP_KERNEL); - if (wm5110 == NULL) + if (wm8997 == NULL) return -ENOMEM; - platform_set_drvdata(pdev, wm5110); + platform_set_drvdata(pdev, wm8997); + + /* Set of_node to parent from the SPI device to allow DAPM to + * locate regulator supplies */ + pdev->dev.of_node = arizona->dev->of_node; - wm5110->core.arizona = arizona; - wm5110->core.num_inputs = 8; + wm8997->core.arizona = arizona; + wm8997->core.num_inputs = 4; - for (i = 0; i < ARRAY_SIZE(wm5110->fll); i++) - wm5110->fll[i].vco_mult = 3; + arizona_init_dvfs(&wm8997->core); + + for (i = 0; i < ARRAY_SIZE(wm8997->fll); i++) + wm8997->fll[i].vco_mult = 1; arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1, ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK, - &wm5110->fll[0]); + &wm8997->fll[0]); arizona_init_fll(arizona, 2, ARIZONA_FLL2_CONTROL_1 - 1, ARIZONA_IRQ_FLL2_LOCK, ARIZONA_IRQ_FLL2_CLOCK_OK, - &wm5110->fll[1]); + &wm8997->fll[1]); + + /* SR2 fixed at 8kHz, SR3 fixed at 16kHz */ + regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_2, + ARIZONA_SAMPLE_RATE_2_MASK, 0x11); + regmap_update_bits(arizona->regmap, ARIZONA_SAMPLE_RATE_3, + ARIZONA_SAMPLE_RATE_3_MASK, 0x12); - for (i = 0; i < ARRAY_SIZE(wm5110_dai); i++) - arizona_init_dai(&wm5110->core, i); + for (i = 0; i < ARRAY_SIZE(wm8997_dai); i++) + arizona_init_dai(&wm8997->core, i); /* Latch volume update bits */ - for (i = 0; i < ARRAY_SIZE(wm5110_digital_vu); i++) - regmap_update_bits(arizona->regmap, wm5110_digital_vu[i], - WM5110_DIG_VU, WM5110_DIG_VU); + for (i = 0; i < ARRAY_SIZE(wm8997_digital_vu); i++) + regmap_update_bits(arizona->regmap, wm8997_digital_vu[i], + WM8997_DIG_VU, WM8997_DIG_VU); pm_runtime_enable(&pdev->dev); pm_runtime_idle(&pdev->dev); - return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm5110, - wm5110_dai, ARRAY_SIZE(wm5110_dai)); + return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8997, + wm8997_dai, ARRAY_SIZE(wm8997_dai)); } -static int wm5110_remove(struct platform_device *pdev) +static int wm8997_remove(struct platform_device *pdev) { snd_soc_unregister_codec(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -1166,18 +1254,18 @@ static int wm5110_remove(struct platform_device *pdev) return 0; } -static struct platform_driver wm5110_codec_driver = { +static struct platform_driver wm8997_codec_driver = { .driver = { - .name = "wm5110-codec", + .name = "wm8997-codec", .owner = THIS_MODULE, }, - .probe = wm5110_probe, - .remove = wm5110_remove, + .probe = wm8997_probe, + .remove = wm8997_remove, }; -module_platform_driver(wm5110_codec_driver); +module_platform_driver(wm8997_codec_driver); -MODULE_DESCRIPTION("ASoC WM5110 driver"); -MODULE_AUTHOR("Mark Brown "); +MODULE_DESCRIPTION("ASoC WM8997 driver"); +MODULE_AUTHOR("Charles Keepax "); MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:wm5110-codec"); +MODULE_ALIAS("platform:wm8997-codec"); diff --git a/sound/soc/codecs/wm5110.h b/sound/soc/codecs/wm8997.h similarity index 63% rename from sound/soc/codecs/wm5110.h rename to sound/soc/codecs/wm8997.h index e6c0cd4235c..5e91c6a7d56 100644 --- a/sound/soc/codecs/wm5110.h +++ b/sound/soc/codecs/wm8997.h @@ -1,5 +1,5 @@ /* - * wm5110.h -- WM5110 ALSA SoC Audio driver + * wm8997.h -- WM8997 ALSA SoC Audio driver * * Copyright 2012 Wolfson Microelectronics plc * @@ -10,14 +10,14 @@ * published by the Free Software Foundation. */ -#ifndef _WM5110_H -#define _WM5110_H +#ifndef _WM8997_H +#define _WM8997_H #include "arizona.h" -#define WM5110_FLL1 1 -#define WM5110_FLL2 2 -#define WM5110_FLL1_REFCLK 3 -#define WM5110_FLL2_REFCLK 4 +#define WM8997_FLL1 1 +#define WM8997_FLL2 2 +#define WM8997_FLL1_REFCLK 3 +#define WM8997_FLL2_REFCLK 4 #endif diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c index d785e46be47..0821e0b5b53 100644 --- a/sound/soc/codecs/wm_adsp.c +++ b/sound/soc/codecs/wm_adsp.c @@ -16,11 +16,14 @@ #include #include #include +#include #include #include #include -#include #include +#include +#include +#include #include #include #include @@ -34,6 +37,8 @@ #include "arizona.h" #include "wm_adsp.h" +#define WM_ADSP_CONTROL_MAX 44 + #define adsp_crit(_dsp, fmt, ...) \ dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__) #define adsp_err(_dsp, fmt, ...) \ @@ -114,10 +119,20 @@ #define ADSP2_CONTROL 0x0 #define ADSP2_CLOCKING 0x1 +#define ADSP2V2_CLOCKING 0x2 #define ADSP2_STATUS1 0x4 -#define ADSP2_WDMA_CONFIG_1 0x30 -#define ADSP2_WDMA_CONFIG_2 0x31 -#define ADSP2_RDMA_CONFIG_1 0x34 +#define ADSP2_WDMA_CONFIG_1 0x30 +#define ADSP2_WDMA_CONFIG_2 0x31 +#define ADSP2V2_WDMA_CONFIG_2 0x32 +#define ADSP2_RDMA_CONFIG_1 0x34 + +#define ADSP2_SCRATCH0 0x40 +#define ADSP2_SCRATCH1 0x41 +#define ADSP2_SCRATCH2 0x42 +#define ADSP2_SCRATCH3 0x43 + +#define ADSP2V2_SCRATCH0_1 0x40 +#define ADSP2V2_SCRATCH2_3 0x42 /* * ADSP2 Control @@ -147,6 +162,17 @@ #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ +/* + * ADSP2V2 clocking + */ +#define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ +#define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ + +#define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ +#define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ +#define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ + /* * ADSP2 Status 1 */ @@ -155,6 +181,53 @@ #define ADSP2_RAM_RDY_SHIFT 0 #define ADSP2_RAM_RDY_WIDTH 1 +/* + * ADSP2 Lock support + */ + +#define ADSP2_LOCK_CODE_0 0x5555 +#define ADSP2_LOCK_CODE_1 0xAAAA + +#define ADSP2_WATCHDOG 0x0A +#define ADSP2_BUS_ERR_ADDR 0x52 +#define ADSP2_REGION_LOCK_STATUS 0x64 +#define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 +#define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 +#define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A +#define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C +#define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E +#define ADSP2_LOCK_REGION_CTRL 0x7A +#define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C + +#define ADSP2_REGION_LOCK_ERR_MASK 0x8000 +#define ADSP2_SLAVE_ERR_MASK 0x4000 +#define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 +#define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 +#define ADSP2_CTRL_ERR_EINT 0x0001 + +#define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF +#define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF +#define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 +#define ADSP2_PMEM_ERR_ADDR_SHIFT 16 +#define ADSP2_WDT_ENA_MASK 0xFFFFFFFD + +#define ADSP2_LOCK_REGION_SHIFT 16 + +#define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 +#define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 +#define WM_ADSP_ACKED_CTL_MIN_VALUE 0 +#define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF +/* ADSP2V1 accessed through 16-bit register map so only low 16-bits atomic */ +#define WM_ADSP_ACKED_CTL_MAX_VALUE_V1 0xFFFF + +/* + * Event control messages + */ +#define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 + +static int wm_adsp_init_host_buf_info(struct wm_adsp_compr_buf *buf); +static void wm_adsp_free_host_buf_info(struct wm_adsp_compr_buf *buf); + struct wm_adsp_buf { struct list_head list; void *buf; @@ -192,37 +265,419 @@ static void wm_adsp_buf_free(struct list_head *list) } } -#define WM_ADSP_NUM_FW 4 +/* Must remain a power of two */ +#define WM_ADSP_CAPTURE_BUFFER_SIZE 1048576 + +#define WM_ADSP_FW_MBC_VSS 0 +#define WM_ADSP_FW_HIFI 1 +#define WM_ADSP_FW_TX 2 +#define WM_ADSP_FW_TX_SPK 3 +#define WM_ADSP_FW_RX 4 +#define WM_ADSP_FW_RX_ANC 5 +#define WM_ADSP_FW_CTRL 6 +#define WM_ADSP_FW_ASR 7 +#define WM_ADSP_FW_TRACE 8 +#define WM_ADSP_FW_SPK_PROT 9 +#define WM_ADSP_FW_MISC 10 -#define WM_ADSP_FW_MBC_VSS 0 -#define WM_ADSP_FW_TX 1 -#define WM_ADSP_FW_TX_SPK 2 -#define WM_ADSP_FW_RX_ANC 3 +#define WM_ADSP_NUM_FW 11 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { - [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", - [WM_ADSP_FW_TX] = "Tx", - [WM_ADSP_FW_TX_SPK] = "Tx Speaker", - [WM_ADSP_FW_RX_ANC] = "Rx ANC", + [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", + [WM_ADSP_FW_HIFI] = "MasterHiFi", + [WM_ADSP_FW_TX] = "Tx", + [WM_ADSP_FW_TX_SPK] = "Tx Speaker", + [WM_ADSP_FW_RX] = "Rx", + [WM_ADSP_FW_RX_ANC] = "Rx ANC", + [WM_ADSP_FW_CTRL] = "Voice Ctrl", + [WM_ADSP_FW_ASR] = "ASR Assist", + [WM_ADSP_FW_TRACE] = "Dbg Trace", + [WM_ADSP_FW_SPK_PROT] = "Protection", + [WM_ADSP_FW_MISC] = "Misc", +}; + +struct wm_adsp_system_config_xm_hdr { + __be32 sys_enable; + __be32 fw_id; + __be32 fw_rev; + __be32 boot_status; + __be32 watchdog; + __be32 dma_buffer_size; + __be32 rdma[6]; + __be32 wdma[8]; + __be32 build_job_name[3]; + __be32 build_job_number; +}; + +struct wm_adsp_alg_xm_struct { + __be32 magic; + __be32 smoothing; + __be32 threshold; + __be32 host_buf_ptr; + __be32 start_seq; + __be32 high_water_mark; + __be32 low_water_mark; + __be64 smoothed_power; +}; + +struct wm_adsp_host_buffer { + __be32 X_buf_base; /* XM base addr of first X area */ + __be32 X_buf_size; /* Size of 1st X area in words */ + __be32 X_buf_base2; /* XM base addr of 2nd X area */ + __be32 X_buf_brk; /* Total X size in words */ + __be32 Y_buf_base; /* YM base addr of Y area */ + __be32 wrap; /* Total size X and Y in words */ + __be32 high_water_mark; /* Point at which IRQ is asserted */ + __be32 irq_count; /* bits 1-31 count IRQ assertions */ + __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */ + __be32 next_write_index; /* word index of next write */ + __be32 next_read_index; /* word index of next read */ + __be32 error; /* error if any */ + __be32 oldest_block_index; /* word index of oldest surviving */ + __be32 requested_rewind; /* how many blocks rewind was done */ + __be32 reserved_space; /* internal */ + __be32 min_free; /* min free space since stream start */ + __be32 blocks_written[2]; /* total blocks written (64 bit) */ + __be32 words_written[2]; /* total words written (64 bit) */ +}; + +#define WM_ADSP_DATA_WORD_SIZE 3 +#define WM_ADSP_MIN_FRAGMENTS 1 +#define WM_ADSP_MAX_FRAGMENTS 256 +#define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE) +#define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE) + + +#define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7 + +#define WM_ADSP_DEFAULT_WATERMARK DIV_ROUND_UP(2048, WM_ADSP_DATA_WORD_SIZE) + +#define ADSP2_SYSTEM_CONFIG_XM_PTR \ + (offsetof(struct wmfw_adsp2_id_hdr, xm) / sizeof(__be32)) + +#define WM_ADSP_ALG_XM_PTR \ + (sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32)) + +#define HOST_BUFFER_FIELD(field) \ + (offsetof(struct wm_adsp_host_buffer, field) / sizeof(__be32)) + +#define ALG_XM_FIELD(field) \ + (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32)) + +static struct wm_adsp_buffer_region_def ez2control_regions[] = { + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(X_buf_base), + .size_offset = HOST_BUFFER_FIELD(X_buf_size), + }, + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(X_buf_base2), + .size_offset = HOST_BUFFER_FIELD(X_buf_brk), + }, + { + .mem_type = WMFW_ADSP2_YM, + .base_offset = HOST_BUFFER_FIELD(Y_buf_base), + .size_offset = HOST_BUFFER_FIELD(wrap), + }, +}; + +static struct wm_adsp_fw_caps ez2control_caps[] = { + { + .id = SND_AUDIOCODEC_PCM, + .desc = { + .max_ch = 2, + .sample_rates = { 16000 }, + .num_sample_rates = 1, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .num_host_regions = ARRAY_SIZE(ez2control_regions), + .host_region_defs = ez2control_regions, + }, +}; + +static struct wm_adsp_buffer_region_def trace_regions[] = { + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(X_buf_base), + .size_offset = HOST_BUFFER_FIELD(X_buf_size), + }, + { + .mem_type = WMFW_ADSP2_XM, + .base_offset = HOST_BUFFER_FIELD(X_buf_base2), + .size_offset = HOST_BUFFER_FIELD(X_buf_brk), + }, + { + .mem_type = WMFW_ADSP2_YM, + .base_offset = HOST_BUFFER_FIELD(Y_buf_base), + .size_offset = HOST_BUFFER_FIELD(wrap), + }, +}; + +static struct wm_adsp_fw_caps trace_caps[] = { + { + .id = SND_AUDIOCODEC_PCM, + .desc = { + .max_ch = 8, + .sample_rates = { + 4000,8000,11025,12000,16000,22050, + 24000,32000,44100,48000,64000,88200, + 96000,176400,192000 + }, + .num_sample_rates = 15, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .num_host_regions = ARRAY_SIZE(trace_regions), + .host_region_defs = trace_regions, + }, +}; + +static struct wm_adsp_fw_defs wm_adsp_fw[WM_ADSP_NUM_FW] = { + [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, + [WM_ADSP_FW_HIFI] = { .file = "hifi" }, + [WM_ADSP_FW_TX] = { .file = "tx" }, + [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, + [WM_ADSP_FW_RX] = { .file = "rx" }, + [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, + [WM_ADSP_FW_CTRL] = { + .file = "ctrl", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(ez2control_caps), + .caps = ez2control_caps, + }, + [WM_ADSP_FW_ASR] = { .file = "asr" }, + [WM_ADSP_FW_TRACE] = { + .file = "trace", + .compr_direction = SND_COMPRESS_CAPTURE, + .num_caps = ARRAY_SIZE(trace_caps), + .caps = trace_caps, + }, + [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" }, + [WM_ADSP_FW_MISC] = { .file = "misc" }, }; -static struct { - const char *file; -} wm_adsp_fw[WM_ADSP_NUM_FW] = { - [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, - [WM_ADSP_FW_TX] = { .file = "tx" }, - [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, - [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, +struct wm_coeff_ctl_ops { + int (*xget)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*xput)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*xinfo)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +}; + +struct wm_coeff_ctl { + const char *name; + const char *fw_name; + struct wm_adsp_alg_region alg_region; + struct wm_coeff_ctl_ops ops; + struct wm_adsp *dsp; + unsigned int enabled:1; + struct list_head list; + void *cache; + unsigned int offset; + size_t len; + unsigned int set:1; + struct snd_kcontrol *kcontrol; + unsigned int flags; + struct mutex lock; + unsigned int type; +}; + +static const char *wm_adsp_mem_region_name(unsigned int type) +{ + switch (type) { + case WMFW_ADSP1_PM: + return "PM"; + case WMFW_ADSP1_DM: + return "DM"; + case WMFW_ADSP2_XM: + return "XM"; + case WMFW_ADSP2_YM: + return "YM"; + case WMFW_ADSP1_ZM: + return "ZM"; + default: + return NULL; + } +} + +#ifdef CONFIG_DEBUG_FS +static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + mutex_lock(&dsp->debugfs_lock); + kfree(dsp->wmfw_file_name); + dsp->wmfw_file_name = tmp; + mutex_unlock(&dsp->debugfs_lock); +} + +static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) +{ + char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); + + mutex_lock(&dsp->debugfs_lock); + kfree(dsp->bin_file_name); + dsp->bin_file_name = tmp; + mutex_unlock(&dsp->debugfs_lock); +} + +static void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ + mutex_lock(&dsp->debugfs_lock); + kfree(dsp->wmfw_file_name); + kfree(dsp->bin_file_name); + dsp->wmfw_file_name = NULL; + dsp->bin_file_name = NULL; + mutex_unlock(&dsp->debugfs_lock); +} + +static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->debugfs_lock); + + if (!dsp->wmfw_file_name || !dsp->running) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->wmfw_file_name, + strlen(dsp->wmfw_file_name)); + + mutex_unlock(&dsp->debugfs_lock); + return ret; +} + +static ssize_t wm_adsp_debugfs_bin_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct wm_adsp *dsp = file->private_data; + ssize_t ret; + + mutex_lock(&dsp->debugfs_lock); + + if (!dsp->bin_file_name || !dsp->running) + ret = 0; + else + ret = simple_read_from_buffer(user_buf, count, ppos, + dsp->bin_file_name, + strlen(dsp->bin_file_name)); + + mutex_unlock(&dsp->debugfs_lock); + return ret; +} + +static const struct { + const char *name; + const struct file_operations fops; +} wm_adsp_debugfs_fops[] = { + { + .name = "wmfw_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_wmfw_read, + }, + }, + { + .name = "bin_file_name", + .fops = { + .open = simple_open, + .read = wm_adsp_debugfs_bin_read, + }, + }, }; +static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_codec *codec) +{ + struct dentry *root = NULL; + char *root_name; + int i; + + if (!codec->debugfs_codec_root) { + adsp_err(dsp, "No codec debugfs root\n"); + goto err; + } + + root_name = kmalloc(PAGE_SIZE, GFP_KERNEL); + if (!root_name) + goto err; + + snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num); + root = debugfs_create_dir(root_name, codec->debugfs_codec_root); + kfree(root_name); + + if (!root) + goto err; + + if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running)) + goto err; + + if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id)) + goto err; + + if (!debugfs_create_x32("fw_version", S_IRUGO, root, + &dsp->fw_id_version)) + goto err; + + for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) { + if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name, + S_IRUGO, root, dsp, + &wm_adsp_debugfs_fops[i].fops)) + goto err; + } + + dsp->debugfs_root = root; + return; + +err: + debugfs_remove_recursive(root); + adsp_err(dsp, "Failed to create debugfs\n"); +} + +static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ + wm_adsp_debugfs_clear(dsp); + debugfs_remove_recursive(dsp->debugfs_root); +} +#else +static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp, + struct snd_soc_codec *codec) +{ +} + +static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) +{ +} + +static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, + const char *s) +{ +} + +static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp) +{ +} +#endif + static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; - struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); - ucontrol->value.integer.value[0] = adsp[e->shift_l].fw; + ucontrol->value.integer.value[0] = dsp[e->shift_l].fw; return 0; } @@ -232,75 +687,49 @@ static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, { struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; - struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec); - if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw) + if (ucontrol->value.integer.value[0] == dsp[e->shift_l].fw) return 0; - if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW) + if (ucontrol->value.integer.value[0] >= dsp[e->shift_l].num_firmwares) return -EINVAL; - if (adsp[e->shift_l].running) + if (dsp[e->shift_l].running) return -EBUSY; - adsp[e->shift_l].fw = ucontrol->value.integer.value[0]; + dsp[e->shift_l].fw = ucontrol->value.integer.value[0]; return 0; } -static const struct soc_enum wm_adsp_fw_enum[] = { +static struct soc_enum wm_adsp_fw_enum[] = { SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), + SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), }; -const struct snd_kcontrol_new wm_adsp1_fw_controls[] = { +const struct snd_kcontrol_new wm_adsp_fw_controls[] = { SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0], wm_adsp_fw_get, wm_adsp_fw_put), SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1], wm_adsp_fw_get, wm_adsp_fw_put), SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2], wm_adsp_fw_get, wm_adsp_fw_put), -}; -EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls); - -#if IS_ENABLED(CONFIG_SND_SOC_ARIZONA) -static const struct soc_enum wm_adsp2_rate_enum[] = { - SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1, - ARIZONA_DSP1_RATE_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), - SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1, - ARIZONA_DSP1_RATE_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), - SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1, - ARIZONA_DSP1_RATE_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), - SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1, - ARIZONA_DSP1_RATE_SHIFT, 0xf, - ARIZONA_RATE_ENUM_SIZE, - arizona_rate_text, arizona_rate_val), -}; - -const struct snd_kcontrol_new wm_adsp2_fw_controls[] = { - SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0], + SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3], wm_adsp_fw_get, wm_adsp_fw_put), - SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]), - SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1], + SOC_ENUM_EXT("DSP5 Firmware", wm_adsp_fw_enum[4], wm_adsp_fw_get, wm_adsp_fw_put), - SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]), - SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2], + SOC_ENUM_EXT("DSP6 Firmware", wm_adsp_fw_enum[5], wm_adsp_fw_get, wm_adsp_fw_put), - SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]), - SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3], + SOC_ENUM_EXT("DSP7 Firmware", wm_adsp_fw_enum[6], wm_adsp_fw_get, wm_adsp_fw_put), - SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]), }; -EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls); -#endif +EXPORT_SYMBOL_GPL(wm_adsp_fw_controls); static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, int type) @@ -314,560 +743,1565 @@ static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, return NULL; } -static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region, +static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, unsigned int offset) { - switch (region->type) { + if (WARN_ON(!mem)) + return offset; + + switch (mem->type) { case WMFW_ADSP1_PM: - return region->base + (offset * 3); + return mem->base + (offset * 3); case WMFW_ADSP1_DM: - return region->base + (offset * 2); + return mem->base + (offset * 2); case WMFW_ADSP2_XM: - return region->base + (offset * 2); + return mem->base + (offset * 2); case WMFW_ADSP2_YM: - return region->base + (offset * 2); + return mem->base + (offset * 2); case WMFW_ADSP1_ZM: - return region->base + (offset * 2); + return mem->base + (offset * 2); default: WARN_ON(NULL != "Unknown memory region type"); return offset; } } -static int wm_adsp_load(struct wm_adsp *dsp) +static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) { - LIST_HEAD(buf_list); - const struct firmware *firmware; - struct regmap *regmap = dsp->regmap; - unsigned int pos = 0; - const struct wmfw_header *header; - const struct wmfw_adsp1_sizes *adsp1_sizes; - const struct wmfw_adsp2_sizes *adsp2_sizes; - const struct wmfw_footer *footer; - const struct wmfw_region *region; - const struct wm_adsp_region *mem; - const char *region_name; - char *file, *text; - struct wm_adsp_buf *buf; - unsigned int reg; - int regions = 0; - int ret, offset, type, sizes; - - file = kzalloc(PAGE_SIZE, GFP_KERNEL); - if (file == NULL) - return -ENOMEM; + u16 scratch[4]; + int ret; - snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num, - wm_adsp_fw[dsp->fw].file); - file[PAGE_SIZE - 1] = '\0'; + ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0, + scratch, sizeof(scratch)); - ret = request_firmware(&firmware, file, dsp->dev); - if (ret != 0) { - adsp_err(dsp, "Failed to request '%s'\n", file); - goto out; + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + return; } - ret = -EINVAL; - pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); - if (pos >= firmware->size) { - adsp_err(dsp, "%s: file too short, %zu bytes\n", - file, firmware->size); - goto out_fw; - } + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + be16_to_cpu(scratch[0]), + be16_to_cpu(scratch[1]), + be16_to_cpu(scratch[2]), + be16_to_cpu(scratch[3])); +} - header = (void*)&firmware->data[0]; +static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) +{ + u32 scratch[2]; + int ret; - if (memcmp(&header->magic[0], "WMFW", 4) != 0) { - adsp_err(dsp, "%s: invalid magic\n", file); - goto out_fw; - } + ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1, + scratch, sizeof(scratch)); - if (header->ver != 0) { - adsp_err(dsp, "%s: unknown file format %d\n", - file, header->ver); - goto out_fw; + if (ret) { + adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret); + return; } - if (header->core != dsp->type) { - adsp_err(dsp, "%s: invalid core %d != %d\n", - file, header->core, dsp->type); - goto out_fw; + scratch[0] = be32_to_cpu(scratch[0]); + scratch[1] = be32_to_cpu(scratch[1]); + + adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", + scratch[0] & 0xFFFF, + scratch[0] >> 16, + scratch[1] & 0xFFFF, + scratch[1] >> 16); +} + +static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) +{ + const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; + struct wm_adsp *dsp = ctl->dsp; + const struct wm_adsp_region *mem; + + mem = wm_adsp_find_region(dsp, alg_region->type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", + alg_region->type); + return -EINVAL; } - switch (dsp->type) { - case WMFW_ADSP1: - pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); - adsp1_sizes = (void *)&(header[1]); - footer = (void *)&(adsp1_sizes[1]); - sizes = sizeof(*adsp1_sizes); + *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset); - adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", - file, le32_to_cpu(adsp1_sizes->dm), - le32_to_cpu(adsp1_sizes->pm), - le32_to_cpu(adsp1_sizes->zm)); - break; + return 0; +} - case WMFW_ADSP2: - pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer); - adsp2_sizes = (void *)&(header[1]); - footer = (void *)&(adsp2_sizes[1]); - sizes = sizeof(*adsp2_sizes); +static int wm_coeff_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value; - adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", - file, le32_to_cpu(adsp2_sizes->xm), - le32_to_cpu(adsp2_sizes->ym), - le32_to_cpu(adsp2_sizes->pm), - le32_to_cpu(adsp2_sizes->zm)); - break; + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; + + switch (ctl->dsp->rev) { + case 0: + uinfo->value.integer.max = + WM_ADSP_ACKED_CTL_MAX_VALUE_V1; + break; + default: + uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; + break; + } + uinfo->value.integer.step = 1; + uinfo->count = 1; + break; default: - BUG_ON(NULL == "Unknown DSP type"); - goto out_fw; + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = ctl->len; + break; } - if (le32_to_cpu(header->len) != sizeof(*header) + - sizes + sizeof(*footer)) { - adsp_err(dsp, "%s: unexpected header length %d\n", - file, le32_to_cpu(header->len)); - goto out_fw; - } + return 0; +} - adsp_dbg(dsp, "%s: timestamp %llu\n", file, - le64_to_cpu(footer->timestamp)); +static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, + unsigned int event_id) +{ + struct wm_adsp *dsp = ctl->dsp; + u32 val = cpu_to_be32(event_id); + unsigned int reg; + int i, ret; - while (pos < firmware->size && - pos - firmware->size > sizeof(*region)) { - region = (void *)&(firmware->data[pos]); - region_name = "Unknown"; - reg = 0; - text = NULL; - offset = le32_to_cpu(region->offset) & 0xffffff; - type = be32_to_cpu(region->type) & 0xff; - mem = wm_adsp_find_region(dsp, type); - - switch (type) { - case WMFW_NAME_TEXT: - region_name = "Firmware name"; - text = kzalloc(le32_to_cpu(region->len) + 1, - GFP_KERNEL); - break; - case WMFW_INFO_TEXT: - region_name = "Information"; - text = kzalloc(le32_to_cpu(region->len) + 1, - GFP_KERNEL); + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", + event_id, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); + + ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); + return ret; + } + + /* Poll for ack, we initially poll at 1ms intervals for firmwares + * that respond quickly, then go to 10ms polls. A firmware is unlikely + * to ack instantly so we do the first 1ms delay before reading the + * control to avoid a pointless bus transaction + */ + for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { + switch (i) { + case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS: + usleep_range(1000, 2000); + ++i; break; - case WMFW_ABSOLUTE: - region_name = "Absolute"; - reg = offset; - break; - case WMFW_ADSP1_PM: - BUG_ON(!mem); - region_name = "PM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; - case WMFW_ADSP1_DM: - BUG_ON(!mem); - region_name = "DM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; - case WMFW_ADSP2_XM: - BUG_ON(!mem); - region_name = "XM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; - case WMFW_ADSP2_YM: - BUG_ON(!mem); - region_name = "YM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; - case WMFW_ADSP1_ZM: - BUG_ON(!mem); - region_name = "ZM"; - reg = wm_adsp_region_to_reg(mem, offset); - break; - default: - adsp_warn(dsp, - "%s.%d: Unknown region type %x at %d(%x)\n", - file, regions, type, pos, pos); + default: + usleep_range(10000, 20000); + i += 10; break; } - adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, - regions, le32_to_cpu(region->len), offset, - region_name); + ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); + if (ret) { + adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); + return ret; + } - if (text) { - memcpy(text, region->data, le32_to_cpu(region->len)); - adsp_info(dsp, "%s: %s\n", file, text); - kfree(text); + if (val == 0) { + adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); + return 0; } + } - if (reg) { - buf = wm_adsp_buf_alloc(region->data, - le32_to_cpu(region->len), - &buf_list); - if (!buf) { - adsp_err(dsp, "Out of memory\n"); - return -ENOMEM; - } + adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", + reg, ctl->alg_region.alg, + wm_adsp_mem_region_name(ctl->alg_region.type), + ctl->offset); - ret = regmap_raw_write_async(regmap, reg, buf->buf, - le32_to_cpu(region->len)); - if (ret != 0) { - adsp_err(dsp, - "%s.%d: Failed to write %d bytes at %d in %s: %d\n", - file, regions, - le32_to_cpu(region->len), offset, - region_name, ret); - goto out_fw; - } - } + return -ETIMEDOUT; +} - pos += le32_to_cpu(region->len) + sizeof(*region); - regions++; - } +static int wm_coeff_put_acked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct wm_coeff_ctl *ctl = + (struct wm_coeff_ctl *)kcontrol->private_value; + unsigned int val = ucontrol->value.integer.value[0]; - ret = regmap_async_complete(regmap); - if (ret != 0) { - adsp_err(dsp, "Failed to complete async write: %d\n", ret); - goto out_fw; + if (!ctl->enabled) + return -EPERM; + + if (val == 0) + return 0; /* 0 means no event */ + + return wm_coeff_write_acked_control(ctl, val); +} + +static int wm_coeff_write_control(struct wm_coeff_ctl *ctl, + const void *buf, size_t len) +{ + struct wm_adsp *dsp = ctl->dsp; + void *scratch; + int ret; + unsigned int reg; + + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; + + scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + ret = regmap_raw_write(dsp->regmap, reg, scratch, + len); + if (ret) { + adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", + len, reg, ret); + kfree(scratch); + return ret; } + adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); - if (pos > firmware->size) - adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", - file, regions, pos - firmware->size); + kfree(scratch); -out_fw: - regmap_async_complete(regmap); - wm_adsp_buf_free(&buf_list); - release_firmware(firmware); -out: - kfree(file); + return 0; +} + +static int wm_coeff_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value; + char *p = ucontrol->value.bytes.data; + int ret = 0; + + mutex_lock(&ctl->lock); + + memcpy(ctl->cache, p, ctl->len); + + ctl->set = 1; + if (!ctl->enabled) + goto out; + ret = wm_coeff_write_control(ctl, p, ctl->len); + +out: + mutex_unlock(&ctl->lock); return ret; } -static int wm_adsp_setup_algs(struct wm_adsp *dsp) +static int wm_coeff_read_control(struct wm_coeff_ctl *ctl, + void *buf, size_t len) { - struct regmap *regmap = dsp->regmap; - struct wmfw_adsp1_id_hdr adsp1_id; - struct wmfw_adsp2_id_hdr adsp2_id; - struct wmfw_adsp1_alg_hdr *adsp1_alg; - struct wmfw_adsp2_alg_hdr *adsp2_alg; - void *alg, *buf; - struct wm_adsp_alg_region *region; - const struct wm_adsp_region *mem; - unsigned int pos, term; - size_t algs, buf_size; - __be32 val; - int i, ret; + struct wm_adsp *dsp = ctl->dsp; + void *scratch; + int ret; + unsigned int reg; - switch (dsp->type) { - case WMFW_ADSP1: - mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); - break; - case WMFW_ADSP2: - mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); - break; - default: - mem = NULL; - break; - } + ret = wm_coeff_base_reg(ctl, ®); + if (ret) + return ret; - if (mem == NULL) { - BUG_ON(mem != NULL); - return -EINVAL; + scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); + if (!scratch) + return -ENOMEM; + + ret = regmap_raw_read(dsp->regmap, reg, scratch, len); + if (ret) { + adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", + len, reg, ret); + kfree(scratch); + return ret; } + adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); - switch (dsp->type) { - case WMFW_ADSP1: - ret = regmap_raw_read(regmap, mem->base, &adsp1_id, - sizeof(adsp1_id)); - if (ret != 0) { - adsp_err(dsp, "Failed to read algorithm info: %d\n", - ret); - return ret; - } + memcpy(buf, scratch, len); + kfree(scratch); - buf = &adsp1_id; - buf_size = sizeof(adsp1_id); + return 0; +} - algs = be32_to_cpu(adsp1_id.algs); - dsp->fw_id = be32_to_cpu(adsp1_id.fw.id); - adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", - dsp->fw_id, - (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16, - (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8, - be32_to_cpu(adsp1_id.fw.ver) & 0xff, - algs); +static int wm_coeff_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value; + char *p = ucontrol->value.bytes.data; + int ret = 0; - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP1_ZM; - region->alg = be32_to_cpu(adsp1_id.fw.id); - region->base = be32_to_cpu(adsp1_id.zm); - list_add_tail(®ion->list, &dsp->alg_regions); + mutex_lock(&ctl->lock); - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP1_DM; - region->alg = be32_to_cpu(adsp1_id.fw.id); - region->base = be32_to_cpu(adsp1_id.dm); - list_add_tail(®ion->list, &dsp->alg_regions); + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { + if (ctl->enabled) + ret = wm_coeff_read_control(ctl, p, ctl->len); + else + ret = -EPERM; + goto out; + } else if (!ctl->flags && ctl->enabled) { + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + } - pos = sizeof(adsp1_id) / 2; - term = pos + ((sizeof(*adsp1_alg) * algs) / 2); - break; + memcpy(p, ctl->cache, ctl->len); - case WMFW_ADSP2: - ret = regmap_raw_read(regmap, mem->base, &adsp2_id, - sizeof(adsp2_id)); - if (ret != 0) { - adsp_err(dsp, "Failed to read algorithm info: %d\n", - ret); - return ret; - } +out: + mutex_unlock(&ctl->lock); + return ret; +} - buf = &adsp2_id; - buf_size = sizeof(adsp2_id); +static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* Although it's not useful to read an acked control, we must satisfy + * user-side assumptions that all controls are readable and that a + * write of the same value should be filtered out (it's valid to send + * the same event number again to the firmware). We therefore return 0, + * meaning "no event" so valid event numbers will always be a change + */ + ucontrol->value.integer.value[0] = 0; - algs = be32_to_cpu(adsp2_id.algs); - dsp->fw_id = be32_to_cpu(adsp2_id.fw.id); - adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", - dsp->fw_id, - (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16, - (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8, - be32_to_cpu(adsp2_id.fw.ver) & 0xff, - algs); + return 0; +} - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP2_XM; - region->alg = be32_to_cpu(adsp2_id.fw.id); - region->base = be32_to_cpu(adsp2_id.xm); - list_add_tail(®ion->list, &dsp->alg_regions); +struct wmfw_ctl_work { + struct wm_adsp *dsp; + struct wm_coeff_ctl *ctl; + struct work_struct work; +}; - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP2_YM; - region->alg = be32_to_cpu(adsp2_id.fw.id); - region->base = be32_to_cpu(adsp2_id.ym); - list_add_tail(®ion->list, &dsp->alg_regions); +static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) +{ + struct snd_kcontrol_new *kcontrol; + int ret; - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP2_ZM; - region->alg = be32_to_cpu(adsp2_id.fw.id); - region->base = be32_to_cpu(adsp2_id.zm); - list_add_tail(®ion->list, &dsp->alg_regions); + if (!ctl || !ctl->name) + return -EINVAL; - pos = sizeof(adsp2_id) / 2; - term = pos + ((sizeof(*adsp2_alg) * algs) / 2); - break; + kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); + if (!kcontrol) + return -ENOMEM; + kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; + + kcontrol->name = ctl->name; + kcontrol->info = wm_coeff_info; + kcontrol->private_value = (unsigned long)ctl; + + if (ctl->flags) { + if (ctl->flags & WMFW_CTL_FLAG_WRITEABLE) + kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_WRITE; + if (ctl->flags & WMFW_CTL_FLAG_READABLE) + kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_READ; + if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) + kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE; + } else { + kcontrol->access = SNDRV_CTL_ELEM_ACCESS_READWRITE; + kcontrol->access |= SNDRV_CTL_ELEM_ACCESS_VOLATILE; + } + switch (ctl->type) { + case WMFW_CTL_TYPE_ACKED: + kcontrol->get = wm_coeff_get_acked; + kcontrol->put = wm_coeff_put_acked; + break; default: - BUG_ON(NULL == "Unknown DSP type"); - return -EINVAL; + kcontrol->get = wm_coeff_get; + kcontrol->put = wm_coeff_put; + break; } - if (algs == 0) { - adsp_err(dsp, "No algorithms\n"); - return -EINVAL; - } + ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1); + if (ret < 0) + goto err_kcontrol; - if (algs > 1024) { - adsp_err(dsp, "Algorithm count %zx excessive\n", algs); - print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET, - buf, buf_size); - return -EINVAL; - } + kfree(kcontrol); - /* Read the terminator first to validate the length */ - ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val)); - if (ret != 0) { - adsp_err(dsp, "Failed to read algorithm list end: %d\n", - ret); - return ret; - } + ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name); - if (be32_to_cpu(val) != 0xbedead) - adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n", - term, be32_to_cpu(val)); + return 0; - alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA); - if (!alg) - return -ENOMEM; +err_kcontrol: + kfree(kcontrol); + return ret; +} - ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2); - if (ret != 0) { - adsp_err(dsp, "Failed to read algorithm list: %d\n", - ret); - goto out; - } +static int wm_coeff_init_control_caches(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret = 0; - adsp1_alg = alg; - adsp2_alg = alg; - - for (i = 0; i < algs; i++) { - switch (dsp->type) { - case WMFW_ADSP1: - adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", - i, be32_to_cpu(adsp1_alg[i].alg.id), - (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, - (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, - be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, - be32_to_cpu(adsp1_alg[i].dm), - be32_to_cpu(adsp1_alg[i].zm)); - - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP1_DM; - region->alg = be32_to_cpu(adsp1_alg[i].alg.id); - region->base = be32_to_cpu(adsp1_alg[i].dm); - list_add_tail(®ion->list, &dsp->alg_regions); - - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP1_ZM; - region->alg = be32_to_cpu(adsp1_alg[i].alg.id); - region->base = be32_to_cpu(adsp1_alg[i].zm); - list_add_tail(®ion->list, &dsp->alg_regions); - break; + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (!ctl->enabled || (ctl->flags & WMFW_CTL_FLAG_VOLATILE)) + continue; - case WMFW_ADSP2: - adsp_info(dsp, - "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", - i, be32_to_cpu(adsp2_alg[i].alg.id), - (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, - (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, - be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, - be32_to_cpu(adsp2_alg[i].xm), - be32_to_cpu(adsp2_alg[i].ym), - be32_to_cpu(adsp2_alg[i].zm)); - - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP2_XM; - region->alg = be32_to_cpu(adsp2_alg[i].alg.id); - region->base = be32_to_cpu(adsp2_alg[i].xm); - list_add_tail(®ion->list, &dsp->alg_regions); - - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP2_YM; - region->alg = be32_to_cpu(adsp2_alg[i].alg.id); - region->base = be32_to_cpu(adsp2_alg[i].ym); - list_add_tail(®ion->list, &dsp->alg_regions); - - region = kzalloc(sizeof(*region), GFP_KERNEL); - if (!region) - return -ENOMEM; - region->type = WMFW_ADSP2_ZM; - region->alg = be32_to_cpu(adsp2_alg[i].alg.id); - region->base = be32_to_cpu(adsp2_alg[i].zm); - list_add_tail(®ion->list, &dsp->alg_regions); - break; - } + mutex_lock(&ctl->lock); + + if (!ctl->set) + ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); + + mutex_unlock(&ctl->lock); + + if (ret < 0) + return ret; } -out: - kfree(alg); - return ret; + return 0; } -static int wm_adsp_load_coeff(struct wm_adsp *dsp) +static int wm_coeff_sync_controls(struct wm_adsp *dsp) { - LIST_HEAD(buf_list); - struct regmap *regmap = dsp->regmap; - struct wmfw_coeff_hdr *hdr; - struct wmfw_coeff_item *blk; - const struct firmware *firmware; - const struct wm_adsp_region *mem; - struct wm_adsp_alg_region *alg_region; - const char *region_name; - int ret, pos, blocks, type, offset, reg; - char *file; - struct wm_adsp_buf *buf; - int tmp; + struct wm_coeff_ctl *ctl; + int ret = 0; - file = kzalloc(PAGE_SIZE, GFP_KERNEL); - if (file == NULL) - return -ENOMEM; + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (!ctl->enabled || (ctl->flags & WMFW_CTL_FLAG_VOLATILE)) + continue; - snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num, - wm_adsp_fw[dsp->fw].file); - file[PAGE_SIZE - 1] = '\0'; + mutex_lock(&ctl->lock); - ret = request_firmware(&firmware, file, dsp->dev); - if (ret != 0) { - adsp_warn(dsp, "Failed to request '%s'\n", file); - ret = 0; - goto out; + if (ctl->set) + ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len); + + mutex_unlock(&ctl->lock); + + if (ret < 0) + return ret; } - ret = -EINVAL; - if (sizeof(*hdr) >= firmware->size) { - adsp_err(dsp, "%s: file too short, %zu bytes\n", - file, firmware->size); - goto out_fw; + return 0; +} + +static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, + unsigned int event) +{ + struct wm_coeff_ctl *ctl; + int ret; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) + continue; + + ret = wm_coeff_write_acked_control(ctl, event); + if (ret) + adsp_warn(dsp, + "Failed to send 0x%x event to alg 0x%x (%d)\n", + event, ctl->alg_region.alg, ret); } +} - hdr = (void*)&firmware->data[0]; - if (memcmp(hdr->magic, "WMDR", 4) != 0) { - adsp_err(dsp, "%s: invalid magic\n", file); - goto out_fw; +static void wm_adsp_ctl_work(struct work_struct *work) +{ + struct wmfw_ctl_work *ctl_work = container_of(work, + struct wmfw_ctl_work, + work); + + wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl); + kfree(ctl_work); +} + +static int wm_adsp_create_ctl_blk(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region, + unsigned int offset, unsigned int len, + const char *subname, unsigned int subname_len, + unsigned int flags, unsigned int type, + int block) +{ + struct wm_coeff_ctl *ctl; + struct wmfw_ctl_work *ctl_work; + char name[WM_ADSP_CONTROL_MAX]; + const char *region_name; + int ret; + + region_name = wm_adsp_mem_region_name(alg_region->type); + if (!region_name) { + adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); + return -EINVAL; } - switch (be32_to_cpu(hdr->rev) & 0xff) { + switch (dsp->fw_ver) { + case 0: case 1: + snprintf(name, WM_ADSP_CONTROL_MAX, "DSP%d %s %x:%d", + dsp->num, region_name, alg_region->alg, block); break; default: - adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", - file, be32_to_cpu(hdr->rev) & 0xff); - ret = -EINVAL; - goto out_fw; - } + ret = snprintf(name, WM_ADSP_CONTROL_MAX, "DSP%d%c %.10s %x:%d", + dsp->num, *region_name, + dsp->firmwares[dsp->fw].name, + alg_region->alg, block); - adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, - (le32_to_cpu(hdr->ver) >> 16) & 0xff, - (le32_to_cpu(hdr->ver) >> 8) & 0xff, - le32_to_cpu(hdr->ver) & 0xff); + /* Truncate the subname from the start if it is too long */ + if (subname) { + int avail = WM_ADSP_CONTROL_MAX - ret - 2; + int skip = 0; - pos = le32_to_cpu(hdr->len); + if (subname_len > avail) + skip = subname_len - avail; - blocks = 0; - while (pos < firmware->size && - pos - firmware->size > sizeof(*blk)) { - blk = (void*)(&firmware->data[pos]); + snprintf(name + ret, WM_ADSP_CONTROL_MAX - ret, " %.*s", + subname_len - skip, subname + skip); + } + break; + } - type = le16_to_cpu(blk->type); - offset = le16_to_cpu(blk->offset); + list_for_each_entry(ctl, &dsp->ctl_list, + list) { + if (!strcmp(ctl->name, name)) { + if (!ctl->enabled) + ctl->enabled = 1; + return 0; + } + } - adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", - file, blocks, le32_to_cpu(blk->id), - (le32_to_cpu(blk->ver) >> 16) & 0xff, - (le32_to_cpu(blk->ver) >> 8) & 0xff, - le32_to_cpu(blk->ver) & 0xff); - adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", - file, blocks, le32_to_cpu(blk->len), offset, type); + ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); + if (!ctl) + return -ENOMEM; + ctl->fw_name = dsp->firmwares[dsp->fw].name; + ctl->alg_region = *alg_region; + ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); + if (!ctl->name) { + ret = -ENOMEM; + goto err_ctl; + } + ctl->enabled = 1; + ctl->set = 0; + ctl->ops.xget = wm_coeff_get; + ctl->ops.xput = wm_coeff_put; + ctl->dsp = dsp; + + ctl->flags = flags; + ctl->type = type; + ctl->offset = offset; + if (len > 512) { + adsp_warn(dsp, "Truncating control %s from %d\n", + ctl->name, len); + len = 512; + } + ctl->len = len; + ctl->cache = kzalloc(ctl->len, GFP_KERNEL); + if (!ctl->cache) { + ret = -ENOMEM; + goto err_ctl_name; + } + mutex_init(&ctl->lock); - reg = 0; + mutex_lock(&dsp->ctl_lock); + list_add(&ctl->list, &dsp->ctl_list); + mutex_unlock(&dsp->ctl_lock); + + if (flags & WMFW_CTL_FLAG_SYS) + return 0; + + ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); + if (!ctl_work) { + ret = -ENOMEM; + goto err_ctl_cache; + } + + ctl_work->dsp = dsp; + ctl_work->ctl = ctl; + INIT_WORK(&ctl_work->work, wm_adsp_ctl_work); + schedule_work(&ctl_work->work); + + return 0; + +err_ctl_cache: + kfree(ctl->cache); +err_ctl_name: + kfree(ctl->name); +err_ctl: + kfree(ctl); + + return ret; +} + +static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl) +{ + kfree(ctl->cache); + kfree(ctl->name); + kfree(ctl); +} + +static int wm_adsp_create_control(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region, + unsigned int offset, unsigned int len, + const char *subname, unsigned int subname_len, + unsigned int flags, unsigned int type) +{ + unsigned int ctl_len; + int block = 0; + int ret; + + while (len) { + ctl_len = len; + if (ctl_len > 512) + ctl_len = 512; + + ret = wm_adsp_create_ctl_blk(dsp, alg_region, offset, + ctl_len, subname, subname_len, + flags, type, block); + if (ret < 0) + return ret; + + offset += ctl_len / 4; + len -= ctl_len; + + block++; + } + + return 0; +} + +static int wm_adsp_hpimp_update(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + int ret = 0; + u32 tmp; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->type != WMFW_CTL_TYPE_HP_IMP) + continue; + if (!dsp->hpimp_cb) { + adsp_err(dsp, + "HP imp callback not registered: %s\n", + ctl->name); + return -EINVAL; + } + + mutex_lock(&ctl->lock); + + tmp = dsp->hpimp_cb(dsp->dev); + tmp = cpu_to_be32(tmp & 0x00ffffffu); + memcpy(ctl->cache, &tmp, sizeof(tmp)); + ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len); + + mutex_unlock(&ctl->lock); + + if (ret < 0) + return ret; + } + + return 0; +} + +struct wm_coeff_parsed_alg { + int id; + const u8 *name; + int name_len; + int ncoeff; +}; + +struct wm_coeff_parsed_coeff { + int offset; + int mem_type; + const u8 *name; + int name_len; + int ctl_type; + int flags; + int len; +}; + +static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) +{ + int length; + + switch (bytes) { + case 1: + length = **pos; + break; + case 2: + length = le16_to_cpu(*((u16 *)*pos)); + break; + default: + return 0; + } + + if (str) + *str = *pos + bytes; + + *pos += ((length + bytes) + 3) & ~0x03; + + return length; +} + +static int wm_coeff_parse_int(int bytes, const u8 **pos) +{ + int val = 0; + + switch (bytes) { + case 2: + val = le16_to_cpu(*((u16 *)*pos)); + break; + case 4: + val = le32_to_cpu(*((u32 *)*pos)); + break; + default: + break; + } + + *pos += bytes; + + return val; +} + +static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_alg *blk) +{ + const struct wmfw_adsp_alg_data *raw; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_alg_data *)*data; + *data = raw->data; + + blk->id = le32_to_cpu(raw->id); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ncoeff = le32_to_cpu(raw->ncoeff); + break; + default: + blk->id = wm_coeff_parse_int(sizeof(raw->id), data); + blk->name_len = wm_coeff_parse_string(sizeof(u8), data, + &blk->name); + /* Discard description we have no use for it in the driver */ + wm_coeff_parse_string(sizeof(u16), data, NULL); + blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data); + break; + } + + adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); + adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); +} + +static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, + struct wm_coeff_parsed_coeff *blk) +{ + const struct wmfw_adsp_coeff_data *raw; + const u8 *tmp; + int length; + + switch (dsp->fw_ver) { + case 0: + case 1: + raw = (const struct wmfw_adsp_coeff_data *)*data; + *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); + + blk->offset = le16_to_cpu(raw->hdr.offset); + blk->mem_type = le16_to_cpu(raw->hdr.type); + blk->name = raw->name; + blk->name_len = strlen(raw->name); + blk->ctl_type = le16_to_cpu(raw->ctl_type); + blk->flags = le16_to_cpu(raw->flags); + blk->len = le32_to_cpu(raw->len); + break; + default: + tmp = *data; + blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); + blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp); + length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp); + blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp, + &blk->name); + /* Discard extended name we have no use for it in the driver */ + wm_coeff_parse_string(sizeof(u8), &tmp, NULL); + /* Discard description we have no use for it in the driver */ + wm_coeff_parse_string(sizeof(u16), &tmp, NULL); + blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp); + blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp); + blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp); + + *data = *data + sizeof(raw->hdr) + length; + break; + } + + adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); + adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); + adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); + adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); + adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); + adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); +} + +static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp, + const struct wm_coeff_parsed_coeff *coeff_blk, + unsigned int f_required, + unsigned int f_illegal) +{ + if ((coeff_blk->flags & f_illegal) || + ((coeff_blk->flags & f_required) != f_required)) { + adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", + coeff_blk->flags, coeff_blk->ctl_type); + return -EINVAL; + } + + return 0; +} + +static int wm_adsp_parse_coeff(struct wm_adsp *dsp, + const struct wmfw_region *region) +{ + struct wm_adsp_alg_region alg_region = {}; + struct wm_coeff_parsed_alg alg_blk; + struct wm_coeff_parsed_coeff coeff_blk; + const u8 *data = region->data; + int i, ret; + + wm_coeff_parse_alg(dsp, &data, &alg_blk); + for (i = 0; i < alg_blk.ncoeff; i++) { + wm_coeff_parse_coeff(dsp, &data, &coeff_blk); + + switch (coeff_blk.ctl_type) { + case SNDRV_CTL_ELEM_TYPE_BYTES: + break; + case WMFW_CTL_TYPE_HP_IMP: + if (!(coeff_blk.flags & WMFW_CTL_FLAG_WRITEABLE)) { + adsp_err(dsp, + "HP imp coeff not writeable: %.*s\n", + coeff_blk.name_len, + coeff_blk.name); + continue; + } + if (coeff_blk.len != WMFW_CTL_HP_IMP_LEN) { + adsp_err(dsp, "Bad HP imp coeff len: %d\n", + coeff_blk.len); + continue; + } + break; + case WMFW_CTL_TYPE_ACKED: + if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) + continue; /* ignore */ + + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + case WMFW_CTL_TYPE_HOSTEVENT: + ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, + WMFW_CTL_FLAG_SYS | + WMFW_CTL_FLAG_VOLATILE | + WMFW_CTL_FLAG_WRITEABLE | + WMFW_CTL_FLAG_READABLE, + 0); + if (ret) + return -EINVAL; + break; + default: + adsp_err(dsp, "Unknown control type: %d\n", + coeff_blk.ctl_type); + return -EINVAL; + } + + alg_region.type = coeff_blk.mem_type; + alg_region.alg = alg_blk.id; + + ret = wm_adsp_create_control(dsp, &alg_region, + coeff_blk.offset, + coeff_blk.len, + coeff_blk.name, + coeff_blk.name_len, + coeff_blk.flags, + coeff_blk.ctl_type); + if (ret < 0) + adsp_err(dsp, "Failed to create control: %.*s, %d\n", + coeff_blk.name_len, coeff_blk.name, ret); + } + + return 0; +} + +static int wm_adsp_write_blocks(struct wm_adsp *dsp, const u8 *data, size_t len, + unsigned reg, struct list_head *list) + +{ + size_t to_write = PAGE_SIZE; + size_t remain = len; + struct wm_adsp_buf *buf; + int ret; + + while (remain > 0) { + if (remain < PAGE_SIZE) + to_write = remain; + + buf = wm_adsp_buf_alloc(data, to_write, list); + if (!buf) { + adsp_err(dsp, "Out of memory\n"); + return -ENOMEM; + } + + ret = regmap_raw_write_async(dsp->regmap, reg, + buf->buf, to_write); + if (ret != 0) { + adsp_err(dsp, + "Failed to write %zd bytes at %d\n", + to_write, reg); + + return ret; + } + + data += to_write; + reg += to_write / 2; + remain -= to_write; + } + + return 0; +} + +static int wm_adsp_load(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + const struct firmware *firmware; + struct regmap *regmap = dsp->regmap; + unsigned int pos = 0; + const struct wmfw_header *header; + const struct wmfw_adsp1_sizes *adsp1_sizes; + const struct wmfw_adsp2_sizes *adsp2_sizes; + const struct wmfw_footer *footer; + const struct wmfw_region *region; + const struct wm_adsp_region *mem; + const char *region_name; + char *file, *text; + unsigned int reg; + int regions = 0; + int ret, offset, type, sizes; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + if (dsp->part_rev) { + snprintf(file, PAGE_SIZE, "%s%c-dsp%d-%s.wmfw", + dsp->part, dsp->part_rev, dsp->num, + dsp->firmwares[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + mutex_lock(dsp->fw_lock); + ret = request_firmware(&firmware, file, dsp->dev); + mutex_unlock(dsp->fw_lock); + } else { + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, + dsp->num, dsp->firmwares[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + mutex_lock(dsp->fw_lock); + ret = request_firmware(&firmware, file, dsp->dev); + mutex_unlock(dsp->fw_lock); + } + if (ret != 0) { + adsp_err(dsp, "Failed to request: '%s'\n", file); + goto out; + } + ret = -EINVAL; + + pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); + if (pos >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", + file, firmware->size); + goto out_fw; + } + + header = (void*)&firmware->data[0]; + + if (memcmp(&header->magic[0], "WMFW", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + switch (header->ver) { + case 0: + adsp_warn(dsp, "%s: Depreciated file format %d\n", + file, header->ver); + break; + case 1: + case 2: + break; + default: + adsp_err(dsp, "%s: unknown file format %d\n", + file, header->ver); + goto out_fw; + } + + adsp_info(dsp, "Firmware version: %d\n", header->ver); + dsp->fw_ver = header->ver; + + if (header->core != dsp->type) { + adsp_err(dsp, "%s: invalid core %d != %d\n", + file, header->core, dsp->type); + goto out_fw; + } + + switch (dsp->type) { + case WMFW_ADSP1: + pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); + adsp1_sizes = (void *)&(header[1]); + footer = (void *)&(adsp1_sizes[1]); + sizes = sizeof(*adsp1_sizes); + + adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", + file, le32_to_cpu(adsp1_sizes->dm), + le32_to_cpu(adsp1_sizes->pm), + le32_to_cpu(adsp1_sizes->zm)); + break; + + case WMFW_ADSP2: + pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer); + adsp2_sizes = (void *)&(header[1]); + footer = (void *)&(adsp2_sizes[1]); + sizes = sizeof(*adsp2_sizes); + + adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", + file, le32_to_cpu(adsp2_sizes->xm), + le32_to_cpu(adsp2_sizes->ym), + le32_to_cpu(adsp2_sizes->pm), + le32_to_cpu(adsp2_sizes->zm)); + break; + + default: + BUG_ON(NULL == "Unknown DSP type"); + goto out_fw; + } + + if (le32_to_cpu(header->len) != sizeof(*header) + + sizes + sizeof(*footer)) { + adsp_err(dsp, "%s: unexpected header length %d\n", + file, le32_to_cpu(header->len)); + goto out_fw; + } + + adsp_dbg(dsp, "%s: timestamp %llu\n", file, + le64_to_cpu(footer->timestamp)); + + while (pos < firmware->size && + pos - firmware->size > sizeof(*region)) { + region = (void *)&(firmware->data[pos]); region_name = "Unknown"; + reg = 0; + text = NULL; + offset = le32_to_cpu(region->offset) & 0xffffff; + type = be32_to_cpu(region->type) & 0xff; + mem = wm_adsp_find_region(dsp, type); + switch (type) { - case (WMFW_NAME_TEXT << 8): - case (WMFW_INFO_TEXT << 8): + case WMFW_NAME_TEXT: + region_name = "Firmware name"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); break; - case (WMFW_ABSOLUTE << 8): - /* + case WMFW_ALGORITHM_DATA: + region_name = "Algorithm"; + ret = wm_adsp_parse_coeff(dsp, region); + if (ret != 0) + goto out_fw; + break; + case WMFW_INFO_TEXT: + region_name = "Information"; + text = kzalloc(le32_to_cpu(region->len) + 1, + GFP_KERNEL); + break; + case WMFW_ABSOLUTE: + region_name = "Absolute"; + reg = offset; + break; + case WMFW_ADSP1_PM: + case WMFW_ADSP1_DM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + case WMFW_ADSP1_ZM: + BUG_ON(!mem); + region_name = wm_adsp_mem_region_name(type); + reg = wm_adsp_region_to_reg(mem, offset); + break; + default: + adsp_warn(dsp, + "%s.%d: Unknown region type %x at %d(%x)\n", + file, regions, type, pos, pos); + break; + } + + adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, + regions, le32_to_cpu(region->len), offset, + region_name); + + if (text) { + memcpy(text, region->data, le32_to_cpu(region->len)); + adsp_info(dsp, "%s: %s\n", file, text); + kfree(text); + } + + if (reg) { + ret = wm_adsp_write_blocks(dsp, region->data, + le32_to_cpu(region->len), + reg, &buf_list); + if (ret != 0) { + adsp_err(dsp, + "%s.%d: Failed writing data at %d in %s: %d\n", + file, regions, + offset, region_name, ret); + goto out_buf; + } + } + + pos += le32_to_cpu(region->len) + sizeof(*region); + regions++; + } + + ret = regmap_async_complete(regmap); + if (ret != 0) { + adsp_err(dsp, "Failed to complete async write: %d\n", ret); + goto out_buf; + } + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", + file, regions, pos - firmware->size); + + wm_adsp_debugfs_save_wmfwname(dsp, file); + +out_buf: + wm_adsp_buf_free(&buf_list); +out_fw: + release_firmware(firmware); +out: + kfree(file); + + return ret; +} + +static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, + const struct wm_adsp_alg_region *alg_region) +{ + struct wm_coeff_ctl *ctl; + + list_for_each_entry(ctl, &dsp->ctl_list, list) { + if (ctl->fw_name == dsp->firmwares[dsp->fw].name && + alg_region->alg == ctl->alg_region.alg && + alg_region->type == ctl->alg_region.type) { + ctl->alg_region.base = alg_region->base; + } + } +} + +static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, + unsigned int pos, unsigned int len) +{ + void *alg; + int ret; + __be32 val; + + if (n_algs == 0) { + adsp_err(dsp, "No algorithms\n"); + return ERR_PTR(-EINVAL); + } + + if (n_algs > 1024) { + adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); + return ERR_PTR(-EINVAL); + } + + /* Read the terminator first to validate the length */ + ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list end: %d\n", + ret); + return ERR_PTR(ret); + } + + if (be32_to_cpu(val) != 0xbedead) + adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n", + pos + len, be32_to_cpu(val)); + + alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA); + if (!alg) + return ERR_PTR(-ENOMEM); + + ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm list: %d\n", ret); + kfree(alg); + return ERR_PTR(ret); + } + + return alg; +} + +static struct wm_adsp_alg_region * + wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id) +{ + struct wm_adsp_alg_region *alg_region; + + list_for_each_entry(alg_region, &dsp->alg_regions, list) { + if (id == alg_region->alg && type == alg_region->type) + return alg_region; + } + + return NULL; +} + +static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp, + int type, __be32 id, + __be32 base) +{ + struct wm_adsp_alg_region *alg_region; + + alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); + if (!alg_region) + return ERR_PTR(-ENOMEM); + + alg_region->type = type; + alg_region->alg = be32_to_cpu(id); + alg_region->base = be32_to_cpu(base); + + list_add_tail(&alg_region->list, &dsp->alg_regions); + + if (dsp->fw_ver > 0) + wm_adsp_ctl_fixup_base(dsp, alg_region); + + return alg_region; +} + +static void wm_adsp_free_alg_regions(struct wm_adsp *dsp) +{ + struct wm_adsp_alg_region *alg_region; + + while (!list_empty(&dsp->alg_regions)) { + alg_region = list_first_entry(&dsp->alg_regions, + struct wm_adsp_alg_region, + list); + list_del(&alg_region->list); + kfree(alg_region); + } +} + +static int wm_adsp1_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp1_id_hdr adsp1_id; + struct wmfw_adsp1_alg_hdr *adsp1_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, + sizeof(adsp1_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + n_algs = be32_to_cpu(adsp1_id.n_algs); + dsp->fw_id = be32_to_cpu(adsp1_id.fw.id); + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", + dsp->fw_id, + (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_id.fw.ver) & 0xff, + n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, + adsp1_id.fw.id, adsp1_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, + adsp1_id.fw.id, adsp1_id.dm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(adsp1_id) / 2; + len = (sizeof(*adsp1_alg) * n_algs) / 2; + + adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); + if (IS_ERR(adsp1_alg)) + return PTR_ERR(adsp1_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", + i, be32_to_cpu(adsp1_alg[i].alg.id), + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp1_alg[i].dm), + be32_to_cpu(adsp1_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, + adsp1_alg[i].alg.id, + adsp1_alg[i].dm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].dm); + len -= be32_to_cpu(adsp1_alg[i].dm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region DM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, + adsp1_alg[i].alg.id, + adsp1_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp1_alg[i + 1].zm); + len -= be32_to_cpu(adsp1_alg[i].zm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp1_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp1_alg); + return ret; +} + +static int wm_adsp2_setup_algs(struct wm_adsp *dsp) +{ + struct wmfw_adsp2_id_hdr adsp2_id; + struct wmfw_adsp2_alg_hdr *adsp2_alg; + struct wm_adsp_alg_region *alg_region; + const struct wm_adsp_region *mem; + unsigned int pos, len; + size_t n_algs; + int i, ret; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); + if (WARN_ON(!mem)) + return -EINVAL; + + ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, + sizeof(adsp2_id)); + if (ret != 0) { + adsp_err(dsp, "Failed to read algorithm info: %d\n", + ret); + return ret; + } + + n_algs = be32_to_cpu(adsp2_id.n_algs); + dsp->fw_id = be32_to_cpu(adsp2_id.fw.id); + dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver); + adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", + dsp->fw_id, + (dsp->fw_id_version & 0xff0000) >> 16, + (dsp->fw_id_version & 0xff00) >> 8, + dsp->fw_id_version & 0xff, + n_algs); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + adsp2_id.fw.id, adsp2_id.xm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + adsp2_id.fw.id, adsp2_id.ym); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_id.fw.id, adsp2_id.zm); + if (IS_ERR(alg_region)) + return PTR_ERR(alg_region); + + pos = sizeof(adsp2_id) / 2; + len = (sizeof(*adsp2_alg) * n_algs) / 2; + + adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len); + if (IS_ERR(adsp2_alg)) + return PTR_ERR(adsp2_alg); + + for (i = 0; i < n_algs; i++) { + adsp_info(dsp, + "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", + i, be32_to_cpu(adsp2_alg[i].alg.id), + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, + (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, + be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, + be32_to_cpu(adsp2_alg[i].xm), + be32_to_cpu(adsp2_alg[i].ym), + be32_to_cpu(adsp2_alg[i].zm)); + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, + adsp2_alg[i].alg.id, + adsp2_alg[i].xm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].xm); + len -= be32_to_cpu(adsp2_alg[i].xm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region XM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, + adsp2_alg[i].alg.id, + adsp2_alg[i].ym); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].ym); + len -= be32_to_cpu(adsp2_alg[i].ym); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region YM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + + alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, + adsp2_alg[i].alg.id, + adsp2_alg[i].zm); + if (IS_ERR(alg_region)) { + ret = PTR_ERR(alg_region); + goto out; + } + if (dsp->fw_ver == 0) { + if (i + 1 < n_algs) { + len = be32_to_cpu(adsp2_alg[i + 1].zm); + len -= be32_to_cpu(adsp2_alg[i].zm); + len *= 4; + wm_adsp_create_control(dsp, alg_region, 0, + len, NULL, 0, 0, + SNDRV_CTL_ELEM_TYPE_BYTES); + } else { + adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", + be32_to_cpu(adsp2_alg[i].alg.id)); + } + } + } + +out: + kfree(adsp2_alg); + return ret; +} + +static int wm_adsp_load_coeff(struct wm_adsp *dsp) +{ + LIST_HEAD(buf_list); + struct regmap *regmap = dsp->regmap; + struct wmfw_coeff_hdr *hdr; + struct wmfw_coeff_item *blk; + const struct firmware *firmware; + const struct wm_adsp_region *mem; + struct wm_adsp_alg_region *alg_region; + const char *region_name; + int ret = 0; + int err, pos, blocks, type, offset, reg; + char *file; + + if (dsp->firmwares[dsp->fw].binfile && + !(strcmp(dsp->firmwares[dsp->fw].binfile, "None"))) + return 0; + + file = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (file == NULL) + return -ENOMEM; + + if (dsp->firmwares[dsp->fw].binfile) + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, + dsp->num, dsp->firmwares[dsp->fw].binfile); + else + snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, + dsp->num, dsp->firmwares[dsp->fw].file); + file[PAGE_SIZE - 1] = '\0'; + + mutex_lock(dsp->fw_lock); + ret = request_firmware(&firmware, file, dsp->dev); + mutex_unlock(dsp->fw_lock); + if (ret != 0) { + adsp_warn(dsp, "Failed to request '%s'\n", file); + ret = 0; + goto out; + } + ret = -EINVAL; + + if (sizeof(*hdr) >= firmware->size) { + adsp_err(dsp, "%s: file too short, %zu bytes\n", + file, firmware->size); + goto out_fw; + } + + hdr = (void*)&firmware->data[0]; + if (memcmp(hdr->magic, "WMDR", 4) != 0) { + adsp_err(dsp, "%s: invalid magic\n", file); + goto out_fw; + } + + switch (be32_to_cpu(hdr->rev) & 0xff) { + case 1: + break; + default: + adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", + file, be32_to_cpu(hdr->rev) & 0xff); + ret = -EINVAL; + goto out_fw; + } + + adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, + (le32_to_cpu(hdr->ver) >> 16) & 0xff, + (le32_to_cpu(hdr->ver) >> 8) & 0xff, + le32_to_cpu(hdr->ver) & 0xff); + + pos = le32_to_cpu(hdr->len); + + blocks = 0; + while (pos < firmware->size && + pos - firmware->size > sizeof(*blk)) { + blk = (void*)(&firmware->data[pos]); + + type = le16_to_cpu(blk->type); + offset = le16_to_cpu(blk->offset); + + adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", + file, blocks, le32_to_cpu(blk->id), + (le32_to_cpu(blk->ver) >> 16) & 0xff, + (le32_to_cpu(blk->ver) >> 8) & 0xff, + le32_to_cpu(blk->ver) & 0xff); + adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", + file, blocks, le32_to_cpu(blk->len), offset, type); + + reg = 0; + region_name = "Unknown"; + switch (type) { + case (WMFW_NAME_TEXT << 8): + case (WMFW_INFO_TEXT << 8): + break; + case (WMFW_ABSOLUTE << 8): + /* * Old files may use this for global * coefficients. */ @@ -877,413 +2311,1746 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp) mem = wm_adsp_find_region(dsp, type); if (!mem) { adsp_err(dsp, "No ZM\n"); - break; + ret = -EINVAL; + goto out_fw; } reg = wm_adsp_region_to_reg(mem, 0); - } else { - region_name = "register"; - reg = offset; - } - break; + } else { + region_name = "register"; + reg = offset; + } + break; + + case WMFW_ADSP1_DM: + case WMFW_ADSP1_ZM: + case WMFW_ADSP2_XM: + case WMFW_ADSP2_YM: + adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", + file, blocks, le32_to_cpu(blk->len), + type, le32_to_cpu(blk->id)); + + mem = wm_adsp_find_region(dsp, type); + if (!mem) { + adsp_err(dsp, "No base for region %x\n", type); + ret = -EINVAL; + goto out_fw; + } + + alg_region = wm_adsp_find_alg_region(dsp, type, + le32_to_cpu(blk->id)); + if (alg_region) { + reg = alg_region->base; + reg = wm_adsp_region_to_reg(mem, reg); + reg += offset; + } else { + adsp_err(dsp, "No %x for algorithm %x\n", + type, le32_to_cpu(blk->id)); + } + break; + + default: + adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", + file, blocks, type, pos); + ret = -EINVAL; + goto out_fw; + } + + if (reg) { + ret = wm_adsp_write_blocks(dsp, blk->data, + le32_to_cpu(blk->len), + reg, &buf_list); + + if (ret != 0) { + adsp_err(dsp, + "%s.%d: Failed to write to %x in %s: %d\n", + file, blocks, reg, region_name, ret); + goto out_fw; + } + } + + pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; + blocks++; + } + + if (pos > firmware->size) + adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", + file, blocks, pos - firmware->size); + + wm_adsp_debugfs_save_binname(dsp, file); + + err = regmap_async_complete(regmap); + if (err != 0) { + adsp_err(dsp, "Failed to complete async write: %d\n", err); + if (!ret) + ret = err; + } + +out_fw: + release_firmware(firmware); + wm_adsp_buf_free(&buf_list); +out: + kfree(file); + return ret; +} + +int wm_adsp1_init(struct wm_adsp *dsp) +{ + INIT_LIST_HEAD(&dsp->alg_regions); + +#ifdef CONFIG_DEBUG_FS + mutex_init(&dsp->debugfs_lock); +#endif + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp1_init); + +static int wm_adsp_get_features(struct wm_adsp *dsp) +{ + memset(&dsp->fw_features, 0, sizeof(dsp->fw_features)); + + switch (dsp->fw_id) { + case 0x4000d: + case 0x40036: + case 0x5f003: + case 0x6000d: + case 0x60037: + case 0x60053: + case 0x7000d: + case 0x70036: + case 0x8000d: + case 0x80053: + case 0x9000d: + /* ez2control */ + dsp->fw_features.ez2control_trigger = true; + dsp->fw_features.host_read_buf = true; + break; + case 0x4001e: + case 0x5001e: + case 0x6001e: + case 0x7001e: + case 0x8001e: + case 0x9001e: + case 0xd001e: + /* trace firmware */ + dsp->fw_features.host_read_buf = true; + break; + case 0x40019: + case 0x4001f: + case 0x5001f: + case 0x7001f: + dsp->fw_features.edac_shutdown = true; + default: + break; + } + + return 0; +} + + +int wm_adsp1_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = w->codec; + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + int ret; + unsigned int val; + + dsp->card = codec->card; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, ADSP1_SYS_ENA); + + /* + * For simplicity set the DSP clock rate to be the + * SYSCLK rate rather than making it configurable. + */ + if(dsp->sysclk_reg) { + ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); + if (ret != 0) { + adsp_err(dsp, "Failed to read SYSCLK state: %d\n", + ret); + return ret; + } + + val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; + + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP1_CONTROL_31, + ADSP1_CLK_SEL_MASK, val); + if (ret != 0) { + adsp_err(dsp, "Failed to set clock rate: %d\n", + ret); + return ret; + } + } + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err; + + ret = wm_adsp1_setup_algs(dsp); + if (ret != 0) + goto err; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + /* Start the core running */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, + ADSP1_CORE_ENA | ADSP1_START); + break; + + case SND_SOC_DAPM_PRE_PMD: + /* Halt the core */ + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_CORE_ENA | ADSP1_START, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, + ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); + + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); + + list_for_each_entry(ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + break; + + default: + break; + } + + return 0; + +err: + regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, + ADSP1_SYS_ENA, 0); + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp1_event); + +static int wm_adsp2_ena(struct wm_adsp *dsp) +{ + unsigned int val; + int ret, count; + + switch (dsp->rev) { + case 0: + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, ADSP2_SYS_ENA); + + if (ret != 0) + return ret; + + /* Wait for the RAM to start, should be near instantaneous */ + for (count = 0; count < 10; ++count) { + ret = regmap_read(dsp->regmap, + dsp->base + ADSP2_STATUS1, + &val); + if (ret != 0) + return ret; + + if (val & ADSP2_RAM_RDY) + break; + + msleep(1); + } + + if (!(val & ADSP2_RAM_RDY)) { + adsp_err(dsp, "Failed to start DSP RAM\n"); + return -EBUSY; + } + adsp_dbg(dsp, "RAM ready after %d polls\n", count); + break; + default: + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, ADSP2_MEM_ENA); + + if (ret != 0) + return ret; + + break; + } + + return 0; +} + +static void wm_adsp2_boot_work(struct work_struct *work) +{ + struct wm_adsp *dsp = container_of(work, + struct wm_adsp, + boot_work); + int ret; + + ret = wm_adsp2_ena(dsp); + if (ret != 0) + return; + + ret = wm_adsp_load(dsp); + if (ret != 0) + goto err; + + ret = wm_adsp2_setup_algs(dsp); + if (ret != 0) + goto err; + + ret = wm_adsp_load_coeff(dsp); + if (ret != 0) + goto err; + + /* Initialize caches for enabled and unset controls */ + ret = wm_coeff_init_control_caches(dsp); + if (ret != 0) + goto err; + + /* Sync set controls */ + ret = wm_coeff_sync_controls(dsp); + if (ret != 0) + goto err; + + /* Check firmware features */ + ret = wm_adsp_get_features(dsp); + if (ret != 0) + goto err; + + /* Populate HP impedance coefficients */ + ret = wm_adsp_hpimp_update(dsp); + if (ret != 0) + goto err; + + dsp->running = true; + + return; + +err: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); +} + +static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq) +{ + int ret; + unsigned int mask, val; + + switch (dsp->rev) { + case 0: + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CLOCKING, + ADSP2_CLK_SEL_MASK, + freq << ADSP2_CLK_SEL_SHIFT); + if (ret != 0) { + adsp_err(dsp, "Failed to set clock rate: %d\n", ret); + return; + } + break; + default: + mutex_lock(&dsp->rate_lock); + + mask = ADSP2V2_RATE_MASK; + val = dsp->rate_cache << ADSP2V2_RATE_SHIFT; + + switch (dsp->rev) { + case 0: + case 1: + /* use legacy frequency registers */ + mask |= ADSP2V2_CLK_SEL_MASK; + val |= (freq << ADSP2V2_CLK_SEL_SHIFT); + break; + default: + /* Configure exact dsp frequency */ + ret = regmap_write(dsp->regmap, + dsp->base + ADSP2V2_CLOCKING, + freq); + if (ret != 0) { + adsp_err(dsp, + "Failed to set DSP freq: %d\n", + ret); + mutex_unlock(&dsp->rate_lock); + return; + } + break; + } + + ret = dsp->rate_put_cb(dsp, mask, val); + if (ret != 0) { + adsp_err(dsp, "Failed to set DSP_CLK rate: %d\n", ret); + mutex_unlock(&dsp->rate_lock); + return; + } + + mutex_unlock(&dsp->rate_lock); + break; + } +} + +int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event, + unsigned int freq) +{ + struct snd_soc_codec *codec = w->codec; + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + + dsp->card = codec->card; + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + wm_adsp2_set_dspclk(dsp, freq); + queue_work(system_unbound_wq, &dsp->boot_work); + break; + default: + break; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_early_event); + +static void wm_adsp_edac_shutdown(struct wm_adsp *dsp) +{ + int i, ret; + unsigned int val = 1; + const struct wm_adsp_region *mem; + + mem = wm_adsp_find_region(dsp, WMFW_ADSP2_YM); + if (!mem) { + adsp_err(dsp, "Failed to locate YM\n"); + return; + } + + ret = regmap_write(dsp->regmap, mem->base + 0x1, val); + if (ret != 0) { + adsp_err(dsp, + "Failed to inform eDAC to shutdown: %d\n", + ret); + return; + } + + for (i = 0; i < 5; ++i) { + ret = regmap_read(dsp->regmap, mem->base + 0x1, &val); + if (ret != 0) { + adsp_err(dsp, + "Failed to check for eDAC shutdown: %d\n", + ret); + return; + } + + if (!val) + break; + + msleep(1); + } + + if (val) + adsp_err(dsp, "Failed to shutdown eDAC firmware\n"); +} + +static inline void wm_adsp_stop_watchdog(struct wm_adsp *dsp) +{ + switch (dsp->rev) { + case 0: + case 1: + return; + default: + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_WATCHDOG, + ADSP2_WDT_ENA_MASK, 0); + } +} + +int wm_adsp2_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = w->codec; + struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); + struct wm_adsp *dsp = &dsps[w->shift]; + struct wm_coeff_ctl *ctl; + int ret; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + flush_work(&dsp->boot_work); + + if (!dsp->running) + return -EIO; + + wm_adsp2_lock(dsp, dsp->lock_regions); + + ret = regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, + ADSP2_CORE_ENA | ADSP2_START); + + if (ret != 0) + goto err; + + if (dsp->fw_features.host_read_buf && + dsp->firmwares[dsp->fw].num_caps != 0) { + ret = wm_adsp_init_host_buf_info(&dsp->compr_buf); + if (ret < 0) { + adsp_err(dsp, + "Failed to init host buffer (%d)\n", + ret); + goto err; + } + } + + break; + + case SND_SOC_DAPM_PRE_PMD: + /* Log firmware state, it can be useful for analysis */ + switch (dsp->rev) { + case 0: + wm_adsp2_show_fw_status(dsp); + break; + default: + wm_adsp2v2_show_fw_status(dsp); + break; + }; + + if (dsp->fw_features.edac_shutdown) + wm_adsp_edac_shutdown(dsp); + else + wm_adsp_signal_event_controls(dsp, + WM_ADSP_FW_EVENT_SHUTDOWN); + + wm_adsp_stop_watchdog(dsp); + + if (dsp->fw_features.host_read_buf) { + adsp_dbg(dsp, "host buf invalidated by DSP shutdown\n"); + wm_adsp_free_host_buf_info(&dsp->compr_buf); + } + + wm_adsp_debugfs_clear(dsp); + + dsp->fw_id = 0; + dsp->fw_id_version = 0; + dsp->running = false; + + switch (dsp->rev) { + case 0: + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, 0); + + /* Make sure DMAs are quiesced */ + regmap_write(dsp->regmap, + dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2_WDMA_CONFIG_2, 0); + + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA, 0); + break; + default: + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_CORE_ENA | ADSP2_START, 0); + + /* Make sure DMAs are quiesced */ + regmap_write(dsp->regmap, + dsp->base + ADSP2_RDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2_WDMA_CONFIG_1, 0); + regmap_write(dsp->regmap, + dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); + + regmap_update_bits(dsp->regmap, + dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA | ADSP2_MEM_ENA, 0); + + break; + } + + list_for_each_entry(ctl, &dsp->ctl_list, list) + ctl->enabled = 0; + + wm_adsp_free_alg_regions(dsp); + + adsp_info(dsp, "Shutdown complete\n"); + break; + + default: + break; + } + + return 0; +err: + regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp2_event); + +#ifdef CONFIG_OF +static int wm_adsp_of_parse_caps(struct wm_adsp *dsp, + struct device_node *np, + struct wm_adsp_fw_defs *fw) +{ + const char *prop = "wlf,compr-caps"; + int i; + int len_prop; + u32 of_cap; + + if (!of_get_property(np, prop, &len_prop)) + return -EINVAL; + + len_prop /= sizeof(u32); + + if (len_prop < 5 || len_prop > 5 + MAX_NUM_SAMPLE_RATES) + return -EOVERFLOW; + + fw->num_caps = 1; + fw->caps = devm_kzalloc(dsp->dev, + sizeof(struct wm_adsp_fw_caps), + GFP_KERNEL); + if (!fw->caps) + return -ENOMEM; + + fw->caps->num_host_regions = ARRAY_SIZE(ez2control_regions); + fw->caps->host_region_defs = + devm_kzalloc(dsp->dev, + sizeof(ez2control_regions), + GFP_KERNEL); + if (!fw->caps->host_region_defs) + return -ENOMEM; + + memcpy(fw->caps->host_region_defs, + ez2control_regions, + sizeof(ez2control_regions)); + + of_property_read_u32_index(np, prop, 0, &of_cap); + fw->caps->id = of_cap; + of_property_read_u32_index(np, prop, 1, &of_cap); + fw->caps->desc.max_ch = of_cap; + of_property_read_u32_index(np, prop, 2, &of_cap); + fw->caps->desc.formats = of_cap; + of_property_read_u32_index(np, prop, 3, &of_cap); + fw->compr_direction = of_cap; + + for (i = 4; i < len_prop; ++i) { + of_property_read_u32_index(np, prop, i, &of_cap); + fw->caps->desc.sample_rates[i - 4] = of_cap; + } + fw->caps->desc.num_sample_rates = i - 4; + + return 0; +} + +static int wm_adsp_of_parse_firmware(struct wm_adsp *dsp, + struct device_node *np) +{ + struct device_node *fws = of_get_child_by_name(np, "firmware"); + struct device_node *fw = NULL; + const char **ctl_names; + int ret; + int i; + + if (!fws) + return 0; + + i = 0; + while ((fw = of_get_next_child(fws, fw)) != NULL) + i++; + + if (i == 0) + return 0; + + dsp->num_firmwares = i; + + dsp->firmwares = devm_kzalloc(dsp->dev, + i * sizeof(struct wm_adsp_fw_defs), + GFP_KERNEL); + if (!dsp->firmwares) + return -ENOMEM; + + ctl_names = devm_kzalloc(dsp->dev, + i * sizeof(const char *), + GFP_KERNEL); + if (!ctl_names) + return -ENOMEM; + + i = 0; + while ((fw = of_get_next_child(fws, fw)) != NULL) { + ctl_names[i] = fw->name; + dsp->firmwares[i].name = fw->name; + + ret = of_property_read_string(fw, "wlf,wmfw-file", + &dsp->firmwares[i].file); + if (ret < 0) { + adsp_err(dsp, + "Firmware filename missing/malformed: %d\n", + ret); + return ret; + } + + ret = of_property_read_string(fw, "wlf,bin-file", + &dsp->firmwares[i].binfile); + if (ret < 0) + dsp->firmwares[i].binfile = NULL; + + wm_adsp_of_parse_caps(dsp, fw, &dsp->firmwares[i]); + + i++; + } + + wm_adsp_fw_enum[dsp->num - 1].max = dsp->num_firmwares; + wm_adsp_fw_enum[dsp->num - 1].texts = ctl_names; + + return dsp->num_firmwares; +} + +static int wm_adsp_of_parse_adsp(struct wm_adsp *dsp) +{ + struct device_node *np = of_get_child_by_name(dsp->dev->of_node, + "adsps"); + struct device_node *core = NULL; + unsigned int addr; + int ret; + + if (!np) + return 0; + + while ((core = of_get_next_child(np, core)) != NULL) { + ret = of_property_read_u32(core, "reg", &addr); + if (ret < 0) { + adsp_err(dsp, + "Failed to get ADSP base address: %d\n", + ret); + return ret; + } + + if (addr == dsp->base) + break; + } + + if (!core) + return 0; + + return wm_adsp_of_parse_firmware(dsp, core); +} +#else +static inline int wm_adsp_of_parse_adsp(struct wm_adsp *dsp) +{ + return 0; +} +#endif + +int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec) +{ + wm_adsp2_init_debugfs(dsp, codec); + + return snd_soc_add_codec_controls(codec, + &wm_adsp_fw_controls[dsp->num - 1], + 1); +} +EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe); + +int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec) +{ + wm_adsp2_cleanup_debugfs(dsp); + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove); + +int wm_adsp2_init(struct wm_adsp *dsp, struct mutex *fw_lock) +{ + int ret, i; + const char **ctl_names; + + switch (dsp->rev) { + case 0: + /* + * Disable the DSP memory by default when in reset for a small + * power saving + */ + ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, + ADSP2_MEM_ENA, 0); + if (ret != 0) { + adsp_err(dsp, "Failed to clear memory retention: %d\n", + ret); + return ret; + } + break; + + default: + break; + } + + INIT_LIST_HEAD(&dsp->alg_regions); + INIT_LIST_HEAD(&dsp->ctl_list); + INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work); + mutex_init(&dsp->ctl_lock); + mutex_init(&dsp->rate_lock); + mutex_init(&dsp->compr_buf.lock); + + dsp->fw_lock = fw_lock; + + dsp->compr_buf.dsp = dsp; + + if (!dsp->num_firmwares) { + if (!dsp->dev->of_node || wm_adsp_of_parse_adsp(dsp) <= 0) { + dsp->num_firmwares = WM_ADSP_NUM_FW; + dsp->firmwares = wm_adsp_fw; + for (i = 0; i < dsp->num_firmwares; i++) + dsp->firmwares[i].name = wm_adsp_fw_text[i]; + } + } else { + ctl_names = devm_kzalloc(dsp->dev, + dsp->num_firmwares * sizeof(const char *), + GFP_KERNEL); + + for (i = 0; i < dsp->num_firmwares; i++) + ctl_names[i] = dsp->firmwares[i].name; + + wm_adsp_fw_enum[dsp->num - 1].max = dsp->num_firmwares; + wm_adsp_fw_enum[dsp->num - 1].texts = ctl_names; + } + +#ifdef CONFIG_DEBUG_FS + mutex_init(&dsp->debugfs_lock); +#endif + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp2_init); + +void wm_adsp2_remove(struct wm_adsp *dsp) +{ + struct wm_coeff_ctl *ctl; + + while (!list_empty(&dsp->ctl_list)) { + ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl, + list); + list_del(&ctl->list); + wm_adsp_free_ctl_blk(ctl); + } + + if (dsp->firmwares != wm_adsp_fw) { + if (wm_adsp_fw_enum[dsp->num - 1].texts != wm_adsp_fw_text) + kfree(wm_adsp_fw_enum[dsp->num - 1].texts); + + kfree(dsp->firmwares); + } +} +EXPORT_SYMBOL_GPL(wm_adsp2_remove); + +static bool wm_adsp_compress_supported(const struct wm_adsp *dsp, + const struct snd_compr_stream *stream) +{ + if (dsp->fw >= 0 && dsp->fw < dsp->num_firmwares) { + const struct wm_adsp_fw_defs *fw_defs = + &dsp->firmwares[dsp->fw]; + + if (fw_defs->num_caps == 0) + return false; + + if (fw_defs->compr_direction == stream->direction) + return true; + } + + return false; +} + +int wm_adsp_compr_open(struct wm_adsp_compr *compr, + struct snd_compr_stream *stream) +{ + if (compr->stream) + return -EBUSY; + + if (!wm_adsp_compress_supported(compr->dsp, stream)) { + adsp_err(compr->dsp, + "Firmware does not support compressed stream\n"); + return -EINVAL; + } + + compr->buf = &compr->dsp->compr_buf; + compr->stream = stream; + stream->runtime->private_data = compr; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_open); + +int wm_adsp_compr_free(struct snd_compr_stream *stream) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp_compr_buf *buf; + + if (!compr) + return -EINVAL; + + /* Take buffer lock to prevent race conditions with the IRQ handler + * while we disconnect the buffer from the stream + */ + if (compr->buf) { + buf = compr->buf; + mutex_lock(&buf->lock); + + compr->buf = NULL; + compr->stream = NULL; + + mutex_unlock(&buf->lock); + } + + compr->copied_total = 0; + compr->sample_rate = 0; + + stream->runtime->private_data = NULL; + + kfree(compr->capt_buf); + compr->capt_buf = NULL; + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_free); + +static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + const struct wm_adsp_fw_caps *caps; + const struct snd_codec_desc *desc; + int i, j; + + if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE || + params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE || + params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS || + params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS || + params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) { + adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n", + params->buffer.fragment_size, + params->buffer.fragments); + return -EINVAL; + } + + for (i = 0; i < dsp->firmwares[dsp->fw].num_caps; i++) { + caps = &dsp->firmwares[dsp->fw].caps[i]; + desc = &caps->desc; + + if (caps->id != params->codec.id) + continue; + + if (stream->direction == SND_COMPRESS_PLAYBACK) { + if (desc->max_ch < params->codec.ch_out) + continue; + } else { + if (desc->max_ch < params->codec.ch_in) + continue; + } + + if (!(desc->formats & (1 << params->codec.format))) + continue; + + for (j = 0; j < desc->num_sample_rates; ++j) + if (desc->sample_rates[j] == params->codec.sample_rate) + return 0; + } + + adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n", + params->codec.id, params->codec.ch_in, params->codec.ch_out, + params->codec.sample_rate, params->codec.format); + + return -EINVAL; +} + +static int wm_adsp_streambuf_alloc(struct wm_adsp_compr *compr, + const struct snd_compr_params *params) +{ + unsigned int size; + + if (params->buffer.fragment_size == 0) + return -EINVAL; + + compr->max_read_words = + params->buffer.fragment_size / WM_ADSP_DATA_WORD_SIZE; + + if (!compr->capt_buf) { + size = compr->max_read_words * sizeof(*compr->capt_buf); + compr->capt_buf = kmalloc(size, GFP_DMA | GFP_KERNEL); + + if (!compr->capt_buf) + return -ENOMEM; + } + + compr->irq_watermark = params->buffer.fragment_size / + WM_ADSP_DATA_WORD_SIZE; + + return 0; +} + +int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + int ret; + + ret = wm_adsp_compr_check_params(stream, params); + if (ret) + return ret; + + ret = wm_adsp_streambuf_alloc(compr, params); + + compr->sample_rate = params->codec.sample_rate; + + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params); + +int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp *dsp = compr->dsp; + int i; + + memset(caps, 0, sizeof(*caps)); + + caps->direction = stream->direction; + caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE; + caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE; + caps->min_fragments = WM_ADSP_MIN_FRAGMENTS; + caps->max_fragments = WM_ADSP_MAX_FRAGMENTS; + + if (dsp->firmwares[dsp->fw].caps) { + for (i = 0; i < dsp->firmwares[dsp->fw].num_caps; i++) + caps->codecs[i] = dsp->firmwares[dsp->fw].caps[i].id; + + caps->num_codecs = i; + caps->direction = dsp->firmwares[dsp->fw].compr_direction; + } + + return 0; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps); + +static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, + unsigned int num_words, + u32 *data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, + mem_type); + unsigned int i, reg; + int ret; + + if (!mem) + return -EINVAL; + + reg = wm_adsp_region_to_reg(mem, mem_addr); + + ret = regmap_raw_read(dsp->regmap, reg, data, + sizeof(*data) * num_words); + if (ret < 0) + return ret; + + for (i = 0; i < num_words; ++i) + data[i] = be32_to_cpu(data[i]) & 0x00ffffffu; + + return 0; +} + +static int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 *data) +{ + return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data); +} + +static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, + unsigned int mem_addr, u32 data) +{ + struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, + mem_type); + unsigned int reg; + + if (!mem) + return -EINVAL; + + reg = wm_adsp_region_to_reg(mem, mem_addr); + + data = cpu_to_be32(data & 0x00ffffffu); + + return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data)); +} + +static inline int wm_adsp_host_buffer_read(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 *data) +{ + lockdep_assert_held(&buf->lock); + + return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM, + buf->host_buf_ptr + + field_offset, + data); +} + +static inline int wm_adsp_host_buffer_write(struct wm_adsp_compr_buf *buf, + unsigned int field_offset, u32 data) +{ + lockdep_assert_held(&buf->lock); + + return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM, + buf->host_buf_ptr + + field_offset, + data); +} + +static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf) +{ + struct wm_adsp_alg_region *alg_region; + struct wm_adsp *dsp = buf->dsp; + u32 xmalg, addr, magic; + int i, ret; + + alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); + xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32); + + addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); + if (ret < 0) + return ret; + + if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC) + return -EINVAL; + + addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); + for (i = 0; i < 5; ++i) { + ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, + &buf->host_buf_ptr); + if (ret < 0) + return ret; + + if (buf->host_buf_ptr) + break; + + msleep(10); + } + + if (!buf->host_buf_ptr) + return -EIO; + + adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr); + + return 0; +} + +static int wm_adsp_populate_buffer_regions(struct wm_adsp_compr_buf *buf) +{ + int i, ret; + u32 offset = 0; + struct wm_adsp *dsp = buf->dsp; + struct wm_adsp_buffer_region_def *host_region_defs = + dsp->firmwares[dsp->fw].caps->host_region_defs; + struct wm_adsp_buffer_region *region; + + lockdep_assert_held(&buf->lock); + + BUG_ON(buf->host_regions != NULL); + + buf->host_regions = + kcalloc(dsp->firmwares[dsp->fw].caps->num_host_regions, + sizeof(*buf->host_regions), + GFP_KERNEL); + + if (!buf->host_regions) + return -ENOMEM; + + for (i = 0; i < dsp->firmwares[dsp->fw].caps->num_host_regions; ++i) { + region = &buf->host_regions[i]; + + region->offset = offset; + region->mem_type = host_region_defs[i].mem_type; + + ret = wm_adsp_host_buffer_read(buf, + host_region_defs[i].base_offset, + ®ion->base_addr); + if (ret < 0) + return ret; + + ret = wm_adsp_host_buffer_read(buf, + host_region_defs[i].size_offset, + &offset); + if (ret < 0) + return ret; + + region->cumulative_size = offset; + + adsp_dbg(dsp, + "Region %d type %d base %04x off %04x size %04x\n", + i, region->mem_type, region->base_addr, + region->offset, region->cumulative_size); + } + + return 0; +} + +static int wm_adsp_init_host_buf_info(struct wm_adsp_compr_buf *buf) +{ + int ret; + + mutex_lock(&buf->lock); + + buf->read_index = -1; + buf->irq_ack = 0xFFFFFFFF; + buf->error = 0; + buf->avail = 0; + + ret = wm_adsp_buffer_locate(buf); + if (ret < 0) { + adsp_err(buf->dsp, "Failed to acquire host buffer: %d\n", ret); + goto out; + } + + ret = wm_adsp_populate_buffer_regions(buf); + if (ret < 0) + adsp_err(buf->dsp, "Failed to populate host buffer: %d\n", ret); + +out: + mutex_unlock(&buf->lock); + + return ret; +} + +static void wm_adsp_free_host_buf_info(struct wm_adsp_compr_buf *buf) +{ + struct wm_adsp_buffer_region *host_regions; + + mutex_lock(&buf->lock); + + host_regions = buf->host_regions; + buf->host_regions = NULL; + buf->host_buf_ptr = 0; + + mutex_unlock(&buf->lock); + + kfree(host_regions); +} + +static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) +{ + const struct wm_adsp *dsp = buf->dsp; + int last_region = dsp->firmwares[dsp->fw].caps->num_host_regions - 1; + + return buf->host_regions[last_region].cumulative_size; +} + +static int wm_adsp_stream_start(struct wm_adsp_compr *compr) +{ + struct wm_adsp_compr_buf *buf = compr->buf; + int ret; + + mutex_lock(&buf->lock); + + if (!buf->host_buf_ptr) { + adsp_warn(buf->dsp, "No host buffer info\n"); + ret = -EIO; + goto out_unlock; + } + + buf->read_index = -1; + buf->avail = 0; + + ret = wm_adsp_host_buffer_write(buf, + HOST_BUFFER_FIELD(high_water_mark), + compr->irq_watermark); + if (ret < 0) + goto out_unlock; + + adsp_dbg(buf->dsp, "Set watermark to %u\n", compr->irq_watermark); + +out_unlock: + mutex_unlock(&buf->lock); + + return ret; +} + +int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + return wm_adsp_stream_start(compr); + case SNDRV_PCM_TRIGGER_STOP: + return 0; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); + +static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf) +{ + u32 next_read_index, next_write_index; + int write_index, read_index, avail; + int ret; + + lockdep_assert_held(&buf->lock); + + /* Only sync the read index if we haven't already read a valid index */ + if (buf->read_index < 0) { + ret = wm_adsp_host_buffer_read(buf, + HOST_BUFFER_FIELD(next_read_index), + &next_read_index); + if (ret < 0) + return ret; + + read_index = sign_extend32(next_read_index, 23); + + if (read_index < 0) { + adsp_dbg(buf->dsp, "Avail check on unstarted stream\n"); + return 0; + } + + buf->read_index = read_index; + } + + ret = wm_adsp_host_buffer_read(buf, + HOST_BUFFER_FIELD(next_write_index), + &next_write_index); + if (ret < 0) + return ret; + + write_index = sign_extend32(next_write_index, 23); + + avail = write_index - buf->read_index; + if (avail < 0) + avail += wm_adsp_buffer_size(buf); + + adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n", + buf->read_index, write_index, avail); + + buf->avail = avail; + + return 0; +} + +static int wm_adsp_buffer_has_error_locked(struct wm_adsp_compr_buf *buf) +{ + int ret; + + lockdep_assert_held(&buf->lock); + + if (buf->error != 0) + return -EIO; + + ret = wm_adsp_host_buffer_read(buf, + HOST_BUFFER_FIELD(error), + &buf->error); + if (ret < 0) { + adsp_err(buf->dsp, "Failed to read error field: %d\n", ret); + return ret; + } - case WMFW_ADSP1_DM: - case WMFW_ADSP1_ZM: - case WMFW_ADSP2_XM: - case WMFW_ADSP2_YM: - adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", - file, blocks, le32_to_cpu(blk->len), - type, le32_to_cpu(blk->id)); + if (buf->error != 0) { + /* log the first time we see the error */ + adsp_warn(buf->dsp, "DSP stream error occurred: %d\n", + buf->error); + return -EIO; + } - mem = wm_adsp_find_region(dsp, type); - if (!mem) { - adsp_err(dsp, "No base for region %x\n", type); - break; - } + return 0; +} - reg = 0; - list_for_each_entry(alg_region, - &dsp->alg_regions, list) { - if (le32_to_cpu(blk->id) == alg_region->alg && - type == alg_region->type) { - reg = alg_region->base; - reg = wm_adsp_region_to_reg(mem, - reg); - reg += offset; - } - } +int wm_adsp_compr_irq(struct wm_adsp_compr *compr, bool *trigger) +{ + struct wm_adsp_compr_buf *buf = &compr->dsp->compr_buf; + int ret; - if (reg == 0) - adsp_err(dsp, "No %x for algorithm %x\n", - type, le32_to_cpu(blk->id)); - break; + if (!buf) + return -ENODEV; - default: - adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", - file, blocks, type, pos); - break; - } + mutex_lock(&buf->lock); - if (reg) { - buf = wm_adsp_buf_alloc(blk->data, - le32_to_cpu(blk->len), - &buf_list); - if (!buf) { - adsp_err(dsp, "Out of memory\n"); - ret = -ENOMEM; - goto out_fw; - } + if (!buf->host_buf_ptr) { + adsp_warn(buf->dsp, "No host buffer info\n"); + ret = -EIO; + goto out_buf_unlock; + } - adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", - file, blocks, le32_to_cpu(blk->len), - reg); - ret = regmap_raw_write_async(regmap, reg, buf->buf, - le32_to_cpu(blk->len)); - if (ret != 0) { - adsp_err(dsp, - "%s.%d: Failed to write to %x in %s\n", - file, blocks, reg, region_name); - } - } + ret = wm_adsp_buffer_has_error_locked(buf); + if (ret) + goto out_notify; /* Wake the poll to report error */ - tmp = le32_to_cpu(blk->len) % 4; - if (tmp) - pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk); - else - pos += le32_to_cpu(blk->len) + sizeof(*blk); + ret = wm_adsp_host_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), + &buf->irq_ack); + if (ret < 0) { + adsp_err(buf->dsp, "Failed to get irq_count: %d\n", ret); + goto out_buf_unlock; + } - blocks++; + if (trigger) { + /* irq_count = 2 only on the initial trigger */ + if (buf->irq_ack == 2) + *trigger = true; + else + *trigger = false; } - ret = regmap_async_complete(regmap); - if (ret != 0) - adsp_err(dsp, "Failed to complete async write: %d\n", ret); + /* Fetch read_index and update count of available data */ + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + adsp_err(buf->dsp, "Error reading read_index: %d\n", ret); + goto out_buf_unlock; + } - if (pos > firmware->size) - adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", - file, blocks, pos - firmware->size); +out_notify: + if (compr->stream) + snd_compr_fragment_elapsed(compr->stream); -out_fw: - regmap_async_complete(regmap); - release_firmware(firmware); - wm_adsp_buf_free(&buf_list); -out: - kfree(file); +out_buf_unlock: + mutex_unlock(&buf->lock); return ret; } +EXPORT_SYMBOL_GPL(wm_adsp_compr_irq); -int wm_adsp1_init(struct wm_adsp *adsp) +static int wm_adsp_buffer_ack_irq(struct wm_adsp_compr_buf *buf) { - INIT_LIST_HEAD(&adsp->alg_regions); + if (buf->irq_ack & 0x01) + return 0; - return 0; + adsp_dbg(buf->dsp, "Acking buffer IRQ(0x%x)\n", buf->irq_ack); + + buf->irq_ack |= 0x01; + + return wm_adsp_host_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack), + buf->irq_ack); } -EXPORT_SYMBOL_GPL(wm_adsp1_init); -int wm_adsp1_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) +int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp) { - struct snd_soc_codec *codec = w->codec; - struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); - struct wm_adsp *dsp = &dsps[w->shift]; - int ret; - int val; - - switch (event) { - case SND_SOC_DAPM_POST_PMU: - regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, - ADSP1_SYS_ENA, ADSP1_SYS_ENA); + struct wm_adsp_compr *compr = stream->runtime->private_data; + struct wm_adsp_compr_buf *buf = compr->buf; + int ret = 0; - /* - * For simplicity set the DSP clock rate to be the - * SYSCLK rate rather than making it configurable. - */ - if(dsp->sysclk_reg) { - ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); - if (ret != 0) { - adsp_err(dsp, "Failed to read SYSCLK state: %d\n", - ret); - return ret; - } + mutex_lock(&buf->lock); - val = (val & dsp->sysclk_mask) - >> dsp->sysclk_shift; + tstamp->copied_total = compr->copied_total; + tstamp->sampling_rate = compr->sample_rate; - ret = regmap_update_bits(dsp->regmap, - dsp->base + ADSP1_CONTROL_31, - ADSP1_CLK_SEL_MASK, val); - if (ret != 0) { - adsp_err(dsp, "Failed to set clock rate: %d\n", - ret); - return ret; - } - } + if (!buf->host_buf_ptr) { + adsp_warn(buf->dsp, "No host buffer info\n"); + ret = -EIO; + goto out_buf_unlock; + } - ret = wm_adsp_load(dsp); - if (ret != 0) - goto err; + ret = wm_adsp_buffer_has_error_locked(buf); + if (ret) + goto out_buf_unlock; - ret = wm_adsp_setup_algs(dsp); - if (ret != 0) - goto err; + if (buf->avail < compr->max_read_words) { + ret = wm_adsp_buffer_update_avail(buf); + if (ret < 0) { + adsp_err(compr->dsp, "Error reading avail: %d\n", ret); + goto out_buf_unlock; + } - ret = wm_adsp_load_coeff(dsp); - if (ret != 0) - goto err; + /* + * If we really have less than 1 fragment available ack the + * last DSP IRQ and rely on the IRQ to inform us when a whole + * fragment is available. + */ + if (buf->avail < compr->max_read_words) { + ret = wm_adsp_buffer_ack_irq(buf); + if (ret < 0) { + adsp_err(compr->dsp, + "Failed to ack buffer IRQ: %d\n", ret); + goto out_buf_unlock; + } + } + } - /* Start the core running */ - regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, - ADSP1_CORE_ENA | ADSP1_START, - ADSP1_CORE_ENA | ADSP1_START); - break; + tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE; - case SND_SOC_DAPM_PRE_PMD: - /* Halt the core */ - regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, - ADSP1_CORE_ENA | ADSP1_START, 0); + adsp_dbg(compr->dsp, "tstamp->copied_total=%d (avail=%d)\n", + tstamp->copied_total, buf->avail); - regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, - ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); + mutex_unlock(&buf->lock); - regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, - ADSP1_SYS_ENA, 0); - break; + return ret; - default: - break; - } +out_buf_unlock: + /* Get user-space to issue a read so it can detect the error */ + tstamp->copied_total += compr->irq_watermark * WM_ADSP_DATA_WORD_SIZE; - return 0; + mutex_unlock(&buf->lock); -err: - regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, - ADSP1_SYS_ENA, 0); return ret; } -EXPORT_SYMBOL_GPL(wm_adsp1_event); +EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); -static int wm_adsp2_ena(struct wm_adsp *dsp) +static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) { - unsigned int val; - int ret, count; + struct wm_adsp_compr_buf *buf = compr->buf; + struct wm_adsp *dsp = buf->dsp; + const struct wm_adsp_buffer_region *host_regions = buf->host_regions; + int num_regions = dsp->firmwares[dsp->fw].caps->num_host_regions; + u8 *pack_in = (u8 *)compr->capt_buf; + u8 *pack_out = (u8 *)compr->capt_buf; + unsigned int adsp_addr; + int mem_type, nwords; + int i, j, ret; + + lockdep_assert_held(&buf->lock); + BUG_ON(!buf->host_regions); + + /* Calculate read parameters */ + for (i = 0; i < num_regions; ++i) + if (buf->read_index < host_regions[i].cumulative_size) + break; - ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, - ADSP2_SYS_ENA, ADSP2_SYS_ENA); - if (ret != 0) - return ret; + if (i == num_regions) + return -EINVAL; - /* Wait for the RAM to start, should be near instantaneous */ - for (count = 0; count < 10; ++count) { - ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, - &val); - if (ret != 0) - return ret; + mem_type = host_regions[i].mem_type; + adsp_addr = host_regions[i].base_addr + + (buf->read_index - host_regions[i].offset); - if (val & ADSP2_RAM_RDY) - break; + nwords = host_regions[i].cumulative_size - buf->read_index; - msleep(1); - } + if (nwords > target) + nwords = target; + if (nwords > buf->avail) + nwords = buf->avail; + if (nwords > compr->max_read_words) + nwords = compr->max_read_words; + if (!nwords) + return 0; - if (!(val & ADSP2_RAM_RDY)) { - adsp_err(dsp, "Failed to start DSP RAM\n"); - return -EBUSY; + /* Read data from DSP */ + ret = wm_adsp_read_data_block(dsp, mem_type, adsp_addr, + nwords, compr->capt_buf); + if (ret < 0) + return ret; + + /* Remove the padding bytes from the data read from the DSP */ + for (i = 0; i < nwords; i++) { + for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++) + *pack_out++ = *pack_in++; + + pack_in += sizeof(*(compr->capt_buf)) - WM_ADSP_DATA_WORD_SIZE; } - adsp_dbg(dsp, "RAM ready after %d polls\n", count); - adsp_info(dsp, "RAM ready after %d polls\n", count); + /* update read index to account for words read */ + buf->read_index += nwords; + if (buf->read_index == wm_adsp_buffer_size(buf)) + buf->read_index = 0; - return 0; + ret = wm_adsp_host_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index), + buf->read_index); + if (ret < 0) + return ret; + + /* update avail to account for words read */ + buf->avail -= nwords; + + return nwords; } -int wm_adsp2_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) +static int wm_adsp_compr_read(struct wm_adsp_compr *compr, + char __user *buf, size_t count) { - struct snd_soc_codec *codec = w->codec; - struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); - struct wm_adsp *dsp = &dsps[w->shift]; - struct wm_adsp_alg_region *alg_region; - unsigned int val; + struct wm_adsp *dsp = compr->dsp; + int ntotal = 0; + int nwords, nbytes; int ret; - switch (event) { - case SND_SOC_DAPM_POST_PMU: - /* - * For simplicity set the DSP clock rate to be the - * SYSCLK rate rather than making it configurable. - */ - ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val); - if (ret != 0) { - adsp_err(dsp, "Failed to read SYSCLK state: %d\n", - ret); - return ret; - } - val = (val & ARIZONA_SYSCLK_FREQ_MASK) - >> ARIZONA_SYSCLK_FREQ_SHIFT; + lockdep_assert_held(&compr->buf->lock); + BUG_ON(!compr->buf->host_regions); - ret = regmap_update_bits(dsp->regmap, - dsp->base + ADSP2_CLOCKING, - ADSP2_CLK_SEL_MASK, val); - if (ret != 0) { - adsp_err(dsp, "Failed to set clock rate: %d\n", - ret); - return ret; + adsp_dbg(dsp, "Requested read of %zu bytes\n", count); + + ret = wm_adsp_buffer_has_error_locked(compr->buf); + if (ret) + return ret; + + count /= WM_ADSP_DATA_WORD_SIZE; + + do { + nwords = wm_adsp_buffer_capture_block(compr, count); + if (nwords < 0) { + adsp_err(dsp, "Failed to capture block: %d\n", nwords); + return nwords; } - if (dsp->dvfs) { - ret = regmap_read(dsp->regmap, - dsp->base + ADSP2_CLOCKING, &val); - if (ret != 0) { - dev_err(dsp->dev, - "Failed to read clocking: %d\n", ret); - return ret; - } + nbytes = nwords * WM_ADSP_DATA_WORD_SIZE; - if ((val & ADSP2_CLK_SEL_MASK) >= 3) { - ret = regulator_enable(dsp->dvfs); - if (ret != 0) { - dev_err(dsp->dev, - "Failed to enable supply: %d\n", - ret); - return ret; - } + adsp_dbg(dsp, "Read %d bytes\n", nbytes); - ret = regulator_set_voltage(dsp->dvfs, - 1800000, - 1800000); - if (ret != 0) { - dev_err(dsp->dev, - "Failed to raise supply: %d\n", - ret); - return ret; - } - } + if (copy_to_user(buf + ntotal, compr->capt_buf, nbytes)) { + adsp_err(dsp, "Failed to copy data to user: %d, %d\n", + ntotal, nbytes); + return -EFAULT; } - ret = wm_adsp2_ena(dsp); - if (ret != 0) - return ret; + count -= nwords; + ntotal += nbytes; + } while (nwords > 0 && count > 0); - ret = wm_adsp_load(dsp); - if (ret != 0) - goto err; + compr->copied_total += ntotal; - ret = wm_adsp_setup_algs(dsp); - if (ret != 0) - goto err; + return ntotal; +} - ret = wm_adsp_load_coeff(dsp); - if (ret != 0) - goto err; +int wm_adsp_compr_copy(struct snd_compr_stream *stream, + char __user *buf, size_t count) +{ + struct wm_adsp_compr *compr = stream->runtime->private_data; + int ret; - ret = regmap_update_bits(dsp->regmap, - dsp->base + ADSP2_CONTROL, - ADSP2_CORE_ENA | ADSP2_START, - ADSP2_CORE_ENA | ADSP2_START); - if (ret != 0) - goto err; + mutex_lock(&compr->buf->lock); - dsp->running = true; - break; - case SND_SOC_DAPM_PRE_PMD: - dsp->running = false; + if (!compr->buf->host_buf_ptr) { + adsp_warn(compr->buf->dsp, "No host buffer info\n"); + ret = -EIO; + goto out_buf_unlock; + } - regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, - ADSP2_SYS_ENA | ADSP2_CORE_ENA | - ADSP2_START, 0); + if (stream->direction == SND_COMPRESS_CAPTURE) + ret = wm_adsp_compr_read(compr, buf, count); + else + ret = -ENOTSUPP; - /* Make sure DMAs are quiesced */ - regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); - regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); - regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); +out_buf_unlock: + mutex_unlock(&compr->buf->lock); - if (dsp->dvfs) { - ret = regulator_set_voltage(dsp->dvfs, 1200000, - 1800000); - if (ret != 0) - dev_warn(dsp->dev, - "Failed to lower supply: %d\n", - ret); + return ret; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_copy); - ret = regulator_disable(dsp->dvfs); - if (ret != 0) - dev_err(dsp->dev, - "Failed to enable supply: %d\n", - ret); - } +void wm_adsp_compr_init(struct wm_adsp *dsp, struct wm_adsp_compr *compr) +{ + compr->dsp = dsp; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_init); - while (!list_empty(&dsp->alg_regions)) { - alg_region = list_first_entry(&dsp->alg_regions, - struct wm_adsp_alg_region, - list); - list_del(&alg_region->list); - kfree(alg_region); - } - break; +void wm_adsp_compr_destroy(struct wm_adsp_compr *compr) +{ + if (!compr->dsp) + return; +} +EXPORT_SYMBOL_GPL(wm_adsp_compr_destroy); - default: - break; + +/* DSP lock region support */ +int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions) +{ + struct regmap *regmap_32bit = dsp->regmap; + unsigned int lockcode0, lockcode1, lock_reg; + + if (!(lock_regions & WM_ADSP2_REGION_ALL)) + return 0; + + lock_regions &= WM_ADSP2_REGION_ALL; + lock_reg = dsp->base + + ADSP2_LOCK_REGION_1_LOCK_REGION_0; + + while (lock_regions) { + lockcode0 = lockcode1 = 0; + if (lock_regions & BIT(0)) { + lockcode0 = ADSP2_LOCK_CODE_0; + lockcode1 = ADSP2_LOCK_CODE_1; + } + if (lock_regions & BIT(1)) { + lockcode0 |= ADSP2_LOCK_CODE_0 << + ADSP2_LOCK_REGION_SHIFT; + lockcode1 |= ADSP2_LOCK_CODE_1 << + ADSP2_LOCK_REGION_SHIFT; + } + regmap_write(regmap_32bit, + lock_reg, lockcode0); + regmap_write(regmap_32bit, + lock_reg, lockcode1); + lock_regions >>= 2; + lock_reg += 2; } return 0; -err: - regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, - ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); - return ret; } -EXPORT_SYMBOL_GPL(wm_adsp2_event); +EXPORT_SYMBOL_GPL(wm_adsp2_lock); -int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs) +irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) { - int ret; + unsigned int reg_val; + int ret = 0; + struct regmap *regmap = dsp->regmap; - /* - * Disable the DSP memory by default when in reset for a small - * power saving. - */ - ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL, - ADSP2_MEM_ENA, 0); + ret = regmap_read(regmap, dsp->base + + ADSP2_LOCK_REGION_CTRL, ®_val); if (ret != 0) { - adsp_err(adsp, "Failed to clear memory retention: %d\n", ret); - return ret; + adsp_err(dsp, + "Failed to read Region Lock Ctrl register: %d\n", + ret); + goto exit; } - INIT_LIST_HEAD(&adsp->alg_regions); - - if (dvfs) { - adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD"); - if (IS_ERR(adsp->dvfs)) { - ret = PTR_ERR(adsp->dvfs); - dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret); - return ret; - } + if (reg_val & ADSP2_WDT_TIMEOUT_STS_MASK) { + adsp_err(dsp, "watchdog timeout error\n"); + wm_adsp_stop_watchdog(dsp); + } - ret = regulator_enable(adsp->dvfs); - if (ret != 0) { - dev_err(adsp->dev, "Failed to enable DCVDD: %d\n", - ret); - return ret; - } + if (reg_val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { + if (reg_val & ADSP2_SLAVE_ERR_MASK) + adsp_err(dsp, "bus error: slave error\n"); + else + adsp_err(dsp, "bus error: region lock error\n"); - ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000); + ret = regmap_read(regmap, dsp->base + + ADSP2_BUS_ERR_ADDR, ®_val); if (ret != 0) { - dev_err(adsp->dev, "Failed to initialise DVFS: %d\n", + adsp_err(dsp, + "Failed to read Bus Err Addr register: %d\n", ret); - return ret; + goto exit; } + adsp_err(dsp, "bus error address = 0x%x\n", + (reg_val & ADSP2_BUS_ERR_ADDR_MASK)); - ret = regulator_disable(adsp->dvfs); + ret = regmap_read(regmap, dsp->base + + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, + ®_val); if (ret != 0) { - dev_err(adsp->dev, "Failed to disable DCVDD: %d\n", + adsp_err(dsp, + "Failed to read Pmem Xmem Err Addr register: %d\n", ret); - return ret; + goto exit; } + adsp_err(dsp, "xmem error address = 0x%x\n", + (reg_val & ADSP2_XMEM_ERR_ADDR_MASK)); + adsp_err(dsp, "pmem error address = 0x%x\n", + (reg_val & ADSP2_PMEM_ERR_ADDR_MASK) + >> ADSP2_PMEM_ERR_ADDR_SHIFT); } - return 0; + regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, + ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); +exit: + return IRQ_HANDLED; } -EXPORT_SYMBOL_GPL(wm_adsp2_init); - +EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h index fea51462752..351b491eb5c 100644 --- a/sound/soc/codecs/wm_adsp.h +++ b/sound/soc/codecs/wm_adsp.h @@ -13,12 +13,33 @@ #ifndef __WM_ADSP_H #define __WM_ADSP_H +#include #include #include +#include #include "wmfw.h" -struct regulator; +#define WM_ADSP2_REGION_0 BIT(0) +#define WM_ADSP2_REGION_1 BIT(1) +#define WM_ADSP2_REGION_2 BIT(2) +#define WM_ADSP2_REGION_3 BIT(3) +#define WM_ADSP2_REGION_4 BIT(4) +#define WM_ADSP2_REGION_5 BIT(5) +#define WM_ADSP2_REGION_6 BIT(6) +#define WM_ADSP2_REGION_7 BIT(7) +#define WM_ADSP2_REGION_8 BIT(8) +#define WM_ADSP2_REGION_9 BIT(9) +#define WM_ADSP2_REGION_1_3 (WM_ADSP2_REGION_1 | \ + WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3) +#define WM_ADSP2_REGION_1_9 (WM_ADSP2_REGION_1 | \ + WM_ADSP2_REGION_2 | WM_ADSP2_REGION_3 | \ + WM_ADSP2_REGION_4 | WM_ADSP2_REGION_5 | \ + WM_ADSP2_REGION_6 | WM_ADSP2_REGION_7 | \ + WM_ADSP2_REGION_8 | WM_ADSP2_REGION_9) +#define WM_ADSP2_REGION_ALL (WM_ADSP2_REGION_0 | WM_ADSP2_REGION_1_9) + +struct wm_adsp; struct wm_adsp_region { int type; @@ -32,49 +53,178 @@ struct wm_adsp_alg_region { unsigned int base; }; +struct wm_adsp_buffer_region { + unsigned int offset; + unsigned int cumulative_size; + unsigned int mem_type; + unsigned int base_addr; +}; + +struct wm_adsp_buffer_region_def { + unsigned int mem_type; + unsigned int base_offset; + unsigned int size_offset; +}; + +struct wm_adsp_fw_caps { + u32 id; + struct snd_codec_desc desc; + int num_host_regions; + struct wm_adsp_buffer_region_def *host_region_defs; +}; + +struct wm_adsp_fw_defs { + const char *name; + const char *file; + const char *binfile; + int compr_direction; + int num_caps; + struct wm_adsp_fw_caps *caps; +}; + +struct wm_adsp_fw_features { + bool edac_shutdown:1; + bool ez2control_trigger:1; + bool host_read_buf:1; +}; + +struct wm_adsp_compr_buf { + struct mutex lock; + struct wm_adsp *dsp; + struct wm_adsp_buffer_region *host_regions; + u32 host_buf_ptr; + u32 error; + u32 irq_ack; + int read_index; + int avail; +}; + +struct wm_adsp_compr { + struct wm_adsp *dsp; + struct wm_adsp_compr_buf *buf; + + u32 *capt_buf; + + u32 irq_watermark; + int max_read_words; + + size_t copied_total; + + struct snd_compr_stream *stream; + + unsigned int sample_rate; +}; + struct wm_adsp { const char *part; + char part_rev; int num; int type; + int rev; struct device *dev; struct regmap *regmap; + struct snd_soc_card *card; int base; int sysclk_reg; int sysclk_mask; int sysclk_shift; + unsigned int rate_cache; + struct mutex rate_lock; + int (*rate_put_cb) (struct wm_adsp *adsp, unsigned int mask, + unsigned int val); + struct list_head alg_regions; int fw_id; + int fw_id_version; const struct wm_adsp_region *mem; int num_mems; int fw; - bool running; + int fw_ver; + u32 running; + + struct mutex ctl_lock; + struct list_head ctl_list; + + struct wm_adsp_compr_buf compr_buf; + + int num_firmwares; + struct wm_adsp_fw_defs *firmwares; - struct regulator *dvfs; + struct wm_adsp_fw_features fw_features; + + struct mutex *fw_lock; + struct work_struct boot_work; + + unsigned int lock_regions; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_root; + struct mutex debugfs_lock; + char *wmfw_file_name; + char *bin_file_name; +#endif + + unsigned int (*hpimp_cb)(struct device *dev); }; #define WM_ADSP1(wname, num) \ { .id = snd_soc_dapm_pga, .name = wname, .reg = SND_SOC_NOPM, \ .shift = num, .event = wm_adsp1_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD } + +#define WM_ADSP2(wname, num, event_fn) \ +{ .id = snd_soc_dapm_dai_link, .name = wname " Preloader", \ + .reg = SND_SOC_NOPM, .shift = num, .event = event_fn, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD }, \ +{ .id = snd_soc_dapm_out_drv, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = num, .event = wm_adsp2_event, \ .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } -#define WM_ADSP2(wname, num) \ -{ .id = snd_soc_dapm_pga, .name = wname, .reg = SND_SOC_NOPM, \ - .shift = num, .event = wm_adsp2_event, \ - .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } - -extern const struct snd_kcontrol_new wm_adsp1_fw_controls[]; -extern const struct snd_kcontrol_new wm_adsp2_fw_controls[]; +extern const struct snd_kcontrol_new wm_adsp_fw_controls[]; -int wm_adsp1_init(struct wm_adsp *adsp); -int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs); +int wm_adsp1_init(struct wm_adsp *dsp); +int wm_adsp2_init(struct wm_adsp *dsp, struct mutex *fw_lock); +void wm_adsp2_remove(struct wm_adsp *dsp); +int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec); +int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec); int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); + +int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event, + unsigned int freq); + +int wm_adsp2_lock(struct wm_adsp *adsp, unsigned int regions); +irqreturn_t wm_adsp2_bus_error(struct wm_adsp *adsp); + int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event); +static inline bool wm_adsp_fw_has_voice_trig(const struct wm_adsp *dsp) +{ + return dsp->fw_features.ez2control_trigger; +} + +extern int wm_adsp_compr_irq(struct wm_adsp_compr *compr, bool *trigger); +extern int wm_adsp_compr_open(struct wm_adsp_compr *compr, + struct snd_compr_stream *stream); +extern int wm_adsp_compr_free(struct snd_compr_stream *stream); +extern int wm_adsp_compr_set_params(struct snd_compr_stream *stream, + struct snd_compr_params *params); +extern int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, + struct snd_compr_caps *caps); +extern int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd); +extern int wm_adsp_compr_pointer(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); +extern int wm_adsp_compr_copy(struct snd_compr_stream *stream, + char __user *buf, size_t count); +extern void wm_adsp_compr_init(struct wm_adsp *dsp, struct wm_adsp_compr *compr); +extern void wm_adsp_compr_destroy(struct wm_adsp_compr *compr); + #endif + diff --git a/sound/soc/codecs/wmfw.h b/sound/soc/codecs/wmfw.h index ef163360a74..2b14800d109 100644 --- a/sound/soc/codecs/wmfw.h +++ b/sound/soc/codecs/wmfw.h @@ -15,6 +15,24 @@ #include +#define WMFW_MAX_ALG_NAME 256 +#define WMFW_MAX_ALG_DESCR_NAME 256 + +#define WMFW_MAX_COEFF_NAME 256 +#define WMFW_MAX_COEFF_DESCR_NAME 256 + +#define WMFW_CTL_FLAG_SYS 0x8000 +#define WMFW_CTL_FLAG_VOLATILE 0x0004 +#define WMFW_CTL_FLAG_WRITEABLE 0x0002 +#define WMFW_CTL_FLAG_READABLE 0x0001 + +/* Non-ALSA coefficient types start at 0x1000 */ +#define WMFW_CTL_TYPE_ACKED 0x1000 /* acked control */ +#define WMFW_CTL_TYPE_HOSTEVENT 0x1001 /* event control */ +#define WMFW_CTL_TYPE_HP_IMP 0x1003 /* headphone impedance */ + +#define WMFW_CTL_HP_IMP_LEN 4 + struct wmfw_header { char magic[4]; __le32 len; @@ -61,7 +79,7 @@ struct wmfw_adsp1_id_hdr { struct wmfw_id_hdr fw; __be32 zm; __be32 dm; - __be32 algs; + __be32 n_algs; } __packed; struct wmfw_adsp2_id_hdr { @@ -69,7 +87,7 @@ struct wmfw_adsp2_id_hdr { __be32 zm; __be32 xm; __be32 ym; - __be32 algs; + __be32 n_algs; } __packed; struct wmfw_alg_hdr { @@ -90,6 +108,28 @@ struct wmfw_adsp2_alg_hdr { __be32 ym; } __packed; +struct wmfw_adsp_alg_data { + __le32 id; + u8 name[WMFW_MAX_ALG_NAME]; + u8 descr[WMFW_MAX_ALG_DESCR_NAME]; + __le32 ncoeff; + u8 data[]; +} __packed; + +struct wmfw_adsp_coeff_data { + struct { + __le16 offset; + __le16 type; + __le32 size; + } hdr; + u8 name[WMFW_MAX_COEFF_NAME]; + u8 descr[WMFW_MAX_COEFF_DESCR_NAME]; + __le16 ctl_type; + __le16 flags; + __le32 len; + u8 data[]; +} __packed; + struct wmfw_coeff_hdr { u8 magic[4]; __le32 len; @@ -117,9 +157,10 @@ struct wmfw_coeff_item { #define WMFW_ADSP1 1 #define WMFW_ADSP2 2 -#define WMFW_ABSOLUTE 0xf0 -#define WMFW_NAME_TEXT 0xfe -#define WMFW_INFO_TEXT 0xff +#define WMFW_ABSOLUTE 0xf0 +#define WMFW_ALGORITHM_DATA 0xf2 +#define WMFW_NAME_TEXT 0xfe +#define WMFW_INFO_TEXT 0xff #define WMFW_ADSP1_PM 2 #define WMFW_ADSP1_DM 3 diff --git a/sound/soc/codecs/wsa881x-regmap.c b/sound/soc/codecs/wsa881x-regmap.c index 03c508b0f34..5c87f7fd264 100644 --- a/sound/soc/codecs/wsa881x-regmap.c +++ b/sound/soc/codecs/wsa881x-regmap.c @@ -155,7 +155,7 @@ static struct reg_default wsa881x_defaults[] = { }; /* Default register reset values for WSA881x rev 1.0 or 1.1 */ -static struct reg_default wsa881x_rev_1_x[] = { +static struct reg_sequence wsa881x_rev_1_x[] = { {WSA881X_INTR_MASK, 0x1F}, {WSA881X_OTP_REG_28, 0xFF}, {WSA881X_OTP_REG_29, 0xFF}, @@ -179,7 +179,7 @@ static struct reg_default wsa881x_rev_1_x[] = { }; /* Default register reset values for WSA881x rev 2.0 */ -static struct reg_default wsa881x_rev_2_0[] = { +static struct reg_sequence wsa881x_rev_2_0[] = { {WSA881X_RESET_CTL, 0x00}, {WSA881X_TADC_VALUE_CTL, 0x01}, {WSA881X_INTR_MASK, 0x1B}, diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c index ea9e5f0d40b..b4cab8578bd 100644 --- a/sound/soc/codecs/wsa881x.c +++ b/sound/soc/codecs/wsa881x.c @@ -402,7 +402,7 @@ static const struct file_operations codec_debug_ops = { .read = codec_debug_read, }; -static const struct reg_default wsa881x_pre_pmu_pa[] = { +static const struct reg_sequence wsa881x_pre_pmu_pa[] = { {WSA881X_SPKR_DRV_GAIN, 0x41}, {WSA881X_SPKR_MISC_CTL1, 0x01}, {WSA881X_ADC_EN_DET_TEST_I, 0x01}, @@ -411,25 +411,25 @@ static const struct reg_default wsa881x_pre_pmu_pa[] = { {WSA881X_SPKR_PWRSTG_DBG, 0xA0}, }; -static const struct reg_default wsa881x_pre_pmu_pa_2_0[] = { +static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = { {WSA881X_SPKR_DRV_GAIN, 0x41}, {WSA881X_SPKR_MISC_CTL1, 0x87}, }; -static const struct reg_default wsa881x_post_pmu_pa[] = { +static const struct reg_sequence wsa881x_post_pmu_pa[] = { {WSA881X_SPKR_PWRSTG_DBG, 0x00}, {WSA881X_ADC_EN_DET_TEST_V, 0x00}, {WSA881X_ADC_EN_MODU_V, 0x00}, {WSA881X_ADC_EN_DET_TEST_I, 0x00}, }; -static const struct reg_default wsa881x_vi_txfe_en[] = { +static const struct reg_sequence wsa881x_vi_txfe_en[] = { {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85}, {WSA881X_SPKR_PROT_ATEST2, 0x0A}, {WSA881X_SPKR_PROT_FE_GAIN, 0xCF}, }; -static const struct reg_default wsa881x_vi_txfe_en_2_0[] = { +static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = { {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85}, {WSA881X_SPKR_PROT_ATEST2, 0x0A}, {WSA881X_SPKR_PROT_FE_GAIN, 0xCF}, diff --git a/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c index 39b7c03288c..3791d41e9f0 100644 --- a/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c @@ -2094,7 +2094,7 @@ static int msm_compr_get_codec_caps(struct snd_compr_stream *cstream, case SND_AUDIOCODEC_MP3: codec->num_descriptors = 2; codec->descriptor[0].max_ch = 2; - codec->descriptor[0].sample_rates = SNDRV_PCM_RATE_8000_48000; + codec->descriptor[0].sample_rates[0] = SNDRV_PCM_RATE_8000_48000; codec->descriptor[0].bit_rate[0] = 320; /* 320kbps */ codec->descriptor[0].bit_rate[1] = 128; codec->descriptor[0].num_bitrates = 2; @@ -2105,7 +2105,7 @@ static int msm_compr_get_codec_caps(struct snd_compr_stream *cstream, case SND_AUDIOCODEC_AAC: codec->num_descriptors = 2; codec->descriptor[1].max_ch = 2; - codec->descriptor[1].sample_rates = SNDRV_PCM_RATE_8000_48000; + codec->descriptor[1].sample_rates[0] = SNDRV_PCM_RATE_8000_48000; codec->descriptor[1].bit_rate[0] = 320; /* 320kbps */ codec->descriptor[1].bit_rate[1] = 128; codec->descriptor[1].num_bitrates = 2; diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c index caca6fcc913..4833edabe46 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c @@ -530,6 +530,15 @@ static int soc_ac97_dev_register(struct snd_soc_codec *codec) } #endif +static void codec2codec_close_delayed_work(struct work_struct *work) +{ + /* Currently nothing to do for c2c links + * Since c2c links are internal nodes in the DAPM graph and + * don't interface with the outside world or application layer + * we don't have to do any special handling on close. + */ +} + #ifdef CONFIG_PM_SLEEP /* powers down audio subsystem for suspend */ int snd_soc_suspend(struct device *dev) @@ -1160,7 +1169,8 @@ static int soc_probe_platform(struct snd_soc_card *card, /* Create DAPM widgets for each DAI stream */ list_for_each_entry(dai, &dai_list, list) { - if (dai->dev != platform->dev) + if (dai->dev != platform->dev || + dai->playback_widget || dai->capture_widget) continue; snd_soc_dapm_new_dai_widgets(&platform->dapm, dai); @@ -1429,6 +1439,9 @@ static int soc_probe_link_dais(struct snd_soc_card *card, int num, int order) return ret; } } else { + INIT_DELAYED_WORK(&rtd->delayed_work, + codec2codec_close_delayed_work); + /* link the DAI widgets */ play_w = codec_dai->playback_widget; capture_w = cpu_dai->capture_widget; @@ -2334,6 +2347,22 @@ static int snd_soc_add_controls(struct snd_card *card, struct device *dev, return 0; } +struct snd_kcontrol *snd_soc_card_get_kcontrol(struct snd_soc_card *soc_card, + const char *name) +{ + struct snd_card *card = soc_card->snd_card; + struct snd_kcontrol *kctl; + + if (unlikely(!name)) + return NULL; + + list_for_each_entry(kctl, &card->controls, list) + if (!strncmp(kctl->id.name, name, sizeof(kctl->id.name))) + return kctl; + return NULL; +} +EXPORT_SYMBOL_GPL(snd_soc_card_get_kcontrol); + /** * snd_soc_add_codec_controls - add an array of controls to a codec. * Convenience function to add a list of controls. Many codecs were @@ -3129,11 +3158,11 @@ int snd_soc_bytes_get(struct snd_kcontrol *kcontrol, break; case 2: ((u16 *)(&ucontrol->value.bytes.data))[0] - &= ~params->mask; + &= cpu_to_be16(~params->mask); break; case 4: ((u32 *)(&ucontrol->value.bytes.data))[0] - &= ~params->mask; + &= cpu_to_be32(~params->mask); break; default: return -EINVAL; @@ -3203,6 +3232,18 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol, } EXPORT_SYMBOL_GPL(snd_soc_bytes_put); +int snd_soc_bytes_info_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *ucontrol) +{ + struct soc_bytes_ext *params = (void *)kcontrol->private_value; + + ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; + ucontrol->count = params->max; + + return 0; +} +EXPORT_SYMBOL_GPL(snd_soc_bytes_info_ext); + /** * snd_soc_info_xr_sx - signed multi register info callback * @kcontrol: mreg control diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index f8c840ff822..0fcb5f279d3 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -62,6 +62,7 @@ static int dapm_up_seq[] = { [snd_soc_dapm_mux] = 5, [snd_soc_dapm_virt_mux] = 5, [snd_soc_dapm_value_mux] = 5, + [snd_soc_dapm_demux] = 5, [snd_soc_dapm_dac] = 6, [snd_soc_dapm_mixer] = 7, [snd_soc_dapm_mixer_named_ctl] = 7, @@ -93,6 +94,9 @@ static int dapm_down_seq[] = { [snd_soc_dapm_mux] = 9, [snd_soc_dapm_virt_mux] = 9, [snd_soc_dapm_value_mux] = 9, + [snd_soc_dapm_demux] = 9, + [snd_soc_dapm_aif_in] = 10, + [snd_soc_dapm_aif_out] = 10, [snd_soc_dapm_dai_in] = 10, [snd_soc_dapm_dai_out] = 10, [snd_soc_dapm_dai_link] = 11, @@ -204,6 +208,83 @@ static inline struct snd_soc_card *dapm_get_soc_card( return NULL; } +struct dapm_kcontrol_data { + struct list_head paths; + struct snd_soc_dapm_widget_list wlist; +}; + +static int dapm_kcontrol_data_alloc(struct snd_soc_dapm_widget *widget, + struct snd_kcontrol *kcontrol) +{ + struct dapm_kcontrol_data *data; + + data = kzalloc(sizeof(*data) + sizeof(widget), GFP_KERNEL); + if (!data) { + dev_err(widget->dapm->dev, + "ASoC: can't allocate kcontrol data for %s\n", + widget->name); + return -ENOMEM; + } + + data->wlist.widgets[0] = widget; + data->wlist.num_widgets = 1; + INIT_LIST_HEAD(&data->paths); + + kcontrol->private_data = &data->wlist; + + return 0; +} + +static void dapm_kcontrol_free(struct snd_kcontrol *kctl) +{ + struct dapm_kcontrol_data *data = container_of(snd_kcontrol_chip(kctl), + struct dapm_kcontrol_data, wlist); + kfree(data); +} + +static int dapm_kcontrol_add_widget(struct snd_kcontrol *kcontrol, + struct snd_soc_dapm_widget *widget) +{ + struct dapm_kcontrol_data *data = container_of( + snd_kcontrol_chip(kcontrol), struct dapm_kcontrol_data, wlist); + struct dapm_kcontrol_data *new_data; + unsigned int n = data->wlist.num_widgets + 1; + + new_data = krealloc(data, sizeof(*data) + sizeof(widget) * n, + GFP_KERNEL); + if (!new_data) + return -ENOMEM; + + new_data->wlist.widgets[n - 1] = widget; + new_data->wlist.num_widgets = n; + + kcontrol->private_data = &new_data->wlist; + + return 0; +} + +static void dapm_kcontrol_add_path(const struct snd_kcontrol *kcontrol, + struct snd_soc_dapm_path *path) +{ + struct dapm_kcontrol_data *data = container_of( + snd_kcontrol_chip(kcontrol), struct dapm_kcontrol_data, wlist); + + list_add_tail(&path->list_kcontrol, &data->paths); +} + +static struct list_head *dapm_kcontrol_get_path_list( + const struct snd_kcontrol *kcontrol) +{ + struct dapm_kcontrol_data *data = container_of( + snd_kcontrol_chip(kcontrol), struct dapm_kcontrol_data, wlist); + + return &data->paths; +} + +#define dapm_kcontrol_for_each_path(path, kcontrol) \ + list_for_each_entry(path, dapm_kcontrol_get_path_list(kcontrol), \ + list_kcontrol) + static void dapm_reset(struct snd_soc_card *card) { struct snd_soc_dapm_widget *w; @@ -295,6 +376,35 @@ static int soc_widget_update_bits_locked(struct snd_soc_dapm_widget *w, return change; } +static struct snd_soc_dapm_widget * +dapm_wcache_lookup(struct snd_soc_dapm_wcache *wcache, const char *name) +{ + struct snd_soc_dapm_widget *w = wcache->widget; + struct list_head *wlist; + const int depth = 2; + int i = 0; + + if (w) { + wlist = &w->dapm->card->widgets; + + list_for_each_entry_from(w, wlist, list) { + if (!strcmp(name, w->name)) + return w; + + if (++i == depth) + break; + } + } + + return NULL; +} + +static inline void dapm_wcache_update(struct snd_soc_dapm_wcache *wcache, + struct snd_soc_dapm_widget *w) +{ + wcache->widget = w; +} + /** * snd_soc_dapm_set_bias_level - set the bias level for the system * @dapm: DAPM context @@ -366,7 +476,8 @@ static void dapm_set_path_status(struct snd_soc_dapm_widget *w, } } break; - case snd_soc_dapm_mux: { + case snd_soc_dapm_mux: + case snd_soc_dapm_demux: { struct soc_enum *e = (struct soc_enum *) w->kcontrol_news[i].private_value; int val, item; @@ -462,7 +573,10 @@ static int dapm_connect_mux(struct snd_soc_dapm_context *dapm, list_add(&path->list_sink, &dest->sources); list_add(&path->list_source, &src->sinks); path->name = (char*)e->texts[i]; - dapm_set_path_status(dest, path, 0); + if (src->id == snd_soc_dapm_demux) + dapm_set_path_status(src, path, 0); + else + dapm_set_path_status(dest, path, 0); return 0; } } @@ -529,9 +643,6 @@ static int dapm_create_or_share_mixmux_kcontrol(struct snd_soc_dapm_widget *w, size_t prefix_len; int shared; struct snd_kcontrol *kcontrol; - struct snd_soc_dapm_widget_list *wlist; - int wlistentries; - size_t wlistsize; bool wname_in_long_name, kcname_in_long_name; size_t name_len; char *long_name; @@ -551,25 +662,6 @@ static int dapm_create_or_share_mixmux_kcontrol(struct snd_soc_dapm_widget *w, shared = dapm_is_shared_kcontrol(dapm, w, &w->kcontrol_news[kci], &kcontrol); - if (kcontrol) { - wlist = kcontrol->private_data; - wlistentries = wlist->num_widgets + 1; - } else { - wlist = NULL; - wlistentries = 1; - } - - wlistsize = sizeof(struct snd_soc_dapm_widget_list) + - wlistentries * sizeof(struct snd_soc_dapm_widget *); - wlist = krealloc(wlist, wlistsize, GFP_KERNEL); - if (wlist == NULL) { - dev_err(dapm->dev, "ASoC: can't allocate widget list for %s\n", - w->name); - return -ENOMEM; - } - wlist->num_widgets = wlistentries; - wlist->widgets[wlistentries - 1] = w; - if (!kcontrol) { if (shared) { wname_in_long_name = false; @@ -588,11 +680,11 @@ static int dapm_create_or_share_mixmux_kcontrol(struct snd_soc_dapm_widget *w, case snd_soc_dapm_mux: case snd_soc_dapm_virt_mux: case snd_soc_dapm_value_mux: + case snd_soc_dapm_demux: wname_in_long_name = true; kcname_in_long_name = false; break; default: - kfree(wlist); return -EINVAL; } } @@ -602,10 +694,8 @@ static int dapm_create_or_share_mixmux_kcontrol(struct snd_soc_dapm_widget *w, strlen(w->kcontrol_news[kci].name) + 1; long_name = kmalloc(name_len, GFP_KERNEL); - if (long_name == NULL) { - kfree(wlist); + if (long_name == NULL) return -ENOMEM; - } /* * The control will get a prefix from the control @@ -627,22 +717,33 @@ static int dapm_create_or_share_mixmux_kcontrol(struct snd_soc_dapm_widget *w, name = w->kcontrol_news[kci].name; } - kcontrol = snd_soc_cnew(&w->kcontrol_news[kci], wlist, name, + kcontrol = snd_soc_cnew(&w->kcontrol_news[kci], NULL, name, prefix); + kcontrol->private_free = dapm_kcontrol_free; + + ret = dapm_kcontrol_data_alloc(w, kcontrol); + if (ret) { + snd_ctl_free_one(kcontrol); + kfree(long_name); + return ret; + } + ret = snd_ctl_add(card, kcontrol); if (ret < 0) { dev_err(dapm->dev, "ASoC: failed to add widget %s dapm kcontrol %s: %d\n", w->name, name, ret); - kfree(wlist); kfree(long_name); return ret; } path->long_name = long_name; + } else { + ret = dapm_kcontrol_add_widget(kcontrol, w); + if (ret) + return ret; } - kcontrol->private_data = wlist; w->kcontrols[kci] = kcontrol; path->kcontrol = kcontrol; @@ -665,12 +766,15 @@ static int dapm_new_mixer(struct snd_soc_dapm_widget *w) if (w->kcontrols[i]) { path->kcontrol = w->kcontrols[i]; + dapm_kcontrol_add_path(w->kcontrols[i], path); continue; } ret = dapm_create_or_share_mixmux_kcontrol(w, i, path); if (ret < 0) return ret; + + dapm_kcontrol_add_path(w->kcontrols[i], path); } } @@ -681,30 +785,56 @@ static int dapm_new_mixer(struct snd_soc_dapm_widget *w) static int dapm_new_mux(struct snd_soc_dapm_widget *w) { struct snd_soc_dapm_context *dapm = w->dapm; - struct snd_soc_dapm_path *path; + struct snd_soc_dapm_path *path = NULL; + const char *type; int ret; + switch (w->id) { + case snd_soc_dapm_mux: + case snd_soc_dapm_virt_mux: + case snd_soc_dapm_value_mux: + type = "mux"; + break; + case snd_soc_dapm_demux: + type = "demux"; + break; + default: + return -EINVAL; + } + if (w->num_kcontrols != 1) { dev_err(dapm->dev, - "ASoC: mux %s has incorrect number of controls\n", + "ASoC: %s %s has incorrect number of controls\n", type, w->name); return -EINVAL; } - if (list_empty(&w->sources)) { - dev_err(dapm->dev, "ASoC: mux %s has no paths\n", w->name); + if (w->id == snd_soc_dapm_demux) + path = list_first_entry(&w->sinks, struct snd_soc_dapm_path, + list_source); + else + path = list_first_entry(&w->sources, struct snd_soc_dapm_path, + list_sink); + if (!path) { + dev_err(dapm->dev, "ASoC: %s %s has no paths\n", type, w->name); return -EINVAL; } - path = list_first_entry(&w->sources, struct snd_soc_dapm_path, - list_sink); - ret = dapm_create_or_share_mixmux_kcontrol(w, 0, path); if (ret < 0) return ret; - list_for_each_entry(path, &w->sources, list_sink) - path->kcontrol = w->kcontrols[0]; + if (w->id == snd_soc_dapm_demux) { + list_for_each_entry(path, &w->sinks, list_source) { + path->kcontrol = w->kcontrols[0]; + dapm_kcontrol_add_path(w->kcontrols[0], path); + } + } else { + list_for_each_entry(path, &w->sources, list_sink) { + path->kcontrol = w->kcontrols[0]; + dapm_kcontrol_add_path(w->kcontrols[0], path); + } + } return 0; } @@ -1950,14 +2080,12 @@ static int soc_dapm_mux_update_power(struct snd_soc_dapm_widget *widget, if (widget->id != snd_soc_dapm_mux && widget->id != snd_soc_dapm_virt_mux && - widget->id != snd_soc_dapm_value_mux) + widget->id != snd_soc_dapm_value_mux && + widget->id != snd_soc_dapm_demux) return -ENODEV; /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->dapm->card->paths, list) { - if (path->kcontrol != kcontrol) - continue; - + dapm_kcontrol_for_each_path(path, kcontrol) { if (!path->name || !e->texts[mux]) continue; @@ -2010,11 +2138,7 @@ static int soc_dapm_mixer_update_power(struct snd_soc_dapm_widget *widget, return -ENODEV; /* find dapm widget path assoc with kcontrol */ - list_for_each_entry(path, &widget->dapm->card->paths, list) { - if (path->kcontrol != kcontrol) - continue; - - /* found, now check type */ + dapm_kcontrol_for_each_path(path, kcontrol) { found = 1; path->connect = connect; dapm_mark_dirty(path->source, "mixer connection"); @@ -2220,6 +2344,53 @@ int snd_soc_dapm_sync(struct snd_soc_dapm_context *dapm) } EXPORT_SYMBOL_GPL(snd_soc_dapm_sync); +static int snd_soc_dapm_check_dynamic_path(struct snd_soc_dapm_context *dapm, + struct snd_soc_dapm_widget *source, struct snd_soc_dapm_widget *sink, + const char *control) +{ + bool dynamic_source = false; + bool dynamic_sink = false; + + if (!control) + return 0; + + switch (source->id) { + case snd_soc_dapm_demux: + dynamic_source = true; + break; + default: + break; + } + + switch (sink->id) { + case snd_soc_dapm_mux: + case snd_soc_dapm_virt_mux: + case snd_soc_dapm_value_mux: + case snd_soc_dapm_switch: + case snd_soc_dapm_mixer: + case snd_soc_dapm_mixer_named_ctl: + dynamic_sink = true; + break; + default: + break; + } + + if (dynamic_source && dynamic_sink) { + dev_err(dapm->dev, + "Direct connection between demux and mixer/mux not " \ + "supported for path %s -> [%s] -> %s\n", + source->name, control, sink->name); + return -EINVAL; + } else if (!dynamic_source && !dynamic_sink) { + dev_err(dapm->dev, + "Control not supported for path %s -> [%s] -> %s\n", + source->name, control, sink->name); + return -EINVAL; + } + + return 0; +} + static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, const struct snd_soc_dapm_route *route) { @@ -2245,6 +2416,12 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, source = route->source; } + wsource = dapm_wcache_lookup(&dapm->path_source_cache, source); + wsink = dapm_wcache_lookup(&dapm->path_sink_cache, sink); + + if (wsink && wsource) + goto skip_search; + /* * find src and dest widgets over all widgets but favor a widget from * current DAPM context @@ -2252,14 +2429,20 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, list_for_each_entry(w, &dapm->card->widgets, list) { if (!wsink && !(strcmp(w->name, sink))) { wtsink = w; - if (w->dapm == dapm) + if (w->dapm == dapm) { wsink = w; + if (wsource) + break; + } continue; } if (!wsource && !(strcmp(w->name, source))) { wtsource = w; - if (w->dapm == dapm) + if (w->dapm == dapm) { wsource = w; + if (wsink) + break; + } } } /* use widget from another DAPM context if not found from this */ @@ -2279,6 +2462,10 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, return -ENODEV; } +skip_search: + dapm_wcache_update(&dapm->path_sink_cache, wsink); + dapm_wcache_update(&dapm->path_source_cache, wsource); + path = kzalloc(sizeof(struct snd_soc_dapm_path), GFP_KERNEL); if (!path) return -ENOMEM; @@ -2315,6 +2502,19 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, return 0; } + ret = snd_soc_dapm_check_dynamic_path(dapm, wsource, wsink, control); + + if (ret) + goto dynamic_path_err; + + if (wsource->id == snd_soc_dapm_demux) { + ret = dapm_connect_mux(dapm, wsource, wsink, path, control, + &wsource->kcontrol_news[0]); + if (ret != 0) + goto err; + goto end; + } + /* connect dynamic paths */ switch (wsink->id) { case snd_soc_dapm_adc: @@ -2336,6 +2536,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, case snd_soc_dapm_dai_in: case snd_soc_dapm_dai_out: case snd_soc_dapm_dai_link: + case snd_soc_dapm_demux: list_add(&path->list, &dapm->card->paths); list_add(&path->list_sink, &wsink->sources); list_add(&path->list_source, &wsource->sinks); @@ -2367,6 +2568,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, return 0; } +end: dapm_mark_dirty(wsource, "Route added"); dapm_mark_dirty(wsink, "Route added"); @@ -2375,6 +2577,7 @@ static int snd_soc_dapm_add_route(struct snd_soc_dapm_context *dapm, err: dev_warn(dapm->dev, "ASoC: no dapm match for %s --> %s --> %s\n", source, control, sink); +dynamic_path_err: kfree(path); return ret; } @@ -2611,6 +2814,7 @@ int snd_soc_dapm_new_widgets(struct snd_soc_dapm_context *dapm) case snd_soc_dapm_mux: case snd_soc_dapm_virt_mux: case snd_soc_dapm_value_mux: + case snd_soc_dapm_demux: dapm_new_mux(w); break; case snd_soc_dapm_pga: @@ -3145,6 +3349,7 @@ snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm, case snd_soc_dapm_mux: case snd_soc_dapm_virt_mux: case snd_soc_dapm_value_mux: + case snd_soc_dapm_demux: w->power_check = dapm_generic_check_power; break; case snd_soc_dapm_adc: @@ -3186,7 +3391,7 @@ snd_soc_dapm_new_control(struct snd_soc_dapm_context *dapm, INIT_LIST_HEAD(&w->sinks); INIT_LIST_HEAD(&w->list); INIT_LIST_HEAD(&w->dirty); - list_add(&w->list, &dapm->card->widgets); + list_add_tail(&w->list, &dapm->card->widgets); /* machine layer set ups unconnected pins and insertions */ w->connected = 1;