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aml_dmx.c
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aml_dmx.c
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/*
* AMLOGIC demux driver.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/wait.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <linux/fcntl.h>
#include <asm/irq.h>
#include <linux/uaccess.h>
#include <linux/poll.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/cacheflush.h>
#include <linux/dma-mapping.h>
#ifdef ARC_700
#include <asm/arch/am_regs.h>
#else
#include "c_stb_define.h"
#include "c_stb_regs_define.h"
#endif
#define DMX_USE_SWFILTER 0x100
#include <linux/pinctrl/pinmux.h>
#include "streambuf.h"
#include "aml_dvb.h"
#include "aml_dvb_reg.h"
#include <linux/vmalloc.h>
#define ENABLE_SEC_BUFF_WATCHDOG
#define USE_AHB_MODE
#define pr_dbg_flag(_f, fmt, _args...)\
do {\
if (debug_dmx&(_f))\
printk("DMX: %s: "fmt, __func__, ## _args);\
} while (0)
#define pr_dbg_irq_flag(_f, fmt, _args...)\
do {\
if (debug_irq&(_f))\
printk("DMX: %s: "fmt, __func__, ## _args);\
} while (0)
#define pr_dbg(fmt, args...) pr_dbg_flag(0x1, fmt, ## args)
#define pr_dbg_sf(fmt, args...) pr_dbg_flag(0x4, fmt, ## args)
#define pr_dbg_ss(fmt, args...) pr_dbg_flag(0x8, fmt, ## args)
#define pr_dbg_irq(fmt, args...)pr_dbg_irq_flag(0x1, fmt, ## args)
#define pr_dbg_irq_dvr(fmt, args...)pr_dbg_irq_flag(0x2, fmt, ## args)
#define pr_dbg_irq_sf(fmt, args...) pr_dbg_irq_flag(0x4, fmt, ## args)
#define pr_dbg_irq_ss(fmt, args...) pr_dbg_irq_flag(0x8, fmt, ## args)
#define pr_error(fmt, args...) printk("DMX: " fmt, ## args)
#define pr_inf(fmt, args...) printk("DMX: " fmt, ## args)
#define dump(b, l) \
do { \
int i; \
printk("dump: "); \
for (i = 0; i < (l); i++) {\
if (!(i&0xf)) \
printk("\n\t"); \
printk("%02x ", *(((unsigned char *)(b))+i)); \
} \
printk("\n"); \
} while (0)
MODULE_PARM_DESC(debug_dmx, "\n\t\t Enable demux debug information");
static int debug_dmx;
module_param(debug_dmx, int, 0644);
MODULE_PARM_DESC(debug_irq, "\n\t\t Enable demux IRQ debug information");
static int debug_irq;
module_param(debug_irq, int, 0644);
static int npids = CHANNEL_COUNT;
#define MOD_PARAM_DECLARE_CHANPIDS(_dmx) \
MODULE_PARM_DESC(debug_dmx##_dmx##_chanpids, "\n\t\t pids of dmx channels"); \
static short debug_dmx##_dmx##_chanpids[CHANNEL_COUNT] = \
{[0 ... (CHANNEL_COUNT - 1)] = -1}; \
module_param_array(debug_dmx##_dmx##_chanpids, short, &npids, 0444)
MOD_PARAM_DECLARE_CHANPIDS(0);
MOD_PARAM_DECLARE_CHANPIDS(1);
MOD_PARAM_DECLARE_CHANPIDS(2);
#define set_debug_dmx_chanpids(_dmx, _idx, _pid)\
do { \
if ((_dmx) == 0) \
debug_dmx0_chanpids[(_idx)] = (_pid); \
else if ((_dmx) == 1) \
debug_dmx1_chanpids[(_idx)] = (_pid); \
else if ((_dmx) == 2) \
debug_dmx2_chanpids[(_idx)] = (_pid); \
} while (0)
MODULE_PARM_DESC(debug_sf_user, "\n\t\t only for sf mode check");
static int debug_sf_user;
module_param(debug_sf_user, int, 0644);
MODULE_PARM_DESC(force_sec_sf, "\n\t\t force sf mode for sec filter");
static int force_sec_sf;
module_param(force_sec_sf, int, 0644);
MODULE_PARM_DESC(force_pes_sf, "\n\t\t force sf mode for pes filter");
static int force_pes_sf;
module_param(force_pes_sf, int, 0644);
#define DMX_READ_REG(i, r)\
((i)?((i == 1)?READ_MPEG_REG(r##_2) :\
READ_MPEG_REG(r##_3)) : READ_MPEG_REG(r))
#define DMX_WRITE_REG(i, r, d)\
do {\
if (i == 1) {\
WRITE_MPEG_REG(r##_2, d);\
} else if (i == 2) {\
WRITE_MPEG_REG(r##_3, d);\
} \
else {\
WRITE_MPEG_REG(r, d);\
} \
} while (0)
#define READ_PERI_REG READ_CBUS_REG
#define WRITE_PERI_REG WRITE_CBUS_REG
#define READ_ASYNC_FIFO_REG(i, r)\
((i) ? READ_PERI_REG(ASYNC_FIFO2_##r) : READ_PERI_REG(ASYNC_FIFO_##r))
#define WRITE_ASYNC_FIFO_REG(i, r, d)\
do {\
if (i == 1) {\
WRITE_PERI_REG(ASYNC_FIFO2_##r, d);\
} else {\
WRITE_PERI_REG(ASYNC_FIFO_##r, d);\
} \
} while (0)
#define CLEAR_ASYNC_FIFO_REG_MASK(i, reg, mask) \
WRITE_ASYNC_FIFO_REG(i, reg, \
(READ_ASYNC_FIFO_REG(i, reg)&(~(mask))))
#define DVR_FEED(f) \
((f) && ((f)->type == DMX_TYPE_TS) && \
(((f)->ts_type & (TS_PACKET | TS_DEMUX)) == TS_PACKET))
#define MOD_PARAM_DECLARE_CHANREC(_dmx) \
MODULE_PARM_DESC(dmx##_dmx##_chanrec_enable, \
"\n\t\t record by channel, one time use in the beginning"); \
static int dmx##_dmx##_chanrec_enable; \
module_param(dmx##_dmx##_chanrec_enable, int, 0644); \
MODULE_PARM_DESC(dmx##_dmx##_chanrec, "\n\t\t record channels bits"); \
static int dmx##_dmx##_chanrec; \
module_param(dmx##_dmx##_chanrec, int, 0644)
MOD_PARAM_DECLARE_CHANREC(0);
MOD_PARAM_DECLARE_CHANREC(1);
MOD_PARAM_DECLARE_CHANREC(2);
#define MOD_PARAM_DECLARE_CHANPROC(_dmx) \
MODULE_PARM_DESC(dmx##_dmx##_chanproc_enable, "channel further processing"); \
static int dmx##_dmx##_chanproc_enable; \
module_param(dmx##_dmx##_chanproc_enable, int, 0644); \
MODULE_PARM_DESC(dmx##_dmx##_chanproc, "further process channels bits"); \
static int dmx##_dmx##_chanproc; \
module_param(dmx##_dmx##_chanproc, int, 0644)
MOD_PARAM_DECLARE_CHANPROC(0);
MOD_PARAM_DECLARE_CHANPROC(1);
MOD_PARAM_DECLARE_CHANPROC(2);
#define DMX_CH_OP_CHANREC 0
#define DMX_CH_OP_CHANPROC 1
static inline int _setbit(int v, int b) { return v|(1<<b); }
static inline int _clrbit(int v, int b) { return v&~(1<<b); }
static inline int _set(int v, int b) { return b; }
static void dmxn_op_chan(int dmx, int ch, int(*op)(int, int), int ch_op)
{
int enable_0, enable_1, enable_2;
int *set_0, *set_1, *set_2;
int reg;
if (ch_op == DMX_CH_OP_CHANREC) {
enable_0 = dmx0_chanrec_enable;
enable_1 = dmx1_chanrec_enable;
enable_2 = dmx2_chanrec_enable;
set_0 = &dmx0_chanrec;
set_1 = &dmx1_chanrec;
set_2 = &dmx2_chanrec;
reg = DEMUX_CHAN_RECORD_EN;
} else if (ch_op == DMX_CH_OP_CHANPROC) {
enable_0 = dmx0_chanproc_enable;
enable_1 = dmx1_chanproc_enable;
enable_2 = dmx2_chanproc_enable;
set_0 = &dmx0_chanproc;
set_1 = &dmx1_chanproc;
set_2 = &dmx2_chanproc;
reg = DEMUX_CHAN_PROCESS_EN;
} else {
return;
}
if (dmx == 0) {
if (enable_0) {
*set_0 = op(*set_0, ch);
WRITE_MPEG_REG(reg+DEMUX_1_OFFSET, *set_0);
}
} else if (dmx == 1) {
if (enable_1) {
*set_1 = op(*set_1, ch);
WRITE_MPEG_REG(reg+DEMUX_2_OFFSET, *set_1);
}
} else if (dmx == 2) {
if (enable_2) {
*set_2 = op(*set_2, ch);
WRITE_MPEG_REG(reg+DEMUX_3_OFFSET, *set_2);
}
}
}
#define dmx_add_recchan(_dmx, _chid) \
do { \
pr_dbg("dmx[%d]_add_recchan[%d]\n", _dmx, _chid); \
dmxn_op_chan(_dmx, _chid, _setbit, DMX_CH_OP_CHANREC); \
} while (0)
#define dmx_rm_recchan(_dmx, _chid) \
do { \
pr_dbg("dmx[%d]_rm_recchan[%ld]\n", _dmx, _chid); \
dmxn_op_chan(_dmx, _chid, _clrbit, DMX_CH_OP_CHANREC); \
} while (0)
#define dmx_set_recchan(_dmx, _chs) \
do { \
pr_dbg("dmx[%d]_set_recchan[%d]\n", _dmx, _chs); \
dmxn_op_chan(_dmx, _chs, _set, DMX_CH_OP_CHANREC); \
} while (0)
#define dmx_add_procchan(_dmx, _chid) \
do { \
pr_dbg("dmx[%d]_add_procchan[%d]\n", _dmx, _chid); \
dmxn_op_chan(_dmx, _chid, _setbit, DMX_CH_OP_CHANPROC); \
} while (0)
#define dmx_rm_procchan(_dmx, _chid) \
do { \
pr_dbg("dmx[%d]_rm_procchan[%ld]\n", _dmx, _chid); \
dmxn_op_chan(_dmx, _chid, _clrbit, DMX_CH_OP_CHANPROC); \
} while (0)
#define dmx_set_procchan(_dmx, _chs) \
do { \
pr_dbg("dmx[%d]_set_procchan[%d]\n", _dmx, _chs); \
dmxn_op_chan(_dmx, _chs, _set, DMX_CH_OP_CHANPROC); \
} while (0)
#define NO_SUB
#define SYS_CHAN_COUNT (4)
#define SEC_GRP_LEN_0 (0xc)
#define SEC_GRP_LEN_1 (0xc)
#define SEC_GRP_LEN_2 (0xc)
#define SEC_GRP_LEN_3 (0xc)
#define LARGE_SEC_BUFF_MASK 0xFFFFFFFF
#define LARGE_SEC_BUFF_COUNT 32
#define WATCHDOG_TIMER 250
#define ASYNCFIFO_BUFFER_SIZE_DEFAULT (512*1024)
#define DEMUX_INT_MASK\
((0<<(AUDIO_SPLICING_POINT)) |\
(0<<(VIDEO_SPLICING_POINT)) |\
(0<<(OTHER_PES_READY)) |\
(1<<(SUB_PES_READY)) |\
(1<<(SECTION_BUFFER_READY)) |\
(0<<(OM_CMD_READ_PENDING)) |\
(1<<(TS_ERROR_PIN)) |\
(1<<(NEW_PDTS_READY)) |\
(0<<(DUPLICATED_PACKET)) |\
(0<<(DIS_CONTINUITY_PACKET)))
#define TS_SRC_MAX 3
/*Reset the demux device*/
#define RESET_DEMUX2 (1<<15)
#define RESET_DEMUX1 (1<<14)
#define RESET_DEMUX0 (1<<13)
#define RESET_S2P1 (1<<12)
#define RESET_S2P0 (1<<11)
#define RESET_DES (1<<10)
#define RESET_TOP (1<<9)
static int dmx_remove_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed);
static void reset_async_fifos(struct aml_dvb *dvb);
static int dmx_add_feed(struct aml_dmx *dmx, struct dvb_demux_feed *feed);
static int dmx_smallsec_set(struct aml_smallsec *ss, int enable, int bufsize,
int force);
static int dmx_timeout_set(struct aml_dmxtimeout *dto, int enable,
int timeout, int ch_dis, int nomatch,
int force);
/*Audio & Video PTS value*/
static u32 video_pts;
static u32 audio_pts;
static u32 first_video_pts;
static u32 first_audio_pts;
static int demux_skipbyte;
static int tsfile_clkdiv = 4;
#define SF_DMX_ID 2
#define SF_AFIFO_ID 1
#define sf_dmx_sf(_dmx) \
(((_dmx)->id == SF_DMX_ID) \
&& ((struct aml_dvb *)(_dmx)->demux.priv)->swfilter.user)
#define sf_afifo_sf(_afifo) \
(((_afifo)->id == SF_AFIFO_ID) && (_afifo)->dvb->swfilter.user)
#define dmx_get_dev(dmx) (((struct aml_dvb *)((dmx)->demux.priv))->dev)
#define asyncfifo_get_dev(afifo) ((afifo)->dvb->dev)
/*Section buffer watchdog*/
static void section_buffer_watchdog_func(unsigned long arg)
{
struct aml_dvb *dvb = (struct aml_dvb *)arg;
struct aml_dmx *dmx;
u32 section_busy32 = 0, om_cmd_status32 = 0,
demux_channel_activity32 = 0;
u16 demux_int_status1 = 0;
u32 device_no = 0;
u32 filter_number = 0;
u32 i = 0;
unsigned long flags;
spin_lock_irqsave(&dvb->slock, flags);
for (device_no = 0; device_no < DMX_DEV_COUNT; device_no++) {
dmx = &dvb->dmx[device_no];
if (dvb->dmx_watchdog_disable[device_no])
continue;
if (!dmx->init)
continue;
om_cmd_status32 =
DMX_READ_REG(device_no, OM_CMD_STATUS);
demux_channel_activity32 =
DMX_READ_REG(device_no, DEMUX_CHANNEL_ACTIVITY);
section_busy32 =
DMX_READ_REG(device_no, SEC_BUFF_BUSY);
#if 1
if (om_cmd_status32 & 0x8fc2) {
/* bit 15:12 -- om_cmd_count */
/* bit 11:9 -- overflow_count */
/* bit 8:6 -- om_overwrite_count */
/* bit 1 -- om_cmd_overflow */
/*BUG: If the recoder is running, return */
if (dmx->record)
goto end;
/*Reset the demux */
pr_dbg("reset the demux\n"
"%04x\t%03x\t%03x\t%03x\t%01x\t%01x\t"
"%x\t%x\tdmx%d:status:0x%x\n",
(om_cmd_status32 >> 12) & 0xf,
(om_cmd_status32 >> 9) & 0x7,
(om_cmd_status32 >> 6) & 0x7,
(om_cmd_status32 >> 3) & 0x7,
(om_cmd_status32 >> 2) & 0x1,
(om_cmd_status32 >> 1) & 0x1,
demux_channel_activity32, section_busy32,
dmx->id, om_cmd_status32);
dmx_reset_dmx_hw_ex_unlock(dvb, dmx, 0);
goto end;
}
#else
/* bit 15:12 -- om_cmd_count (read only) */
/* bit 11:9 -- overflow_count //
bit 11:9 -- om_cmd_wr_ptr (read only) */
/* bit 8:6 -- om_overwrite_count //
bit 8:6 -- om_cmd_rd_ptr (read only) */
/* bit 5:3 -- type_stb_om_w_rd (read only) */
/* bit 2 -- unit_start_stb_om_w_rd (read only) */
/* bit 1 -- om_cmd_overflow (read only) */
/* bit 0 -- om_cmd_pending (read) */
/* bit 0 -- om_cmd_read_finished (write) */
if (om_cmd_status32 & 0x0002) {
pr_error("reset the demux\n");
dmx_reset_hw_ex(dvb, 0);
goto end;
}
#endif
section_busy32 =
DMX_READ_REG(device_no, SEC_BUFF_BUSY);
if (LARGE_SEC_BUFF_MASK ==
(section_busy32 & LARGE_SEC_BUFF_MASK)) {
/*All the largest section buffers occupied,
* clear buffers */
DMX_WRITE_REG(device_no,
SEC_BUFF_READY, section_busy32);
} else {
for (i = 0; i < SEC_BUF_COUNT; i++) {
if (!(section_busy32 & (1 << i)))
continue;
DMX_WRITE_REG(device_no, SEC_BUFF_NUMBER, i);
filter_number = DMX_READ_REG(device_no,
SEC_BUFF_NUMBER);
filter_number >>= 8;
if ((filter_number >= FILTER_COUNT)
/* >=31, do not handle this case */
|| ((filter_number < FILTER_COUNT)
&& dmx->filter[filter_number].used))
section_busy32 &= ~(1 << i);
}
if (section_busy32 & (dmx->smallsec.enable ?
0x7FFFFFFF :
LARGE_SEC_BUFF_MASK)) {
/*Clear invalid buffers */
DMX_WRITE_REG(device_no,
SEC_BUFF_READY,
section_busy32);
pr_error("clear invalid buffer 0x%x\n",
section_busy32);
}
#if 0
section_busy32 = 0x7fffffff;
for (i = 0; i < SEC_BUF_BUSY_SIZE; i++) {
dmx->section_busy[i] = (
(i == SEC_BUF_BUSY_SIZE - 1) ?
DMX_READ_REG(device_no, SEC_BUFF_BUSY) :
dmx->section_busy[i + 1]);
section_busy32 &= dmx->section_busy[i];
}
/*count the number of '1' bits */
i = section_busy32;
i = (i & 0x55555555) + ((i & 0xaaaaaaaa) >> 1);
i = (i & 0x33333333) + ((i & 0xcccccccc) >> 2);
i = (i & 0x0f0f0f0f) + ((i & 0xf0f0f0f0) >> 4);
i = (i & 0x00ff00ff) + ((i & 0xff00ff00) >> 8);
i = (i & 0x0000ffff) + ((i & 0xffff0000) >> 16);
if (i > LARGE_SEC_BUFF_COUNT) {
/*too long some of the section
buffers are being processed */
DMX_WRITE_REG(device_no, SEC_BUFF_READY,
section_busy32);
}
#endif
}
demux_int_status1 =
DMX_READ_REG(device_no, STB_INT_STATUS) & 0xfff7;
if (demux_int_status1 & (1 << TS_ERROR_PIN)) {
DMX_WRITE_REG(device_no,
STB_INT_STATUS,
(1 << TS_ERROR_PIN));
}
}
end:
spin_unlock_irqrestore(&dvb->slock, flags);
#ifdef ENABLE_SEC_BUFF_WATCHDOG
mod_timer(&dvb->watchdog_timer,
jiffies + msecs_to_jiffies(WATCHDOG_TIMER));
#endif
return;
}
static inline int sec_filter_match(struct aml_dmx *dmx, struct aml_filter *f,
u8 *p)
{
int b;
u8 neq = 0;
if (!f->used || !dmx->channel[f->chan_id].used)
return 0;
for (b = 0; b < FILTER_LEN; b++) {
u8 xor = p[b] ^ f->value[b];
if (xor & f->maskandmode[b])
return 0;
if (xor & f->maskandnotmode[b])
neq = 1;
}
if (f->neq && !neq)
return 0;
return 1;
}
static int section_crc(struct aml_dmx *dmx, struct aml_filter *f, u8 *p)
{
int sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
struct dvb_demux_feed *feed = dmx->channel[f->chan_id].feed;
if (feed->feed.sec.check_crc) {
struct dvb_demux *demux = feed->demux;
struct dmx_section_feed *sec = &feed->feed.sec;
int section_syntax_indicator;
section_syntax_indicator = ((p[1] & 0x80) != 0);
sec->seclen = sec_len;
sec->crc_val = ~0;
if (demux->check_crc32(feed, p, sec_len)) {
pr_error("section CRC check failed!\n");
#if 0
int i;
for (i = 0; i < sec_len; i++) {
pr_dbg("%02x ", p[i]);
if (!((i + 1) % 16))
pr_dbg("\n");
}
pr_dbg("\nerror section data\n");
#endif
return 0;
}
#if 0
int i;
for (i = 0; i < sec_len; i++) {
pr_dbg("%02x ", p[i]);
if (!((i + 1) % 16))
pr_dbg("\n");
}
pr_dbg("\nsection data\n");
#endif
}
return 1;
}
static void section_notify(struct aml_dmx *dmx, struct aml_filter *f, u8 *p)
{
int sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
struct dvb_demux_feed *feed = dmx->channel[f->chan_id].feed;
if (feed && feed->cb.sec)
feed->cb.sec(p, sec_len, NULL, 0, f->filter);
}
static void hardware_match_section(struct aml_dmx *dmx,
u16 sec_num, u16 buf_num)
{
u8 *p = (u8 *) dmx->sec_buf[buf_num].addr;
struct aml_filter *f;
int chid, i;
int need_crc = 1;
if (sec_num >= FILTER_COUNT) {
pr_dbg("sec_num invalid: %d\n", sec_num);
return;
}
dma_sync_single_for_cpu(dmx_get_dev(dmx),
dmx->sec_pages_map + (buf_num << 0x0c),
(1 << 0x0c), DMA_FROM_DEVICE);
f = &dmx->filter[sec_num];
chid = f->chan_id;
for (i = 0; i < FILTER_COUNT; i++) {
f = &dmx->filter[i];
if (f->chan_id != chid)
continue;
if (sec_filter_match(dmx, f, p)) {
if (need_crc) {
if (!section_crc(dmx, f, p))
return;
need_crc = 0;
}
section_notify(dmx, f, p);
}
}
}
static void software_match_section(struct aml_dmx *dmx, u16 buf_num)
{
u8 *p = (u8 *) dmx->sec_buf[buf_num].addr;
struct aml_filter *f, *fmatch = NULL;
int i, fid = -1;
dma_sync_single_for_cpu(dmx_get_dev(dmx),
dmx->sec_pages_map + (buf_num << 0x0c),
(1 << 0x0c), DMA_FROM_DEVICE);
for (i = 0; i < FILTER_COUNT; i++) {
f = &dmx->filter[i];
if (sec_filter_match(dmx, f, p)) {
pr_dbg("[software match]filter %d match, pid %d\n",
i, dmx->channel[f->chan_id].pid);
if (!fmatch) {
fmatch = f;
fid = i;
} else {
pr_dbg("software match]Muli-filter match this\n"
"section, will skip this section\n");
return;
}
}
}
if (fmatch) {
pr_dbg("[software match]dispatch\n"
"section to filter %d pid %d\n",
fid, dmx->channel[fmatch->chan_id].pid);
if (section_crc(dmx, fmatch, p))
section_notify(dmx, fmatch, p);
} else {
pr_dbg("[software match]this section do not\n"
"match any filter!!!\n");
}
}
static int _rbuf_write(struct dvb_ringbuffer *buf, const u8 *src, size_t len)
{
ssize_t free;
if (!len)
return 0;
if (!buf->data)
return 0;
free = dvb_ringbuffer_free(buf);
if (len > free) {
pr_error("sf: buffer overflow\n");
return -EOVERFLOW;
}
return dvb_ringbuffer_write(buf, src, len);
}
static int _rbuf_filter_pkts(struct dvb_ringbuffer *rb,
u8 *wrapbuf,
void (*swfilter_packets)(struct dvb_demux *demux,
const u8 *buf,
size_t count),
struct dvb_demux *demux)
{
ssize_t len1 = 0;
ssize_t len2 = 0;
size_t off;
size_t count;
size_t size;
if (debug_irq & 0x4)
dump(&rb->data[rb->pread], (debug_irq & 0xFFF00) >> 8);
/*
rb|====--------===[0x47]====|
^ ^
wr rd
*/
len1 = rb->pwrite - rb->pread;
if (len1 < 0) {
len1 = rb->size - rb->pread;
len2 = rb->pwrite;
}
for (off = 0; off < len1; off++) {
if (rb->data[rb->pread + off] == 0x47)
break;
}
if (off)
pr_dbg_irq_sf("off ->|%zd\n", off);
len1 -= off;
rb->pread = (rb->pread + off) % rb->size;
count = len1 / 188;
if (count) {
pr_dbg_irq_sf("pkt >> 1[%zd<->%zd]\n", rb->pread, rb->pwrite);
swfilter_packets(demux, rb->data + rb->pread, count);
size = count * 188;
len1 -= size;
rb->pread += size;
}
if (len2 && len1 && ((len1 + len2) > 188)) {
pr_dbg_irq_sf("pkt >> 2[%zd<->%zd]\n", rb->pread, rb->pwrite);
size = 188 - len1;
memcpy(wrapbuf, rb->data + rb->pread, len1);
memcpy(wrapbuf + len1, rb->data, size);
swfilter_packets(demux, wrapbuf, 1);
rb->pread = size;
len2 -= size;
}
if (len2) {
pr_dbg_irq_sf("pkt >> 3[%zd<->%zd]\n", rb->pread, rb->pwrite);
count = len2 / 188;
if (count) {
swfilter_packets(demux, rb->data + rb->pread, count);
rb->pread += count * 188;
}
}
return 0;
}
static void smallsection_match_section(struct aml_dmx *dmx, u8 *p, u16 sec_num)
{
struct aml_filter *f;
int chid, i;
int need_crc = 1;
if (sec_num >= FILTER_COUNT) {
pr_dbg("sec_num invalid: %d\n", sec_num);
return;
}
f = &dmx->filter[sec_num];
chid = f->chan_id;
for (i = 0; i < FILTER_COUNT; i++) {
f = &dmx->filter[i];
if (f->chan_id != chid)
continue;
if (sec_filter_match(dmx, f, p)) {
if (need_crc) {
if (!section_crc(dmx, f, p))
return;
need_crc = 0;
}
section_notify(dmx, f, p);
}
}
}
static void process_smallsection(struct aml_dmx *dmx)
{
u32 v, wr, rd;
u32 data32;
struct aml_smallsec *ss = &dmx->smallsec;
v = DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL);
wr = (v >> 8) & 0xff;
rd = (v >> 16) & 0xff;
if (rd != wr) {
int n1 = wr - rd,
n2 = 0,
max = (ss->bufsize>>8);
int i;
u8 *p;
int sec_len;
pr_dbg_irq_ss("secbuf[31] ctrl:0x%x\n", v);
if (n1 < 0) {
n1 = max - rd;
n2 = wr;
}
if (n1) {
pr_dbg_irq_ss("n1:%d\n", n1);
dma_sync_single_for_cpu(dmx_get_dev(dmx),
ss->buf_map+(rd<<8),
n1<<8,
DMA_FROM_DEVICE);
for (i = 0; i < n1; i++) {
p = (u8 *)ss->buf+((rd+i)<<8);
sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
smallsection_match_section(dmx, p,
*(p+sec_len+1));
}
}
if (n2) {
pr_dbg_irq_ss("n2:%d\n", n2);
dma_sync_single_for_cpu(dmx_get_dev(dmx),
ss->buf_map,
n2<<8,
DMA_FROM_DEVICE);
for (i = 0; i < n2; i++) {
p = (u8 *)ss->buf+(i<<8);
sec_len = (((p[1] & 0xF) << 8) | p[2]) + 3;
smallsection_match_section(dmx, p,
*(p+sec_len+1));
}
}
rd = wr;
data32 = (DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL)
& 0xff00ffff)
| (rd << 16);
DMX_WRITE_REG(dmx->id, DEMUX_SMALL_SEC_CTL, data32);
}
}
static void process_section(struct aml_dmx *dmx)
{
u32 ready, i, sec_busy;
u16 sec_num;
ready = DMX_READ_REG(dmx->id, SEC_BUFF_READY);
if (ready) {
pr_dbg("section ready:%08x\n",ready);
#ifdef USE_AHB_MODE
/* WRITE_ISA_REG(AHB_BRIDGE_CTRL1,
READ_ISA_REG (AHB_BRIDGE_CTRL1) | (1 << 31)); */
/* WRITE_ISA_REG(AHB_BRIDGE_CTRL1,
READ_ISA_REG (AHB_BRIDGE_CTRL1) & (~ (1 << 31))); */
#endif
if ((ready & (1<<31)) && dmx->smallsec.enable) {
u32 v, wr, rd;
v = DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL);
wr = (v >> 8) & 0xff;
rd = (v >> 16) & 0xff;
if ((wr < rd) && (5 > (rd - wr)))
pr_error("warning: small ss buf [w%dr%d]\n",
wr, rd);
pr_dbg_irq_ss("ss>%x\n",
DMX_READ_REG(dmx->id, DEMUX_SMALL_SEC_CTL));
process_smallsection(dmx);
/*tasklet_hi_schedule(&dmx->dmx_tasklet);*/
/*tasklet_schedule(&dmx->dmx_tasklet);*/
DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, (1<<31));
return;
}
for (i = 0; i < SEC_BUF_COUNT; i++) {
if (!(ready & (1 << i)))
continue;
/* get section busy */
sec_busy = DMX_READ_REG(dmx->id, SEC_BUFF_BUSY);
/* get filter number */
DMX_WRITE_REG(dmx->id, SEC_BUFF_NUMBER, i);
sec_num = (DMX_READ_REG(dmx->id, SEC_BUFF_NUMBER) >> 8);
pr_dbg("%d. sec_busy:%08x sec_num:%d\n", i, sec_busy, sec_num);
/*
* sec_buf_watchdog_count dispatch:
* byte0 -- always busy=0 's watchdog count
* byte1 -- always busy=1 & filter_num=31 's
* watchdog count
*/
/* sec_busy is not set, check busy=0 watchdog count */
if (!(sec_busy & (1 << i))) {
/* clear other wd count of this buffer */
dmx->sec_buf_watchdog_count[i] &= 0x000000ff;
dmx->sec_buf_watchdog_count[i] += 0x1;
pr_dbg("bit%d ready=1, busy=0,\n"
"sec_num=%d for %d times\n",
i, sec_num,
dmx->sec_buf_watchdog_count[i]);
if (dmx->sec_buf_watchdog_count[i] >= 5) {
pr_dbg("busy=0 reach the max count,\n"
"try software match.\n");
software_match_section(dmx, i);
dmx->sec_buf_watchdog_count[i] = 0;
DMX_WRITE_REG(dmx->id, SEC_BUFF_READY,
(1 << i));
}
continue;
}
/* filter_num == 31 && busy == 1,check watchdog count */
if (sec_num >= FILTER_COUNT) {
/* clear other wd count of this buffer */
dmx->sec_buf_watchdog_count[i] &= 0x0000ff00;
dmx->sec_buf_watchdog_count[i] += 0x100;
pr_dbg("bit%d ready=1,busy=1,\n"
"sec_num=%d for %d times\n",
i, sec_num,
dmx->sec_buf_watchdog_count[i] >> 8);
if (dmx->sec_buf_watchdog_count[i] >= 0x500) {
pr_dbg("busy=1&filter_num=31\n"
" reach the max count, clear\n"
" the buf ready & busy!\n");
software_match_section(dmx, i);
dmx->sec_buf_watchdog_count[i] = 0;
DMX_WRITE_REG(dmx->id,
SEC_BUFF_READY,
(1 << i));
DMX_WRITE_REG(dmx->id,
SEC_BUFF_BUSY,
(1 << i));
}
continue;
}
/* now, ready & busy are both set and
filter number is valid */
if (dmx->sec_buf_watchdog_count[i] != 0)
dmx->sec_buf_watchdog_count[i] = 0;
/* process this section */
hardware_match_section(dmx, sec_num, i);
/* clear the ready & busy bit */
DMX_WRITE_REG(dmx->id, SEC_BUFF_READY, (1 << i));
DMX_WRITE_REG(dmx->id, SEC_BUFF_BUSY, (1 << i));
}
}
}
#ifdef NO_SUB
static void process_sub(struct aml_dmx *dmx)
{
u32 rd_ptr = 0;
u32 wr_ptr = READ_MPEG_REG(PARSER_SUB_WP);
u32 start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
u32 end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
u32 buffer1 = 0, buffer2 = 0;
unsigned char *buffer1_virt = 0, *buffer2_virt = 0;
u32 len1 = 0, len2 = 0;
rd_ptr = READ_MPEG_REG(PARSER_SUB_RP);
if (!rd_ptr)
return;
if (rd_ptr > wr_ptr) {
len1 = end_ptr - rd_ptr + 8;
buffer1 = rd_ptr;
len2 = wr_ptr - start_ptr;
buffer2 = start_ptr;
rd_ptr = start_ptr + len2;
} else if (rd_ptr < wr_ptr) {
len1 = wr_ptr - rd_ptr;
buffer1 = rd_ptr;
rd_ptr += len1;
len2 = 0;
} else if (rd_ptr == wr_ptr) {
pr_dbg("no data\n");
}
if (buffer1)
buffer1_virt = phys_to_virt(buffer1);
if (buffer2)
buffer2_virt = phys_to_virt(buffer2);
if (len1)
dma_sync_single_for_cpu(dmx_get_dev(dmx),
(dma_addr_t) buffer1, len1,
DMA_FROM_DEVICE);
if (len2)
dma_sync_single_for_cpu(dmx_get_dev(dmx),
(dma_addr_t) buffer2, len2,
DMA_FROM_DEVICE);
if (dmx->channel[2].used) {
if (dmx->channel[2].feed && dmx->channel[2].feed->cb.ts) {
dmx->channel[2].feed->cb.ts(buffer1_virt, len1,
buffer2_virt, len2,
&dmx->channel[2].feed->feed.ts);
}
}
WRITE_MPEG_REG(PARSER_SUB_RP, rd_ptr);
}
#endif
static void process_pes(struct aml_dmx *dmx)
{
}
static void process_om_read(struct aml_dmx *dmx)
{
unsigned i;
unsigned short om_cmd_status_data_0 = 0;
unsigned short om_cmd_status_data_1 = 0;
/* unsigned short om_cmd_status_data_2 = 0;*/
unsigned short om_cmd_data_out = 0;
om_cmd_status_data_0 = DMX_READ_REG(dmx->id, OM_CMD_STATUS);
om_cmd_status_data_1 = DMX_READ_REG(dmx->id, OM_CMD_DATA);
/* om_cmd_status_data_2 = DMX_READ_REG(dmx->id, OM_CMD_DATA2);*/
if (om_cmd_status_data_0 & 1) {
DMX_WRITE_REG(dmx->id, OM_DATA_RD_ADDR,
(1 << 15) | ((om_cmd_status_data_1 & 0xff) << 2));
for (i = 0; i < (((om_cmd_status_data_1 >> 7) & 0x1fc) >> 1);
i++) {
om_cmd_data_out = DMX_READ_REG(dmx->id, OM_DATA_RD);
}