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kubalewskikuba-moo
kubalewski
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ice: add callbacks for Embedded SYNC enablement on dpll pins
Allow the user to get and set configuration of Embedded SYNC feature on the ice driver dpll pins. Reviewed-by: Aleksandr Loktionov <[email protected]> Signed-off-by: Arkadiusz Kubalewski <[email protected]> Reviewed-by: Jiri Pirko <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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+221
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‎drivers/net/ethernet/intel/ice/ice_dpll.c

+220-3
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50
1010
#define ICE_DPLL_PIN_IDX_INVALID 0xff
1111
#define ICE_DPLL_RCLK_NUM_PER_PF 1
12+
#define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25
1213

1314
/**
1415
* enum ice_dpll_pin_type - enumerate ice pin types:
@@ -30,6 +31,10 @@ static const char * const pin_type_name[] = {
3031
[ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
3132
};
3233

34+
static const struct dpll_pin_frequency ice_esync_range[] = {
35+
DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ),
36+
};
37+
3338
/**
3439
* ice_dpll_is_reset - check if reset is in progress
3540
* @pf: private board structure
@@ -394,8 +399,8 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
394399

395400
switch (pin_type) {
396401
case ICE_DPLL_PIN_TYPE_INPUT:
397-
ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL,
398-
NULL, &pin->flags[0],
402+
ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status,
403+
NULL, NULL, &pin->flags[0],
399404
&pin->freq, &pin->phase_adjust);
400405
if (ret)
401406
goto err;
@@ -430,7 +435,7 @@ ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
430435
goto err;
431436

432437
parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL;
433-
if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) {
438+
if (ICE_AQC_GET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) {
434439
pin->state[pf->dplls.eec.dpll_idx] =
435440
parent == pf->dplls.eec.dpll_idx ?
436441
DPLL_PIN_STATE_CONNECTED :
@@ -1098,6 +1103,214 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
10981103
return 0;
10991104
}
11001105

1106+
/**
1107+
* ice_dpll_output_esync_set - callback for setting embedded sync
1108+
* @pin: pointer to a pin
1109+
* @pin_priv: private data pointer passed on pin registration
1110+
* @dpll: registered dpll pointer
1111+
* @dpll_priv: private data pointer passed on dpll registration
1112+
* @freq: requested embedded sync frequency
1113+
* @extack: error reporting
1114+
*
1115+
* Dpll subsystem callback. Handler for setting embedded sync frequency value
1116+
* on output pin.
1117+
*
1118+
* Context: Acquires pf->dplls.lock
1119+
* Return:
1120+
* * 0 - success
1121+
* * negative - error
1122+
*/
1123+
static int
1124+
ice_dpll_output_esync_set(const struct dpll_pin *pin, void *pin_priv,
1125+
const struct dpll_device *dpll, void *dpll_priv,
1126+
u64 freq, struct netlink_ext_ack *extack)
1127+
{
1128+
struct ice_dpll_pin *p = pin_priv;
1129+
struct ice_dpll *d = dpll_priv;
1130+
struct ice_pf *pf = d->pf;
1131+
u8 flags = 0;
1132+
int ret;
1133+
1134+
if (ice_dpll_is_reset(pf, extack))
1135+
return -EBUSY;
1136+
mutex_lock(&pf->dplls.lock);
1137+
if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
1138+
flags = ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
1139+
if (freq == DPLL_PIN_FREQUENCY_1_HZ) {
1140+
if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) {
1141+
ret = 0;
1142+
} else {
1143+
flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
1144+
ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags,
1145+
0, 0, 0);
1146+
}
1147+
} else {
1148+
if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)) {
1149+
ret = 0;
1150+
} else {
1151+
flags &= ~ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
1152+
ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags,
1153+
0, 0, 0);
1154+
}
1155+
}
1156+
mutex_unlock(&pf->dplls.lock);
1157+
1158+
return ret;
1159+
}
1160+
1161+
/**
1162+
* ice_dpll_output_esync_get - callback for getting embedded sync config
1163+
* @pin: pointer to a pin
1164+
* @pin_priv: private data pointer passed on pin registration
1165+
* @dpll: registered dpll pointer
1166+
* @dpll_priv: private data pointer passed on dpll registration
1167+
* @esync: on success holds embedded sync pin properties
1168+
* @extack: error reporting
1169+
*
1170+
* Dpll subsystem callback. Handler for getting embedded sync frequency value
1171+
* and capabilities on output pin.
1172+
*
1173+
* Context: Acquires pf->dplls.lock
1174+
* Return:
1175+
* * 0 - success
1176+
* * negative - error
1177+
*/
1178+
static int
1179+
ice_dpll_output_esync_get(const struct dpll_pin *pin, void *pin_priv,
1180+
const struct dpll_device *dpll, void *dpll_priv,
1181+
struct dpll_pin_esync *esync,
1182+
struct netlink_ext_ack *extack)
1183+
{
1184+
struct ice_dpll_pin *p = pin_priv;
1185+
struct ice_dpll *d = dpll_priv;
1186+
struct ice_pf *pf = d->pf;
1187+
1188+
if (ice_dpll_is_reset(pf, extack))
1189+
return -EBUSY;
1190+
mutex_lock(&pf->dplls.lock);
1191+
if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY) ||
1192+
p->freq != DPLL_PIN_FREQUENCY_10_MHZ) {
1193+
mutex_unlock(&pf->dplls.lock);
1194+
return -EOPNOTSUPP;
1195+
}
1196+
esync->range = ice_esync_range;
1197+
esync->range_num = ARRAY_SIZE(ice_esync_range);
1198+
if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) {
1199+
esync->freq = DPLL_PIN_FREQUENCY_1_HZ;
1200+
esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT;
1201+
} else {
1202+
esync->freq = 0;
1203+
esync->pulse = 0;
1204+
}
1205+
mutex_unlock(&pf->dplls.lock);
1206+
1207+
return 0;
1208+
}
1209+
1210+
/**
1211+
* ice_dpll_input_esync_set - callback for setting embedded sync
1212+
* @pin: pointer to a pin
1213+
* @pin_priv: private data pointer passed on pin registration
1214+
* @dpll: registered dpll pointer
1215+
* @dpll_priv: private data pointer passed on dpll registration
1216+
* @freq: requested embedded sync frequency
1217+
* @extack: error reporting
1218+
*
1219+
* Dpll subsystem callback. Handler for setting embedded sync frequency value
1220+
* on input pin.
1221+
*
1222+
* Context: Acquires pf->dplls.lock
1223+
* Return:
1224+
* * 0 - success
1225+
* * negative - error
1226+
*/
1227+
static int
1228+
ice_dpll_input_esync_set(const struct dpll_pin *pin, void *pin_priv,
1229+
const struct dpll_device *dpll, void *dpll_priv,
1230+
u64 freq, struct netlink_ext_ack *extack)
1231+
{
1232+
struct ice_dpll_pin *p = pin_priv;
1233+
struct ice_dpll *d = dpll_priv;
1234+
struct ice_pf *pf = d->pf;
1235+
u8 flags_en = 0;
1236+
int ret;
1237+
1238+
if (ice_dpll_is_reset(pf, extack))
1239+
return -EBUSY;
1240+
mutex_lock(&pf->dplls.lock);
1241+
if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
1242+
flags_en = ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
1243+
if (freq == DPLL_PIN_FREQUENCY_1_HZ) {
1244+
if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) {
1245+
ret = 0;
1246+
} else {
1247+
flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
1248+
ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0,
1249+
flags_en, 0, 0);
1250+
}
1251+
} else {
1252+
if (!(p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)) {
1253+
ret = 0;
1254+
} else {
1255+
flags_en &= ~ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
1256+
ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0,
1257+
flags_en, 0, 0);
1258+
}
1259+
}
1260+
mutex_unlock(&pf->dplls.lock);
1261+
1262+
return ret;
1263+
}
1264+
1265+
/**
1266+
* ice_dpll_input_esync_get - callback for getting embedded sync config
1267+
* @pin: pointer to a pin
1268+
* @pin_priv: private data pointer passed on pin registration
1269+
* @dpll: registered dpll pointer
1270+
* @dpll_priv: private data pointer passed on dpll registration
1271+
* @esync: on success holds embedded sync pin properties
1272+
* @extack: error reporting
1273+
*
1274+
* Dpll subsystem callback. Handler for getting embedded sync frequency value
1275+
* and capabilities on input pin.
1276+
*
1277+
* Context: Acquires pf->dplls.lock
1278+
* Return:
1279+
* * 0 - success
1280+
* * negative - error
1281+
*/
1282+
static int
1283+
ice_dpll_input_esync_get(const struct dpll_pin *pin, void *pin_priv,
1284+
const struct dpll_device *dpll, void *dpll_priv,
1285+
struct dpll_pin_esync *esync,
1286+
struct netlink_ext_ack *extack)
1287+
{
1288+
struct ice_dpll_pin *p = pin_priv;
1289+
struct ice_dpll *d = dpll_priv;
1290+
struct ice_pf *pf = d->pf;
1291+
1292+
if (ice_dpll_is_reset(pf, extack))
1293+
return -EBUSY;
1294+
mutex_lock(&pf->dplls.lock);
1295+
if (!(p->status & ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP) ||
1296+
p->freq != DPLL_PIN_FREQUENCY_10_MHZ) {
1297+
mutex_unlock(&pf->dplls.lock);
1298+
return -EOPNOTSUPP;
1299+
}
1300+
esync->range = ice_esync_range;
1301+
esync->range_num = ARRAY_SIZE(ice_esync_range);
1302+
if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) {
1303+
esync->freq = DPLL_PIN_FREQUENCY_1_HZ;
1304+
esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT;
1305+
} else {
1306+
esync->freq = 0;
1307+
esync->pulse = 0;
1308+
}
1309+
mutex_unlock(&pf->dplls.lock);
1310+
1311+
return 0;
1312+
}
1313+
11011314
/**
11021315
* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
11031316
* @pin: pointer to a pin
@@ -1222,6 +1435,8 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
12221435
.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
12231436
.phase_adjust_set = ice_dpll_input_phase_adjust_set,
12241437
.phase_offset_get = ice_dpll_phase_offset_get,
1438+
.esync_set = ice_dpll_input_esync_set,
1439+
.esync_get = ice_dpll_input_esync_get,
12251440
};
12261441

12271442
static const struct dpll_pin_ops ice_dpll_output_ops = {
@@ -1232,6 +1447,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
12321447
.direction_get = ice_dpll_output_direction,
12331448
.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
12341449
.phase_adjust_set = ice_dpll_output_phase_adjust_set,
1450+
.esync_set = ice_dpll_output_esync_set,
1451+
.esync_get = ice_dpll_output_esync_get,
12351452
};
12361453

12371454
static const struct dpll_device_ops ice_dpll_ops = {

‎drivers/net/ethernet/intel/ice/ice_dpll.h

+1
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ struct ice_dpll_pin {
3131
struct dpll_pin_properties prop;
3232
u32 freq;
3333
s32 phase_adjust;
34+
u8 status;
3435
};
3536

3637
/** ice_dpll - store info required for DPLL control

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