vivado_implementation.md

Although the Vivado GUI can be used to help you manage projects, perform simulation, and implement your design, you will need to run the Vivado tools in command line mode for assignments in this class. This page provides instructions and examples for running the implementation tools in vivado for both interactive tcl mode and as a batch script. More details on the Vivado tcl implementation tools can be found here.

Vivado TCL Command Line

To learn how to run the Vivado TCL tools it is best to run them in the interactive TCL mode so you can see their output and become comfortable with the commands. Later you will put all of these commands into a .tcl script that you can run as a batch script as described below.

Enter the Vivado tcl interpreter running vivado in interactive mode as follows:

vivado -mode tcl

You will then enter the various commands to complete the implementation as described below.

Load Files

Before beginning the implementation process, you will need to load your HDL files and constraints files into the Vivado environment.

1. Loading HDL files
   The first step involves compiling your HDL files into a representation that can be synthesized. Although your files have been previously compiled for simulation in QuestaSim, they must be compiled again within the Vivado tools. You can load the files using the read_verilog command with the -sv option. The following example demonstrates how to compile two files in the Vivado tools:

read_verilog -sv tx.sv
read_verilog -sv tx_top.sv

Note that since we are not simulating in this process, you do not need to compile the testbench files - these files are only used for simulation in QuestaSim.

2. Load the xdc files
   The next step involves loading the XDC file that contains the pin constraints for your design. Your design will not be able to be synthesized and implemented without these constraints. This is done using the read_xdc command. The following command demonstrates how to load the .xdc file:

read_xdc top.xdc

Design Synthesis

Once your files are properly loaded into the Vivado environment, you can begin the synthesis process. Synthesis is performed using the synth_design command. This command requires at least two options: the top-level module name and the part number of the FPGA you are targeting. The following example demonstrates how to run the synthesis command for a top-level module named top and the part we are using on the NexysDDR board:

Sometimes you will need to change the top-level parameters of your design as part of the synthesis step. This can be done using the -generic option. For example, the option -generic {BAUD_RATE=115200} would change the top-level BAUD_RATE of your design if you wanted to synthesize a design with a different baud rate.

This command may take some time to execute and will produce a lot of text output. It is possible that the synthesis will fail due to errors in your design. Even though your design simulates correctly, you may have not coded your HDL properly to result in a successful synthesis. You may spend a fair amount of time iterating through your design when you have synthesis errors. If you resolve synthesis errors, you should resimulate your design to make sure it is still working properly.

The synthesis process is very important and there is a lot of important information within the synthesis logs generated by Vivado. You should get in the habit of reviewing this log to learn more about your implemented design. In addition, you should look for any warnings and resolve all warnings before proceeding to implementation. The synthesis tool may generate a number of warnings and you may need to downgrade some warning messages to info messages to get a clean synthesis. This summary describes how to add lines to your .xdc file to adjust the severity of messages generated by the synthesis tool.

Implementation (Placement and Routing)

After generating a successful synthesis, the next step is to complete the implementation process. This involves optimizing your design, placing your design into specific sites within the FPGA, performing routing, and generating a configuration bitstream. These steps are performed by using the following Vivado commands:

opt_design
place_design
route_design

Like the synthesis step, there may be errors in this process that will require you to go back and make changes to your HDL code.

Implementation Checkpoint and Logs

The state of your implemented design is held within the Vivado tool and this state is lost if you quit the tool. It is often important to save the state of your implemented design so you can return to it later. You can save the state of your design by using the write_checkpoint command. You should generate a checkpoint file for every design you implement (i.e., after placement and routing).

Later, you can load the state of your design by using the read_checkpoint command.

There are several commands that will generate reports to help you understand your design. These reports will be required in all of your implementation assignments.

• io: A summary of the I/O ports used in your design
• timing_summary: A summary of your design timing, the timing constraints and violations in your design. We will be carefully reviewing this report in future assignments'
• utilization: A summary of the resources used in your design
• drc: A summary of the "design rule checks" for your design

Execute each of the following commands after implementation to generate these reports:

report_io -file io.rpt
report_timing_summary -max_paths 10 -report_unconstrained -file timing_summary_routed.rpt -warn_on_violation
report_utilization -file utilization_impl.rpt
report_drc -file drc_routed.rpt

Bitstream Generation

If you have successfully completed the implementation process, you can proceed to the bitstream generation step to generate the bitstream for downloading to the FPGA board. The following command demonstrates how to generate the bitstream file:

write_bitstream -force tx.bit

Build Script

It is tedious to type all of these implementation commands in by hand every time you want to implement your design. Further, you need to provide a way to perform this process as part of a makefile without any interaction. You can create a .tcl script that contains all of these commands and run this script to implement your design. For this assignment, create a build .tcl script that contains all of the commands needed to synthesize and implement your design. You can run your implementation script as a single command from the command line as follows: vivado -mode batch -source tx_synth.tcl -log tx_implement.log

The following example demonstrates a tcl script that includes all of these steps:

read_verilog -sv tx.sv
read_verilog -sv tx_top.sv
read_xdc top.xdc
synth_design -top top -part xc7a100tcsg324-1
opt_design
place_design
route_design
write_checkpoint -force checkpoint_impl.dcp
report_io -file io.rpt
report_timing_summary -max_paths 10 -report_unconstrained -file timing_summary_routed.rpt -warn_on_violation
report_utilization -file utilization_impl.rpt
report_drc -file drc_routed.rpt
write_bitstream -force tx.bit