Codegen mismatch

[kassane]

copied from: https://gist.github.com/kassane/7bdb782a1984d0c6581ae7b44e1fc0c2

Initial test:

Sources

export fn __start() void {}

void __start() {}

build output

$> ./zig-bootstrap/out/zig-x86_64-relsafe-espressif-linux-musl-baseline/zig build-obj -target xtensa-freestanding -mcpu=esp32s3 starttt.zig

====== expected this output: =========
e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32␃

======== instead found this: =========
e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32␃

======================================
First difference occurs on line 1:
expected:
e-m:e-p:32:32-v1:8:8-i64:64-i128:128-n32
              ^ ('\x76')
found:
e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32
              ^ ('\x69')
thread 382042 panic: attempt to unwrap error
Unwind error at address `exe:0xa2efae6` (error.InvalidDebugInfo), trace may be incomplete

[1]    382042 IOT instruction (core dumped)  ./zig-bootstrap/out/zig-x86_64-relsafe-espressif-linux-musl-baseline/zig 

$> ./zig-bootstrap/out/zig-x86_64-relsafe-espressif-linux-musl-baseline/zig cc -c -target xtensa-freestanding -mcpu=esp32s3 start.c
$> ./zig-bootstrap/out/host/bin/llvm-objdump -x start.o
start.o:        file format elf32-xtensa
architecture: xtensa
start address: 0x00000000

Program Header:

Dynamic Section:

Sections:
Idx Name             Size     VMA      Type
  0                  00000000 00000000 
  1 .text            00000007 00000000 TEXT
  2 .debug_abbrev    00000027 00000000 DEBUG
  3 .debug_info      00000038 00000000 DEBUG
  4 .rela.debug_info 00000060 00000000 
  5 .debug_str       00000085 00000000 DEBUG
  6 .comment         0000006a 00000000 
  7 .debug_line      00000039 00000000 DEBUG
  8 .rela.debug_line 0000000c 00000000 
  9 .llvm_addrsig    00000000 00000000 
 10 .note.GNU-stack  00000000 00000000 
 11 .symtab          000000a0 00000000 
 12 .shstrtab        0000009b 00000000 
 13 .strtab          0000000f 00000000 

SYMBOL TABLE:
00000000 l    df *ABS*  00000000 start.c
00000000 l    d  .text  00000000 .text
00000000 l    d  .debug_abbrev  00000000 .debug_abbrev
00000000 l    d  .debug_info    00000000 .debug_info
00000000 l    d  .debug_line    00000000 .debug_line
00000000 l    d  .llvm_addrsig  00000000 .llvm_addrsig
00000000 l    d  .debug_str     00000000 .debug_str
00000000 l    d  .comment       00000000 .comment
00000000 g     F .text  00000007 __start

RELOCATION RECORDS FOR [.debug_info]:
OFFSET   TYPE                     VALUE
00000006 R_XTENSA_32              .debug_abbrev
0000000c R_XTENSA_32              .debug_str+0x6
00000012 R_XTENSA_32              .debug_str+0x7d
00000016 R_XTENSA_32              .debug_line
0000001a R_XTENSA_32              .debug_str+0x6f
0000001e R_XTENSA_32              .text
00000027 R_XTENSA_32              .text
00000031 R_XTENSA_32              .debug_str

RELOCATION RECORDS FOR [.debug_line]:
OFFSET   TYPE                     VALUE
0000002f R_XTENSA_32              .text

build C (and maybe C++) works... no zig yet.
Probably found issue on https://github.com/kassane/zig-espressif-bootstrap/blob/xtensa/zig/src/codegen/llvm.zig 🤔

---

Note: This non-upstream support simply seeks to add a new target architecture option, like tools offered by espressif.

• Xtensa Support ziglang/zig#5467
• espressif/llvm-project@d2ada55

[kassane]

update: https://gist.github.com/kassane/7bdb782a1984d0c6581ae7b44e1fc0c2?permalink_comment_id=4917091#gistcomment-4917091

[kassane]

fixed: kassane/zig@869c0da