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vivado_2490.backup.log
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#-----------------------------------------------------------
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
# Start of session at: Mon Mar 20 07:42:36 2023
# Process ID: 2490
# Current directory: /media/jeffee/T7/vivado
# Command line: vivado
# Log file: /media/jeffee/T7/vivado/vivado.log
# Journal file: /media/jeffee/T7/vivado/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /media/jeffee/T7/vivado/UART/UART.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.1/data/ip'.
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
open_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:06 . Memory (MB): peak = 7104.586 ; gain = 36.246 ; free physical = 769 ; free virtual = 2155
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
set_property top uart_top [current_fileset]
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.ip_user_files/bd/uart/ip/uart_Debounce_Switch_0_0/sim/uart_Debounce_Switch_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_Debounce_Switch_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.ip_user_files/bd/uart/ip/uart_uart_top_0_0/sim/uart_uart_top_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_uart_top_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.ip_user_files/bd/uart/sim/uart.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/uart_rx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/uart_tx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/uart_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_top
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/Debounce_Switch.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Debounce_Switch
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/bd/uart/hdl/uart_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sim_1/new/uart_top_TB.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_top_TB
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sim_1/new/uart_rx_TB.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx_TB
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sim_1/new/uart_tx_TB.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx_TB
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.uart_tx(CLK_FREQ=100,BAUD_RATE=1...
Compiling module xil_defaultlib.uart_rx(CLK_FREQ=100,BAUD_RATE=1...
Compiling module xil_defaultlib.uart_top(CLK_FREQ=100,BAUD_RATE=...
Compiling module xil_defaultlib.uart_top_TB
Compiling module xil_defaultlib.glbl
Built simulation snapshot uart_top_TB_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "uart_top_TB_behav -key {Behavioral:sim_1:Functional:uart_top_TB} -tclbatch {uart_top_TB.tcl} -protoinst "protoinst_files/uart.protoinst" -view {/media/jeffee/T7/vivado/UART/uart_top_TB_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
open_wave_config /media/jeffee/T7/vivado/UART/uart_top_TB_behav.wcfg
source uart_top_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'uart_top_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 7225.676 ; gain = 49.797 ; free physical = 546 ; free virtual = 2091
run 1 ms
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
open_bd_design {/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/bd/uart/uart.bd}
Adding component instance block -- xilinx.com:module_ref:Debounce_Switch:1.0 - Debounce_Switch_0
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
CRITICAL WARNING: [BD 41-1726] Unable to resolve module-source for block '/Debounce_Switch_0'.
Given inputs for module-source, Top-module name : Debounce_Switch, Module Type : RTL.
Please review and update or add design-sources to this project to resolve this module-reference.
Adding component instance block -- xilinx.com:module_ref:uart_top:1.0 - uart_top_0
CRITICAL WARNING: [filemgmt 56-176] Module references are not supported in manual compile order mode and will be ignored.
CRITICAL WARNING: [BD 41-1726] Unable to resolve module-source for block '/uart_top_0'.
Given inputs for module-source, Top-module name : uart_top, Module Type : RTL.
Please review and update or add design-sources to this project to resolve this module-reference.
WARNING: [BD 41-1731] Type mismatch between connected pins: /iClk(clk) and /uart_top_0/iClk(undef)
Successfully read diagram <uart> from BD file </media/jeffee/T7/vivado/UART/UART.srcs/sources_1/bd/uart/uart.bd>
open_bd_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 7261.426 ; gain = 0.000 ; free physical = 362 ; free virtual = 1987
regenerate_bd_layout
validate_bd_design -force
WARNING: [BD 41-927] Following properties on pin /uart_top_0/iClk have been updated from connected ip, but BD cell '/uart_top_0' does not accept parameter changes, so they may not be synchronized with cell properties:
PHASE = 0.000
Please resolve any mismatches by directly setting properties on BD cell </uart_top_0> to completely resolve these warnings.
close_bd_design [get_bd_designs uart]
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.ip_user_files/bd/uart/ip/uart_Debounce_Switch_0_0/sim/uart_Debounce_Switch_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_Debounce_Switch_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.ip_user_files/bd/uart/ip/uart_uart_top_0_0/sim/uart_uart_top_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_uart_top_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.ip_user_files/bd/uart/sim/uart.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/uart_rx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/uart_tx.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/uart_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_top
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/new/Debounce_Switch.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module Debounce_Switch
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sources_1/bd/uart/hdl/uart_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sim_1/new/uart_top_TB.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_top_TB
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sim_1/new/uart_rx_TB.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_rx_TB
INFO: [VRFC 10-2263] Analyzing Verilog file "/media/jeffee/T7/vivado/UART/UART.srcs/sim_1/new/uart_tx_TB.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_tx_TB
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.uart_tx(CLK_FREQ=100,BAUD_RATE=1...
Compiling module xil_defaultlib.uart_rx(CLK_FREQ=100,BAUD_RATE=1...
Compiling module xil_defaultlib.uart_top(CLK_FREQ=100,BAUD_RATE=...
Compiling module xil_defaultlib.uart_top_TB
Compiling module xil_defaultlib.glbl
Built simulation snapshot uart_top_TB_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7273.129 ; gain = 11.703 ; free physical = 378 ; free virtual = 1991
run 1 ms
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "uart_top_TB_behav -key {Behavioral:sim_1:Functional:uart_top_TB} -tclbatch {uart_top_TB.tcl} -protoinst "protoinst_files/uart.protoinst" -view {/media/jeffee/T7/vivado/UART/uart_top_TB_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
open_wave_config /media/jeffee/T7/vivado/UART/uart_top_TB_behav.wcfg
source uart_top_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'uart_top_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 7288.137 ; gain = 15.008 ; free physical = 314 ; free virtual = 1933
run 1 ms
export_ip_user_files -of_objects [get_files /media/jeffee/T7/vivado/UART/uart_top_TB_behav.wcfg] -no_script -reset -force -quiet
remove_files -fileset sim_1 /media/jeffee/T7/vivado/UART/uart_top_TB_behav.wcfg
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "uart_top_TB_behav -key {Behavioral:sim_1:Functional:uart_top_TB} -tclbatch {uart_top_TB.tcl} -protoinst "protoinst_files/uart.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
source uart_top_TB.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'uart_top_TB_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 7298.145 ; gain = 2.984 ; free physical = 290 ; free virtual = 1909
run 1 ms
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 7298.145 ; gain = 0.000 ; free physical = 311 ; free virtual = 1933
run 1 ms
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7298.145 ; gain = 0.000 ; free physical = 298 ; free virtual = 1919
run 1 ms
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7298.145 ; gain = 0.000 ; free physical = 294 ; free virtual = 1916
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/tools/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_top_TB' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj uart_top_TB_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/media/jeffee/T7/vivado/UART/UART.sim/sim_1/behav/xsim'
xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 7ad585d8f386467ab5c91725ac5ce52d --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_top_TB_behav xil_defaultlib.uart_top_TB xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Vivado Simulator 2020.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/uart.protoinst
WARNING: [Wavedata 42-558] Couldn't load one or more protocol instances from protoinst file protoinst_files/uart.protoinst for the following reason(s):
There are no instances of module "uart" in the design.
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7298.145 ; gain = 0.000 ; free physical = 288 ; free virtual = 1910
run 80 us
set_property needs_refresh false [get_runs synth_1]
set_property needs_refresh false [get_runs impl_1]
set_property needs_refresh false [get_runs uart_Debounce_Switch_0_0_synth_1]
set_property needs_refresh false [get_runs uart_uart_top_0_0_synth_1]
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Mon Mar 20 07:59:05 2023...