cpu_tb.vcd

$date
	Mon Mar 14 23:06:47 2022
$end
$version
	Icarus Verilog
$end
$timescale
	10ps
$end
$scope module cpu_tb $end
$var wire 8 ! bus [7:0] $end
$var wire 1 " instr_in $end
$var reg 8 # _bus [7:0] $end
$var reg 1 $ address_send $end
$var reg 1 % clk $end
$var reg 1 & debug $end
$var reg 4 ' flags [3:0] $end
$var reg 1 ( instr_load $end
$var reg 4 ) opcode [3:0] $end
$var reg 4 * pr_address [3:0] $end
$var reg 8 + pr_data [7:0] $end
$var reg 1 , pr_mode $end
$var reg 1 - rst $end
$var integer 32 . _cnt [31:0] $end
$scope module cpu_ $end
$var wire 1 $ address_send $end
$var wire 8 / bus [7:0] $end
$var wire 8 0 bus_out [7:0] $end
$var wire 1 % clk $end
$var wire 1 & debug $end
$var wire 4 1 flags [3:0] $end
$var wire 1 2 instr_in $end
$var wire 1 ( instr_load $end
$var wire 1 3 instr_out $end
$var wire 4 4 pr_address [3:0] $end
$var wire 8 5 pr_data [7:0] $end
$var wire 1 , pr_mode $end
$var wire 1 - rst $end
$var wire 8 6 unbuffered_out [7:0] $end
$var wire 4 7 step_out [3:0] $end
$var wire 1 8 reg_out_in $end
$var wire 4 9 reg_flags_in [3:0] $end
$var wire 1 : reg_b_out $end
$var wire 1 ; reg_b_in $end
$var wire 1 < reg_a_out $end
$var wire 1 = reg_a_in $end
$var wire 1 > ram_out $end
$var wire 1 ? ram_in $end
$var wire 4 @ ram_address [3:0] $end
$var wire 1 A pc_out $end
$var wire 1 B pc_jmp $end
$var wire 1 C pc_inc $end
$var wire 4 D opcode [3:0] $end
$var wire 1 E mar_in $end
$var wire 4 F mar_address [3:0] $end
$var wire 1 G halt $end
$var wire 1 H alu_sub $end
$var wire 1 I alu_out $end
$scope module c $end
$var wire 1 % clk $end
$var wire 1 & debug $end
$var wire 4 J flags [3:0] $end
$var wire 1 2 instr_in $end
$var wire 1 3 instr_out $end
$var wire 1 - rst $end
$var wire 4 K step_out [3:0] $end
$var wire 1 8 reg_out_in $end
$var wire 4 L reg_flags_in [3:0] $end
$var wire 1 : reg_b_out $end
$var wire 1 ; reg_b_in $end
$var wire 1 < reg_a_out $end
$var wire 1 = reg_a_in $end
$var wire 1 > ram_out $end
$var wire 1 ? ram_in $end
$var wire 1 A pc_out $end
$var wire 1 B pc_jmp $end
$var wire 1 C pc_inc $end
$var wire 4 M opcode [3:0] $end
$var wire 1 E mar_in $end
$var wire 1 G halt $end
$var wire 1 H alu_sub $end
$var wire 1 I alu_out $end
$var reg 18 N control_bits [17:0] $end
$var reg 4 O step [3:0] $end
$var integer 32 P ADD [31:0] $end
$var integer 32 Q CARRY [31:0] $end
$var integer 32 R HLT [31:0] $end
$var integer 32 S JC [31:0] $end
$var integer 32 T JMP [31:0] $end
$var integer 32 U JZ [31:0] $end
$var integer 32 V LDA [31:0] $end
$var integer 32 W LDB [31:0] $end
$var integer 32 X LDI [31:0] $end
$var integer 32 Y NOP [31:0] $end
$var integer 32 Z OUT [31:0] $end
$var integer 32 [ PARITY [31:0] $end
$var integer 32 \ SIGN [31:0] $end
$var integer 32 ] STA [31:0] $end
$var integer 32 ^ SUB [31:0] $end
$var integer 32 _ ZERO [31:0] $end
$upscope $end
$scope module ir $end
$var wire 8 ` bus_in [7:0] $end
$var wire 1 & debug $end
$var wire 1 2 instr_load_in $end
$var wire 1 3 instr_send_in $end
$var wire 4 a opcode [3:0] $end
$var wire 1 - rst $end
$var wire 4 b address_out [3:0] $end
$var reg 4 c high [3:0] $end
$var reg 4 d low [3:0] $end
$upscope $end
$scope module mar_ $end
$var wire 4 e address_in [3:0] $end
$var wire 4 f address_out [3:0] $end
$var wire 1 & debug $end
$var wire 1 E enable_in $end
$var wire 1 - rst $end
$var reg 4 g _address [3:0] $end
$upscope $end
$scope module mx24 $end
$var wire 4 h address_1 [3:0] $end
$var wire 4 i address_2 [3:0] $end
$var wire 1 , select $end
$var wire 4 j address_out [3:0] $end
$upscope $end
$scope module pc $end
$var wire 8 k cnt [7:0] $end
$var wire 1 & debug $end
$var wire 1 C inc $end
$var wire 1 A out_en $end
$var wire 1 - rst $end
$var reg 4 l _cnt [3:0] $end
$var reg 8 m _cnt_buffer [7:0] $end
$upscope $end
$scope module r $end
$var wire 4 n address [3:0] $end
$var wire 8 o bus [7:0] $end
$var wire 1 & debug $end
$var wire 8 p prg_data [7:0] $end
$var wire 1 , prg_mode $end
$var wire 1 > re_en $end
$var wire 1 ? wr_en $end
$scope begin $ivl_for_loop0 $end
$var integer 32 q i [31:0] $end
$upscope $end
$upscope $end
$scope module reg_a $end
$var wire 8 r bus [7:0] $end
$var wire 8 s bus_out [7:0] $end
$var wire 1 = data_load $end
$var wire 1 < data_send $end
$var wire 1 & debug $end
$var wire 1 - rst $end
$var wire 8 t unbuffered_out [7:0] $end
$var reg 8 u data [7:0] $end
$upscope $end
$scope module reg_b $end
$var wire 8 v bus [7:0] $end
$var wire 8 w bus_out [7:0] $end
$var wire 1 ; data_load $end
$var wire 1 : data_send $end
$var wire 1 & debug $end
$var wire 1 - rst $end
$var wire 8 x unbuffered_out [7:0] $end
$var reg 8 y data [7:0] $end
$upscope $end
$scope module reg_out $end
$var wire 8 z bus [7:0] $end
$var wire 8 { bus_out [7:0] $end
$var wire 1 8 data_load $end
$var wire 1 : data_send $end
$var wire 1 & debug $end
$var wire 1 - rst $end
$var wire 8 | unbuffered_out [7:0] $end
$var reg 8 } data [7:0] $end
$upscope $end
$upscope $end
$scope begin $ivl_for_loop1 $end
$var integer 32 ~ i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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$end
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