logic.vhd.bak

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 8.0 (Build Build 231 07/10/2008)
-- Created on Thu Oct 20 15:31:09 2011

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY logic IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		C0 : IN STD_LOGIC;
		P0 : IN STD_LOGIC;
		P1 : IN STD_LOGIC;
		P2 : IN STD_LOGIC;
		P3 : IN STD_LOGIC;
		G0 : IN STD_LOGIC;
		G1 : IN STD_LOGIC;
		G2 : IN STD_LOGIC;
		G3 : IN STD_LOGIC;
		C1 : OUT STD_LOGIC;
		C2 : OUT STD_LOGIC;
		C3 : OUT STD_LOGIC;
		C4 : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END logic;


--  Architecture Body

ARCHITECTURE logic_architecture OF logic IS

	
BEGIN
	C1 <= G0 or (P0 and G0);
	C2 <= G1 or (P1 and G0) or (P1 and P0 and C0);
	C3 <= G2 or (P2 and G1) or (P2 and P1 and G0) or (P2 and P1 and P0 and C0);
	C4 <= G3 or (P3 and G2) or (P3 and P2 and P1 and G0) or (P3 and P2 and P1 and C0);
END logic_architecture;