@@ -91,6 +91,26 @@ _FL_DEFPIN(12, BSP_IO_PORT_01_PIN_10, R_PORT1_BASE ); _FL_DEFPIN(13, BSP_IO_PORT
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_FL_DEFPIN (14 , BSP_IO_PORT_00_PIN_14, R_PORT0_BASE ); _FL_DEFPIN(15 , BSP_IO_PORT_00_PIN_00, R_PORT0_BASE ); _FL_DEFPIN(16 , BSP_IO_PORT_00_PIN_01, R_PORT0_BASE );
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_FL_DEFPIN (17 , BSP_IO_PORT_00_PIN_02, R_PORT0_BASE ); _FL_DEFPIN(18 , BSP_IO_PORT_01_PIN_01, R_PORT1_BASE ); _FL_DEFPIN(19 , BSP_IO_PORT_01_PIN_00, R_PORT1_BASE );
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+ #elif defined(ARDUINO_THINGPLUS_RA6M5)
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+
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+ #define MAX_PIN 24
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+ // D0-D06
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+ _FL_DEFPIN ( 0 , BSP_IO_PORT_01_PIN_12, R_PORT1_BASE ); _FL_DEFPIN( 1 , BSP_IO_PORT_04_PIN_06, R_PORT4_BASE ); _FL_DEFPIN( 2 , BSP_IO_PORT_04_PIN_05, R_PORT4_BASE );
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+ _FL_DEFPIN ( 3 , BSP_IO_PORT_04_PIN_04, R_PORT4_BASE ); _FL_DEFPIN( 4 , BSP_IO_PORT_04_PIN_03, R_PORT4_BASE ); _FL_DEFPIN( 5 , BSP_IO_PORT_04_PIN_02, R_PORT4_BASE );
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+ _FL_DEFPIN ( 6 , BSP_IO_PORT_02_PIN_07, R_PORT2_BASE );
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+
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+ // D07-D12 (A0-A5)
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+ _FL_DEFPIN ( 7 , BSP_IO_PORT_00_PIN_14, R_PORT0_BASE ); _FL_DEFPIN( 8 , BSP_IO_PORT_00_PIN_15, R_PORT0_BASE ); _FL_DEFPIN( 9 , BSP_IO_PORT_05_PIN_05, R_PORT5_BASE );
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+ _FL_DEFPIN (10 , BSP_IO_PORT_05_PIN_04, R_PORT5_BASE ); _FL_DEFPIN(11 , BSP_IO_PORT_05_PIN_03, R_PORT5_BASE ); _FL_DEFPIN(12 , BSP_IO_PORT_05_PIN_02, R_PORT5_BASE );
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+
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+ // D13-D21
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+ _FL_DEFPIN (13 , BSP_IO_PORT_01_PIN_05, R_PORT1_BASE ); _FL_DEFPIN(14 , BSP_IO_PORT_01_PIN_06, R_PORT1_BASE ); _FL_DEFPIN(15 , BSP_IO_PORT_04_PIN_01, R_PORT4_BASE );
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+ _FL_DEFPIN (16 , BSP_IO_PORT_04_PIN_00, R_PORT4_BASE ); _FL_DEFPIN(17 , BSP_IO_PORT_01_PIN_10, R_PORT1_BASE ); _FL_DEFPIN(18 , BSP_IO_PORT_01_PIN_09, R_PORT1_BASE );
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+ _FL_DEFPIN (19 , BSP_IO_PORT_01_PIN_11, R_PORT1_BASE ); _FL_DEFPIN(20 , BSP_IO_PORT_04_PIN_09, R_PORT4_BASE ); _FL_DEFPIN(21 , BSP_IO_PORT_04_PIN_08, R_PORT4_BASE );
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+
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+ // D30-31
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+ _FL_DEFPIN (30 , BSP_IO_PORT_03_PIN_04, R_PORT3_BASE ); _FL_DEFPIN(31 , BSP_IO_PORT_04_PIN_15, R_PORT4_BASE );
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+
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#elif defined(ARDUINO_ARCH_RENESAS_PORTENTA)
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#define MAX_PIN 22
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