From 733d0ffbf435f9d90ca450478097c71eab6cb329 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jan=20K=C3=A4berich?= <j.kaeberich@gmx.de>
Date: Sun, 5 Jan 2025 18:15:30 +0100
Subject: [PATCH] fix order of LO1 and source unlock LEDs

---
 FPGA/VNA/VNA.gise |  30 ++++++++++++++++++++++--------
 FPGA/VNA/top.bin  | Bin 341712 -> 341712 bytes
 FPGA/VNA/top.vhd  |   4 ++--
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/FPGA/VNA/VNA.gise b/FPGA/VNA/VNA.gise
index 4fb88621..8529fb80 100644
--- a/FPGA/VNA/VNA.gise
+++ b/FPGA/VNA/VNA.gise
@@ -140,6 +140,10 @@
     <transform xil_pn:end_ts="1735897915" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1735897915">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="DFT.vhd"/>
       <outfile xil_pn:name="MAX2871.vhd"/>
       <outfile xil_pn:name="MCP33131.vhd"/>
@@ -174,6 +178,7 @@
     <transform xil_pn:end_ts="1735887598" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735887598">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
@@ -187,6 +192,11 @@
     <transform xil_pn:end_ts="1735897915" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1735897915">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="DFT.vhd"/>
       <outfile xil_pn:name="MAX2871.vhd"/>
       <outfile xil_pn:name="MCP33131.vhd"/>
@@ -218,7 +228,10 @@
     <transform xil_pn:end_ts="1735898134" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8439971377188504826" xil_pn:start_ts="1735898132">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="Test_SPICommands_beh.prj"/>
       <outfile xil_pn:name="Test_SPICommands_isim_beh.exe"/>
@@ -230,6 +243,7 @@
     <transform xil_pn:end_ts="1735898134" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6574364550222252173" xil_pn:start_ts="1735898134">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="Test_SPICommands_isim_beh.wdb"/>
@@ -244,7 +258,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1735889214" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1735889214">
+    <transform xil_pn:end_ts="1736097035" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1736097035">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@@ -273,7 +287,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1735898634" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1735898623">
+    <transform xil_pn:end_ts="1736097046" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1736097035">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -291,11 +305,11 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1735898634" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1735898634">
+    <transform xil_pn:end_ts="1736097046" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1736097046">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1735898638" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1735898634">
+    <transform xil_pn:end_ts="1736097050" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1736097046">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -304,7 +318,7 @@
       <outfile xil_pn:name="top.ngd"/>
       <outfile xil_pn:name="top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1735898720" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1735898638">
+    <transform xil_pn:end_ts="1736097131" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1736097050">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -318,7 +332,7 @@
       <outfile xil_pn:name="top_summary.xml"/>
       <outfile xil_pn:name="top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1735898743" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1735898720">
+    <transform xil_pn:end_ts="1736097154" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1736097131">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -333,7 +347,7 @@
       <outfile xil_pn:name="top_pad.txt"/>
       <outfile xil_pn:name="top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1735898752" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1735898743">
+    <transform xil_pn:end_ts="1736097164" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1736097154">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -386,7 +400,7 @@
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="InputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1735898743" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1735898738">
+    <transform xil_pn:end_ts="1736097154" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1736097149">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
diff --git a/FPGA/VNA/top.bin b/FPGA/VNA/top.bin
index 38369cdc019243c1bbb820c6ed70d00ab99ff85b..38af89c7edb97085c8101c282d92f4b5973da3f4 100644
GIT binary patch
delta 565
zcmaKoPiPZS5XN`j+qdtzZp_A{k=9h#ij^X2^KZdRDe6rK#iAa)^dNYt7X|gAlp=*<
z!UG3HFnAFnN^q&Kh?EFI1yNT-At(RPW)IR5u{9z}ebsC6GKX(|-^_dyE~UbyRQ*H^
z40*D41&dFpD__0k!E!AXgK|J;kH+x<11A`rf1i<c(~`q23tR*N-Ia!o)xA_pLrFQF
zIVj!Fc5rXu7RV^d%l6D6Y@eenm~G8C|2RLJ)7+ru651QIzpZ_OtE&AD5-xsN1WS%|
z1WtE|z-=wK142D+0R=E{E`ohnUDV3g2uQ5buw?kc#_pRmjc0x0Fku+RHMy&_UF#MI
znayVK<9Fy;FG5YNLPS8|(+=svOh4U%<rT2i?H}+4aO4-^c;P2p(pG`bSBZCHfc9Wm
zAe-;j1ptO=dglK{huXg$N`}+6I=u$VO}(_#B)@yHx``ZCI?^*zX>eJ-%rW_ep4xES
z>jH65ZyeX7c%W?8+z`{}jLDr|O!n^a^pi(5&2VljB>&Qt2E*Yo;P~=5<&!3zG|fjQ
zqX+1a%A=cO{pjVGt^6G80=nbjeO1b{1n~HgiNQWF@nVq;;PnDqpiXl_oiFMhji-H_
O^4V_6kIiG<XWkzUE7GR`

delta 544
zcmZWlO-K}R6!-n#{AXrIS7&r}`xtBcU}e!*+uVhMq7Q;jLI;Jqw1=QWPzK_Hf@mOy
zC^h`4cL@{^1slP_P~$;jZuWJU4jrV6n(RWM444^0*nc}M_27NL@AuyOy%%i6f{j?I
zuLxZ97sn}e2V2CzUB%rj#-fzhSiKuvIMW0d+$&3~wq@2;P5B$EwJw}@hiR?@RdN2D
zY_!wDTr=Dk>ra6Svv^SC2d`3i54pQge%0Xks#v+LQfY*73diuW<2Osb<@kmhZtbl?
zofm!v%cOW7qBOn3A`~yfyoirl^u7#RpwpWQbb{`Et3V_wf)6USS6HL4M;qV)buVJ8
zOyd)HqzZ}L$vE5>`LFwF<)`eK+J*`f^T*rBPGTcH`T>SF`wKpS<7-sdg%K%5C-Vy^
z^l_WnPf~b*f*w}?yrcujL&U%C_{pkz5zH9gjXl_0mil{_+3$8qyhu%Dx%2T3TVymB
zVXDd%U4D+N?|7|d&>#)$f=1~RsME`Rct}Ehlt^Po4d=hbwHS@H;pxecp>)Ly8E;8r
zv-XzE3{O%b!woN&;jMsYmkM6*DQ<zLJ-gL?R315;<tcjD!`HFv`Xz5DD>3ZKzNV=h
NKZdq(lS(<B_yYku%BcVV

diff --git a/FPGA/VNA/top.vhd b/FPGA/VNA/top.vhd
index 89b8ea1a..33df71b8 100644
--- a/FPGA/VNA/top.vhd
+++ b/FPGA/VNA/top.vhd
@@ -459,8 +459,8 @@ begin
 	LEDS(0) <= user_leds(2);
 	-- Lock status of PLLs
 	LEDS(1) <= clk_locked;
-	LEDS(2) <= SOURCE_LD;
-	LEDS(3) <= LO1_LD;
+	LEDS(2) <= LO1_LD;
+	LEDS(3) <= SOURCE_LD;
 	-- Sweep and active port
 	PORT_SELECT2 <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);
 	PORT2_SELECT <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);