New revision of Simple UART for FPGA

Author: jakubcabal

README.md

@@ -2,19 +2,16 @@
 
 Simple UART (Universal Asynchronous Receiver & Transmitter) module for serial communication with an FPGA. The UART module was implemented using VHDL.
 
-**The default settings are 115200 baud rate, 8 data bits, 1 stop bit, no parity, disable input data FIFO, 50 MHz system clock.**
+**Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!**
 
-The UART module was tested in hardware. In the near future it will be implemented generic support settings of stop bits. Stay tuned!
+The UART module was simulated and tested in hardware.
 
 **Synthesis resource usage summary:**
 
-Parity | Input FIFO | LE (LUT) | FF | BRAM
---- | --- | --- | --- | ---
-none | disable | 72 | 46 | 0
-none | enable | 110 | 63 | 1
-even/odd | disable | 82 | 49 | 0
-even/odd | enable | 121 | 66 | 1
-mark/space | disable | 77 | 49 | 0
-mark/space | enable | 115 | 66 | 1
+Parity | LE (LUT) | FF | BRAM
+--- | --- | --- | ---
+none | 80 | 55 | 0
+even/odd | 91 | 58 | 0
+mark/space | 84 | 58 | 0
 
-*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 with default settings for FPGA Altera Cyclone II.*
+*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 for FPGA Altera Cyclone II with these settings: 115200 baud rate and 50 MHz system clock .*

example/uart_loopback.vhd

@@ -1,103 +1,67 @@
--- The MIT License (MIT)
---
--- Copyright (c) 2015 Jakub Cabal
---
--- Permission is hereby granted, free of charge, to any person obtaining a copy
--- of this software and associated documentation files (the "Software"), to deal
--- in the Software without restriction, including without limitation the rights
--- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--- copies of the Software, and to permit persons to whom the Software is
--- furnished to do so, subject to the following conditions:
---
--- The above copyright notice and this permission notice shall be included in
--- all copies or substantial portions of the Software.
--- 
--- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--- SOFTWARE.
---
--- Website: https://github.com/jakubcabal/uart_for_fpga
+--------------------------------------------------------------------------------
+-- PROJECT: SIMPLE UART FOR FPGA
+--------------------------------------------------------------------------------
+-- MODULE:  UART LOOPBACK EXAMPLE TOP MODULE
+-- AUTHORS: Jakub Cabal <[email protected]>
+-- lICENSE: The MIT License (MIT)
+-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
 --------------------------------------------------------------------------------
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
- 
+
+-- UART FOR FPGA REQUIRES: 1 START BIT, 8 DATA BITS, 1 STOP BIT!!!
+-- OTHER PARAMETERS CAN BE SET USING GENERICS.
+
 entity UART_LOOPBACK is
     Generic (
-        BAUD_RATE  : integer := 115200; -- baud rate value
-        DATA_BITS  : integer := 8;      -- legal values: 5,6,7,8
-        PARITY_BIT : string  := "none"; -- legal values: "none", "even", "odd", "mark", "space"
         CLK_FREQ   : integer := 50e6;   -- set system clock frequency in Hz
-        INPUT_FIFO : boolean := True;   -- enable input data FIFO
-        FIFO_DEPTH : integer := 256     -- set depth of input data FIFO
+        BAUD_RATE  : integer := 115200; -- baud rate value
+        PARITY_BIT : string  := "none"  -- legal values: "none", "even", "odd", "mark", "space"
     );
     Port (
         CLK        : in  std_logic; -- system clock
         RST_N      : in  std_logic; -- low active synchronous reset
         -- UART INTERFACE
-        TX_UART    : out std_logic;
-        RX_UART    : in  std_logic;
+        UART_TXD   : out std_logic;
+        UART_RXD   : in  std_logic;
         -- DEBUG INTERFACE
         BUSY       : out std_logic;
-        FRAME_ERR  : out std_logic;
-        DATA_VLD   : out std_logic
+        FRAME_ERR  : out std_logic
     );
 end UART_LOOPBACK;
 
 architecture FULL of UART_LOOPBACK is
 
-    signal data        : std_logic_vector(DATA_BITS-1 downto 0);
-    signal valid       : std_logic;
-    signal reset       : std_logic;
-    signal frame_error : std_logic;
-    signal send        : std_logic;
+    signal data    : std_logic_vector(7 downto 0);
+    signal valid   : std_logic;
+    signal reset   : std_logic;
 
 begin
 
 	reset <= not RST_N;
-	send <= valid WHEN (frame_error = '0') ELSE '0';
- 
+
 	uart_i: entity work.UART
     generic map (
-        BAUD_RATE   => BAUD_RATE,
-        DATA_BITS   => DATA_BITS,
-        PARITY_BIT  => PARITY_BIT,
         CLK_FREQ    => CLK_FREQ,
-        INPUT_FIFO  => INPUT_FIFO,
-        FIFO_DEPTH  => FIFO_DEPTH
+        BAUD_RATE   => BAUD_RATE,
+        PARITY_BIT  => PARITY_BIT
     )
     port map (
         CLK         => CLK,
         RST         => reset,
         -- UART INTERFACE
-        TX_UART     => TX_UART,
-        RX_UART     => RX_UART,
+        UART_TXD    => UART_TXD,
+        UART_RXD    => UART_RXD,
         -- USER DATA OUTPUT INTERFACE
         DATA_OUT    => data,
         DATA_VLD    => valid,
-        FRAME_ERROR => frame_error,
+        FRAME_ERROR => FRAME_ERR,
         -- USER DATA INPUT INTERFACE
         DATA_IN     => data,
-        DATA_SEND   => send,
+        DATA_SEND   => valid,
         BUSY        => BUSY
     );
 
-    frame_err_gen : process (CLK)
-    begin
-        if (rising_edge(CLK)) then
-            if (reset = '1') then
-                FRAME_ERR <= '0';
-            elsif (valid = '1') then
-            	FRAME_ERR <= frame_error;
-            end if;
-        end if;
-    end process;
-
-    DATA_VLD <= valid;
-
-end FULL;
+end FULL;

example/uart_loopback_tb.vhd

@@ -1,71 +1,50 @@
--- The MIT License (MIT)
---
--- Copyright (c) 2015 Jakub Cabal
---
--- Permission is hereby granted, free of charge, to any person obtaining a copy
--- of this software and associated documentation files (the "Software"), to deal
--- in the Software without restriction, including without limitation the rights
--- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--- copies of the Software, and to permit persons to whom the Software is
--- furnished to do so, subject to the following conditions:
---
--- The above copyright notice and this permission notice shall be included in
--- all copies or substantial portions of the Software.
--- 
--- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--- SOFTWARE.
---
--- Website: https://github.com/jakubcabal/uart_for_fpga
+--------------------------------------------------------------------------------
+-- PROJECT: SIMPLE UART FOR FPGA
+--------------------------------------------------------------------------------
+-- MODULE:  TESTBANCH OF UART LOOPBACK EXAMPLE TOP MODULE
+-- AUTHORS: Jakub Cabal <[email protected]>
+-- lICENSE: The MIT License (MIT)
+-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
 --------------------------------------------------------------------------------
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
- 
+
 entity UART_LOOPBACK_TB is
 end UART_LOOPBACK_TB;
- 
-architecture FULL of UART_LOOPBACK_TB is 
-
-	signal CLK         : std_logic := '0';
-	signal RST_N       : std_logic := '0';
-	signal tx_uart     : std_logic;
-	signal rx_uart     : std_logic := '1';
-	signal data_vld    : std_logic;
-	signal frame_error : std_logic;
-	signal busy        : std_logic;
-
-   	constant clk_period  : time := 20 ns;
-	constant uart_period : time := 8696 ns;
+
+architecture FULL of UART_LOOPBACK_TB is
+
+	signal CLK           : std_logic := '0';
+	signal RST_N         : std_logic := '0';
+	signal tx_uart       : std_logic;
+	signal rx_uart       : std_logic := '1';
+    signal busy          : std_logic;
+    signal frame_error   : std_logic;
+
+  	constant clk_period  : time := 20 ns;
+	constant uart_period : time := 8680.56 ns;
 	constant data_value  : std_logic_vector(7 downto 0) := "10100111";
 	constant data_value2 : std_logic_vector(7 downto 0) := "00110110";
- 
+
 begin
- 
+
 	utt: entity work.UART_LOOPBACK
     generic map (
-        BAUD_RATE   => 115200,
-        DATA_BITS   => 8,
-        PARITY_BIT  => "none",
         CLK_FREQ    => 50e6,
-        INPUT_FIFO  => True,
-        FIFO_DEPTH  => 256
+        BAUD_RATE   => 115200,
+        PARITY_BIT  => "none"
     )
     port map (
         CLK         => CLK,
         RST_N       => RST_N,
-        -- UART RS232 INTERFACE
-        TX_UART     => tx_uart,
-        RX_UART     => rx_uart,
+        -- UART INTERFACE
+        UART_TXD    => tx_uart,
+        UART_RXD    => rx_uart,
         -- DEBUG INTERFACE
         BUSY        => busy,
-        FRAME_ERR   => frame_error,
-        DATA_VLD    => data_vld
+        FRAME_ERR   => frame_error
     );
 
 	clk_process : process
@@ -81,16 +60,16 @@ begin
 		rx_uart <= '1';
 		RST_N <= '0';
 		wait for 100 ns;
-      	RST_N <= '1';
+    	RST_N <= '1';
 
 		wait for uart_period;
 
 		rx_uart <= '0'; -- start bit
 		wait for uart_period;
 
-		for i in 0 to 7 loop
-			rx_uart <= data_value(i); -- data bits
-			wait for uart_period;
+		for i in 0 to (data_value'LENGTH-1) loop
+		    rx_uart <= data_value(i); -- data bits
+		    wait for uart_period;
 		end loop;
 
 		rx_uart <= '1'; -- stop bit
@@ -99,9 +78,9 @@ begin
 		rx_uart <= '0'; -- start bit
 		wait for uart_period;
 
-		for i in 0 to 7 loop
-			rx_uart <= data_value2(i); -- data bits
-			wait for uart_period;
+		for i in 0 to (data_value2'LENGTH-1) loop
+  			rx_uart <= data_value2(i); -- data bits
+        	wait for uart_period;
 		end loop;
 
 		rx_uart <= '1'; -- stop bit
@@ -110,7 +89,7 @@ begin
 		rx_uart <= '0'; -- start bit
 		wait for uart_period;
 
-		for i in 0 to 7 loop
+		for i in 0 to (data_value'LENGTH-1) loop
 			rx_uart <= data_value(i); -- data bits
 			wait for uart_period;
 		end loop;
@@ -121,7 +100,7 @@ begin
 		rx_uart <= '0'; -- start bit
 		wait for uart_period;
 
-		for i in 0 to 7 loop
+		for i in 0 to (data_value2'LENGTH-1) loop
 			rx_uart <= data_value2(i); -- data bits
 			wait for uart_period;
 		end loop;
@@ -133,4 +112,4 @@ begin
 
 	end process;
 
-end FULL;
+end FULL;