diff --git a/compiler/src/iree/compiler/Codegen/Common/test/propagate_reshapes_by_expansion.mlir b/compiler/src/iree/compiler/Codegen/Common/test/propagate_reshapes_by_expansion.mlir
index db715dea9d07..94ddf0e2e07e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/test/propagate_reshapes_by_expansion.mlir
+++ b/compiler/src/iree/compiler/Codegen/Common/test/propagate_reshapes_by_expansion.mlir
@@ -10,7 +10,7 @@ func.func @reshape_and_lowering_config(%src: tensor<3x4xf16>, %dest: tensor<12xf
 
 // CHECK-LABEL: func @reshape_and_lowering_config
 //  CHECK-SAME:   %[[SRC:[A-Za-z0-9]+]]: tensor<3x4xf16>
-//       CHECK:   %[[COPY1:.+]] = linalg.generic {{.*}} ins(%[[SRC]]
+//       CHECK:   %[[COPY1:.+]] = linalg.copy{{.*}} ins(%[[SRC]]
 //       CHECK:   %[[COLLAPSE:.+]] = tensor.collapse_shape %[[COPY1]]
 //       CHECK:   linalg.copy
 //  CHECK-SAME:     lowering_config = #iree_gpu.derived_thread_config
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_pipeline_test.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_pipeline_test.mlir
index b4f8d8259925..1cea88a10082 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_pipeline_test.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/rocdl_pipeline_test.mlir
@@ -96,54 +96,6 @@ hal.executable @dot_dispatch_0 {
 
 // -----
 
-#map = affine_map<(d0) -> (d0)>
-#pipeline_layout = #hal.pipeline.layout<bindings = [
-  #hal.pipeline.binding<storage_buffer>,
-  #hal.pipeline.binding<storage_buffer>,
-  #hal.pipeline.binding<storage_buffer>
-]>
-hal.executable @ext_fp8_dispatch {
-  hal.executable.variant @rocm_hsaco_fb target(<"rocm", "rocm-hsaco-fb">) {
-    hal.executable.export @ext_fp8_dispatch layout(#pipeline_layout) {
-    ^bb0(%arg0: !hal.device, %arg1: index, %arg2 : index, %arg3 : index):
-      %x, %y, %z = flow.dispatch.workgroup_count_from_dag_root %arg1, %arg2, %arg3
-      hal.return %x, %y, %z : index, index, index
-    }
-    builtin.module {
-      func.func @ext_fp8_dispatch() {
-        %c0 = arith.constant 0 : index
-        %0 = hal.interface.binding.subspan layout(#pipeline_layout) binding(0) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<4096xf8E4M3FNUZ>>
-        %1 = hal.interface.binding.subspan layout(#pipeline_layout) binding(1) alignment(64) offset(%c0) flags(ReadOnly) : !flow.dispatch.tensor<readonly:tensor<4096xf8E5M2FNUZ>>
-        %2 = hal.interface.binding.subspan layout(#pipeline_layout) binding(2) alignment(64) offset(%c0) : !flow.dispatch.tensor<writeonly:tensor<4096xf32>>
-        %3 = flow.dispatch.tensor.load %0, offsets = [0], sizes = [4096], strides = [1] : !flow.dispatch.tensor<readonly:tensor<4096xf8E4M3FNUZ>> -> tensor<4096xf8E4M3FNUZ>
-        %4 = flow.dispatch.tensor.load %1, offsets = [0], sizes = [4096], strides = [1] : !flow.dispatch.tensor<readonly:tensor<4096xf8E5M2FNUZ>> -> tensor<4096xf8E5M2FNUZ>
-        %5 = tensor.empty() : tensor<4096xf32>
-        %6 = linalg.generic {indexing_maps = [#map, #map, #map],
-                             iterator_types = ["parallel"]}
-                             ins(%3, %4 : tensor<4096xf8E4M3FNUZ>, tensor<4096xf8E5M2FNUZ>)
-                             outs(%5 : tensor<4096xf32>) {
-        ^bb0(%in0: f8E4M3FNUZ, %in1: f8E5M2FNUZ, %out: f32):
-          %7 = arith.extf %in0 : f8E4M3FNUZ to f32
-          %8 = arith.extf %in1 : f8E5M2FNUZ to f32
-          %9 = arith.addf %7, %8 : f32
-          linalg.yield %9 : f32
-        } -> tensor<4096xf32>
-        flow.dispatch.tensor.store %6, %2, offsets = [0], sizes = [4096], strides = [1] : tensor<4096xf32> -> !flow.dispatch.tensor<writeonly:tensor<4096xf32>>
-        return
-      }
-    }
-  }
-}
-
-//   CDNA3-LABEL: hal.executable public @ext_fp8_dispatch
-//         CDNA3:   hal.executable.variant public @rocm
-// CDNA3-COUNT-16:     rocdl.cvt.f32.fp8 %{{.*}} : f32
-// CDNA3-COUNT-16:     rocdl.cvt.f32.bf8 %{{.*}} : f32
-//         CDNA3:     %[[ADD:.+]] = llvm.fadd %{{.*}}, %{{.*}} : vector<16xf32>
-//         CDNA3:     llvm.store %[[ADD]], %{{.*}} : vector<16xf32>, !llvm.ptr<1>
-
-// -----
-
 // Verify that the ceildivsi op gets expanded and lowered successfully all the way to
 // the llvm dialect.
 
diff --git a/tests/e2e/regression/BUILD.bazel b/tests/e2e/regression/BUILD.bazel
index e9760ca97582..be0ad07c4c7b 100644
--- a/tests/e2e/regression/BUILD.bazel
+++ b/tests/e2e/regression/BUILD.bazel
@@ -193,7 +193,6 @@ iree_check_single_backend_test_suite(
     name = "check_regression_compilation_only_vmvx_ukernels",
     srcs = [
         "dynamic_matmuls_on_same_accumulator_issue_12060.mlir",
-        "dynamic_tosa_clamp.mlir",
     ],
     compiler_flags = [
         "--iree-vmvx-enable-microkernels",
diff --git a/tests/e2e/regression/CMakeLists.txt b/tests/e2e/regression/CMakeLists.txt
index 9e56ebceb717..bb18506f745d 100644
--- a/tests/e2e/regression/CMakeLists.txt
+++ b/tests/e2e/regression/CMakeLists.txt
@@ -237,7 +237,6 @@ iree_check_single_backend_test_suite(
     check_regression_compilation_only_vmvx_ukernels
   SRCS
     "dynamic_matmuls_on_same_accumulator_issue_12060.mlir"
-    "dynamic_tosa_clamp.mlir"
   TARGET_BACKEND
     "vmvx"
   COMPILER_FLAGS
diff --git a/tests/e2e/regression/dynamic_tosa_clamp.mlir b/tests/e2e/regression/dynamic_tosa_clamp.mlir
deleted file mode 100644
index 25b0e2027559..000000000000
--- a/tests/e2e/regression/dynamic_tosa_clamp.mlir
+++ /dev/null
@@ -1,6 +0,0 @@
-// Minimized from dynamic_tosa_quantized_fully_connected_issue_10859.mlir
-
-func.func @clamp(%arg0: tensor<?xi8>) ->tensor<?xi8>{
-  %1 = tosa.clamp %arg0 {max_val = 127 : i8, min_val = -128 : i8} : (tensor<?xi8>) -> tensor<?xi8>
-  return %1 : tensor<?xi8>
-}
diff --git a/third_party/llvm-project b/third_party/llvm-project
index e481943f5f02..4c4fd6b03149 160000
--- a/third_party/llvm-project
+++ b/third_party/llvm-project
@@ -1 +1 @@
-Subproject commit e481943f5f02ce841677cd0a08ca1651c89384a7
+Subproject commit 4c4fd6b03149348cf11af245ad2603d24144a9d5