From 8653c3c58637b91b957d08295585409d0810dd75 Mon Sep 17 00:00:00 2001
From: mkorbel1 <max.korbel@intel.com>
Date: Fri, 22 Sep 2023 18:55:48 +0000
Subject: [PATCH] =?UTF-8?q?Deploying=20to=20docs=20from=20@=20intel/rohd@8?=
 =?UTF-8?q?e9959ca45e4ff5fd4d7af6b2ac915aae66b27aa=20=F0=9F=9A=80?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 rohd/Module/inputs.html                                   | 8 +++++++-
 .../instantiationVerilogWithParameters.html               | 4 ++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/rohd/Module/inputs.html b/rohd/Module/inputs.html
index 6fe332625..7873a1250 100644
--- a/rohd/Module/inputs.html
+++ b/rohd/Module/inputs.html
@@ -66,6 +66,11 @@ <h1><span class="kind-property">inputs</span> property
 
 <section class="multi-line-signature">
   
+  <div>
+    <ol class="annotation-list">
+        <li>@<a href="https://pub.dev/documentation/meta/1.10.0/meta/protected-constant.html">protected</a></li>
+    </ol>
+  </div>
   <span class="returntype"><a href="https://api.dart.dev/stable/3.1.2/dart-core/Map-class.html">Map</a><span class="signature">&lt;<wbr><span class="type-parameter"><a href="https://api.dart.dev/stable/3.1.2/dart-core/String-class.html">String</a></span>, <span class="type-parameter"><a href="../../rohd/Logic-class.html">Logic</a></span>&gt;</span></span>
   <span class="name ">inputs</span>
   
@@ -81,7 +86,8 @@ <h1><span class="kind-property">inputs</span> property
 
 <section class="summary source-code" id="source">
   <h2><span>Implementation</span></h2>
-  <pre class="language-dart"><code class="language-dart">Map&lt;String, Logic&gt; get inputs =&gt; UnmodifiableMapView&lt;String, Logic&gt;(_inputs);</code></pre>
+  <pre class="language-dart"><code class="language-dart">@protected
+Map&lt;String, Logic&gt; get inputs =&gt; UnmodifiableMapView&lt;String, Logic&gt;(_inputs);</code></pre>
 </section>
 
 </section>
diff --git a/rohd/SystemVerilogSynthesizer/instantiationVerilogWithParameters.html b/rohd/SystemVerilogSynthesizer/instantiationVerilogWithParameters.html
index e1bb7a292..e870f070a 100644
--- a/rohd/SystemVerilogSynthesizer/instantiationVerilogWithParameters.html
+++ b/rohd/SystemVerilogSynthesizer/instantiationVerilogWithParameters.html
@@ -111,12 +111,16 @@ <h2><span>Implementation</span></h2>
 
   &#47;&#47;non-custom needs more details
   final connections = &lt;String&gt;[];
+
+  &#47;&#47; ignore: invalid_use_of_protected_member
   module.inputs.forEach((signalName, logic) {
     connections.add(&#39;.$signalName(${inputs[signalName]})&#39;);
   });
+
   module.outputs.forEach((signalName, logic) {
     connections.add(&#39;.$signalName(${outputs[signalName]})&#39;);
   });
+
   final connectionsStr = connections.join(&#39;,&#39;);
   var parameterString = &#39;&#39;;
   if (parameters != null) {