pcm-latency: what is it measuring?

[seyerman-intel]

What cycles/latency are included in pcm-latency L1 miss latency? Is it the load-to-use latency of an L1 miss, or are in-core cycles (before L1) not counted? I have a benchmark where all L1 misses are memory accesses, and I sometimes see latencies of ~50 ns, which seems low for the full load-to-use cycle of a memory access.

[opcm]

here is a related question and an answer: #518