From c72269f7090e0db24c0cf0c62f7d311fd3d46450 Mon Sep 17 00:00:00 2001 From: Jianhui Li Date: Thu, 14 Dec 2023 11:23:05 -0800 Subject: [PATCH] Update XeGPU.md --- docs/rfcs/XeGPU.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/rfcs/XeGPU.md b/docs/rfcs/XeGPU.md index bde4721dd..bce2785b4 100644 --- a/docs/rfcs/XeGPU.md +++ b/docs/rfcs/XeGPU.md @@ -256,4 +256,4 @@ The same syntax of nbarrrier, mfence, and compile_hint operations work on VC mod ## Notes -Currently, there is no lower-level GPU IR like NVVM available for Intel GPU compiler toolchain. XeGPU dialect uses SPIRV Intel extension to access joint-matrix or SPIR-V external function to access intel GPU VC intrinsics. This may change in the future, so we expect XeGPU lowering may change accordingly. +Currently, there is no lower-level GPU IR like NVVM available for the Intel GPU compiler toolchain. XeGPU dialect uses LLVM or SPIRV intrinsic to access advanced intel GPU instructions. When the lower-level software changes, we expect XeGPU lowering passes to change accordingly.