From 601a5f5264d9cefbdd6f876bca02b9a5cc9e64ce Mon Sep 17 00:00:00 2001
From: Igor Zamyatin <igor.zamyatin@intel.com>
Date: Tue, 17 Dec 2024 14:41:56 -0600
Subject: [PATCH] [XeGPU] Relaxing cache attr restriction for xegpu store ops
 (#986)

---
 ...u-temporary-downstream-defintion-changes-and-vec.patch | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch b/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch
index ab0f29aeb..8b737c936 100644
--- a/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch
+++ b/build_tools/patches/0008-xegpu-temporary-downstream-defintion-changes-and-vec.patch
@@ -56,6 +56,14 @@ diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp b/mlir/lib/Dialect/XeGPU/IR/
 index 5bd3c370e385..898e8564e3fe 100644
 --- a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
 +++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
+@@ -70,6 +70,7 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
+     return true;
+   auto kind = attr.getValue();
+   return kind == CachePolicy::CACHED || kind == CachePolicy::UNCACHED ||
++         kind == CachePolicy::STREAMING ||
+          kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
+ }
+
 @@ -237,7 +237,7 @@ LogicalResult LoadNdOp::verify() {
        emitWarning("Invalid transpose attr. It is ignored.");
    }