From 6550f7e281fc09a4314618735de723d5dacd29ae Mon Sep 17 00:00:00 2001 From: Nils Fitinghoff Date: Mon, 28 Oct 2024 16:44:54 +0100 Subject: [PATCH] Add imxrt1180 feature and pads Derived from the 1189 CM33 SVD. The pad definitions are exactly the same in the CM7 SVD; confirmed by diffing the iomuxc output for the CM33- and CM7-based outputs. --- CHANGELOG.md | 2 + Cargo.toml | 1 + README.md | 1 + iomuxc.py | 3 + src/imxrt1180/mod.rs | 7 + src/imxrt1180/pads.rs | 2482 +++++++++++++++++++++++++++++++++++++++++ src/lib.rs | 4 + 7 files changed, 2500 insertions(+) create mode 100644 src/imxrt1180/mod.rs create mode 100644 src/imxrt1180/pads.rs diff --git a/CHANGELOG.md b/CHANGELOG.md index de86dbe..ad2bf49 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -15,6 +15,8 @@ Enable an open drain when preparing I2C pins on 10xx MCUs. - Add remaining FlexPWM pins for the 1060 MCUs. +- Add i.MX RT 1180 support with the `"imxrt1180"` feature. + ## [0.2.7] 2024-06-10 - Fix many 1170 GPIO implementations, most which incorrectly specified their diff --git a/Cargo.toml b/Cargo.toml index a311f88..2091e0b 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -13,6 +13,7 @@ keywords = ["imxrt", "nxp", "embedded", "no_std"] categories = ["embedded", "no-std"] [features] +imxrt1180 = [] imxrt1170 = [] imxrt1060 = [] imxrt1020 = [] diff --git a/README.md b/README.md index 72f8b1c..3106769 100644 --- a/README.md +++ b/README.md @@ -42,6 +42,7 @@ instance, the 1060 feature supports 1061 and 1062 chip variants. | 1020 | `"imxrt1020"` | | 1060 | `"imxrt1060"` | | 1170 | `"imxrt1170"` | +| 1180 | `"imxrt1180"` | Read on if you're interested in adding support for another i.MX RT microcontroller, or if you want to expand existing support. diff --git a/iomuxc.py b/iomuxc.py index 1d0e030..3846a46 100755 --- a/iomuxc.py +++ b/iomuxc.py @@ -115,10 +115,13 @@ def iomuxc(path): root = tree.getroot() iomuxc = root.find("./peripherals/peripheral[name='IOMUXC']") iomuxc_lpsr = root.find("./peripherals/peripheral[name='IOMUXC_LPSR']") + iomuxc_aon = root.find("./peripherals/peripheral[name='IOMUXC_AON']") pads = extract_pads(iomuxc) if iomuxc_lpsr is not None: pads |= extract_pads(iomuxc_lpsr) + if iomuxc_aon is not None: + pads |= extract_pads(iomuxc_aon) # Create pad groups. groups = defaultdict(list) diff --git a/src/imxrt1180/mod.rs b/src/imxrt1180/mod.rs new file mode 100644 index 0000000..83ac2eb --- /dev/null +++ b/src/imxrt1180/mod.rs @@ -0,0 +1,7 @@ +//! Pads for the i.MX RT 1170 processor family. +//! +//! The module exports all of the i.MX RT 1170 processor's pads. Pads that can support +//! peripheral functions are tagged with `imxrt-iomuxc` traits. + +mod pads; +pub use pads::*; diff --git a/src/imxrt1180/pads.rs b/src/imxrt1180/pads.rs new file mode 100644 index 0000000..b82f0af --- /dev/null +++ b/src/imxrt1180/pads.rs @@ -0,0 +1,2482 @@ +// Generated by iomuxc.py +#![allow(non_camel_case_types)] + +/// Pads with the prefix GPIO_EMC_B1. +pub mod gpio_emc_b1 { + + const GPIO_EMC_B1_00_MUX_ADDR: u32 = 0x42a10010; + const GPIO_EMC_B1_00_PAD_ADDR: u32 = 0x42a10258; + pub type GPIO_EMC_B1_00 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_EMC_B1_01_MUX_ADDR: u32 = 0x42a10014; + const GPIO_EMC_B1_01_PAD_ADDR: u32 = 0x42a1025c; + pub type GPIO_EMC_B1_01 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_EMC_B1_02_MUX_ADDR: u32 = 0x42a10018; + const GPIO_EMC_B1_02_PAD_ADDR: u32 = 0x42a10260; + pub type GPIO_EMC_B1_02 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_EMC_B1_03_MUX_ADDR: u32 = 0x42a1001c; + const GPIO_EMC_B1_03_PAD_ADDR: u32 = 0x42a10264; + pub type GPIO_EMC_B1_03 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_EMC_B1_04_MUX_ADDR: u32 = 0x42a10020; + const GPIO_EMC_B1_04_PAD_ADDR: u32 = 0x42a10268; + pub type GPIO_EMC_B1_04 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 4; + } + + const GPIO_EMC_B1_05_MUX_ADDR: u32 = 0x42a10024; + const GPIO_EMC_B1_05_PAD_ADDR: u32 = 0x42a1026c; + pub type GPIO_EMC_B1_05 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 5; + } + + const GPIO_EMC_B1_06_MUX_ADDR: u32 = 0x42a10028; + const GPIO_EMC_B1_06_PAD_ADDR: u32 = 0x42a10270; + pub type GPIO_EMC_B1_06 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 6; + } + + const GPIO_EMC_B1_07_MUX_ADDR: u32 = 0x42a1002c; + const GPIO_EMC_B1_07_PAD_ADDR: u32 = 0x42a10274; + pub type GPIO_EMC_B1_07 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 7; + } + + const GPIO_EMC_B1_08_MUX_ADDR: u32 = 0x42a10030; + const GPIO_EMC_B1_08_PAD_ADDR: u32 = 0x42a10278; + pub type GPIO_EMC_B1_08 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 8; + } + + const GPIO_EMC_B1_09_MUX_ADDR: u32 = 0x42a10034; + const GPIO_EMC_B1_09_PAD_ADDR: u32 = 0x42a1027c; + pub type GPIO_EMC_B1_09 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 9; + } + + const GPIO_EMC_B1_10_MUX_ADDR: u32 = 0x42a10038; + const GPIO_EMC_B1_10_PAD_ADDR: u32 = 0x42a10280; + pub type GPIO_EMC_B1_10 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 10; + } + + const GPIO_EMC_B1_11_MUX_ADDR: u32 = 0x42a1003c; + const GPIO_EMC_B1_11_PAD_ADDR: u32 = 0x42a10284; + pub type GPIO_EMC_B1_11 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 11; + } + + const GPIO_EMC_B1_12_MUX_ADDR: u32 = 0x42a10040; + const GPIO_EMC_B1_12_PAD_ADDR: u32 = 0x42a10288; + pub type GPIO_EMC_B1_12 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 12; + } + + const GPIO_EMC_B1_13_MUX_ADDR: u32 = 0x42a10044; + const GPIO_EMC_B1_13_PAD_ADDR: u32 = 0x42a1028c; + pub type GPIO_EMC_B1_13 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 13; + } + + const GPIO_EMC_B1_14_MUX_ADDR: u32 = 0x42a10048; + const GPIO_EMC_B1_14_PAD_ADDR: u32 = 0x42a10290; + pub type GPIO_EMC_B1_14 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 14; + } + + const GPIO_EMC_B1_15_MUX_ADDR: u32 = 0x42a1004c; + const GPIO_EMC_B1_15_PAD_ADDR: u32 = 0x42a10294; + pub type GPIO_EMC_B1_15 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 15; + } + + const GPIO_EMC_B1_16_MUX_ADDR: u32 = 0x42a10050; + const GPIO_EMC_B1_16_PAD_ADDR: u32 = 0x42a10298; + pub type GPIO_EMC_B1_16 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 16; + } + + const GPIO_EMC_B1_17_MUX_ADDR: u32 = 0x42a10054; + const GPIO_EMC_B1_17_PAD_ADDR: u32 = 0x42a1029c; + pub type GPIO_EMC_B1_17 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 17; + } + + const GPIO_EMC_B1_18_MUX_ADDR: u32 = 0x42a10058; + const GPIO_EMC_B1_18_PAD_ADDR: u32 = 0x42a102a0; + pub type GPIO_EMC_B1_18 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 18; + } + + const GPIO_EMC_B1_19_MUX_ADDR: u32 = 0x42a1005c; + const GPIO_EMC_B1_19_PAD_ADDR: u32 = 0x42a102a4; + pub type GPIO_EMC_B1_19 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 19; + } + + const GPIO_EMC_B1_20_MUX_ADDR: u32 = 0x42a10060; + const GPIO_EMC_B1_20_PAD_ADDR: u32 = 0x42a102a8; + pub type GPIO_EMC_B1_20 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 20; + } + + const GPIO_EMC_B1_21_MUX_ADDR: u32 = 0x42a10064; + const GPIO_EMC_B1_21_PAD_ADDR: u32 = 0x42a102ac; + pub type GPIO_EMC_B1_21 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_21 { + const ALT: u32 = 5; + const OFFSET: u32 = 21; + } + + const GPIO_EMC_B1_22_MUX_ADDR: u32 = 0x42a10068; + const GPIO_EMC_B1_22_PAD_ADDR: u32 = 0x42a102b0; + pub type GPIO_EMC_B1_22 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_22 { + const ALT: u32 = 5; + const OFFSET: u32 = 22; + } + + const GPIO_EMC_B1_23_MUX_ADDR: u32 = 0x42a1006c; + const GPIO_EMC_B1_23_PAD_ADDR: u32 = 0x42a102b4; + pub type GPIO_EMC_B1_23 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_23 { + const ALT: u32 = 5; + const OFFSET: u32 = 23; + } + + const GPIO_EMC_B1_24_MUX_ADDR: u32 = 0x42a10070; + const GPIO_EMC_B1_24_PAD_ADDR: u32 = 0x42a102b8; + pub type GPIO_EMC_B1_24 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_24 { + const ALT: u32 = 5; + const OFFSET: u32 = 24; + } + + const GPIO_EMC_B1_25_MUX_ADDR: u32 = 0x42a10074; + const GPIO_EMC_B1_25_PAD_ADDR: u32 = 0x42a102bc; + pub type GPIO_EMC_B1_25 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_25 { + const ALT: u32 = 5; + const OFFSET: u32 = 25; + } + + const GPIO_EMC_B1_26_MUX_ADDR: u32 = 0x42a10078; + const GPIO_EMC_B1_26_PAD_ADDR: u32 = 0x42a102c0; + pub type GPIO_EMC_B1_26 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_26 { + const ALT: u32 = 5; + const OFFSET: u32 = 26; + } + + const GPIO_EMC_B1_27_MUX_ADDR: u32 = 0x42a1007c; + const GPIO_EMC_B1_27_PAD_ADDR: u32 = 0x42a102c4; + pub type GPIO_EMC_B1_27 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_27 { + const ALT: u32 = 5; + const OFFSET: u32 = 27; + } + + const GPIO_EMC_B1_28_MUX_ADDR: u32 = 0x42a10080; + const GPIO_EMC_B1_28_PAD_ADDR: u32 = 0x42a102c8; + pub type GPIO_EMC_B1_28 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_28 { + const ALT: u32 = 5; + const OFFSET: u32 = 28; + } + + const GPIO_EMC_B1_29_MUX_ADDR: u32 = 0x42a10084; + const GPIO_EMC_B1_29_PAD_ADDR: u32 = 0x42a102cc; + pub type GPIO_EMC_B1_29 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_29 { + const ALT: u32 = 5; + const OFFSET: u32 = 29; + } + + const GPIO_EMC_B1_30_MUX_ADDR: u32 = 0x42a10088; + const GPIO_EMC_B1_30_PAD_ADDR: u32 = 0x42a102d0; + pub type GPIO_EMC_B1_30 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_30 { + const ALT: u32 = 5; + const OFFSET: u32 = 30; + } + + const GPIO_EMC_B1_31_MUX_ADDR: u32 = 0x42a1008c; + const GPIO_EMC_B1_31_PAD_ADDR: u32 = 0x42a102d4; + pub type GPIO_EMC_B1_31 = crate::Pad; + + impl crate::gpio::Pin<2> for GPIO_EMC_B1_31 { + const ALT: u32 = 5; + const OFFSET: u32 = 31; + } + + const GPIO_EMC_B1_32_MUX_ADDR: u32 = 0x42a10090; + const GPIO_EMC_B1_32_PAD_ADDR: u32 = 0x42a102d8; + pub type GPIO_EMC_B1_32 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_32 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_EMC_B1_33_MUX_ADDR: u32 = 0x42a10094; + const GPIO_EMC_B1_33_PAD_ADDR: u32 = 0x42a102dc; + pub type GPIO_EMC_B1_33 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_33 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_EMC_B1_34_MUX_ADDR: u32 = 0x42a10098; + const GPIO_EMC_B1_34_PAD_ADDR: u32 = 0x42a102e0; + pub type GPIO_EMC_B1_34 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_34 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_EMC_B1_35_MUX_ADDR: u32 = 0x42a1009c; + const GPIO_EMC_B1_35_PAD_ADDR: u32 = 0x42a102e4; + pub type GPIO_EMC_B1_35 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_35 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_EMC_B1_36_MUX_ADDR: u32 = 0x42a100a0; + const GPIO_EMC_B1_36_PAD_ADDR: u32 = 0x42a102e8; + pub type GPIO_EMC_B1_36 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_36 { + const ALT: u32 = 5; + const OFFSET: u32 = 4; + } + + const GPIO_EMC_B1_37_MUX_ADDR: u32 = 0x42a100a4; + const GPIO_EMC_B1_37_PAD_ADDR: u32 = 0x42a102ec; + pub type GPIO_EMC_B1_37 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_37 { + const ALT: u32 = 5; + const OFFSET: u32 = 5; + } + + const GPIO_EMC_B1_38_MUX_ADDR: u32 = 0x42a100a8; + const GPIO_EMC_B1_38_PAD_ADDR: u32 = 0x42a102f0; + pub type GPIO_EMC_B1_38 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_38 { + const ALT: u32 = 5; + const OFFSET: u32 = 6; + } + + const GPIO_EMC_B1_39_MUX_ADDR: u32 = 0x42a100ac; + const GPIO_EMC_B1_39_PAD_ADDR: u32 = 0x42a102f4; + pub type GPIO_EMC_B1_39 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_39 { + const ALT: u32 = 5; + const OFFSET: u32 = 7; + } + + const GPIO_EMC_B1_40_MUX_ADDR: u32 = 0x42a100b0; + const GPIO_EMC_B1_40_PAD_ADDR: u32 = 0x42a102f8; + pub type GPIO_EMC_B1_40 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_40 { + const ALT: u32 = 5; + const OFFSET: u32 = 8; + } + + const GPIO_EMC_B1_41_MUX_ADDR: u32 = 0x42a100b4; + const GPIO_EMC_B1_41_PAD_ADDR: u32 = 0x42a102fc; + pub type GPIO_EMC_B1_41 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B1_41 { + const ALT: u32 = 5; + const OFFSET: u32 = 9; + } + + /// All pads with prefix GPIO_EMC_B1. + pub struct Pads { + pub p00: GPIO_EMC_B1_00, + pub p01: GPIO_EMC_B1_01, + pub p02: GPIO_EMC_B1_02, + pub p03: GPIO_EMC_B1_03, + pub p04: GPIO_EMC_B1_04, + pub p05: GPIO_EMC_B1_05, + pub p06: GPIO_EMC_B1_06, + pub p07: GPIO_EMC_B1_07, + pub p08: GPIO_EMC_B1_08, + pub p09: GPIO_EMC_B1_09, + pub p10: GPIO_EMC_B1_10, + pub p11: GPIO_EMC_B1_11, + pub p12: GPIO_EMC_B1_12, + pub p13: GPIO_EMC_B1_13, + pub p14: GPIO_EMC_B1_14, + pub p15: GPIO_EMC_B1_15, + pub p16: GPIO_EMC_B1_16, + pub p17: GPIO_EMC_B1_17, + pub p18: GPIO_EMC_B1_18, + pub p19: GPIO_EMC_B1_19, + pub p20: GPIO_EMC_B1_20, + pub p21: GPIO_EMC_B1_21, + pub p22: GPIO_EMC_B1_22, + pub p23: GPIO_EMC_B1_23, + pub p24: GPIO_EMC_B1_24, + pub p25: GPIO_EMC_B1_25, + pub p26: GPIO_EMC_B1_26, + pub p27: GPIO_EMC_B1_27, + pub p28: GPIO_EMC_B1_28, + pub p29: GPIO_EMC_B1_29, + pub p30: GPIO_EMC_B1_30, + pub p31: GPIO_EMC_B1_31, + pub p32: GPIO_EMC_B1_32, + pub p33: GPIO_EMC_B1_33, + pub p34: GPIO_EMC_B1_34, + pub p35: GPIO_EMC_B1_35, + pub p36: GPIO_EMC_B1_36, + pub p37: GPIO_EMC_B1_37, + pub p38: GPIO_EMC_B1_38, + pub p39: GPIO_EMC_B1_39, + pub p40: GPIO_EMC_B1_40, + pub p41: GPIO_EMC_B1_41, + } + /// Erased pads with prefix GPIO_EMC_B1. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 42]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_EMC_B1_00::new(), + p01: GPIO_EMC_B1_01::new(), + p02: GPIO_EMC_B1_02::new(), + p03: GPIO_EMC_B1_03::new(), + p04: GPIO_EMC_B1_04::new(), + p05: GPIO_EMC_B1_05::new(), + p06: GPIO_EMC_B1_06::new(), + p07: GPIO_EMC_B1_07::new(), + p08: GPIO_EMC_B1_08::new(), + p09: GPIO_EMC_B1_09::new(), + p10: GPIO_EMC_B1_10::new(), + p11: GPIO_EMC_B1_11::new(), + p12: GPIO_EMC_B1_12::new(), + p13: GPIO_EMC_B1_13::new(), + p14: GPIO_EMC_B1_14::new(), + p15: GPIO_EMC_B1_15::new(), + p16: GPIO_EMC_B1_16::new(), + p17: GPIO_EMC_B1_17::new(), + p18: GPIO_EMC_B1_18::new(), + p19: GPIO_EMC_B1_19::new(), + p20: GPIO_EMC_B1_20::new(), + p21: GPIO_EMC_B1_21::new(), + p22: GPIO_EMC_B1_22::new(), + p23: GPIO_EMC_B1_23::new(), + p24: GPIO_EMC_B1_24::new(), + p25: GPIO_EMC_B1_25::new(), + p26: GPIO_EMC_B1_26::new(), + p27: GPIO_EMC_B1_27::new(), + p28: GPIO_EMC_B1_28::new(), + p29: GPIO_EMC_B1_29::new(), + p30: GPIO_EMC_B1_30::new(), + p31: GPIO_EMC_B1_31::new(), + p32: GPIO_EMC_B1_32::new(), + p33: GPIO_EMC_B1_33::new(), + p34: GPIO_EMC_B1_34::new(), + p35: GPIO_EMC_B1_35::new(), + p36: GPIO_EMC_B1_36::new(), + p37: GPIO_EMC_B1_37::new(), + p38: GPIO_EMC_B1_38::new(), + p39: GPIO_EMC_B1_39::new(), + p40: GPIO_EMC_B1_40::new(), + p41: GPIO_EMC_B1_41::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + self.p21.erase(), + self.p22.erase(), + self.p23.erase(), + self.p24.erase(), + self.p25.erase(), + self.p26.erase(), + self.p27.erase(), + self.p28.erase(), + self.p29.erase(), + self.p30.erase(), + self.p31.erase(), + self.p32.erase(), + self.p33.erase(), + self.p34.erase(), + self.p35.erase(), + self.p36.erase(), + self.p37.erase(), + self.p38.erase(), + self.p39.erase(), + self.p40.erase(), + self.p41.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_EMC_B2. +pub mod gpio_emc_b2 { + + const GPIO_EMC_B2_00_MUX_ADDR: u32 = 0x42a100b8; + const GPIO_EMC_B2_00_PAD_ADDR: u32 = 0x42a10300; + pub type GPIO_EMC_B2_00 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 10; + } + + const GPIO_EMC_B2_01_MUX_ADDR: u32 = 0x42a100bc; + const GPIO_EMC_B2_01_PAD_ADDR: u32 = 0x42a10304; + pub type GPIO_EMC_B2_01 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 11; + } + + const GPIO_EMC_B2_02_MUX_ADDR: u32 = 0x42a100c0; + const GPIO_EMC_B2_02_PAD_ADDR: u32 = 0x42a10308; + pub type GPIO_EMC_B2_02 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 12; + } + + const GPIO_EMC_B2_03_MUX_ADDR: u32 = 0x42a100c4; + const GPIO_EMC_B2_03_PAD_ADDR: u32 = 0x42a1030c; + pub type GPIO_EMC_B2_03 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 13; + } + + const GPIO_EMC_B2_04_MUX_ADDR: u32 = 0x42a100c8; + const GPIO_EMC_B2_04_PAD_ADDR: u32 = 0x42a10310; + pub type GPIO_EMC_B2_04 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 14; + } + + const GPIO_EMC_B2_05_MUX_ADDR: u32 = 0x42a100cc; + const GPIO_EMC_B2_05_PAD_ADDR: u32 = 0x42a10314; + pub type GPIO_EMC_B2_05 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 15; + } + + const GPIO_EMC_B2_06_MUX_ADDR: u32 = 0x42a100d0; + const GPIO_EMC_B2_06_PAD_ADDR: u32 = 0x42a10318; + pub type GPIO_EMC_B2_06 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 16; + } + + const GPIO_EMC_B2_07_MUX_ADDR: u32 = 0x42a100d4; + const GPIO_EMC_B2_07_PAD_ADDR: u32 = 0x42a1031c; + pub type GPIO_EMC_B2_07 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 17; + } + + const GPIO_EMC_B2_08_MUX_ADDR: u32 = 0x42a100d8; + const GPIO_EMC_B2_08_PAD_ADDR: u32 = 0x42a10320; + pub type GPIO_EMC_B2_08 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 18; + } + + const GPIO_EMC_B2_09_MUX_ADDR: u32 = 0x42a100dc; + const GPIO_EMC_B2_09_PAD_ADDR: u32 = 0x42a10324; + pub type GPIO_EMC_B2_09 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 19; + } + + const GPIO_EMC_B2_10_MUX_ADDR: u32 = 0x42a100e0; + const GPIO_EMC_B2_10_PAD_ADDR: u32 = 0x42a10328; + pub type GPIO_EMC_B2_10 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 20; + } + + const GPIO_EMC_B2_11_MUX_ADDR: u32 = 0x42a100e4; + const GPIO_EMC_B2_11_PAD_ADDR: u32 = 0x42a1032c; + pub type GPIO_EMC_B2_11 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 21; + } + + const GPIO_EMC_B2_12_MUX_ADDR: u32 = 0x42a100e8; + const GPIO_EMC_B2_12_PAD_ADDR: u32 = 0x42a10330; + pub type GPIO_EMC_B2_12 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 22; + } + + const GPIO_EMC_B2_13_MUX_ADDR: u32 = 0x42a100ec; + const GPIO_EMC_B2_13_PAD_ADDR: u32 = 0x42a10334; + pub type GPIO_EMC_B2_13 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 23; + } + + const GPIO_EMC_B2_14_MUX_ADDR: u32 = 0x42a100f0; + const GPIO_EMC_B2_14_PAD_ADDR: u32 = 0x42a10338; + pub type GPIO_EMC_B2_14 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 24; + } + + const GPIO_EMC_B2_15_MUX_ADDR: u32 = 0x42a100f4; + const GPIO_EMC_B2_15_PAD_ADDR: u32 = 0x42a1033c; + pub type GPIO_EMC_B2_15 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 25; + } + + const GPIO_EMC_B2_16_MUX_ADDR: u32 = 0x42a100f8; + const GPIO_EMC_B2_16_PAD_ADDR: u32 = 0x42a10340; + pub type GPIO_EMC_B2_16 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 26; + } + + const GPIO_EMC_B2_17_MUX_ADDR: u32 = 0x42a100fc; + const GPIO_EMC_B2_17_PAD_ADDR: u32 = 0x42a10344; + pub type GPIO_EMC_B2_17 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 27; + } + + const GPIO_EMC_B2_18_MUX_ADDR: u32 = 0x42a10100; + const GPIO_EMC_B2_18_PAD_ADDR: u32 = 0x42a10348; + pub type GPIO_EMC_B2_18 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 28; + } + + const GPIO_EMC_B2_19_MUX_ADDR: u32 = 0x42a10104; + const GPIO_EMC_B2_19_PAD_ADDR: u32 = 0x42a1034c; + pub type GPIO_EMC_B2_19 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 29; + } + + const GPIO_EMC_B2_20_MUX_ADDR: u32 = 0x42a10108; + const GPIO_EMC_B2_20_PAD_ADDR: u32 = 0x42a10350; + pub type GPIO_EMC_B2_20 = crate::Pad; + + impl crate::gpio::Pin<3> for GPIO_EMC_B2_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 30; + } + + /// All pads with prefix GPIO_EMC_B2. + pub struct Pads { + pub p00: GPIO_EMC_B2_00, + pub p01: GPIO_EMC_B2_01, + pub p02: GPIO_EMC_B2_02, + pub p03: GPIO_EMC_B2_03, + pub p04: GPIO_EMC_B2_04, + pub p05: GPIO_EMC_B2_05, + pub p06: GPIO_EMC_B2_06, + pub p07: GPIO_EMC_B2_07, + pub p08: GPIO_EMC_B2_08, + pub p09: GPIO_EMC_B2_09, + pub p10: GPIO_EMC_B2_10, + pub p11: GPIO_EMC_B2_11, + pub p12: GPIO_EMC_B2_12, + pub p13: GPIO_EMC_B2_13, + pub p14: GPIO_EMC_B2_14, + pub p15: GPIO_EMC_B2_15, + pub p16: GPIO_EMC_B2_16, + pub p17: GPIO_EMC_B2_17, + pub p18: GPIO_EMC_B2_18, + pub p19: GPIO_EMC_B2_19, + pub p20: GPIO_EMC_B2_20, + } + /// Erased pads with prefix GPIO_EMC_B2. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 21]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_EMC_B2_00::new(), + p01: GPIO_EMC_B2_01::new(), + p02: GPIO_EMC_B2_02::new(), + p03: GPIO_EMC_B2_03::new(), + p04: GPIO_EMC_B2_04::new(), + p05: GPIO_EMC_B2_05::new(), + p06: GPIO_EMC_B2_06::new(), + p07: GPIO_EMC_B2_07::new(), + p08: GPIO_EMC_B2_08::new(), + p09: GPIO_EMC_B2_09::new(), + p10: GPIO_EMC_B2_10::new(), + p11: GPIO_EMC_B2_11::new(), + p12: GPIO_EMC_B2_12::new(), + p13: GPIO_EMC_B2_13::new(), + p14: GPIO_EMC_B2_14::new(), + p15: GPIO_EMC_B2_15::new(), + p16: GPIO_EMC_B2_16::new(), + p17: GPIO_EMC_B2_17::new(), + p18: GPIO_EMC_B2_18::new(), + p19: GPIO_EMC_B2_19::new(), + p20: GPIO_EMC_B2_20::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_AD. +pub mod gpio_ad { + + const GPIO_AD_00_MUX_ADDR: u32 = 0x42a1010c; + const GPIO_AD_00_PAD_ADDR: u32 = 0x42a10354; + pub type GPIO_AD_00 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_AD_01_MUX_ADDR: u32 = 0x42a10110; + const GPIO_AD_01_PAD_ADDR: u32 = 0x42a10358; + pub type GPIO_AD_01 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_AD_02_MUX_ADDR: u32 = 0x42a10114; + const GPIO_AD_02_PAD_ADDR: u32 = 0x42a1035c; + pub type GPIO_AD_02 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_AD_03_MUX_ADDR: u32 = 0x42a10118; + const GPIO_AD_03_PAD_ADDR: u32 = 0x42a10360; + pub type GPIO_AD_03 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_AD_04_MUX_ADDR: u32 = 0x42a1011c; + const GPIO_AD_04_PAD_ADDR: u32 = 0x42a10364; + pub type GPIO_AD_04 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 4; + } + + const GPIO_AD_05_MUX_ADDR: u32 = 0x42a10120; + const GPIO_AD_05_PAD_ADDR: u32 = 0x42a10368; + pub type GPIO_AD_05 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 5; + } + + const GPIO_AD_06_MUX_ADDR: u32 = 0x42a10124; + const GPIO_AD_06_PAD_ADDR: u32 = 0x42a1036c; + pub type GPIO_AD_06 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 6; + } + + const GPIO_AD_07_MUX_ADDR: u32 = 0x42a10128; + const GPIO_AD_07_PAD_ADDR: u32 = 0x42a10370; + pub type GPIO_AD_07 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 7; + } + + const GPIO_AD_08_MUX_ADDR: u32 = 0x42a1012c; + const GPIO_AD_08_PAD_ADDR: u32 = 0x42a10374; + pub type GPIO_AD_08 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 8; + } + + const GPIO_AD_09_MUX_ADDR: u32 = 0x42a10130; + const GPIO_AD_09_PAD_ADDR: u32 = 0x42a10378; + pub type GPIO_AD_09 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 9; + } + + const GPIO_AD_10_MUX_ADDR: u32 = 0x42a10134; + const GPIO_AD_10_PAD_ADDR: u32 = 0x42a1037c; + pub type GPIO_AD_10 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 10; + } + + const GPIO_AD_11_MUX_ADDR: u32 = 0x42a10138; + const GPIO_AD_11_PAD_ADDR: u32 = 0x42a10380; + pub type GPIO_AD_11 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 11; + } + + const GPIO_AD_12_MUX_ADDR: u32 = 0x42a1013c; + const GPIO_AD_12_PAD_ADDR: u32 = 0x42a10384; + pub type GPIO_AD_12 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 12; + } + + const GPIO_AD_13_MUX_ADDR: u32 = 0x42a10140; + const GPIO_AD_13_PAD_ADDR: u32 = 0x42a10388; + pub type GPIO_AD_13 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 13; + } + + const GPIO_AD_14_MUX_ADDR: u32 = 0x42a10144; + const GPIO_AD_14_PAD_ADDR: u32 = 0x42a1038c; + pub type GPIO_AD_14 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 14; + } + + const GPIO_AD_15_MUX_ADDR: u32 = 0x42a10148; + const GPIO_AD_15_PAD_ADDR: u32 = 0x42a10390; + pub type GPIO_AD_15 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 15; + } + + const GPIO_AD_16_MUX_ADDR: u32 = 0x42a1014c; + const GPIO_AD_16_PAD_ADDR: u32 = 0x42a10394; + pub type GPIO_AD_16 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 16; + } + + const GPIO_AD_17_MUX_ADDR: u32 = 0x42a10150; + const GPIO_AD_17_PAD_ADDR: u32 = 0x42a10398; + pub type GPIO_AD_17 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 17; + } + + const GPIO_AD_18_MUX_ADDR: u32 = 0x42a10154; + const GPIO_AD_18_PAD_ADDR: u32 = 0x42a1039c; + pub type GPIO_AD_18 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 18; + } + + const GPIO_AD_19_MUX_ADDR: u32 = 0x42a10158; + const GPIO_AD_19_PAD_ADDR: u32 = 0x42a103a0; + pub type GPIO_AD_19 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 19; + } + + const GPIO_AD_20_MUX_ADDR: u32 = 0x42a1015c; + const GPIO_AD_20_PAD_ADDR: u32 = 0x42a103a4; + pub type GPIO_AD_20 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 20; + } + + const GPIO_AD_21_MUX_ADDR: u32 = 0x42a10160; + const GPIO_AD_21_PAD_ADDR: u32 = 0x42a103a8; + pub type GPIO_AD_21 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_21 { + const ALT: u32 = 5; + const OFFSET: u32 = 21; + } + + const GPIO_AD_22_MUX_ADDR: u32 = 0x42a10164; + const GPIO_AD_22_PAD_ADDR: u32 = 0x42a103ac; + pub type GPIO_AD_22 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_22 { + const ALT: u32 = 5; + const OFFSET: u32 = 22; + } + + const GPIO_AD_23_MUX_ADDR: u32 = 0x42a10168; + const GPIO_AD_23_PAD_ADDR: u32 = 0x42a103b0; + pub type GPIO_AD_23 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_23 { + const ALT: u32 = 5; + const OFFSET: u32 = 23; + } + + const GPIO_AD_24_MUX_ADDR: u32 = 0x42a1016c; + const GPIO_AD_24_PAD_ADDR: u32 = 0x42a103b4; + pub type GPIO_AD_24 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_24 { + const ALT: u32 = 5; + const OFFSET: u32 = 24; + } + + const GPIO_AD_25_MUX_ADDR: u32 = 0x42a10170; + const GPIO_AD_25_PAD_ADDR: u32 = 0x42a103b8; + pub type GPIO_AD_25 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_25 { + const ALT: u32 = 5; + const OFFSET: u32 = 25; + } + + const GPIO_AD_26_MUX_ADDR: u32 = 0x42a10174; + const GPIO_AD_26_PAD_ADDR: u32 = 0x42a103bc; + pub type GPIO_AD_26 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_26 { + const ALT: u32 = 5; + const OFFSET: u32 = 26; + } + + const GPIO_AD_27_MUX_ADDR: u32 = 0x42a10178; + const GPIO_AD_27_PAD_ADDR: u32 = 0x42a103c0; + pub type GPIO_AD_27 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_27 { + const ALT: u32 = 5; + const OFFSET: u32 = 27; + } + + const GPIO_AD_28_MUX_ADDR: u32 = 0x42a1017c; + const GPIO_AD_28_PAD_ADDR: u32 = 0x42a103c4; + pub type GPIO_AD_28 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_28 { + const ALT: u32 = 5; + const OFFSET: u32 = 28; + } + + const GPIO_AD_29_MUX_ADDR: u32 = 0x42a10180; + const GPIO_AD_29_PAD_ADDR: u32 = 0x42a103c8; + pub type GPIO_AD_29 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_29 { + const ALT: u32 = 5; + const OFFSET: u32 = 29; + } + + const GPIO_AD_30_MUX_ADDR: u32 = 0x42a10184; + const GPIO_AD_30_PAD_ADDR: u32 = 0x42a103cc; + pub type GPIO_AD_30 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_30 { + const ALT: u32 = 5; + const OFFSET: u32 = 30; + } + + const GPIO_AD_31_MUX_ADDR: u32 = 0x42a10188; + const GPIO_AD_31_PAD_ADDR: u32 = 0x42a103d0; + pub type GPIO_AD_31 = crate::Pad; + + impl crate::gpio::Pin<4> for GPIO_AD_31 { + const ALT: u32 = 5; + const OFFSET: u32 = 31; + } + + const GPIO_AD_32_MUX_ADDR: u32 = 0x42a1018c; + const GPIO_AD_32_PAD_ADDR: u32 = 0x42a103d4; + pub type GPIO_AD_32 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_AD_32 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_AD_33_MUX_ADDR: u32 = 0x42a10190; + const GPIO_AD_33_PAD_ADDR: u32 = 0x42a103d8; + pub type GPIO_AD_33 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_AD_33 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_AD_34_MUX_ADDR: u32 = 0x42a10194; + const GPIO_AD_34_PAD_ADDR: u32 = 0x42a103dc; + pub type GPIO_AD_34 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_AD_34 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_AD_35_MUX_ADDR: u32 = 0x42a10198; + const GPIO_AD_35_PAD_ADDR: u32 = 0x42a103e0; + pub type GPIO_AD_35 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_AD_35 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + /// All pads with prefix GPIO_AD. + pub struct Pads { + pub p00: GPIO_AD_00, + pub p01: GPIO_AD_01, + pub p02: GPIO_AD_02, + pub p03: GPIO_AD_03, + pub p04: GPIO_AD_04, + pub p05: GPIO_AD_05, + pub p06: GPIO_AD_06, + pub p07: GPIO_AD_07, + pub p08: GPIO_AD_08, + pub p09: GPIO_AD_09, + pub p10: GPIO_AD_10, + pub p11: GPIO_AD_11, + pub p12: GPIO_AD_12, + pub p13: GPIO_AD_13, + pub p14: GPIO_AD_14, + pub p15: GPIO_AD_15, + pub p16: GPIO_AD_16, + pub p17: GPIO_AD_17, + pub p18: GPIO_AD_18, + pub p19: GPIO_AD_19, + pub p20: GPIO_AD_20, + pub p21: GPIO_AD_21, + pub p22: GPIO_AD_22, + pub p23: GPIO_AD_23, + pub p24: GPIO_AD_24, + pub p25: GPIO_AD_25, + pub p26: GPIO_AD_26, + pub p27: GPIO_AD_27, + pub p28: GPIO_AD_28, + pub p29: GPIO_AD_29, + pub p30: GPIO_AD_30, + pub p31: GPIO_AD_31, + pub p32: GPIO_AD_32, + pub p33: GPIO_AD_33, + pub p34: GPIO_AD_34, + pub p35: GPIO_AD_35, + } + /// Erased pads with prefix GPIO_AD. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 36]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_AD_00::new(), + p01: GPIO_AD_01::new(), + p02: GPIO_AD_02::new(), + p03: GPIO_AD_03::new(), + p04: GPIO_AD_04::new(), + p05: GPIO_AD_05::new(), + p06: GPIO_AD_06::new(), + p07: GPIO_AD_07::new(), + p08: GPIO_AD_08::new(), + p09: GPIO_AD_09::new(), + p10: GPIO_AD_10::new(), + p11: GPIO_AD_11::new(), + p12: GPIO_AD_12::new(), + p13: GPIO_AD_13::new(), + p14: GPIO_AD_14::new(), + p15: GPIO_AD_15::new(), + p16: GPIO_AD_16::new(), + p17: GPIO_AD_17::new(), + p18: GPIO_AD_18::new(), + p19: GPIO_AD_19::new(), + p20: GPIO_AD_20::new(), + p21: GPIO_AD_21::new(), + p22: GPIO_AD_22::new(), + p23: GPIO_AD_23::new(), + p24: GPIO_AD_24::new(), + p25: GPIO_AD_25::new(), + p26: GPIO_AD_26::new(), + p27: GPIO_AD_27::new(), + p28: GPIO_AD_28::new(), + p29: GPIO_AD_29::new(), + p30: GPIO_AD_30::new(), + p31: GPIO_AD_31::new(), + p32: GPIO_AD_32::new(), + p33: GPIO_AD_33::new(), + p34: GPIO_AD_34::new(), + p35: GPIO_AD_35::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + self.p21.erase(), + self.p22.erase(), + self.p23.erase(), + self.p24.erase(), + self.p25.erase(), + self.p26.erase(), + self.p27.erase(), + self.p28.erase(), + self.p29.erase(), + self.p30.erase(), + self.p31.erase(), + self.p32.erase(), + self.p33.erase(), + self.p34.erase(), + self.p35.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_SD_B1. +pub mod gpio_sd_b1 { + + const GPIO_SD_B1_00_MUX_ADDR: u32 = 0x42a1019c; + const GPIO_SD_B1_00_PAD_ADDR: u32 = 0x42a103e4; + pub type GPIO_SD_B1_00 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B1_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 4; + } + + const GPIO_SD_B1_01_MUX_ADDR: u32 = 0x42a101a0; + const GPIO_SD_B1_01_PAD_ADDR: u32 = 0x42a103e8; + pub type GPIO_SD_B1_01 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B1_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 5; + } + + const GPIO_SD_B1_02_MUX_ADDR: u32 = 0x42a101a4; + const GPIO_SD_B1_02_PAD_ADDR: u32 = 0x42a103ec; + pub type GPIO_SD_B1_02 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B1_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 6; + } + + const GPIO_SD_B1_03_MUX_ADDR: u32 = 0x42a101a8; + const GPIO_SD_B1_03_PAD_ADDR: u32 = 0x42a103f0; + pub type GPIO_SD_B1_03 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B1_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 7; + } + + const GPIO_SD_B1_04_MUX_ADDR: u32 = 0x42a101ac; + const GPIO_SD_B1_04_PAD_ADDR: u32 = 0x42a103f4; + pub type GPIO_SD_B1_04 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B1_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 8; + } + + const GPIO_SD_B1_05_MUX_ADDR: u32 = 0x42a101b0; + const GPIO_SD_B1_05_PAD_ADDR: u32 = 0x42a103f8; + pub type GPIO_SD_B1_05 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B1_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 9; + } + + /// All pads with prefix GPIO_SD_B1. + pub struct Pads { + pub p00: GPIO_SD_B1_00, + pub p01: GPIO_SD_B1_01, + pub p02: GPIO_SD_B1_02, + pub p03: GPIO_SD_B1_03, + pub p04: GPIO_SD_B1_04, + pub p05: GPIO_SD_B1_05, + } + /// Erased pads with prefix GPIO_SD_B1. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 6]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_SD_B1_00::new(), + p01: GPIO_SD_B1_01::new(), + p02: GPIO_SD_B1_02::new(), + p03: GPIO_SD_B1_03::new(), + p04: GPIO_SD_B1_04::new(), + p05: GPIO_SD_B1_05::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_SD_B2. +pub mod gpio_sd_b2 { + + const GPIO_SD_B2_00_MUX_ADDR: u32 = 0x42a101b4; + const GPIO_SD_B2_00_PAD_ADDR: u32 = 0x42a103fc; + pub type GPIO_SD_B2_00 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 10; + } + + const GPIO_SD_B2_01_MUX_ADDR: u32 = 0x42a101b8; + const GPIO_SD_B2_01_PAD_ADDR: u32 = 0x42a10400; + pub type GPIO_SD_B2_01 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 11; + } + + const GPIO_SD_B2_02_MUX_ADDR: u32 = 0x42a101bc; + const GPIO_SD_B2_02_PAD_ADDR: u32 = 0x42a10404; + pub type GPIO_SD_B2_02 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 12; + } + + const GPIO_SD_B2_03_MUX_ADDR: u32 = 0x42a101c0; + const GPIO_SD_B2_03_PAD_ADDR: u32 = 0x42a10408; + pub type GPIO_SD_B2_03 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 13; + } + + const GPIO_SD_B2_04_MUX_ADDR: u32 = 0x42a101c4; + const GPIO_SD_B2_04_PAD_ADDR: u32 = 0x42a1040c; + pub type GPIO_SD_B2_04 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 14; + } + + const GPIO_SD_B2_05_MUX_ADDR: u32 = 0x42a101c8; + const GPIO_SD_B2_05_PAD_ADDR: u32 = 0x42a10410; + pub type GPIO_SD_B2_05 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 15; + } + + const GPIO_SD_B2_06_MUX_ADDR: u32 = 0x42a101cc; + const GPIO_SD_B2_06_PAD_ADDR: u32 = 0x42a10414; + pub type GPIO_SD_B2_06 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 16; + } + + const GPIO_SD_B2_07_MUX_ADDR: u32 = 0x42a101d0; + const GPIO_SD_B2_07_PAD_ADDR: u32 = 0x42a10418; + pub type GPIO_SD_B2_07 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 17; + } + + const GPIO_SD_B2_08_MUX_ADDR: u32 = 0x42a101d4; + const GPIO_SD_B2_08_PAD_ADDR: u32 = 0x42a1041c; + pub type GPIO_SD_B2_08 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 18; + } + + const GPIO_SD_B2_09_MUX_ADDR: u32 = 0x42a101d8; + const GPIO_SD_B2_09_PAD_ADDR: u32 = 0x42a10420; + pub type GPIO_SD_B2_09 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 19; + } + + const GPIO_SD_B2_10_MUX_ADDR: u32 = 0x42a101dc; + const GPIO_SD_B2_10_PAD_ADDR: u32 = 0x42a10424; + pub type GPIO_SD_B2_10 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 20; + } + + const GPIO_SD_B2_11_MUX_ADDR: u32 = 0x42a101e0; + const GPIO_SD_B2_11_PAD_ADDR: u32 = 0x42a10428; + pub type GPIO_SD_B2_11 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 21; + } + + const GPIO_SD_B2_12_MUX_ADDR: u32 = 0x42a101e4; + const GPIO_SD_B2_12_PAD_ADDR: u32 = 0x42a1042c; + pub type GPIO_SD_B2_12 = crate::Pad; + + impl crate::gpio::Pin<5> for GPIO_SD_B2_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 22; + } + + /// All pads with prefix GPIO_SD_B2. + pub struct Pads { + pub p00: GPIO_SD_B2_00, + pub p01: GPIO_SD_B2_01, + pub p02: GPIO_SD_B2_02, + pub p03: GPIO_SD_B2_03, + pub p04: GPIO_SD_B2_04, + pub p05: GPIO_SD_B2_05, + pub p06: GPIO_SD_B2_06, + pub p07: GPIO_SD_B2_07, + pub p08: GPIO_SD_B2_08, + pub p09: GPIO_SD_B2_09, + pub p10: GPIO_SD_B2_10, + pub p11: GPIO_SD_B2_11, + pub p12: GPIO_SD_B2_12, + } + /// Erased pads with prefix GPIO_SD_B2. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 13]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_SD_B2_00::new(), + p01: GPIO_SD_B2_01::new(), + p02: GPIO_SD_B2_02::new(), + p03: GPIO_SD_B2_03::new(), + p04: GPIO_SD_B2_04::new(), + p05: GPIO_SD_B2_05::new(), + p06: GPIO_SD_B2_06::new(), + p07: GPIO_SD_B2_07::new(), + p08: GPIO_SD_B2_08::new(), + p09: GPIO_SD_B2_09::new(), + p10: GPIO_SD_B2_10::new(), + p11: GPIO_SD_B2_11::new(), + p12: GPIO_SD_B2_12::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_B1. +pub mod gpio_b1 { + + const GPIO_B1_00_MUX_ADDR: u32 = 0x42a101e8; + const GPIO_B1_00_PAD_ADDR: u32 = 0x42a10430; + pub type GPIO_B1_00 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_B1_01_MUX_ADDR: u32 = 0x42a101ec; + const GPIO_B1_01_PAD_ADDR: u32 = 0x42a10434; + pub type GPIO_B1_01 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_B1_02_MUX_ADDR: u32 = 0x42a101f0; + const GPIO_B1_02_PAD_ADDR: u32 = 0x42a10438; + pub type GPIO_B1_02 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_B1_03_MUX_ADDR: u32 = 0x42a101f4; + const GPIO_B1_03_PAD_ADDR: u32 = 0x42a1043c; + pub type GPIO_B1_03 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_B1_04_MUX_ADDR: u32 = 0x42a101f8; + const GPIO_B1_04_PAD_ADDR: u32 = 0x42a10440; + pub type GPIO_B1_04 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 4; + } + + const GPIO_B1_05_MUX_ADDR: u32 = 0x42a101fc; + const GPIO_B1_05_PAD_ADDR: u32 = 0x42a10444; + pub type GPIO_B1_05 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 5; + } + + const GPIO_B1_06_MUX_ADDR: u32 = 0x42a10200; + const GPIO_B1_06_PAD_ADDR: u32 = 0x42a10448; + pub type GPIO_B1_06 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 6; + } + + const GPIO_B1_07_MUX_ADDR: u32 = 0x42a10204; + const GPIO_B1_07_PAD_ADDR: u32 = 0x42a1044c; + pub type GPIO_B1_07 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 7; + } + + const GPIO_B1_08_MUX_ADDR: u32 = 0x42a10208; + const GPIO_B1_08_PAD_ADDR: u32 = 0x42a10450; + pub type GPIO_B1_08 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 8; + } + + const GPIO_B1_09_MUX_ADDR: u32 = 0x42a1020c; + const GPIO_B1_09_PAD_ADDR: u32 = 0x42a10454; + pub type GPIO_B1_09 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 9; + } + + const GPIO_B1_10_MUX_ADDR: u32 = 0x42a10210; + const GPIO_B1_10_PAD_ADDR: u32 = 0x42a10458; + pub type GPIO_B1_10 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 10; + } + + const GPIO_B1_11_MUX_ADDR: u32 = 0x42a10214; + const GPIO_B1_11_PAD_ADDR: u32 = 0x42a1045c; + pub type GPIO_B1_11 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 11; + } + + const GPIO_B1_12_MUX_ADDR: u32 = 0x42a10218; + const GPIO_B1_12_PAD_ADDR: u32 = 0x42a10460; + pub type GPIO_B1_12 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 12; + } + + const GPIO_B1_13_MUX_ADDR: u32 = 0x42a1021c; + const GPIO_B1_13_PAD_ADDR: u32 = 0x42a10464; + pub type GPIO_B1_13 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B1_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 13; + } + + /// All pads with prefix GPIO_B1. + pub struct Pads { + pub p00: GPIO_B1_00, + pub p01: GPIO_B1_01, + pub p02: GPIO_B1_02, + pub p03: GPIO_B1_03, + pub p04: GPIO_B1_04, + pub p05: GPIO_B1_05, + pub p06: GPIO_B1_06, + pub p07: GPIO_B1_07, + pub p08: GPIO_B1_08, + pub p09: GPIO_B1_09, + pub p10: GPIO_B1_10, + pub p11: GPIO_B1_11, + pub p12: GPIO_B1_12, + pub p13: GPIO_B1_13, + } + /// Erased pads with prefix GPIO_B1. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 14]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_B1_00::new(), + p01: GPIO_B1_01::new(), + p02: GPIO_B1_02::new(), + p03: GPIO_B1_03::new(), + p04: GPIO_B1_04::new(), + p05: GPIO_B1_05::new(), + p06: GPIO_B1_06::new(), + p07: GPIO_B1_07::new(), + p08: GPIO_B1_08::new(), + p09: GPIO_B1_09::new(), + p10: GPIO_B1_10::new(), + p11: GPIO_B1_11::new(), + p12: GPIO_B1_12::new(), + p13: GPIO_B1_13::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_B2. +pub mod gpio_b2 { + + const GPIO_B2_00_MUX_ADDR: u32 = 0x42a10220; + const GPIO_B2_00_PAD_ADDR: u32 = 0x42a10468; + pub type GPIO_B2_00 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 14; + } + + const GPIO_B2_01_MUX_ADDR: u32 = 0x42a10224; + const GPIO_B2_01_PAD_ADDR: u32 = 0x42a1046c; + pub type GPIO_B2_01 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 15; + } + + const GPIO_B2_02_MUX_ADDR: u32 = 0x42a10228; + const GPIO_B2_02_PAD_ADDR: u32 = 0x42a10470; + pub type GPIO_B2_02 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 16; + } + + const GPIO_B2_03_MUX_ADDR: u32 = 0x42a1022c; + const GPIO_B2_03_PAD_ADDR: u32 = 0x42a10474; + pub type GPIO_B2_03 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 17; + } + + const GPIO_B2_04_MUX_ADDR: u32 = 0x42a10230; + const GPIO_B2_04_PAD_ADDR: u32 = 0x42a10478; + pub type GPIO_B2_04 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 18; + } + + const GPIO_B2_05_MUX_ADDR: u32 = 0x42a10234; + const GPIO_B2_05_PAD_ADDR: u32 = 0x42a1047c; + pub type GPIO_B2_05 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 19; + } + + const GPIO_B2_06_MUX_ADDR: u32 = 0x42a10238; + const GPIO_B2_06_PAD_ADDR: u32 = 0x42a10480; + pub type GPIO_B2_06 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 20; + } + + const GPIO_B2_07_MUX_ADDR: u32 = 0x42a1023c; + const GPIO_B2_07_PAD_ADDR: u32 = 0x42a10484; + pub type GPIO_B2_07 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 21; + } + + const GPIO_B2_08_MUX_ADDR: u32 = 0x42a10240; + const GPIO_B2_08_PAD_ADDR: u32 = 0x42a10488; + pub type GPIO_B2_08 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 22; + } + + const GPIO_B2_09_MUX_ADDR: u32 = 0x42a10244; + const GPIO_B2_09_PAD_ADDR: u32 = 0x42a1048c; + pub type GPIO_B2_09 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 23; + } + + const GPIO_B2_10_MUX_ADDR: u32 = 0x42a10248; + const GPIO_B2_10_PAD_ADDR: u32 = 0x42a10490; + pub type GPIO_B2_10 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 24; + } + + const GPIO_B2_11_MUX_ADDR: u32 = 0x42a1024c; + const GPIO_B2_11_PAD_ADDR: u32 = 0x42a10494; + pub type GPIO_B2_11 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 25; + } + + const GPIO_B2_12_MUX_ADDR: u32 = 0x42a10250; + const GPIO_B2_12_PAD_ADDR: u32 = 0x42a10498; + pub type GPIO_B2_12 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 26; + } + + const GPIO_B2_13_MUX_ADDR: u32 = 0x42a10254; + const GPIO_B2_13_PAD_ADDR: u32 = 0x42a1049c; + pub type GPIO_B2_13 = crate::Pad; + + impl crate::gpio::Pin<6> for GPIO_B2_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 27; + } + + /// All pads with prefix GPIO_B2. + pub struct Pads { + pub p00: GPIO_B2_00, + pub p01: GPIO_B2_01, + pub p02: GPIO_B2_02, + pub p03: GPIO_B2_03, + pub p04: GPIO_B2_04, + pub p05: GPIO_B2_05, + pub p06: GPIO_B2_06, + pub p07: GPIO_B2_07, + pub p08: GPIO_B2_08, + pub p09: GPIO_B2_09, + pub p10: GPIO_B2_10, + pub p11: GPIO_B2_11, + pub p12: GPIO_B2_12, + pub p13: GPIO_B2_13, + } + /// Erased pads with prefix GPIO_B2. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 14]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_B2_00::new(), + p01: GPIO_B2_01::new(), + p02: GPIO_B2_02::new(), + p03: GPIO_B2_03::new(), + p04: GPIO_B2_04::new(), + p05: GPIO_B2_05::new(), + p06: GPIO_B2_06::new(), + p07: GPIO_B2_07::new(), + p08: GPIO_B2_08::new(), + p09: GPIO_B2_09::new(), + p10: GPIO_B2_10::new(), + p11: GPIO_B2_11::new(), + p12: GPIO_B2_12::new(), + p13: GPIO_B2_13::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + ] + } + } +} + +/// Pads with the prefix GPIO_AON. +pub mod gpio_aon { + + const GPIO_AON_00_MUX_ADDR: u32 = 0x443c0000; + const GPIO_AON_00_PAD_ADDR: u32 = 0x443c0074; + pub type GPIO_AON_00 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_00 { + const ALT: u32 = 5; + const OFFSET: u32 = 0; + } + + const GPIO_AON_01_MUX_ADDR: u32 = 0x443c0004; + const GPIO_AON_01_PAD_ADDR: u32 = 0x443c0078; + pub type GPIO_AON_01 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_01 { + const ALT: u32 = 5; + const OFFSET: u32 = 1; + } + + const GPIO_AON_02_MUX_ADDR: u32 = 0x443c0008; + const GPIO_AON_02_PAD_ADDR: u32 = 0x443c007c; + pub type GPIO_AON_02 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_02 { + const ALT: u32 = 5; + const OFFSET: u32 = 2; + } + + const GPIO_AON_03_MUX_ADDR: u32 = 0x443c000c; + const GPIO_AON_03_PAD_ADDR: u32 = 0x443c0080; + pub type GPIO_AON_03 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_03 { + const ALT: u32 = 5; + const OFFSET: u32 = 3; + } + + const GPIO_AON_04_MUX_ADDR: u32 = 0x443c0010; + const GPIO_AON_04_PAD_ADDR: u32 = 0x443c0084; + pub type GPIO_AON_04 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_04 { + const ALT: u32 = 5; + const OFFSET: u32 = 4; + } + + const GPIO_AON_05_MUX_ADDR: u32 = 0x443c0014; + const GPIO_AON_05_PAD_ADDR: u32 = 0x443c0088; + pub type GPIO_AON_05 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_05 { + const ALT: u32 = 5; + const OFFSET: u32 = 5; + } + + const GPIO_AON_06_MUX_ADDR: u32 = 0x443c0018; + const GPIO_AON_06_PAD_ADDR: u32 = 0x443c008c; + pub type GPIO_AON_06 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_06 { + const ALT: u32 = 5; + const OFFSET: u32 = 6; + } + + const GPIO_AON_07_MUX_ADDR: u32 = 0x443c001c; + const GPIO_AON_07_PAD_ADDR: u32 = 0x443c0090; + pub type GPIO_AON_07 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_07 { + const ALT: u32 = 5; + const OFFSET: u32 = 7; + } + + const GPIO_AON_08_MUX_ADDR: u32 = 0x443c0020; + const GPIO_AON_08_PAD_ADDR: u32 = 0x443c0094; + pub type GPIO_AON_08 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_08 { + const ALT: u32 = 5; + const OFFSET: u32 = 8; + } + + const GPIO_AON_09_MUX_ADDR: u32 = 0x443c0024; + const GPIO_AON_09_PAD_ADDR: u32 = 0x443c0098; + pub type GPIO_AON_09 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_09 { + const ALT: u32 = 5; + const OFFSET: u32 = 9; + } + + const GPIO_AON_10_MUX_ADDR: u32 = 0x443c0028; + const GPIO_AON_10_PAD_ADDR: u32 = 0x443c009c; + pub type GPIO_AON_10 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_10 { + const ALT: u32 = 5; + const OFFSET: u32 = 10; + } + + const GPIO_AON_11_MUX_ADDR: u32 = 0x443c002c; + const GPIO_AON_11_PAD_ADDR: u32 = 0x443c00a0; + pub type GPIO_AON_11 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_11 { + const ALT: u32 = 5; + const OFFSET: u32 = 11; + } + + const GPIO_AON_12_MUX_ADDR: u32 = 0x443c0030; + const GPIO_AON_12_PAD_ADDR: u32 = 0x443c00a4; + pub type GPIO_AON_12 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_12 { + const ALT: u32 = 5; + const OFFSET: u32 = 12; + } + + const GPIO_AON_13_MUX_ADDR: u32 = 0x443c0034; + const GPIO_AON_13_PAD_ADDR: u32 = 0x443c00a8; + pub type GPIO_AON_13 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_13 { + const ALT: u32 = 5; + const OFFSET: u32 = 13; + } + + const GPIO_AON_14_MUX_ADDR: u32 = 0x443c0038; + const GPIO_AON_14_PAD_ADDR: u32 = 0x443c00ac; + pub type GPIO_AON_14 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_14 { + const ALT: u32 = 5; + const OFFSET: u32 = 14; + } + + const GPIO_AON_15_MUX_ADDR: u32 = 0x443c003c; + const GPIO_AON_15_PAD_ADDR: u32 = 0x443c00b0; + pub type GPIO_AON_15 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_15 { + const ALT: u32 = 5; + const OFFSET: u32 = 15; + } + + const GPIO_AON_16_MUX_ADDR: u32 = 0x443c0040; + const GPIO_AON_16_PAD_ADDR: u32 = 0x443c00b4; + pub type GPIO_AON_16 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_16 { + const ALT: u32 = 5; + const OFFSET: u32 = 16; + } + + const GPIO_AON_17_MUX_ADDR: u32 = 0x443c0044; + const GPIO_AON_17_PAD_ADDR: u32 = 0x443c00b8; + pub type GPIO_AON_17 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_17 { + const ALT: u32 = 5; + const OFFSET: u32 = 17; + } + + const GPIO_AON_18_MUX_ADDR: u32 = 0x443c0048; + const GPIO_AON_18_PAD_ADDR: u32 = 0x443c00bc; + pub type GPIO_AON_18 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_18 { + const ALT: u32 = 5; + const OFFSET: u32 = 18; + } + + const GPIO_AON_19_MUX_ADDR: u32 = 0x443c004c; + const GPIO_AON_19_PAD_ADDR: u32 = 0x443c00c0; + pub type GPIO_AON_19 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_19 { + const ALT: u32 = 5; + const OFFSET: u32 = 19; + } + + const GPIO_AON_20_MUX_ADDR: u32 = 0x443c0050; + const GPIO_AON_20_PAD_ADDR: u32 = 0x443c00c4; + pub type GPIO_AON_20 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_20 { + const ALT: u32 = 5; + const OFFSET: u32 = 20; + } + + const GPIO_AON_21_MUX_ADDR: u32 = 0x443c0054; + const GPIO_AON_21_PAD_ADDR: u32 = 0x443c00c8; + pub type GPIO_AON_21 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_21 { + const ALT: u32 = 5; + const OFFSET: u32 = 21; + } + + const GPIO_AON_22_MUX_ADDR: u32 = 0x443c0058; + const GPIO_AON_22_PAD_ADDR: u32 = 0x443c00cc; + pub type GPIO_AON_22 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_22 { + const ALT: u32 = 5; + const OFFSET: u32 = 22; + } + + const GPIO_AON_23_MUX_ADDR: u32 = 0x443c005c; + const GPIO_AON_23_PAD_ADDR: u32 = 0x443c00d0; + pub type GPIO_AON_23 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_23 { + const ALT: u32 = 5; + const OFFSET: u32 = 23; + } + + const GPIO_AON_24_MUX_ADDR: u32 = 0x443c0060; + const GPIO_AON_24_PAD_ADDR: u32 = 0x443c00d4; + pub type GPIO_AON_24 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_24 { + const ALT: u32 = 5; + const OFFSET: u32 = 24; + } + + const GPIO_AON_25_MUX_ADDR: u32 = 0x443c0064; + const GPIO_AON_25_PAD_ADDR: u32 = 0x443c00d8; + pub type GPIO_AON_25 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_25 { + const ALT: u32 = 5; + const OFFSET: u32 = 25; + } + + const GPIO_AON_26_MUX_ADDR: u32 = 0x443c0068; + const GPIO_AON_26_PAD_ADDR: u32 = 0x443c00dc; + pub type GPIO_AON_26 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_26 { + const ALT: u32 = 5; + const OFFSET: u32 = 26; + } + + const GPIO_AON_27_MUX_ADDR: u32 = 0x443c006c; + const GPIO_AON_27_PAD_ADDR: u32 = 0x443c00e0; + pub type GPIO_AON_27 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_27 { + const ALT: u32 = 5; + const OFFSET: u32 = 27; + } + + const GPIO_AON_28_MUX_ADDR: u32 = 0x443c0070; + const GPIO_AON_28_PAD_ADDR: u32 = 0x443c00e4; + pub type GPIO_AON_28 = crate::Pad; + + impl crate::gpio::Pin<1> for GPIO_AON_28 { + const ALT: u32 = 5; + const OFFSET: u32 = 28; + } + + /// All pads with prefix GPIO_AON. + pub struct Pads { + pub p00: GPIO_AON_00, + pub p01: GPIO_AON_01, + pub p02: GPIO_AON_02, + pub p03: GPIO_AON_03, + pub p04: GPIO_AON_04, + pub p05: GPIO_AON_05, + pub p06: GPIO_AON_06, + pub p07: GPIO_AON_07, + pub p08: GPIO_AON_08, + pub p09: GPIO_AON_09, + pub p10: GPIO_AON_10, + pub p11: GPIO_AON_11, + pub p12: GPIO_AON_12, + pub p13: GPIO_AON_13, + pub p14: GPIO_AON_14, + pub p15: GPIO_AON_15, + pub p16: GPIO_AON_16, + pub p17: GPIO_AON_17, + pub p18: GPIO_AON_18, + pub p19: GPIO_AON_19, + pub p20: GPIO_AON_20, + pub p21: GPIO_AON_21, + pub p22: GPIO_AON_22, + pub p23: GPIO_AON_23, + pub p24: GPIO_AON_24, + pub p25: GPIO_AON_25, + pub p26: GPIO_AON_26, + pub p27: GPIO_AON_27, + pub p28: GPIO_AON_28, + } + /// Erased pads with prefix GPIO_AON. + /// + /// Use [`Pads::erase()`] to get an `ErasedPads` instance. + pub type ErasedPads = [crate::ErasedPad; 29]; + impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + p00: GPIO_AON_00::new(), + p01: GPIO_AON_01::new(), + p02: GPIO_AON_02::new(), + p03: GPIO_AON_03::new(), + p04: GPIO_AON_04::new(), + p05: GPIO_AON_05::new(), + p06: GPIO_AON_06::new(), + p07: GPIO_AON_07::new(), + p08: GPIO_AON_08::new(), + p09: GPIO_AON_09::new(), + p10: GPIO_AON_10::new(), + p11: GPIO_AON_11::new(), + p12: GPIO_AON_12::new(), + p13: GPIO_AON_13::new(), + p14: GPIO_AON_14::new(), + p15: GPIO_AON_15::new(), + p16: GPIO_AON_16::new(), + p17: GPIO_AON_17::new(), + p18: GPIO_AON_18::new(), + p19: GPIO_AON_19::new(), + p20: GPIO_AON_20::new(), + p21: GPIO_AON_21::new(), + p22: GPIO_AON_22::new(), + p23: GPIO_AON_23::new(), + p24: GPIO_AON_24::new(), + p25: GPIO_AON_25::new(), + p26: GPIO_AON_26::new(), + p27: GPIO_AON_27::new(), + p28: GPIO_AON_28::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + [ + self.p00.erase(), + self.p01.erase(), + self.p02.erase(), + self.p03.erase(), + self.p04.erase(), + self.p05.erase(), + self.p06.erase(), + self.p07.erase(), + self.p08.erase(), + self.p09.erase(), + self.p10.erase(), + self.p11.erase(), + self.p12.erase(), + self.p13.erase(), + self.p14.erase(), + self.p15.erase(), + self.p16.erase(), + self.p17.erase(), + self.p18.erase(), + self.p19.erase(), + self.p20.erase(), + self.p21.erase(), + self.p22.erase(), + self.p23.erase(), + self.p24.erase(), + self.p25.erase(), + self.p26.erase(), + self.p27.erase(), + self.p28.erase(), + ] + } + } +} + +/// All of the pads. +pub struct Pads { + pub gpio_emc_b1: gpio_emc_b1::Pads, + pub gpio_emc_b2: gpio_emc_b2::Pads, + pub gpio_ad: gpio_ad::Pads, + pub gpio_sd_b1: gpio_sd_b1::Pads, + pub gpio_sd_b2: gpio_sd_b2::Pads, + pub gpio_b1: gpio_b1::Pads, + pub gpio_b2: gpio_b2::Pads, + pub gpio_aon: gpio_aon::Pads, +} + +impl Pads { + /// Take all pads from this group + /// + /// # Safety + /// + /// You may safely call this once to acquire all of the pads. + /// Subsequent calls may return pads that are mutably aliased + /// elsewhere. Consider calling new() at the start of your program. + #[inline] + pub const unsafe fn new() -> Self { + Self { + gpio_emc_b1: gpio_emc_b1::Pads::new(), + gpio_emc_b2: gpio_emc_b2::Pads::new(), + gpio_ad: gpio_ad::Pads::new(), + gpio_sd_b1: gpio_sd_b1::Pads::new(), + gpio_sd_b2: gpio_sd_b2::Pads::new(), + gpio_b1: gpio_b1::Pads::new(), + gpio_b2: gpio_b2::Pads::new(), + gpio_aon: gpio_aon::Pads::new(), + } + } + + /// Erase all of the pads + /// + /// The return type is an array, where the index indicates the + /// pad offset from the start of the group. For example, AD_B0_03 + /// would be referenced as erased_pads\[3\]. + /// + /// See `ErasedPads` for more information. + #[inline] + pub const fn erase(self) -> ErasedPads { + ErasedPads { + gpio_emc_b1: self.gpio_emc_b1.erase(), + gpio_emc_b2: self.gpio_emc_b2.erase(), + gpio_ad: self.gpio_ad.erase(), + gpio_sd_b1: self.gpio_sd_b1.erase(), + gpio_sd_b2: self.gpio_sd_b2.erase(), + gpio_b1: self.gpio_b1.erase(), + gpio_b2: self.gpio_b2.erase(), + gpio_aon: self.gpio_aon.erase(), + } + } +} + +/// All erased pads. +pub struct ErasedPads { + pub gpio_emc_b1: gpio_emc_b1::ErasedPads, + pub gpio_emc_b2: gpio_emc_b2::ErasedPads, + pub gpio_ad: gpio_ad::ErasedPads, + pub gpio_sd_b1: gpio_sd_b1::ErasedPads, + pub gpio_sd_b2: gpio_sd_b2::ErasedPads, + pub gpio_b1: gpio_b1::ErasedPads, + pub gpio_b2: gpio_b2::ErasedPads, + pub gpio_aon: gpio_aon::ErasedPads, +} diff --git a/src/lib.rs b/src/lib.rs index 57d5aa0..13618c8 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -277,6 +277,10 @@ pub mod imxrt1060; #[cfg_attr(docsrs, doc(cfg(feature = "imxrt1170")))] pub mod imxrt1170; +#[cfg(feature = "imxrt1180")] +#[cfg_attr(docsrs, doc(cfg(feature = "imxrt1180")))] +pub mod imxrt1180; + /// An IOMUXC-capable pad which can support I/O multiplexing /// /// # Safety