From 349e38fff38719ea1ef9d8a9c55c3473727d6616 Mon Sep 17 00:00:00 2001 From: Hatim Thayyil Date: Wed, 31 Jan 2024 09:47:30 +0000 Subject: [PATCH] Add 1050 chip configuration There's no in-tree hardware examples. Nevertheless, it was tested on custom hardware. --- .github/workflows/rust.yml | 3 + CHANGELOG.md | 2 + Cargo.toml | 1 + src/chip/imxrt10xx.rs | 3 + src/chip/imxrt10xx/ccm.rs | 4 +- src/chip/imxrt10xx/imxrt1050.rs | 124 ++++++++++++++++++++++++++++++++ src/lib.rs | 1 + 7 files changed, 136 insertions(+), 2 deletions(-) create mode 100644 src/chip/imxrt10xx/imxrt1050.rs diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml index 00ccaf27..991c81c2 100644 --- a/.github/workflows/rust.yml +++ b/.github/workflows/rust.yml @@ -57,6 +57,8 @@ jobs: chips: - imxrt-ral/imxrt1011,imxrt1010 - imxrt-ral/imxrt1021,imxrt1020 + - imxrt-ral/imxrt1051,imxrt1050 + - imxrt-ral/imxrt1052,imxrt1050 - imxrt-ral/imxrt1061,imxrt1060 - imxrt-ral/imxrt1062,imxrt1060 - imxrt-ral/imxrt1064,imxrt1060 @@ -136,6 +138,7 @@ jobs: chips: - imxrt-ral/imxrt1011,imxrt1010 - imxrt-ral/imxrt1021,imxrt1020 + - imxrt-ral/imxrt1052,imxrt1050 - imxrt-ral/imxrt1062,imxrt1060 - imxrt-ral/imxrt1176_cm7,imxrt1170 runs-on: ubuntu-latest diff --git a/CHANGELOG.md b/CHANGELOG.md index 05b41178..739d0b6a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,8 @@ ## [Unreleased] +Add support for the i.MX RT 1050 processors with the `"imxrt1050"` feature. + Add embedded-hal 1 implementations for the following drivers: - GPIO diff --git a/Cargo.toml b/Cargo.toml index 77c9dd02..719e66f7 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -78,6 +78,7 @@ features = ["imxrt-ral/imxrt1062", "imxrt1060"] default = ["imxrt-usbd"] imxrt1010 = ["imxrt-iomuxc/imxrt1010"] imxrt1020 = ["imxrt-iomuxc/imxrt1020"] +imxrt1050 = ["imxrt-iomuxc/imxrt1050"] imxrt1060 = ["imxrt-iomuxc/imxrt1060"] imxrt1064 = ["imxrt-iomuxc/imxrt1060"] imxrt1170 = ["imxrt-iomuxc/imxrt1170"] diff --git a/src/chip/imxrt10xx.rs b/src/chip/imxrt10xx.rs index ef453cb9..98d770ae 100644 --- a/src/chip/imxrt10xx.rs +++ b/src/chip/imxrt10xx.rs @@ -18,6 +18,9 @@ cfg_if::cfg_if! { } else if #[cfg(chip = "imxrt1020")] { #[path = "imxrt10xx/imxrt1020.rs"] pub(crate) mod config; + } else if #[cfg(any(chip = "imxrt1050"))] { + #[path = "imxrt10xx/imxrt1050.rs"] + pub(crate) mod config; } else if #[cfg(any(chip = "imxrt1060", chip = "imxrt1064"))] { #[path = "imxrt10xx/imxrt1060.rs"] pub(crate) mod config; diff --git a/src/chip/imxrt10xx/ccm.rs b/src/chip/imxrt10xx/ccm.rs index 20e9c2bc..0ed7a732 100644 --- a/src/chip/imxrt10xx/ccm.rs +++ b/src/chip/imxrt10xx/ccm.rs @@ -466,7 +466,7 @@ macro_rules! ccm_flexio { /// Derive from PLL3_PFD2. Pll3Pfd2 = 1, - #[cfg(any(feature = "imxrt1060", feature = "imxrt1064"))] + #[cfg(any(feature = "imxrt1050", feature = "imxrt1060", feature = "imxrt1064"))] /// Derive from PLL5. Pll5 = 2, #[cfg(feature = "imxrt1010")] @@ -487,7 +487,7 @@ macro_rules! ccm_flexio { match ral::read_reg!(ral::ccm, ccm, $sel_reg, $sel_field) { 0 => Selection::Pll4, 1 => Selection::Pll3Pfd2, - #[cfg(any(feature = "imxrt1060", feature = "imxrt1064"))] + #[cfg(any(feature = "imxrt1050", feature = "imxrt1060", feature = "imxrt1064"))] 2 => Selection::Pll5, #[cfg(feature = "imxrt1010")] 2 => Selection::Pll2, diff --git a/src/chip/imxrt10xx/imxrt1050.rs b/src/chip/imxrt10xx/imxrt1050.rs new file mode 100644 index 00000000..82a20a71 --- /dev/null +++ b/src/chip/imxrt10xx/imxrt1050.rs @@ -0,0 +1,124 @@ +//! i.MX RT 1050 chip family features. +//! +//! Use this module to customize features for the +//! 1050 chips. + +pub use imxrt_iomuxc::imxrt1050 as pads; + +#[path = "ccm"] +pub(crate) mod ccm { + pub mod arm_divider; + + #[path = "pre_periph_clk_pll1.rs"] + pub mod pre_periph_clk; + + mod periph_clk2_podf; + mod periph_clk2_sel; + + /// Peripheral clock 2. + pub mod periph_clk2 { + pub use super::periph_clk2_podf::*; + pub use super::periph_clk2_sel::*; + } + + pub(crate) mod analog { + pub mod pll1; + } + + /// Re-exported by the common clock_gate module. + pub(crate) mod clock_gate { + use crate::chip::ccm::clock_gate; + + /// All clock gates downstream of the PERCLK root clock. + pub const PERCLK_CLOCK_GATES: &[clock_gate::Locator] = &[ + clock_gate::pit(), + clock_gate::gpt_bus::<1>(), + clock_gate::gpt_bus::<2>(), + clock_gate::gpt_serial::<1>(), + clock_gate::gpt_serial::<2>(), + ]; + + /// All clock gates downstream of the UART root clock. + pub const UART_CLOCK_GATES: &[clock_gate::Locator] = &[ + clock_gate::lpuart::<1>(), + clock_gate::lpuart::<2>(), + clock_gate::lpuart::<3>(), + clock_gate::lpuart::<4>(), + clock_gate::lpuart::<5>(), + clock_gate::lpuart::<6>(), + clock_gate::lpuart::<7>(), + clock_gate::lpuart::<8>(), + ]; + + /// All clock gates downstream of the LPSPI root clock. + pub const LPSPI_CLOCK_GATES: &[clock_gate::Locator] = &[ + clock_gate::lpspi::<1>(), + clock_gate::lpspi::<2>(), + clock_gate::lpspi::<3>(), + clock_gate::lpspi::<4>(), + ]; + + /// All clock gates downstream of the LPI2C root clock. + pub const LPI2C_CLOCK_GATES: &[clock_gate::Locator] = &[ + clock_gate::lpi2c::<1>(), + clock_gate::lpi2c::<2>(), + clock_gate::lpi2c::<3>(), + clock_gate::lpi2c::<4>(), + ]; + + /// All clock gates downstream of the IPG root clock. + pub const IPG_CLOCK_GATES: &[clock_gate::Locator] = &[ + clock_gate::adc::<1>(), + clock_gate::adc::<2>(), + clock_gate::dma(), + clock_gate::flexpwm::<1>(), + clock_gate::flexpwm::<2>(), + clock_gate::flexpwm::<3>(), + clock_gate::flexpwm::<4>(), + // GPIOs assume that we're not "fast," since the fast + // GPIOs run directly off the ARM / AHB clock. This + // is safe for now, since we don't currently support fast + // GPIOs. + clock_gate::gpio::<1>(), + clock_gate::gpio::<2>(), + clock_gate::gpio::<3>(), + clock_gate::gpio::<4>(), + clock_gate::gpio::<5>(), + clock_gate::trng(), + clock_gate::snvs_lp(), + clock_gate::snvs_hp(), + clock_gate::usb(), + ]; + } + + // TODO + pub(crate) mod clko { + /// CLKO1 output clock selections. + // #[repr(u32)] + #[derive(Debug, Clone, Copy, PartialEq, Eq)] + + pub enum Clko1Selection {} + + /// CLKO2 output clock selections. + // #[repr(u32)] + #[derive(Debug, Clone, Copy, PartialEq, Eq)] + + pub enum Clko2Selection {} + } + + ccm_flexio!( + flexio1_clk, "FLEXIO1", + divider: (CDCDR, FLEXIO1_CLK_PODF), + predivider: (CDCDR, FLEXIO1_CLK_PRED), + selection: (CDCDR, FLEXIO1_CLK_SEL), + ); + + ccm_flexio!( + flexio2_clk, "FLEXIO2", + divider: (CS1CDR, FLEXIO2_CLK_PODF), + predivider: (CS1CDR, FLEXIO2_CLK_PRED), + selection: (CSCMR2, FLEXIO2_CLK_SEL), + ); +} + +pub(crate) const DMA_CHANNEL_COUNT: usize = 32; diff --git a/src/lib.rs b/src/lib.rs index d0993d63..bd48519c 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -47,6 +47,7 @@ //! |-------------------|------------------------------------------------------------------| //! | `"imxrt1010"` | Enable features for the 1010 chips. | //! | `"imxrt1020"` | Enable features for the 1020 chips. | +//! | `"imxrt1050"` | Enable features for the 1050 chips. | //! | `"imxrt1060"` | Enable features for the 1060 chips. | //! | `"imxrt1064"` | Enable features for the 1064 chips. | //! | `"imxrt1170"` | Enable features for the 1170 chips. |