Synthesis failed

[gzzyyxh]

I followed the tutorial for this project strictly, using Vivado 2018.2 on Ubuntu 18.04. According to the synthesis report, the resource usage ratio is zero. If you proceed with the implementation, an odd error will occur and the program will exit!

Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date         : Tue Mar 12 11:33:45 2024
| Host         : gzzyyxh-System-Product-Name running 64-bit Ubuntu 18.04.6 LTS
| Command      : report_utilization -file kcu115_wrapper_utilization_synth.rpt -pb kcu115_wrapper_utilization_synth.pb
| Design       : kcu115_wrapper
| Device       : xcku115flvb2104-2
| Design State : Synthesized
-----------------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity and Clocking Utilization
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization

1. CLB Logic
------------

+-------------------------+------+-------+-----------+-------+
|        Site Type        | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| CLB LUTs*               |    0 |     0 |    663360 |  0.00 |
|   LUT as Logic          |    0 |     0 |    663360 |  0.00 |
|   LUT as Memory         |    0 |     0 |    293760 |  0.00 |
| CLB Registers           |    0 |     0 |   1326720 |  0.00 |
|   Register as Flip Flop |    0 |     0 |   1326720 |  0.00 |
|   Register as Latch     |    0 |     0 |   1326720 |  0.00 |
| CARRY8                  |    0 |     0 |     82920 |  0.00 |
| F7 Muxes                |    0 |     0 |    331680 |  0.00 |
| F8 Muxes                |    0 |     0 |    165840 |  0.00 |
| F9 Muxes                |    0 |     0 |     82920 |  0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 0     |          Yes |           - |          Set |
| 0     |          Yes |           - |        Reset |
| 0     |          Yes |         Set |            - |
| 0     |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. BLOCKRAM
-----------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile |    0 |     0 |      2160 |  0.00 |
|   RAMB36/FIFO* |    0 |     0 |      2160 |  0.00 |
|   RAMB18       |    0 |     0 |      4320 |  0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2


3. ARITHMETIC
-------------

+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs      |    0 |     0 |      5520 |  0.00 |
+-----------+------+-------+-----------+-------+


4. I/O
------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| Bonded IOB |    2 |     0 |       702 |  0.28 |
+------------+------+-------+-----------+-------+


5. CLOCK
--------

+----------------------+------+-------+-----------+-------+
|       Site Type      | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
| GLOBAL CLOCK BUFFERs |    0 |     0 |      1248 |  0.00 |
|   BUFGCE             |    0 |     0 |       576 |  0.00 |
|   BUFGCE_DIV         |    0 |     0 |        96 |  0.00 |
|   BUFG_GT            |    0 |     0 |       384 |  0.00 |
|   BUFGCTRL*          |    0 |     0 |       192 |  0.00 |
| PLLE3_ADV            |    0 |     0 |        48 |  0.00 |
| MMCME3_ADV           |    0 |     0 |        24 |  0.00 |
+----------------------+------+-------+-----------+-------+
* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.


6. ADVANCED
-----------

+------------------+------+-------+-----------+-------+
|     Site Type    | Used | Fixed | Available | Util% |
+------------------+------+-------+-----------+-------+
| GTHE3_CHANNEL    |    0 |     0 |        64 |  0.00 |
| GTHE3_COMMON     |    0 |     0 |        16 |  0.00 |
| IBUFDS_GTE3      |    0 |     0 |        32 |  0.00 |
| OBUFDS_GTE3      |    0 |     0 |        32 |  0.00 |
| OBUFDS_GTE3_ADV  |    0 |     0 |        32 |  0.00 |
| PCIE_3_1         |    0 |     0 |         6 |  0.00 |
| SYSMONE1         |    0 |     0 |         2 |  0.00 |
| LAGUNA Registers |    0 |     0 |     34560 |  0.00 |
|   as TX_REG      |    0 |       |           |       |
|   as RX_REG      |    0 |       |           |       |
+------------------+------+-------+-----------+-------+


7. CONFIGURATION
----------------

+-------------+------+-------+-----------+-------+
|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2     |    0 |     0 |         8 |  0.00 |
| DNA_PORTE2  |    0 |     0 |         2 |  0.00 |
| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
| FRAME_ECCE3 |    0 |     0 |         1 |  0.00 |
| ICAPE3      |    0 |     0 |         2 |  0.00 |
| MASTER_JTAG |    0 |     0 |         2 |  0.00 |
| STARTUPE3   |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| INBUF    |    2 |                 I/O |
| IBUFCTRL |    2 |              Others |
+----------+------+---------------------+


9. Black Boxes
--------------

+------------------------------+------+
|           Ref Name           | Used |
+------------------------------+------+
| kcu115_xdma_0_0              |    1 |
| kcu115_util_vector_logic_0_0 |    1 |
| kcu115_util_ds_buf_0_0       |    1 |
| kcu115_rst_ddr4_0_300M_0     |    1 |
| kcu115_rst_ddr4_0_100M_0     |    1 |
| kcu115_ddr4_0_0              |    1 |
| kcu115_cl_wrapper_0_0        |    1 |
| kcu115_axi_smc_0             |    1 |
| kcu115_auto_cc_0             |    1 |
+------------------------------+------+


10. Instantiated Netlists
-------------------------

+----------+------+
| Ref Name | Used |
+----------+------+


11. SLR Connectivity and Clocking Utilization
---------------------------------------------

+----------+-----------------+---------+-----------------+--------------+-------+-------+
|          | Total SLLs Used | (%)SLLs | BUFGs/BUFGCTRLs | BUFH/BUFHCEs | BUFRs | MMCMs |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| SLR1     |                 |         |               0 |            0 |     0 |     0 |
| ||||||-> |               0 |    0.00 |                 |              |       |       |
| SLR0     |                 |         |               0 |            0 |     0 |     0 |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| Total    |               0 |         |               0 |            0 |     0 |     0 |
+----------+-----------------+---------+-----------------+--------------+-------+-------+


12. SLR Connectivity Matrix
---------------------------

+------+------+------+
|      | SLR1 | SLR0 |
+------+------+------+
| SLR1 |    0 |    0 |
| SLR0 |    0 |    0 |
+------+------+------+


13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------

+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
| SLR Index | CLBs | (%)CLBs | Total LUTs | Memory LUTs | (%)Total LUTs | Registers | BRAMs | URAM | DSPs |
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
| SLR1      |    0 |    0.00 |          0 |           0 |          0.00 |         0 |     0 |    0 |    0 |
| SLR0      |    0 |    0.00 |          0 |           0 |          0.00 |         0 |     0 |    0 |    0 |
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
| Total     |    0 |         |          0 |           0 |               |         0 |     0 |    0 |    0 |
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+


14. SLR IO Utilization
----------------------

+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
| SLR Index | Bonded IOBs | (%)IOBs | Bonded IPADs | (%)IPADs | Bonded OPADs | (%)OPADs | GTs |
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
| SLR1      |           0 |    0.00 |            0 |     0.00 |            0 |     0.00 |   0 |
| SLR0      |           0 |    0.00 |            0 |     0.00 |            0 |     0.00 |   0 |
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
| Total     |           0 |         |            0 |          |            0 |          |   0 |
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+

After following your tutorial strictly, I'm still unable to get any further suggestions. Are you confident that this project will run correctly? My Vivado-generated block design differs from the tutorial's.

I have tried it for at least 7 days. Could you provide me with more information?