-
Notifications
You must be signed in to change notification settings - Fork 19
/
pci_emul.c
2141 lines (1825 loc) · 50.2 KB
/
pci_emul.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*-
* Copyright (c) 2011 NetApp, Inc.
* Copyright (c) 2015 xhyve developers
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <stdint.h>
#include <stdbool.h>
#include <pthread.h>
#include <errno.h>
#include <assert.h>
#include <xhyve/support/linker_set.h>
#include <xhyve/vmm/vmm_api.h>
#include <xhyve/acpi.h>
#include <xhyve/xhyve.h>
#include <xhyve/inout.h>
#include <xhyve/ioapic.h>
#include <xhyve/mem.h>
#include <xhyve/pci_emul.h>
#include <xhyve/pci_irq.h>
#include <xhyve/pci_lpc.h>
#define CONF1_ADDR_PORT 0x0cf8
#define CONF1_DATA_PORT0 0x0cfc
#define CONF1_DATA_PORT1 0x0cfd
#define CONF1_DATA_PORT2 0x0cfe
#define CONF1_DATA_PORT3 0x0cff
#define CONF1_ENABLE 0x80000000ul
#define MAXBUSES (PCI_BUSMAX + 1)
#define MAXSLOTS (PCI_SLOTMAX + 1)
#define MAXFUNCS (PCI_FUNCMAX + 1)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpadded"
struct funcinfo {
char *fi_name;
char *fi_param;
struct pci_devinst *fi_devi;
};
struct intxinfo {
int ii_count;
int ii_pirq_pin;
int ii_ioapic_irq;
};
struct slotinfo {
struct intxinfo si_intpins[4];
struct funcinfo si_funcs[MAXFUNCS];
};
struct businfo {
uint16_t iobase, iolimit; /* I/O window */
uint32_t membase32, memlimit32; /* mmio window below 4GB */
uint64_t membase64, memlimit64; /* mmio window above 4GB */
struct slotinfo slotinfo[MAXSLOTS];
};
#pragma clang diagnostic pop
static struct businfo *pci_businfo[MAXBUSES];
SET_DECLARE(pci_devemu_set, struct pci_devemu);
static uint64_t pci_emul_iobase;
static uint64_t pci_emul_membase32;
static uint64_t pci_emul_membase64;
#define PCI_EMUL_IOBASE 0x2000
#define PCI_EMUL_IOLIMIT 0x10000
#define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
#define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
#define PCI_EMUL_MEMBASE64 0xD000000000UL
#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
static struct pci_devemu *pci_emul_finddev(char *name);
static void pci_lintr_route(struct pci_devinst *pi);
static void pci_lintr_update(struct pci_devinst *pi);
static void pci_cfgrw(int vcpu, int in, int bus, int slot, int func, int coff,
int bytes, uint32_t *val);
static __inline void
CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
{
if (bytes == 1)
pci_set_cfgdata8(pi, coff, ((uint8_t) val));
else if (bytes == 2)
pci_set_cfgdata16(pi, coff, ((uint16_t) val));
else
pci_set_cfgdata32(pi, coff, val);
}
static __inline uint32_t
CFGREAD(struct pci_devinst *pi, int coff, int bytes)
{
if (bytes == 1)
return (pci_get_cfgdata8(pi, coff));
else if (bytes == 2)
return (pci_get_cfgdata16(pi, coff));
else
return (pci_get_cfgdata32(pi, coff));
}
/*
* I/O access
*/
/*
* Slot options are in the form:
*
* <bus>:<slot>:<func>,<emul>[,<config>]
* <slot>[:<func>],<emul>[,<config>]
*
* slot is 0..31
* func is 0..7
* emul is a string describing the type of PCI device e.g. virtio-net
* config is an optional string, depending on the device, that can be
* used for configuration.
* Examples are:
* 1,virtio-net,tap0
* 3:0,dummy
*/
static void
pci_parse_slot_usage(char *aopt)
{
fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt);
}
int
pci_parse_slot(char *opt)
{
struct businfo *bi;
struct slotinfo *si;
char *emul, *config, *str, *cp;
int error, bnum, snum, fnum;
error = -1;
str = strdup(opt);
emul = config = NULL;
if ((cp = strchr(str, ',')) != NULL) {
*cp = '\0';
emul = cp + 1;
if ((cp = strchr(emul, ',')) != NULL) {
*cp = '\0';
config = cp + 1;
}
} else {
pci_parse_slot_usage(opt);
goto done;
}
/* <bus>:<slot>:<func> */
if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) {
bnum = 0;
/* <slot>:<func> */
if (sscanf(str, "%d:%d", &snum, &fnum) != 2) {
fnum = 0;
/* <slot> */
if (sscanf(str, "%d", &snum) != 1) {
snum = -1;
}
}
}
if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS ||
fnum < 0 || fnum >= MAXFUNCS) {
pci_parse_slot_usage(opt);
goto done;
}
if (pci_businfo[bnum] == NULL)
pci_businfo[bnum] = calloc(1, sizeof(struct businfo));
bi = pci_businfo[bnum];
si = &bi->slotinfo[snum];
if (si->si_funcs[fnum].fi_name != NULL) {
fprintf(stderr, "pci slot %d:%d already occupied!\n",
snum, fnum);
goto done;
}
if (pci_emul_finddev(emul) == NULL) {
fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n",
snum, fnum, emul);
goto done;
}
error = 0;
si->si_funcs[fnum].fi_name = emul;
si->si_funcs[fnum].fi_param = config;
done:
if (error)
free(str);
return (error);
}
static int
pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
{
if (offset < pi->pi_msix.pba_offset)
return (0);
if (offset >= pi->pi_msix.pba_offset + ((unsigned) pi->pi_msix.pba_size)) {
return (0);
}
return (1);
}
int
pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
uint64_t value)
{
int msix_entry_offset;
int tab_index;
char *dest;
/* support only 4 or 8 byte writes */
if (size != 4 && size != 8)
return (-1);
/*
* Return if table index is beyond what device supports
*/
tab_index = (int) (offset / MSIX_TABLE_ENTRY_SIZE);
if (tab_index >= pi->pi_msix.table_count)
return (-1);
msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
/* support only aligned writes */
if ((msix_entry_offset % size) != 0)
return (-1);
dest = (char *)(pi->pi_msix.table + tab_index);
dest += msix_entry_offset;
if (size == 4)
*((uint32_t *)((void *) dest)) = (uint32_t) value;
else
*((uint64_t *)((void *) dest)) = value;
return (0);
}
uint64_t
pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
{
char *dest;
int msix_entry_offset;
int tab_index;
uint64_t retval = ~((uint64_t) 0);
/*
* The PCI standard only allows 4 and 8 byte accesses to the MSI-X
* table but we also allow 1 byte access to accomodate reads from
* ddb.
*/
if (size != 1 && size != 4 && size != 8)
return (retval);
msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE;
/* support only aligned reads */
if ((msix_entry_offset % size) != 0) {
return (retval);
}
tab_index = (int) (offset / MSIX_TABLE_ENTRY_SIZE);
if (tab_index < pi->pi_msix.table_count) {
/* valid MSI-X Table access */
dest = (char *)(pi->pi_msix.table + tab_index);
dest += msix_entry_offset;
if (size == 1)
retval = *((uint8_t *)((void *) dest));
else if (size == 4)
retval = *((uint32_t *)((void *) dest));
else
retval = *((uint64_t *)((void *) dest));
} else if (pci_valid_pba_offset(pi, offset)) {
/* return 0 for PBA access */
retval = 0;
}
return (retval);
}
int
pci_msix_table_bar(struct pci_devinst *pi)
{
if (pi->pi_msix.table != NULL)
return (pi->pi_msix.table_bar);
else
return (-1);
}
int
pci_msix_pba_bar(struct pci_devinst *pi)
{
if (pi->pi_msix.table != NULL)
return (pi->pi_msix.pba_bar);
else
return (-1);
}
static int
pci_emul_io_handler(int vcpu, int in, int port, int bytes, uint32_t *eax,
void *arg)
{
struct pci_devinst *pdi = arg;
struct pci_devemu *pe = pdi->pi_d;
uint64_t offset;
int i;
for (i = 0; i <= PCI_BARMAX; i++) {
if ((pdi->pi_bar[i].type == PCIBAR_IO) &&
(((uint64_t) port) >= pdi->pi_bar[i].addr) &&
(((uint64_t) (port + bytes)) <=
(pdi->pi_bar[i].addr + pdi->pi_bar[i].size)))
{
offset = ((uint64_t) port) - pdi->pi_bar[i].addr;
if (in)
*eax = (uint32_t) (*pe->pe_barread)(vcpu, pdi, i, offset,
bytes);
else
(*pe->pe_barwrite)(vcpu, pdi, i, offset, bytes, *eax);
return (0);
}
}
return (-1);
}
static int
pci_emul_mem_handler(int vcpu, int dir, uint64_t addr,
int size, uint64_t *val, void *arg1, long arg2)
{
struct pci_devinst *pdi = arg1;
struct pci_devemu *pe = pdi->pi_d;
uint64_t offset;
int bidx = (int) arg2;
assert(bidx <= PCI_BARMAX);
assert((pdi->pi_bar[bidx].type == PCIBAR_MEM32) ||
(pdi->pi_bar[bidx].type == PCIBAR_MEM64));
assert((addr >= pdi->pi_bar[bidx].addr) &&
((addr + ((uint64_t) size)) <=
(pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size)));
offset = addr - pdi->pi_bar[bidx].addr;
if (dir == MEM_F_WRITE) {
if (size == 8) {
(*pe->pe_barwrite)(vcpu, pdi, bidx, offset, 4, *val & 0xffffffff);
(*pe->pe_barwrite)(vcpu, pdi, bidx, offset + 4, 4, *val >> 32);
} else {
(*pe->pe_barwrite)(vcpu, pdi, bidx, offset, size, *val);
}
} else {
if (size == 8) {
*val = (*pe->pe_barread)(vcpu, pdi, bidx, offset, 4);
*val |= (*pe->pe_barread)(vcpu, pdi, bidx, offset + 4, 4) << 32;
} else {
*val = (*pe->pe_barread)(vcpu, pdi, bidx, offset, size);
}
}
return (0);
}
static int
pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size,
uint64_t *addr)
{
uint64_t base;
assert((size & (size - 1)) == 0); /* must be a power of 2 */
base = roundup2(*baseptr, size);
if (base + size <= limit) {
*addr = base;
*baseptr = base + size;
return (0);
} else
return (-1);
}
int
pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type,
uint64_t size)
{
return (pci_emul_alloc_pbar(pdi, idx, 0, type, size));
}
/*
* Register (or unregister) the MMIO or I/O region associated with the BAR
* register 'idx' of an emulated pci device.
*/
static void
modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
{
int error;
struct inout_port iop;
struct mem_range mr;
switch (pi->pi_bar[idx].type) {
case PCIBAR_IO:
bzero(&iop, sizeof(struct inout_port));
iop.name = pi->pi_name;
iop.port = (int) pi->pi_bar[idx].addr;
iop.size = (int)pi->pi_bar[idx].size;
if (registration) {
iop.flags = IOPORT_F_INOUT;
iop.handler = pci_emul_io_handler;
iop.arg = pi;
error = register_inout(&iop);
} else
error = unregister_inout(&iop);
break;
case PCIBAR_MEM32:
case PCIBAR_MEM64:
bzero(&mr, sizeof(struct mem_range));
mr.name = pi->pi_name;
mr.base = pi->pi_bar[idx].addr;
mr.size = pi->pi_bar[idx].size;
if (registration) {
mr.flags = MEM_F_RW;
mr.handler = pci_emul_mem_handler;
mr.arg1 = pi;
mr.arg2 = idx;
error = register_mem(&mr);
} else
error = unregister_mem(&mr);
break;
case PCIBAR_NONE:
case PCIBAR_MEMHI64:
error = EINVAL;
break;
}
assert(error == 0);
}
static void
unregister_bar(struct pci_devinst *pi, int idx)
{
modify_bar_registration(pi, idx, 0);
}
static void
register_bar(struct pci_devinst *pi, int idx)
{
modify_bar_registration(pi, idx, 1);
}
/* Are we decoding i/o port accesses for the emulated pci device? */
static int
porten(struct pci_devinst *pi)
{
uint16_t cmd;
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
return (cmd & PCIM_CMD_PORTEN);
}
/* Are we decoding memory accesses for the emulated pci device? */
static int
memen(struct pci_devinst *pi)
{
uint16_t cmd;
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
return (cmd & PCIM_CMD_MEMEN);
}
/*
* Update the MMIO or I/O address that is decoded by the BAR register.
*
* If the pci device has enabled the address space decoding then intercept
* the address range decoded by the BAR register.
*/
static void
update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
{
int decode;
if (pi->pi_bar[idx].type == PCIBAR_IO)
decode = porten(pi);
else
decode = memen(pi);
if (decode)
unregister_bar(pi, idx);
switch (type) {
case PCIBAR_IO:
case PCIBAR_MEM32:
pi->pi_bar[idx].addr = addr;
break;
case PCIBAR_MEM64:
pi->pi_bar[idx].addr &= ~0xffffffffUL;
pi->pi_bar[idx].addr |= addr;
break;
case PCIBAR_MEMHI64:
pi->pi_bar[idx].addr &= 0xffffffff;
pi->pi_bar[idx].addr |= addr;
break;
default:
assert(0);
}
if (decode)
register_bar(pi, idx);
}
int
pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
enum pcibar_type type, uint64_t size)
{
int error;
uint64_t *baseptr, limit, addr, mask, lobits, bar;
assert(idx >= 0 && idx <= PCI_BARMAX);
addr = 0;
limit = 0;
if ((size & (size - 1)) != 0)
size = 1UL << flsl((long) size); /* round up to a power of 2 */
/* Enforce minimum BAR sizes required by the PCI standard */
if (type == PCIBAR_IO) {
if (size < 4)
size = 4;
} else {
if (size < 16)
size = 16;
}
switch (type) {
case PCIBAR_NONE:
baseptr = NULL;
addr = mask = lobits = 0;
break;
case PCIBAR_IO:
baseptr = &pci_emul_iobase;
limit = PCI_EMUL_IOLIMIT;
mask = PCIM_BAR_IO_BASE;
lobits = PCIM_BAR_IO_SPACE;
break;
case PCIBAR_MEM64:
/*
* XXX
* Some drivers do not work well if the 64-bit BAR is allocated
* above 4GB. Allow for this by allocating small requests under
* 4GB unless then allocation size is larger than some arbitrary
* number (32MB currently).
*/
if (size > 32 * 1024 * 1024) {
/*
* XXX special case for device requiring peer-peer DMA
*/
if (size == 0x100000000UL)
baseptr = &hostbase;
else
baseptr = &pci_emul_membase64;
limit = PCI_EMUL_MEMLIMIT64;
mask = PCIM_BAR_MEM_BASE;
lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
PCIM_BAR_MEM_PREFETCH;
break;
} else {
baseptr = &pci_emul_membase32;
limit = PCI_EMUL_MEMLIMIT32;
mask = PCIM_BAR_MEM_BASE;
lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64;
}
break;
case PCIBAR_MEM32:
baseptr = &pci_emul_membase32;
limit = PCI_EMUL_MEMLIMIT32;
mask = PCIM_BAR_MEM_BASE;
lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
break;
case PCIBAR_MEMHI64:
printf("pci_emul_alloc_base: invalid bar type %d\n", type);
assert(0);
}
if (baseptr != NULL) {
error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
if (error != 0)
return (error);
}
pdi->pi_bar[idx].type = type;
pdi->pi_bar[idx].addr = addr;
pdi->pi_bar[idx].size = size;
/* Initialize the BAR register in config space */
bar = (addr & mask) | lobits;
pci_set_cfgdata32(pdi, PCIR_BAR(idx), ((uint32_t) bar));
if (type == PCIBAR_MEM64) {
assert(idx + 1 <= PCI_BARMAX);
pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
}
register_bar(pdi, idx);
return (0);
}
#define CAP_START_OFFSET 0x40
static int
pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
{
int i, capoff, reallen;
uint16_t sts;
assert(caplen > 0);
reallen = roundup2(caplen, 4); /* dword aligned */
sts = pci_get_cfgdata16(pi, PCIR_STATUS);
if ((sts & PCIM_STATUS_CAPPRESENT) == 0)
capoff = CAP_START_OFFSET;
else
capoff = pi->pi_capend + 1;
/* Check if we have enough space */
if (capoff + reallen > PCI_REGMAX + 1)
return (-1);
/* Set the previous capability pointer */
if ((sts & PCIM_STATUS_CAPPRESENT) == 0) {
pci_set_cfgdata8(pi, PCIR_CAP_PTR, ((uint8_t) capoff));
pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
} else
pci_set_cfgdata8(pi, pi->pi_prevcap + 1, ((uint8_t) capoff));
/* Copy the capability */
for (i = 0; i < caplen; i++)
pci_set_cfgdata8(pi, capoff + i, capdata[i]);
/* Set the next capability pointer */
pci_set_cfgdata8(pi, capoff + 1, 0);
pi->pi_prevcap = capoff;
pi->pi_capend = capoff + reallen - 1;
return (0);
}
static struct pci_devemu *
pci_emul_finddev(char *name)
{
struct pci_devemu **pdpp, *pdp;
SET_FOREACH(pdpp, pci_devemu_set) {
pdp = *pdpp;
if (!strcmp(pdp->pe_emu, name)) {
return (pdp);
}
}
return (NULL);
}
static int
pci_emul_init(struct pci_devemu *pde, int bus, int slot,
int func, struct funcinfo *fi)
{
struct pci_devinst *pdi;
int err;
pdi = calloc(1, sizeof(struct pci_devinst));
pdi->pi_bus = (uint8_t) bus;
pdi->pi_slot = (uint8_t) slot;
pdi->pi_func = (uint8_t) func;
pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
pdi->pi_lintr.pin = 0;
pdi->pi_lintr.state = IDLE;
pdi->pi_lintr.pirq_pin = 0;
pdi->pi_lintr.ioapic_irq = 0;
pdi->pi_d = pde;
snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
/* Disable legacy interrupts */
pci_set_cfgdata8(pdi, PCIR_INTLINE, 255);
pci_set_cfgdata8(pdi, PCIR_INTPIN, 0);
pci_set_cfgdata8(pdi, PCIR_COMMAND,
PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
err = (*pde->pe_init)(pdi, fi->fi_param);
if (err == 0)
fi->fi_devi = pdi;
else
free(pdi);
return (err);
}
void
pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr)
{
int mmc;
CTASSERT(sizeof(struct msicap) == 14);
/* Number of msi messages must be a power of 2 between 1 and 32 */
assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32);
mmc = ffs(msgnum) - 1;
bzero(msicap, sizeof(struct msicap));
msicap->capid = PCIY_MSI;
msicap->nextptr = (uint8_t) nextptr;
msicap->msgctrl = (uint16_t) (PCIM_MSICTRL_64BIT | (mmc << 1));
}
int
pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
{
struct msicap msicap;
pci_populate_msicap(&msicap, msgnum, 0);
return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
}
static void
pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum,
uint32_t msix_tab_size)
{
CTASSERT(sizeof(struct msixcap) == 12);
assert(msix_tab_size % 4096 == 0);
bzero(msixcap, sizeof(struct msixcap));
msixcap->capid = PCIY_MSIX;
/*
* Message Control Register, all fields set to
* zero except for the Table Size.
* Note: Table size N is encoded as N-1
*/
msixcap->msgctrl = (uint16_t) (msgnum - 1);
/*
* MSI-X BAR setup:
* - MSI-X table start at offset 0
* - PBA table starts at a 4K aligned offset after the MSI-X table
*/
msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK;
msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK);
}
static void
pci_msix_table_init(struct pci_devinst *pi, int table_entries)
{
int i, table_size;
assert(table_entries > 0);
assert(table_entries <= MAX_MSIX_TABLE_ENTRIES);
table_size = table_entries * MSIX_TABLE_ENTRY_SIZE;
pi->pi_msix.table = calloc(1, ((size_t) table_size));
/* set mask bit of vector control register */
for (i = 0; i < table_entries; i++)
pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
}
int
pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
{
uint32_t tab_size;
struct msixcap msixcap;
assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES);
assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0);
tab_size = (uint32_t) (msgnum * MSIX_TABLE_ENTRY_SIZE);
/* Align table size to nearest 4K */
tab_size = roundup2(tab_size, 4096u);
pi->pi_msix.table_bar = barnum;
pi->pi_msix.pba_bar = barnum;
pi->pi_msix.table_offset = 0;
pi->pi_msix.table_count = msgnum;
pi->pi_msix.pba_offset = tab_size;
pi->pi_msix.pba_size = PBA_SIZE(msgnum);
pci_msix_table_init(pi, msgnum);
pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size);
/* allocate memory for MSI-X Table and PBA */
pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
(tab_size + ((uint32_t) pi->pi_msix.pba_size)));
return (pci_emul_add_capability(pi, (u_char *)&msixcap,
sizeof(msixcap)));
}
void
msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
int bytes, uint32_t val)
{
uint16_t msgctrl, rwmask;
int off, table_bar;
off = offset - capoff;
table_bar = pi->pi_msix.table_bar;
/* Message Control Register */
if (off == 2 && bytes == 2) {
rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK;
msgctrl = pci_get_cfgdata16(pi, offset);
msgctrl &= ~rwmask;
msgctrl |= val & rwmask;
val = msgctrl;
pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
pci_lintr_update(pi);
}
CFGWRITE(pi, offset, val, bytes);
}
void
msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
int bytes, uint32_t val)
{
uint16_t msgctrl, rwmask, msgdata, mme;
uint32_t addrlo;
/*
* If guest is writing to the message control register make sure
* we do not overwrite read-only fields.
*/
if ((offset - capoff) == 2 && bytes == 2) {
rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE;
msgctrl = pci_get_cfgdata16(pi, offset);
msgctrl &= ~rwmask;
msgctrl |= val & rwmask;
val = msgctrl;
addrlo = pci_get_cfgdata32(pi, capoff + 4);
if (msgctrl & PCIM_MSICTRL_64BIT)
msgdata = pci_get_cfgdata16(pi, capoff + 12);
else
msgdata = pci_get_cfgdata16(pi, capoff + 8);
mme = msgctrl & PCIM_MSICTRL_MME_MASK;
pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
if (pi->pi_msi.enabled) {
pi->pi_msi.addr = addrlo;
pi->pi_msi.msg_data = msgdata;
pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
} else {
pi->pi_msi.maxmsgnum = 0;
}
pci_lintr_update(pi);
}
CFGWRITE(pi, offset, val, bytes);
}
static void
pciecap_cfgwrite(struct pci_devinst *pi, UNUSED int capoff, int offset,
int bytes, uint32_t val)
{
/* XXX don't write to the readonly parts */
CFGWRITE(pi, offset, val, bytes);
}
#define PCIECAP_VERSION 0x2
int
pci_emul_add_pciecap(struct pci_devinst *pi, int type)
{
int err;
struct pciecap pciecap;
CTASSERT(sizeof(struct pciecap) == 60);
if (type != PCIEM_TYPE_ROOT_PORT)
return (-1);
bzero(&pciecap, sizeof(pciecap));
pciecap.capid = PCIY_EXPRESS;
pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT;
pciecap.link_capabilities = 0x411; /* gen1, x1 */
pciecap.link_status = 0x11; /* gen1, x1 */
err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
return (err);
}
/*
* This function assumes that 'coff' is in the capabilities region of the
* config space.
*/
static void
pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val)
{
int capid;
uint8_t capoff, nextoff;
/* Do not allow un-aligned writes */
if ((offset & (bytes - 1)) != 0)
return;
/* Find the capability that we want to update */
capoff = CAP_START_OFFSET;
while (1) {
nextoff = pci_get_cfgdata8(pi, capoff + 1);
if (nextoff == 0)
break;
if (offset >= capoff && offset < nextoff)
break;
capoff = nextoff;
}
assert(offset >= capoff);
/*
* Capability ID and Next Capability Pointer are readonly.
* However, some o/s's do 4-byte writes that include these.
* For this case, trim the write back to 2 bytes and adjust
* the data.
*/
if (offset == capoff || offset == capoff + 1) {
if (offset == capoff && bytes == 4) {
bytes = 2;
offset += 2;
val >>= 16;
} else
return;
}
capid = pci_get_cfgdata8(pi, capoff);
switch (capid) {
case PCIY_MSI:
msicap_cfgwrite(pi, capoff, offset, bytes, val);
break;
case PCIY_MSIX:
msixcap_cfgwrite(pi, capoff, offset, bytes, val);
break;