diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 7da61295..83208bf3 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -53,7 +53,7 @@ set( CMAKE_C_FLAGS "${CMAKE_C_FLAGS} --specs=nano.specs --specs=nosys.specs -u _
 
 #set( CMAKE_EXE_LINKER_FLAGS "-Wl,--gc-sections -Wl,--print-gc-sections -Wl,-unresolved-symbols=ignore-in-object-files -Wl,-T,${PROJECT_SOURCE_DIR}/rpi.ld" )
 
-set( CMAKE_EXE_LINKER_FLAGS "-Wl,--gc-sections -Wl,-T,${PROJECT_SOURCE_DIR}/rpi.ld" )
+set( CMAKE_EXE_LINKER_FLAGS "-Wl,--no-warn-rwx-segments,--gc-sections -Wl,-T,${PROJECT_SOURCE_DIR}/rpi.ld" )
 
 
 file( GLOB core_files
diff --git a/src/armc-cstubs.c b/src/armc-cstubs.c
index a3952f69..a69f3687 100644
--- a/src/armc-cstubs.c
+++ b/src/armc-cstubs.c
@@ -123,7 +123,7 @@ int _fstat(int file, struct stat *st)
 /* Process-ID; this is sometimes used to generate strings unlikely to conflict
  with other processes. Minimal implementation, for a system without
  processes: */
-int getpid(void)
+int _getpid(void)
 {
   return 1;
 }
@@ -137,7 +137,7 @@ int _isatty(int file)
 }
 
 /* Send a signal. Minimal implementation: */
-int kill(int pid, int sig)
+int _kill(int pid, int sig)
 {
   errno = EINVAL;
   return -1;
@@ -157,7 +157,7 @@ int _lseek(int file, int ptr, int dir)
 }
 
 /* Open a file. Minimal implementation: */
-int open(const char *name, int flags, int mode)
+int _open(const char *name, int flags, int mode)
 {
   return -1;
 }
diff --git a/src/capture_line_ntsc_8bpp.S b/src/capture_line_ntsc_8bpp.S
index b5b0007a..016ed61e 100644
--- a/src/capture_line_ntsc_8bpp.S
+++ b/src/capture_line_ntsc_8bpp.S
@@ -27,10 +27,8 @@ skip_psync_loop_no_oldL\@:
 #else
 
 .macro  SKIP_PSYNC_NO_OLD_CPLD_NTSC
+        mov    r8, #4                    //adds 4 to capture length
         SKIP_PSYNC_COMMON_NO_OLD_CPLD
-        add    r8, r7, r1
-        add    r8, r8, #4
-        str    r8, [r4, #(GPU_COMMAND_offset - GPU_DATA_0_offset)]  //command register
         mov    r9, #0
 skip_psync_loop_no_oldL6\@:
         WAIT_FOR_PSYNC_EDGE_FAST           // wait for next edge of psync
@@ -47,10 +45,8 @@ skip_psync_loop_no_oldL6\@:
 .endm
 
 .macro  SKIP_PSYNC_NO_OLD_CPLD_NTSC_3BPP
+        mov    r8, #2                    //adds 2 to capture length
         SKIP_PSYNC_COMMON_NO_OLD_CPLD
-        add    r8, r7, r1
-        add    r8, r8, #2
-        str    r8, [r4, #(GPU_COMMAND_offset - GPU_DATA_0_offset)]  //command register
         mov    r9, #0
 skip_psync_loop_no_oldL3\@:
         WAIT_FOR_PSYNC_EDGE_FAST           // wait for next edge of psync
diff --git a/src/cpld_rgb.c b/src/cpld_rgb.c
index c4f98656..6950e5a7 100644
--- a/src/cpld_rgb.c
+++ b/src/cpld_rgb.c
@@ -1828,7 +1828,15 @@ static void cpld_calibrate_sub(capture_info_t *capinfo, int elk, int (*raw_metri
    if (!oddeven) {  // if mode 7 cpld using odd/even then let caller set config->half_px_delay as it is actually a quarter pixel delay
       config->half_px_delay = 0;
    }
-   config->full_px_delay = 0;
+   int temp_delay;
+   if (capinfo->mode7) { //dummy calls to alignment to detect bbc or non bbc profile
+      temp_delay = analyze_mode7_alignment(capinfo);
+   } else {
+      temp_delay = analyze_default_alignment(capinfo);
+   }
+   if (temp_delay >= 0) {          //if >=0 then bbc profile
+      config->full_px_delay = 0;   //so set offset to 0 for alignment calibration
+   }
    msgptr = 0;
    msgptr += sprintf(msg, "INFO:                      ");
    for (int i = 0; i < NUM_OFFSETS; i++) {
diff --git a/src/cpld_simple.c b/src/cpld_simple.c
index e25be536..382666b3 100644
--- a/src/cpld_simple.c
+++ b/src/cpld_simple.c
@@ -1,4 +1,5 @@
 #include <stdio.h>
+#include <stdint.h>
 #include "defs.h"
 #include "cpld.h"
 #include "rgb_to_fb.h"
diff --git a/src/defs.h b/src/defs.h
index e714fd9c..0648aae0 100644
--- a/src/defs.h
+++ b/src/defs.h
@@ -117,7 +117,7 @@
 #define RET_EXPIRED                0x10
 #define RET_INTERLACE_CHANGED      0x20
 #define RET_SYNC_TIMING_CHANGED    0x40
-#define RET_VSYNC_POLARITY_CHANGED 0x80
+#define RET_SYNC_POLARITY_CHANGED  0x80
 #define RET_SYNC_STATE_CHANGED    0x100
 
 //paletteFlags
@@ -371,7 +371,7 @@ typedef struct {
 #define EQUALISING_THRESHOLD 3400      // equalising pulses are half sync pulse length and must be filtered out
 #define FRAME_MINIMUM 10000000         // 10ms
 #define FRAME_TIMEOUT 30000000         // 30ms which is over a frame / field @ 50Hz (20ms)
-#define LINE_MINIMUM 20000             // 20uS
+#define LINE_MINIMUM 10000             // 10uS
 #define HSYNC_SCROLL_LO (4000 - 224)
 #define HSYNC_SCROLL_HI (4000 + 224)
 
@@ -578,10 +578,22 @@ typedef struct {
 #define  MODE_SET1       0
 #define  MODE_SET2       1
 
+#define  SYNC_ABORT_FLAG   0x80000000
+#define  LEADING_SYNC_FLAG 0x00010000
 #define  SIMPLE_SYNC_FLAG  0x00008000
 #define  HIGH_LATENCY_FLAG 0x00004000
 #define  OLD_FIRMWARE_FLAG 0x00002000
+
+#define  CPLD_NORMAL      0
+#define  CPLD_BLANK       1
+#define  CPLD_UNKNOWN     2
+#define  CPLD_WRONG       3
+#define  CPLD_MANUAL      4
+#define  CPLD_UPDATE      5
+#define  CPLD_NOT_FITTED  6
+
 #endif
 
 #define Bit32u uint32_t
-#define Bit8u uint8_t
\ No newline at end of file
+#define Bit8u uint8_t
+#define Bitu uint32_t
\ No newline at end of file
diff --git a/src/fatfs/sdcard.c b/src/fatfs/sdcard.c
index 761d3207..858c28bb 100644
--- a/src/fatfs/sdcard.c
+++ b/src/fatfs/sdcard.c
@@ -32,7 +32,9 @@
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
+#include <stdint.h>
 #include <inttypes.h>
+#include <unistd.h>
 #include "block.h"
 
 #include "../rpi-systimer.h"
diff --git a/src/filesystem.c b/src/filesystem.c
index 50058937..3b34a70c 100644
--- a/src/filesystem.c
+++ b/src/filesystem.c
@@ -1,6 +1,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <stdint.h>
 #include "logging.h"
 #include "fatfs/ff.h"
 #include "filesystem.h"
@@ -115,7 +116,7 @@ static int generate_png(capture_info_t *capinfo, uint8_t **png, unsigned int *pn
        uint8_t *pp = png_buffer;
 
            if (png_top != 0) {
-               for (int i = 0; i < (png_top * (png_left + width + png_right)); i += (hdouble + 1)) {
+               for (int i = 0; i < (png_top * (png_left + png_width + png_right)); i++) {
                     *pp++ = 0;
                     *pp++ = 0;
                     *pp++ = 0;
@@ -127,7 +128,7 @@ static int generate_png(capture_info_t *capinfo, uint8_t **png, unsigned int *pn
                 for (int sy = 0; sy < vscale; sy++) {
                     uint8_t *fp = capinfo->fb + capinfo->pitch * y;
                     if (png_left != 0) {
-                        for (int x = 0; x < png_left; x += (hdouble + 1)) {
+                        for (int x = 0; x < png_left; x++) {
                             *pp++ = 0;
                             *pp++ = 0;
                             *pp++ = 0;
@@ -159,7 +160,7 @@ static int generate_png(capture_info_t *capinfo, uint8_t **png, unsigned int *pn
                         }
                     }
                     if (png_right != 0) {
-                        for (int x = 0; x < png_right; x += (hdouble + 1)) {
+                        for (int x = 0; x < png_right; x++) {
                             *pp++ = 0;
                             *pp++ = 0;
                             *pp++ = 0;
@@ -169,7 +170,7 @@ static int generate_png(capture_info_t *capinfo, uint8_t **png, unsigned int *pn
                 }
            }
            if (png_bottom != 0) {
-               for (int i = 0; i < (png_bottom * (png_left + width + png_right)); i += (hdouble + 1)) {
+               for (int i = 0; i < (png_bottom * (png_left + png_width + png_right)); i++) {
                    *pp++ = 0;
                    *pp++ = 0;
                    *pp++ = 0;
diff --git a/src/geometry.c b/src/geometry.c
index 4c1846a6..fcb0daa1 100644
--- a/src/geometry.c
+++ b/src/geometry.c
@@ -867,17 +867,24 @@ void geometry_get_fb_params(capture_info_t *capinfo) {
         int apparent_height = get_vdisplay();
         double_width = (capinfo->sizex2 & SIZEX2_DOUBLE_WIDTH) >> 1;
         double_height = capinfo->sizex2 & SIZEX2_DOUBLE_HEIGHT;
-
+        hscale >>= double_width;
         if (_get_hardware_id() == _RPI && capinfo->bpp == 16 && !uneven) {
             if (get_gscaling() == GSCALING_INTEGER) {
                 int actual_width = (capinfo->chars_per_line << 3);
                 int actual_height = capinfo->nlines;
                 left = (apparent_width - (actual_width * hscale)) / 2;
-                right = left;
                 top = (apparent_height - (actual_height * vscale)) / 2;
-                bottom = top;
-                capinfo->width = actual_width << double_width;
-                capinfo->height = actual_height << double_height;
+                if (left >=0 && top >=0) {
+                    right = left;
+                    bottom = top;
+                    capinfo->width = actual_width;
+                    capinfo->height = actual_height << double_height;
+                } else {
+                    left = 0;
+                    right = 0;
+                    top = 0;
+                    bottom = 0;
+                }
                 //log_info("sizes = %d %d %d %d %d %d %d %d %d %d", apparent_width,apparent_height,actual_width, actual_height ,hscale,vscale,left,right,top,bottom);
             } else {
                 top = 0;
diff --git a/src/jtag/update_cpld.c b/src/jtag/update_cpld.c
index 7ab40378..e2916d74 100644
--- a/src/jtag/update_cpld.c
+++ b/src/jtag/update_cpld.c
@@ -1,4 +1,5 @@
 #include <stdio.h>
+#include <stdint.h>
 #include "../filesystem.h"
 #include "../logging.h"
 #include "../osd.h"
diff --git a/src/logging.c b/src/logging.c
index 7f1566b0..8b9e7938 100644
--- a/src/logging.c
+++ b/src/logging.c
@@ -1,5 +1,6 @@
 #include <stdio.h>
 #include <stdarg.h>
+#include <stdint.h>
 #include "logging.h"
 #include "filesystem.h"
 
diff --git a/src/macros.S b/src/macros.S
index 993f1bd2..b7d342de 100644
--- a/src/macros.S
+++ b/src/macros.S
@@ -412,19 +412,35 @@ clear_regs\@:
         str    r8, [r10, r14]
         subs   r14, r14, #4
         bpl    clear_regs\@
-        ldr    r10, =GPU_workspace
-        str    r8, [r10]
-        str    r8, [r10, #4]
+        ldr    r14, =GPU_workspace
+        str    r8, [r14]
+        str    r8, [r14, #4]
 .endm
 
-.macro  SKIP_PSYNC_COMMON_NO_OLD_CPLD
+.macro  SETUP_GPU_CAPTURE_CPLD
+        push   {r8}
         SETUP_GPU_CAPTURE
+        add    r8, r7, r1                  //now r8 is total samples to capture (offset + video)
+        tst    r3, #BIT_NO_H_SCROLL        // only allow fine sideways scrolling in bbc / electron mode (causes timing issues in ega mode)
+        addeq  r8, r8, #2                  // add 2 extra samples when hscrolling to allow for shift
+        tst    r3, #BIT_HSYNC_EDGE         // if leading edge then don't wait for end of hsync (means scroll detection won't work)
+        addne  r8, r7, r1                  //restore r8 if leading edge as no sideways scrolling allowed
+        orrne  r8, #LEADING_SYNC_FLAG
+        pop    {r14}
+        add    r8, r8, r14                 // adds in extra flags such as high latency capture or additional psync counts used in NTSC artfact capture
+        str    r8, [r10]  //command register
+.endm
+
+.macro  SKIP_PSYNC_COMMON_NO_OLD_CPLD
+        //enters with R8 containing extra gpu flags such as high latency or additional psync counts used in NTSC artfact capture
+        SETUP_GPU_CAPTURE_CPLD
         WAIT_FOR_CSYNC_0_FAST_SKIP_HSYNC
-        bic   r3, r3, #PSYNC_MASK    // wait for zero after CSYNC
         READ_CYCLE_COUNTER r10
+        bic   r3, r3, #PSYNC_MASK    // wait for zero after CSYNC
         push  {r10}
         tst   r3, #BIT_HSYNC_EDGE    // if leading edge then don't wait for end of hsync (means scroll detection won't work)
-        bne   do_skip_psync_no_old\@
+        bne   do_skip_psync_no_old1\@
+
         pop   {r10}
         mov   r6, r9, lsr #16        //HSYNC_SCROLL_HI
         bic   r9, r9, #0xff000000
@@ -453,49 +469,55 @@ clear_regs\@:
         addlt  r8, r8, #1
         orrlt  r3, r3, #BIT_INHIBIT_MODE_DETECT
         tst    r3, #BIT_NO_H_SCROLL
-        moveq  r7, r8                      // only allow fine sideways scrolling in bbc / electron mode (causes timing issues in ega mode)
+        subeq  r10, r8, r7
+        rsbeq  r10, r10, #2
+        addeq  r1, r1, r10                // increase r1 if no adjustment to r7
+        moveq  r7, r8                     // only allow fine sideways scrolling in bbc / electron mode (causes timing issues in ega mode)
         // Skip the configured number of psync edges (modes 0..6: edges every 250ns, mode 7: edges ever 333ns)
-do_skip_psync_no_old\@:
+do_skip_psync_no_old1\@:
         bl     _get_gpu_data_base_r4
+        mov    r8, #SYNC_ABORT_FLAG
+        str    r8, [r4, #(GPU_COMMAND_offset - GPU_DATA_0_offset)]  //command register
 .endm
 
 .macro  SKIP_PSYNC_NO_OLD_CPLD_HIGH_LATENCY
-        SKIP_PSYNC_COMMON_NO_OLD_CPLD
-        add    r8, r7, r1
+        mov    r8, #0
         tst    r3, #BIT_RPI234
         orrne  r8, r8, #HIGH_LATENCY_FLAG  //request high latency capture (slightly faster but only really suitable for 9/12bpp modes)
-        str    r8, [r4, #(GPU_COMMAND_offset - GPU_DATA_0_offset)]  //command register
-skip_psync_no_old_loop\@:
+        SKIP_PSYNC_COMMON_NO_OLD_CPLD
+skip_psync_no_old_loop2\@:
         WAIT_FOR_PSYNC_EDGE_FAST           // wait for next edge of psync
         subs   r7, r7, #1
-        bne    skip_psync_no_old_loop\@
+        bne    skip_psync_no_old_loop2\@
 .endm
 
 .macro  SKIP_PSYNC_NO_OLD_CPLD
+        mov    r8, #0
         SKIP_PSYNC_COMMON_NO_OLD_CPLD
-        add    r8, r7, r1
-        str    r8, [r4, #(GPU_COMMAND_offset - GPU_DATA_0_offset)]  //command register
-skip_psync_no_old_loop\@:
+skip_psync_no_old_loop1\@:
         WAIT_FOR_PSYNC_EDGE_FAST           // wait for next edge of psync
         subs   r7, r7, #1
-        bne    skip_psync_no_old_loop\@
+        bne    skip_psync_no_old_loop1\@
 .endm
 
-
 .macro  SKIP_PSYNC
-        SETUP_GPU_CAPTURE
-        // called if 4 bits per pixel in non-fast mode so has support for old CPLV v1 & v2
+        mov    r8, #0
+        tst    r3, #BIT_OLD_FIRMWARE_SUPPORT
+        orrne  r8, r8, #OLD_FIRMWARE_FLAG    //request old firmware support  (does double reads so slower but only used on 3bpp)
+        SETUP_GPU_CAPTURE_CPLD
         WAIT_FOR_CSYNC_0_SKIP_HSYNC
-        bic    r3, r3, #PSYNC_MASK             // wait for zero after CSYNC
         READ_CYCLE_COUNTER r10
-        push   {r10}
-        tst    r3, #BIT_HSYNC_EDGE    // if leading edge then don't wait for end of hsync (means scroll detection won't work)
-        bne    do_skip_psync\@
-        pop    {r10}
+        bic   r3, r3, #PSYNC_MASK    // wait for zero after CSYNC
+        push  {r10}
+        tst   r3, #BIT_HSYNC_EDGE    // if leading edge then don't wait for end of hsync (means scroll detection won't work)
+        bne   do_skip_psync3\@
+
+        pop   {r10}
         // Wait for the end of hsync
         WAIT_FOR_CSYNC_1
         READ_CYCLE_COUNTER r14
-        push   {r14}
+        push   {r14}     //save timestamp
+
         // Calculate length of low hsync pulse (in ARM cycles = ns)
         subs   r10, r14, r10
         rsbmi  r10, r10, #0
@@ -533,13 +555,15 @@ notoldfirmwarescroll\@:
         orrlt  r3, r3, #BIT_INHIBIT_MODE_DETECT
 doneoldfirmwarescroll\@:
         tst    r3, #BIT_NO_H_SCROLL
+        subeq  r10, r8, r7
+        rsbeq  r10, r10, #2
+        addeq  r1, r1, r10                // increase r1 if no adjustment to r7
         moveq  r7, r8                     // only allow fine sideways scrolling in bbc / electron mode (causes timing issues in ega mode)
+
         // Skip the configured number of psync edges (modes 0..6: edges every 250ns, mode 7: edges ever 333ns)
-do_skip_psync\@:
+do_skip_psync3\@:
         bl     _get_gpu_data_base_r4
-        add    r8, r7, r1
-        tst    r3, #BIT_OLD_FIRMWARE_SUPPORT
-        orrne  r8, r8, #OLD_FIRMWARE_FLAG    //request old firmware support  (does double reads so slower but only used on 3bpp)
+        mov    r8, #SYNC_ABORT_FLAG
         str    r8, [r4, #(GPU_COMMAND_offset - GPU_DATA_0_offset)]  //command register
 skip_psync_loop\@:
         WAIT_FOR_PSYNC_EDGE               // wait for next edge of psync
diff --git a/src/osd.c b/src/osd.c
index 5ce72221..84e91f02 100644
--- a/src/osd.c
+++ b/src/osd.c
@@ -1,5 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
+#include <stdint.h>
 #include <string.h>
 #include <inttypes.h>
 #include <ctype.h>
@@ -113,6 +114,8 @@ static char *default_palette_names[] = {
    "Mono_(3_level)",
    "Mono_(4_level)",
    "Mono_(6_level)",
+   "Mono_(8_level_RGB)",
+   "Mono_(8_level_YUV)",
    "TI-99-4a",
    "Spectrum_48K_9Col",
    "Colour_Genie_S24",
@@ -971,7 +974,7 @@ static uint32_t normal_size_map8_16bpp[0x1000 * 4];
 static char message[MAX_STRING_SIZE];
 
 // Temporary filename for assembling OSD lines
-static char filename[MAX_STRING_SIZE];
+static char filename[MAX_STRING_SIZE * 5];
 
 static char selected_manufacturer[MAX_STRING_SIZE];
 
@@ -1483,7 +1486,7 @@ void osd_display_interface(int line) {
     }
     osd_set(line + 2, 0, osdline);
 #ifdef USE_ARM_CAPTURE
-    osd_set(line + 3, 0, "ARM Capture Version");
+    osd_set(line + 3, 0, "Warning: ARM Capture Version");
 #else
     osd_set(line + 3, 0, "GPU Capture Version");
 #endif
@@ -2945,6 +2948,97 @@ void generate_palettes() {
                     g = r; b = r;
                     break;
 
+#define b3 0x24    // b-y 3
+#define b2 0x04    // b-y 2
+#define b1 0x20    // b-y 1
+#define b0 0x00    // b-y 0
+#define r3 0x09    // r-y 3
+#define r2 0x01    // r-y 2
+#define r1 0x08    // r-y 1
+#define r0 0x00    // r-y 0
+#define g3 0x12    // y 3
+#define g2 0x02    // y 2
+#define g1 0x10    // y 1
+#define g0 0x00    // y 0
+
+                 case PALETTE_MONO8_RGB:
+                    switch (i) {
+                        /*
+                        case g3:
+                            r = 0xff;g=0xff;b=0xff; break;
+                        case r3:
+                        case b3:
+                            r = 0xff;g=0xff;b=0x00; break;
+                        case g2:
+                            r = 0x00;g=0xff;b=0xff; break;
+                        case r2:
+                            r = 0x00;g=0xff;b=0x00; break;
+                        case b2:
+                            r = 0xff;g=0x00;b=0xff; break;
+                        case g1:
+                            r = 0xff;g=0x00;b=0x00; break;
+                        case r1:
+                        case b1:
+                            r = 0x00;g=0x00;b=0xff; break;
+                        case 0:
+                            r = 0x00;g=0x00;b=0x00; break;
+*/
+
+                        case 0:
+                            r = 0x00;g=0x00;b=0x00; break;
+                        case r1 + b1:
+                            r = 0x00;g=0x00;b=0xff; break;
+                        case r1 + b1 + g1:
+                            r = 0xff;g=0x00;b=0x00; break;
+                        case r1 + b2 + g1:
+                            r = 0xff;g=0x00;b=0xff; break;
+                        case r2 + b2 + g1:
+                            r = 0x00;g=0xff;b=0x00; break;
+                        case r2 + b2 + g2:
+                            r = 0x00;g=0xff;b=0xff; break;
+                        case r3 + b3 + g2:
+                            r = 0xff;g=0xff;b=0x00; break;
+                        case r3 + b3 + g3:
+                            r = 0xff;g=0xff;b=0xff; break;
+
+                    }
+                    break;
+
+#define u3 0x24    // b-y 3
+#define u2 0x04    // b-y 2
+#define u1 0x20    // b-y 1
+#define u0 0x00    // b-y 0
+#define v3 0x09    // r-y 3
+#define v2 0x01    // r-y 2
+#define v1 0x08    // r-y 1
+#define v0 0x00    // r-y 0
+#define y3 0x12    // y 3
+#define y2 0x02    // y 2
+#define y1 0x10    // y 1
+#define y0 0x00    // y 0
+
+                 case PALETTE_MONO8_YUV:
+                    switch (i) {
+                        case 0:
+                            r = 0x00;g=0x00;b=0x00; break;
+                        case u1:
+                            r = 0x00;g=0x00;b=0xff; break;
+                        case u1+v1:
+                            r = 0xff;g=0x00;b=0x00; break;
+                        case u1+v1+y1:
+                            r = 0xff;g=0x00;b=0xff; break;
+                        case u2+v2+y1:
+                            r = 0x00;g=0xff;b=0x00; break;
+                        case u3+v3+y1:
+                            r = 0x00;g=0xff;b=0xff; break;
+                        case u3+v3+y2:
+                            r = 0xff;g=0xff;b=0x00; break;
+                        case u3+v3+y3:
+                            r = 0xff;g=0xff;b=0xff; break;
+                    }
+                    break;
+
+
                     case PALETTE_YG_4:
                     switch (i & 0x12) {
                         case 0x00:
@@ -2983,18 +3077,7 @@ void generate_palettes() {
                     break;
 //**********************************************************************************
 
-#define b3 0x24    // b-y 3
-#define b2 0x04    // b-y 2
-#define b1 0x20    // b-y 1
-#define b0 0x00    // b-y 0
-#define r3 0x09    // r-y 3
-#define r2 0x01    // r-y 2
-#define r1 0x08    // r-y 1
-#define r0 0x00    // r-y 0
-#define g3 0x12    // y 3
-#define g2 0x02    // y 2
-#define g1 0x10    // y 1
-#define g0 0x00    // y 0
+
                  case PALETTE_TI: {
                     r=g=b=0;
 
@@ -4784,62 +4867,70 @@ int menu_active() {
    return ! (osd_state == IDLE || osd_state == DURATION || osd_state == A1_CAPTURE || osd_state == A1_CAPTURE_SUB);
 }
 
-void osd_show_cpld_recovery_menu(int update) {
-   static char name[] = "CPLD Recovery Menu";
-   if (update) {
-      strncpy(cpld_firmware_dir, DEFAULT_CPLD_UPDATE_DIR, MIN_STRING_LIMIT);
+void osd_show_cpld_recovery_menu(int cpld_fail_state) {
+   if (cpld_fail_state == CPLD_NOT_FITTED) {
+       current_menu[0] = &main_menu;
+       current_item[0] = 0;
+       depth = 0;
+       osd_state = MENU;
+       osd_refresh();
    } else {
-      if (eight_bit_detected()) {
-          strncpy(cpld_firmware_dir, DEFAULT_CPLD_FIRMWARE_DIR12, MIN_STRING_LIMIT);
-      } else {
-          strncpy(cpld_firmware_dir, DEFAULT_CPLD_FIRMWARE_DIR, MIN_STRING_LIMIT);
-      }
-   }
-   update_cpld_menu.name = name;
-   current_menu[0] = &main_menu;
-   current_item[0] = 0;
-   current_menu[1] = &settings_menu;
-   current_item[1] = 0;
-   current_menu[2] = &update_cpld_menu;
-   current_item[2] = 0;
-   depth = 2;
-   osd_state = MENU;
-   // Change the font size to the large font (no profile will be loaded)
-   set_feature(F_FONT_SIZE, FONTSIZE_12X20);
-   // Bring up the menu
-   osd_refresh();
-   if (!update) {
-       // Add some warnings
-       int line = 6;
-       if (eight_bit_detected()) {
-           line++;
-           osd_set(line++, ATTR_DOUBLE_SIZE,  "IMPORTANT:");
-           line++;
-           osd_set(line++, 0, "RGBtoHDMI has detected an 8/12 bit board");
-           osd_set(line++, 0, "Please select the correct CPLD type");
-           osd_set(line++, 0, "for the computer source (See Wiki)");
-           line++;
-           osd_set(line++, 0, "See Wiki for Atom board CPLD programming");
-           line++;
-           osd_set(line++, 0, "Hold 3 buttons during reset for this menu.");
+       static char name[] = "CPLD Recovery Menu";
+       if (cpld_fail_state == CPLD_UPDATE) {
+          strncpy(cpld_firmware_dir, DEFAULT_CPLD_UPDATE_DIR, MIN_STRING_LIMIT);
        } else {
-           osd_set(line++, ATTR_DOUBLE_SIZE,  "IMPORTANT:");
-           line++;
-           osd_set(line++, 0, "The CPLD type (3_BIT/6-12_BIT) must match");
-           osd_set(line++, 0, "the RGBtoHDMI board type you have:");
-           line++;
-           osd_set(line++, 0, "Use 3_BIT_BBC_CPLD_vxx for Hoglet's");
-           osd_set(line++, 0, "   original RGBtoHD (c) 2018 board");
-           osd_set(line++, 0, "Use 6-12_BIT_BBC_CPLD_vxx for IanB's");
-           osd_set(line++, 0, "   6-bit Issue 2 to 12-bit Issue 4 boards");
-           line++;
-           osd_set(line++, 0, "See Wiki for Atom board CPLD programming");
-           line++;
-           osd_set(line++, 0, "Programming the wrong CPLD type may");
-           osd_set(line++, 0, "cause damage to your RGBtoHDMI board.");
-           osd_set(line++, 0, "Please ask for help if you are not sure.");
-           line++;
-           osd_set(line++, 0, "Hold 3 buttons during reset for this menu.");
+          if (eight_bit_detected()) {
+              strncpy(cpld_firmware_dir, DEFAULT_CPLD_FIRMWARE_DIR12, MIN_STRING_LIMIT);
+          } else {
+              strncpy(cpld_firmware_dir, DEFAULT_CPLD_FIRMWARE_DIR, MIN_STRING_LIMIT);
+          }
+       }
+       update_cpld_menu.name = name;
+       current_menu[0] = &main_menu;
+       current_item[0] = 0;
+       current_menu[1] = &settings_menu;
+       current_item[1] = 0;
+       current_menu[2] = &update_cpld_menu;
+       current_item[2] = 0;
+       depth = 2;
+       osd_state = MENU;
+       // Change the font size to the large font (no profile will be loaded)
+       set_feature(F_FONT_SIZE, FONTSIZE_12X20);
+       // Bring up the menu
+       osd_refresh();
+       if (cpld_fail_state != CPLD_UPDATE) {
+           // Add some warnings
+           int line = 6;
+           if (eight_bit_detected()) {
+               line++;
+               osd_set(line++, ATTR_DOUBLE_SIZE,  "IMPORTANT:");
+               line++;
+               osd_set(line++, 0, "RGBtoHDMI has detected an 8/12 bit board");
+               osd_set(line++, 0, "Please select the correct CPLD type");
+               osd_set(line++, 0, "for the computer source (See Wiki)");
+               line++;
+               osd_set(line++, 0, "See Wiki for Atom board CPLD programming");
+               line++;
+               osd_set(line++, 0, "Hold 3 buttons during reset for this menu.");
+           } else {
+               osd_set(line++, ATTR_DOUBLE_SIZE,  "IMPORTANT:");
+               line++;
+               osd_set(line++, 0, "The CPLD type (3_BIT/6-12_BIT) must match");
+               osd_set(line++, 0, "the RGBtoHDMI board type you have:");
+               line++;
+               osd_set(line++, 0, "Use 3_BIT_BBC_CPLD_vxx for Hoglet's");
+               osd_set(line++, 0, "   original RGBtoHD (c) 2018 board");
+               osd_set(line++, 0, "Use 6-12_BIT_BBC_CPLD_vxx for IanB's");
+               osd_set(line++, 0, "   6-bit Issue 2 to 12-bit Issue 4 boards");
+               line++;
+               osd_set(line++, 0, "See Wiki for Atom board CPLD programming");
+               line++;
+               osd_set(line++, 0, "Programming the wrong CPLD type may");
+               osd_set(line++, 0, "cause damage to your RGBtoHDMI board.");
+               osd_set(line++, 0, "Please ask for help if you are not sure.");
+               line++;
+               osd_set(line++, 0, "Hold 3 buttons during reset for this menu.");
+           }
        }
    }
 }
diff --git a/src/osd.h b/src/osd.h
index ea76941e..3c0fd24c 100644
--- a/src/osd.h
+++ b/src/osd.h
@@ -48,6 +48,8 @@ enum {
    PALETTE_MONO3,
    PALETTE_MONO4,
    PALETTE_MONO6,
+   PALETTE_MONO8_RGB,
+   PALETTE_MONO8_YUV,
    PALETTE_TI,
    PALETTE_SPECTRUM48K,
    PALETTE_CGS24,
diff --git a/src/rgb_to_fb.S b/src/rgb_to_fb.S
index a9423ed1..fd87fbc3 100644
--- a/src/rgb_to_fb.S
+++ b/src/rgb_to_fb.S
@@ -758,12 +758,18 @@ is_elk:
         add    r5, r5, r6
         str    r5, total_lines
         //str    r5, vsync_line          // default for vsync line if undetectable in blanking area
+        mov    r9, #0
 skip_line_loop:
+        str    r9, hsync_measured
         cmp    r5, r6
         ble    skip_line_loop_exit
         bl     show_vsync
         WAIT_FOR_CSYNC_0_LONG
+        READ_CYCLE_COUNTER r12
         WAIT_FOR_CSYNC_1_LONG
+        READ_CYCLE_COUNTER r10
+        subs   r9, r10, r12
+        rsbmi  r9, r9, #0
         subs   r5, r5, #1
         b      skip_line_loop
 skip_line_loop_exit:
@@ -1116,13 +1122,32 @@ done_ntsc_auto:
         strpl  r8, frame_countdown
         bpl    skip_sync_time_test
 
+        tst    r3, #BIT_OSD | BIT_CALIBRATE | BIT_PROBE
+        bne    skip_sync_time_test
+
+        ldr    r0, param_timingset
+        orr    r0, #RET_SYNC_TIMING_CHANGED | RET_SYNC_POLARITY_CHANGED
+
+        ldr    r9, param_autoswitch
+        cmp    r9, #AUTOSWITCH_OFF
+        beq    skip_hsync_time_test
+
+        ldr    r8, param_vsync_type
+        cmp    r8, #VSYNC_POLARITY
+        bne    skip_hsync_time_test
+
+        ldr    r8, hsync_measured                //check measured hsync width
+        ldr    r9, hsync_threshold               //if > threshold then hsync likely inverted and active line has been measured
+        rsb    r7, r9, #LINE_TIMEOUT   //r7 is now timeout length minus sync threshold (~100us - 9uS)
+        cmp    r7, r8    //is timeout length -9uS > measured hsync  (i.e. genuine reading, not a timeout)
+        cmpgt  r8, r9   //if yes is measured hsync > 9uS
+        bgt    exit
+
+skip_hsync_time_test:
         ldr    r8, sync_detected
         cmp    r8, #0
         beq    skip_sync_time_test           // if no sync then timing comparison is meaningless
 
-        tst    r3, #BIT_OSD | BIT_CALIBRATE | BIT_PROBE
-        bne    skip_sync_time_test
-
         ldr    r7, hsync_comparison_lo
         ldr    r8, hsync_comparison_hi
         cmp    r7, r8
@@ -1131,7 +1156,7 @@ done_ntsc_auto:
         ldr    r0, param_timingset
         orr    r0, #RET_SYNC_TIMING_CHANGED
 
-        ldr    r6, hsync_period
+        ldr    r6, total_hsync_period
         ldr    r7, hsync_comparison_lo
         ldr    r8, hsync_comparison_hi
         cmp    r6, r7
@@ -1159,15 +1184,16 @@ done_ntsc_auto:
         cmp    r9, #AUTOSWITCH_OFF
         beq    skip_sync_time_test
 
-        ldr    r8, param_sync_type
-        tst    r8, #SYNC_BIT_COMPOSITE_SYNC       //set if composite so don't check vsync polarity
-        bne    skip_sync_time_test
-
         ldr    r8, param_vsync_type
         cmp    r8, #VSYNC_POLARITY
         bne    skip_sync_time_test
 
-        orr    r0, #RET_VSYNC_POLARITY_CHANGED
+
+        ldr    r8, param_sync_type
+        tst    r8, #SYNC_BIT_COMPOSITE_SYNC       //set if composite so don't check vsync polarity
+        bne    skip_sync_time_test
+
+        orr    r0, #RET_SYNC_POLARITY_CHANGED
 
         mov    r8, #VERSION_MASK
         str    r8, [r4, #-(GPLEV0_OFFSET - GPCLR0_OFFSET)]             //briefly switch to vsync on psync by clearing version bit
@@ -1350,6 +1376,8 @@ exit:
 // Local Variables
 // ======================================================================
         .align 6
+capture_address:
+        .word 0
 dpmsframecount:
         .word 0
 dpms_state:
@@ -1384,8 +1412,7 @@ vsync_line:
 vsync_detected:
         .word 0
 
-capture_address:
-        .word 0
+
 
 detectedlinecount:
         .word 0
@@ -1480,6 +1507,8 @@ vsync_retry_count:
         .word 0
 osd_timer:
         .word 0
+hsync_measured:
+        .word 0
 
         .ltorg
 
@@ -1592,9 +1621,9 @@ seen_short:
         // No, so look back for the next pulse
         bne    vsync_loop
 
-        ldr    r11, hsync_threshold             // normally 10us
-        mov    r11, r11, lsl #1                 // 20us
-wait_hi_20:                                     // make sure sync high for > 20us to avoid malformed vsync pulses (e.g. Apple II)
+        ldr    r11, hsync_threshold             // normally 9us
+        add    r11, r11, r11, lsr #1            // 13.5us
+wait_hi_20:                                     // make sure sync high for > 13.5us to avoid malformed vsync pulses (e.g. Apple II)
         ldr    r8, [r4]
         tst    r8, #CSYNC_MASK
         beq    vsync_loop
diff --git a/src/rgb_to_hdmi.c b/src/rgb_to_hdmi.c
index c1ce99b0..6f5d4f8b 100644
--- a/src/rgb_to_hdmi.c
+++ b/src/rgb_to_hdmi.c
@@ -2,6 +2,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <inttypes.h>
+#include <stdint.h>
 #include <limits.h>
 #include <math.h>
 #include "cache.h"
@@ -148,16 +149,6 @@ typedef void (*func_ptr)();
 #define MAX_PLL_EXTENSION  500000000
 #endif
 
-enum {
-   CPLD_NORMAL,
-   CPLD_BLANK,
-   CPLD_UNKNOWN,
-   CPLD_WRONG,
-   CPLD_MANUAL,
-   CPLD_UPDATE,
-   CPLD_NOT_FITTED
-};
-
 // =============================================================
 // Forward declarations
 // =============================================================
@@ -1847,9 +1838,6 @@ static void cpld_init() {
          cpld = &cpld_bbcv24;
       } else if (cpld_version <= 0x62) {
          cpld = &cpld_bbcv30v62;
-      } else if (cpld_version == 0x7f) {    //cpld board not connected
-         cpld = &cpld_null;
-         cpld_fail_state = CPLD_NOT_FITTED;
       } else {
          cpld = &cpld_bbc;
       }
@@ -1868,12 +1856,7 @@ static void cpld_init() {
            cpld_fail_state = CPLD_WRONG;
        } else {
            if (cpld_version >= 0x70 && cpld_version < 0x80) {
-                if (cpld_version == 0x7f) {    //cpld board not connected
-                    cpld = &cpld_null;
-                    cpld_fail_state = CPLD_NOT_FITTED;
-                } else {
-                    cpld = &cpld_rgb_ttl_24mhz;
-                }
+               cpld = &cpld_rgb_ttl_24mhz;
            } else {
                cpld = &cpld_rgb_ttl;
            }
@@ -1921,9 +1904,13 @@ static void cpld_init() {
        check_file(FORCE_UPDATE_FILE, FORCE_UPDATE_FILE_MESSAGE);
    }
 
+   if (cpld_version >= 0xa0 && cpld_design != DESIGN_NULL) {    //cpld version >=0xa0 is currently invalid so probably a CPLD with other code but this may change if hex version numbers are ever used
+       cpld_fail_state = CPLD_UNKNOWN;
+   }
+
    int keycount = key_press_reset() & 0x07;  //all buttons pressed during reset
    log_info("Keycount = %d", keycount);
-   if (keycount == 7 || cpld_version >= 0xa0) {    //cpld version >=0xa0 is currently invalid but this may change
+   if (keycount == 7) {
        switch(cpld_design) {
            case DESIGN_BBC:
                 cpld = &cpld_null_3bit;
@@ -1944,15 +1931,21 @@ static void cpld_init() {
                 cpld = &cpld_null;
                 break;
        }
-       if (keycount == 7) {
-            cpld_fail_state = CPLD_MANUAL;
-       } else {
-            cpld_fail_state = CPLD_UNKNOWN;
-       }
+       cpld_fail_state = CPLD_MANUAL;
        RPI_SetGpioPinFunction(STROBE_PIN, FS_INPUT);
+   }
 
+   if (cpld_version == 0x7f && cpld_design != DESIGN_NULL) {  //invalid version number of 0x7F is read when cpld board not connected
+       log_info("Invalid version number 0x7F detected. No CPLD board fitted");
+       cpld_fail_state = CPLD_NOT_FITTED;
+       cpld_design = DESIGN_RGB_TTL;
+       cpld_version_id = (cpld_design << VERSION_DESIGN_BIT) | cpld_version;
+       cpld = &cpld_null_6bit;
+       supports8bit = 1;
+       RPI_SetGpioPinFunction(STROBE_PIN, FS_INPUT);
    }
 
+
    // Release the active low version pin. This will damage the cpld if YUV is programmed into a BBC board but not RGB due to above safety test
    delay_in_arm_cycles_cpu_adjust(1000);
    RPI_SetGpioValue(VERSION_PIN, 1);
@@ -3053,9 +3046,11 @@ void setup_profile(int profile_changed) {
     }
     log_info("Detected polarity state = %X, %s (%s)", capinfo->detected_sync_type, sync_names[capinfo->detected_sync_type & SYNC_BIT_MASK], mixed_names[(capinfo->detected_sync_type & SYNC_BIT_MIXED_SYNC) ? 1 : 0]);
 
+    cpld->analyse(capinfo->detected_sync_type, 0); //set to detected sync type when measuring sync timing
     rgb_to_fb(capinfo, extra_flags() | BIT_PROBE); // dummy mode7 probe to setup sync type from capinfo
     // Measure the frame time and set the sampling clock
     calibrate_sampling_clock(profile_changed);
+    cpld->analyse(capinfo->sync_type, 0);          //restore to profile sync preset
 
     if (parameters[F_POWERUP_MESSAGE] && (powerup || osd_timer > 0)) {
         osd_set(0, 0, " ");    //dummy print to turn osd on so interlaced modes can display startup resolution later
@@ -3085,6 +3080,8 @@ void setup_profile(int profile_changed) {
     }
     log_info("Window: H=%d to %d, V=%d to %d", hsync_comparison_lo * 1000 / cpuspeed, hsync_comparison_hi * 1000 / cpuspeed, (int)((double)vsync_comparison_lo * 1000 / cpuspeed)
              , (int)((double)vsync_comparison_hi * 1000 / cpuspeed));
+    hsync_comparison_lo *= (capinfo->nlines - 1);  //actually measure nlines-1 hsyncs to average out jitter
+    hsync_comparison_hi *= (capinfo->nlines - 1);
     log_info("Sync=%s, Det-Sync=%s, Det-HS-Width=%d, HS-Thresh=%d", sync_names[capinfo->sync_type & SYNC_BIT_MASK], sync_names[capinfo->detected_sync_type & SYNC_BIT_MASK], hsync_width, hsync_threshold);
 }
 
@@ -3280,7 +3277,7 @@ void rgb_to_hdmi_main() {
              rgb_to_fb(capinfo, extra_flags() | BIT_PROBE); // dummy mode7 probe to setup parms from capinfo
              status[0] = 0;
              // Immediately load the CPLD Update Menu (renamed to CPLD Recovery Menu)
-             osd_show_cpld_recovery_menu(cpld_fail_state == CPLD_UPDATE);
+             osd_show_cpld_recovery_menu(cpld_fail_state);
              while (1) {
                 if (status[0] != 0) {
                     osd_set(1, 0, status);
@@ -3464,7 +3461,7 @@ void rgb_to_hdmi_main() {
          flags = old_flags;
 
          if (result & RET_SYNC_TIMING_CHANGED) {
-             log_info("Timing exceeds window: H=%d, V=%d, Lines=%d, VSync=%d", hsync_period * 1000 / cpuspeed, (int)((double)vsync_period * 1000 / cpuspeed), (int) (((double)vsync_period/hsync_period) + 0.5), (result & RET_VSYNC_POLARITY_CHANGED) ? 1 : 0);
+             log_info("Timing exceeds window: H=%d, V=%d, Lines=%d, VSync=%d", (int)((double)total_hsync_period * 1000 / cpuspeed / (capinfo->nlines - 1)), (int)((double)vsync_period * 1000 / cpuspeed), (int) (((double)vsync_period/(total_hsync_period/(capinfo->nlines-1))) + 0.5), (result & RET_SYNC_POLARITY_CHANGED) ? 1 : 0);
          }
 
          if (result & RET_SYNC_STATE_CHANGED) {
diff --git a/src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_IIe_TTL/Apple_IIe_50Hz.txt b/src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_II-IIe_TTL/Apple_II-IIe_50Hz.txt
similarity index 100%
rename from src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_IIe_TTL/Apple_IIe_50Hz.txt
rename to src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_II-IIe_TTL/Apple_II-IIe_50Hz.txt
diff --git a/src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_IIe_TTL/Apple_IIe_60Hz.txt b/src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_II-IIe_TTL/Apple_II-IIe_60Hz.txt
similarity index 100%
rename from src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_IIe_TTL/Apple_IIe_60Hz.txt
rename to src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_II-IIe_TTL/Apple_II-IIe_60Hz.txt
diff --git a/src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_IIe_TTL/Default.txt b/src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_II-IIe_TTL/Default.txt
similarity index 100%
rename from src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_IIe_TTL/Default.txt
rename to src/scripts/Profiles/3-12_BIT_BBC/Apple/Apple_II-IIe_TTL/Default.txt
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_50Hz.txt b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_50Hz.txt
new file mode 100644
index 00000000..66120679
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_50Hz.txt	
@@ -0,0 +1,4 @@
+sampling=5,5,5,5,5,5,5,0,1,1,5,0,0,0,0,0,0,3,0,0,100,256,100,256,100,256,0,256
+geometry=176,61,640,202,720,270,1,2,1,2,16042494,1024,15000,313,0,0,0
+palette=RrGgBb_(EGA)
+overclock_core=50
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_60Hz.txt b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_60Hz.txt
new file mode 100644
index 00000000..cf1c7dec
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_60Hz.txt	
@@ -0,0 +1,4 @@
+sampling=5,5,5,5,5,5,5,0,1,1,5,0,0,0,0,0,0,3,0,0,100,256,100,256,100,256,0,256
+geometry=176,31,640,202,720,270,2,5,1,2,16107952,1016,15000,263,0,0,0
+palette=RrGgBb_(EGA)
+overclock_core=50
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_Mono.txt b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_Mono.txt
new file mode 100644
index 00000000..e6857605
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Atari_ST_Mono.txt	
@@ -0,0 +1,3 @@
+sampling=3,3,3,3,3,3,3,0,7,0,7,0,0,0,0,0,0,8,0,0,100,256,100,256,100,256,256,256
+geometry=140,34,640,402,672,480,2,2,0,0,32150436,896,15000,501,0,0,0
+scanline_level=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Default.txt b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Default.txt
new file mode 100644
index 00000000..d2b4e6bf
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/Atari/Atari_ST_(No Blanking)/Default.txt	
@@ -0,0 +1 @@
+auto_switch=1
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Other/EF9340.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Other/EF9340.txt
new file mode 100644
index 00000000..a593ca16
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Other/EF9340.txt
@@ -0,0 +1,2 @@
+sampling=3,3,3,3,3,3,3,0,0,0,5,0,0,0,0,0,0,0,0,0,120,256,120,256,120,256,256,256
+geometry=56,33,320,256,360,288,1,1,3,1,7000000,448,5000,312,4,0,0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Other/EF9345.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Other/EF9345.txt
new file mode 100644
index 00000000..60389b70
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Other/EF9345.txt
@@ -0,0 +1,2 @@
+sampling=3,3,3,3,3,3,3,0,0,0,5,0,0,0,0,0,0,0,0,0,120,256,120,256,120,256,256,256
+geometry=44,33,640,256,672,288,1,2,1,1,12000000,768,5000,312,4,0,0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Other/TS9347_40_COL.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Other/TS9347_40_COL.txt
new file mode 100644
index 00000000..68e96f82
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Other/TS9347_40_COL.txt
@@ -0,0 +1,2 @@
+sampling=3,3,3,3,3,3,3,0,0,0,5,0,0,0,0,0,0,0,0,0,100,256,100,256,100,256,256,256
+geometry=32,29,320,256,400,288,1,1,1,1,9545454,512,5000,312,4,0,0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Other/TS9347_80_COL.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Other/TS9347_80_COL.txt
new file mode 100644
index 00000000..92a02d38
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Other/TS9347_80_COL.txt
@@ -0,0 +1,2 @@
+sampling=3,3,3,3,3,3,3,0,0,0,5,0,0,0,0,0,0,0,0,0,100,256,100,256,100,256,256,256
+geometry=32,29,512,256,640,288,2,5,1,1,14318181,768,5000,312,4,0,0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Default.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Default.txt
new file mode 100644
index 00000000..73e4446e
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Default.txt
@@ -0,0 +1,2 @@
+auto_switch=6
+timing_set=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode0_625_12BPP+H+V.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode0_625_12BPP+H+V.txt
new file mode 100644
index 00000000..dc53fa0d
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode0_625_12BPP+H+V.txt
@@ -0,0 +1,6 @@
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,5,0,0,100,256,100,256,100,256,0,256
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,3,6,0
+hdmi_standby=1
+palette=RrGgBb_(EGA)
+overclock_core=50
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode1_625_9BPP-H+V.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode1_625_9BPP-H+V.txt
new file mode 100644
index 00000000..4a07005e
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode1_625_9BPP-H+V.txt
@@ -0,0 +1,5 @@
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,4,0,0,100,256,100,256,100,256,0,256
+geometry=188,31,640,256,720,280,1,2,1,2,16000000,1024,5000,310,2,6,0
+palette=RrGgBb_(EGA)
+overclock_core=50
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode2_625_6BPP-H-V.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode2_625_6BPP-H-V.txt
new file mode 100644
index 00000000..d91b3928
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode2_625_6BPP-H-V.txt
@@ -0,0 +1,5 @@
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,1,0,0,100,256,100,256,100,256,0,256
+geometry=188,33,640,256,720,280,1,2,1,1,16000000,1024,5000,312,0,6,0
+palette=RrGgBb_(EGA)
+overclock_core=50
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_3BPP-Comp(B).txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode3_625_3BPP+H-V.txt
similarity index 52%
rename from src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_3BPP-Comp(B).txt
rename to src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode3_625_3BPP+H-V.txt
index ef9e790a..51fb41f4 100644
--- a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_3BPP-Comp(B).txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode3_625_3BPP+H-V.txt
@@ -1,3 +1,4 @@
 sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,0,0,0,100,256,100,256,100,256,0,256
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,31,640,256,720,280,1,2,1,1,16000000,1024,5000,310,1,6,0
+overclock_core=50
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode4_525_12BPP-H-V.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode4_525_12BPP-H-V.txt
new file mode 100644
index 00000000..9535afe6
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode4_525_12BPP-H-V.txt
@@ -0,0 +1,5 @@
+sampling=5,5,5,5,5,5,5,0,1,0,6,0,0,0,0,0,0,5,0,0,100,256,100,256,100,256,256,256
+geometry=112,30,640,204,736,234,2,5,1,2,14312500,912,4500,262,0,6,0
+palette=RGBI_(CGA)
+palette_control=2
+ntsc_phase=3
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode5_CGA_(IBM_New)-H-V.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode5_CGA_(IBM_New)-H-V.txt
new file mode 100644
index 00000000..4f8e3cdd
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Mode5_CGA_(IBM_New)-H-V.txt
@@ -0,0 +1,6 @@
+sampling=2,2,2,2,2,2,2,0,1,0,6,0,0,0,0,0,0,1,0,0,100,256,100,256,100,256,256,256
+geometry=112,30,640,204,736,234,2,5,1,2,14318181,912,4500,262,3,6,0
+palette=RGBI_(CGA)
+palette_control=2
+ntsc_colour=1
+ntsc_phase=2
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt
new file mode 100644
index 00000000..214d3fce
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt
@@ -0,0 +1,4 @@
+sampling=4,4,4,4,4,4,4,0,1,0,4,0,0,0,0,3,0,4,0,0,227,53,192,18,100,157,124,88
+geometry=92,29,320,256,384,288,1,1,3,2,9545454,512,5000,312,3,6,0
+palette=Mono_(8_level_YUV)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt
new file mode 100644
index 00000000..4c0efa4a
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt
@@ -0,0 +1,4 @@
+sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,3,0,4,0,0,227,53,192,18,100,157,124,88
+geometry=124,32,480,256,584,288,3,4,1,2,14318181,768,5000,312,0,6,0
+palette=Mono_(8_level_RGB)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeE_Atari_ST_Mono.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeE_Atari_ST_Mono.txt
new file mode 100644
index 00000000..d1121058
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeE_Atari_ST_Mono.txt
@@ -0,0 +1,5 @@
+sampling2=3,3,3,3,3,3,3,0,7,0,7,0,0,0,0,0,0,8,0,0,100,256,100,256,100,256,256,256
+geometry2=140,34,640,402,672,480,2,2,0,0,32150436,896,15000,501,0,0,0
+sampling=3,3,3,3,3,3,3,0,7,0,7,0,0,0,0,0,0,0,0,0,100,256,100,256,100,256,256,256
+geometry=140,34,640,402,672,480,2,2,0,0,32150436,896,15000,501,0,6,0
+scanline_level=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeF_864x1024_64Mhz.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeF_864x1024_64Mhz.txt
new file mode 100644
index 00000000..1897ed7e
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/ModeF_864x1024_64Mhz.txt
@@ -0,0 +1,7 @@
+sampling2=1,1,1,1,1,1,1,0,6,0,3,0,0,0,0,0,0,0,0,0,100,256,100,256,100,256,256,256
+geometry2=88,17,864,1024,872,1028,1,1,0,0,64000000,1024,5000,1056,3,0,0
+sampling=1,1,1,1,1,1,1,0,6,0,6,0,0,0,0,0,0,0,0,0,100,256,100,256,100,256,256,256
+geometry=96,17,864,1024,872,1028,1,1,0,0,64000000,1024,5000,1056,3,6,0
+scanline_level=0
+overclock_cpu=50
+overclock_core=50
diff --git a/src/scripts/Profiles/6-12_BIT_YUV/_Test/Test_6BPP+H+V(P).txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_12BPP+H+V.txt
similarity index 60%
rename from src/scripts/Profiles/6-12_BIT_YUV/_Test/Test_6BPP+H+V(P).txt
rename to src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_12BPP+H+V.txt
index 08c1fefd..382c732f 100644
--- a/src/scripts/Profiles/6-12_BIT_YUV/_Test/Test_6BPP+H+V(P).txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_12BPP+H+V.txt
@@ -1,4 +1,5 @@
-sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,1,0,0,100,256,100,256,100,256,0,256
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,5,0,0,100,256,100,256,100,256,0,256
 geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,3,0,0
 palette=RrGgBb_(EGA)
+overclock_core=50
 powerup_message=0
diff --git a/src/scripts/Profiles/3-12_BIT_BBC/_Test/Test_12BPP-Comp.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_12BPP-Comp.txt
similarity index 100%
rename from src/scripts/Profiles/3-12_BIT_BBC/_Test/Test_12BPP-Comp.txt
rename to src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_12BPP-Comp.txt
diff --git a/src/scripts/Profiles/3-12_BIT_BBC/_Test/Test_3BPP-Comp(B).txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_3BPP-Comp(B).txt
similarity index 100%
rename from src/scripts/Profiles/3-12_BIT_BBC/_Test/Test_3BPP-Comp(B).txt
rename to src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_3BPP-Comp(B).txt
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_4BPP-Comp(S).txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_4BPP-Comp(S).txt
similarity index 100%
rename from src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_4BPP-Comp(S).txt
rename to src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_4BPP-Comp(S).txt
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_6BPP+H+V(P).txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_6BPP+H+V(P).txt
similarity index 100%
rename from src/scripts/Profiles/6-12_BIT_RGB/_Test/Test_6BPP+H+V(P).txt
rename to src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/Unused/Test_6BPP+H+V(P).txt
diff --git a/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/modeD_192Mhz_Test.txt b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/modeD_192Mhz_Test.txt
new file mode 100644
index 00000000..bfc46616
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB/_Test/Multi_Test/modeD_192Mhz_Test.txt
@@ -0,0 +1,7 @@
+sampling2=1,1,1,1,1,1,1,0,5,0,8,0,0,0,0,0,0,0,0,0,120,256,120,256,120,256,256,256
+geometry2=128,32,480,256,576,288,3,4,1,0,12000000,768,5000,314,0,0,0
+sampling=1,1,1,1,1,1,1,0,5,0,8,0,0,0,0,0,0,5,0,0,120,256,120,256,120,256,256,256
+geometry=128,32,480,256,576,288,3,4,1,2,12000000,768,5000,314,0,6,0
+teletext_deinterlace=2
+teletext_scaling=0
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/EF9340.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/EF9340.txt
new file mode 100644
index 00000000..a593ca16
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/EF9340.txt
@@ -0,0 +1,2 @@
+sampling=3,3,3,3,3,3,3,0,0,0,5,0,0,0,0,0,0,0,0,0,120,256,120,256,120,256,256,256
+geometry=56,33,320,256,360,288,1,1,3,1,7000000,448,5000,312,4,0,0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/EF9345.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/EF9345.txt
new file mode 100644
index 00000000..60389b70
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/EF9345.txt
@@ -0,0 +1,2 @@
+sampling=3,3,3,3,3,3,3,0,0,0,5,0,0,0,0,0,0,0,0,0,120,256,120,256,120,256,256,256
+geometry=44,33,640,256,672,288,1,2,1,1,12000000,768,5000,312,4,0,0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/TS9347_40_COL.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/TS9347_40_COL.txt
new file mode 100644
index 00000000..6610a04d
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/TS9347_40_COL.txt
@@ -0,0 +1,3 @@
+sampling=5,5,5,5,5,5,5,0,1,0,8,0,0,0,0,3,1,2,0,0,111,67,102,50,23,93,84,76
+geometry=32,33,360,256,440,280,1,1,3,1,9545454,512,5000,312,4,0,0
+palette=Mono_(8_level_RGB)
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/TS9347_80_COL.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/TS9347_80_COL.txt
new file mode 100644
index 00000000..041c262e
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Other/TS9347_80_COL.txt
@@ -0,0 +1,3 @@
+sampling=5,5,5,5,5,5,5,0,1,0,8,0,0,0,0,3,1,2,0,0,111,67,102,50,23,93,84,76
+geometry=32,33,512,256,696,280,1,2,1,1,14318181,768,5000,312,4,0,0
+palette=Mono_(8_level_RGB)
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Default.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Default.txt
new file mode 100644
index 00000000..73e4446e
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Default.txt
@@ -0,0 +1,2 @@
+auto_switch=6
+timing_set=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode0_4LVL_Term-C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode0_4LVL_Term-C.txt
new file mode 100644
index 00000000..e6959a13
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode0_4LVL_Term-C.txt
@@ -0,0 +1,4 @@
+sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,7,1,0,55,16,55,16,100,34,34,34
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,6,0
+palette=RrGgBb_(EGA)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode1_3LVL_Term+C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode1_3LVL_Term+C.txt
new file mode 100644
index 00000000..6e37679d
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode1_3LVL_Term+C.txt
@@ -0,0 +1,4 @@
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,1,1,0,55,16,55,16,100,256,256,17
+geometry=188,31,640,256,720,280,1,2,1,2,16000000,1024,5000,310,5,6,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode2_3LVL_Clamp+Term+C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode2_3LVL_Clamp+Term+C.txt
new file mode 100644
index 00000000..5ebb5f3a
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode2_3LVL_Clamp+Term+C.txt
@@ -0,0 +1,4 @@
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,0,0,1,1,1,65,26,55,16,100,256,10,17
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,5,6,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode3_3LVL_NoTerm-C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode3_3LVL_NoTerm-C.txt
new file mode 100644
index 00000000..62baf0df
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode3_3LVL_NoTerm-C.txt
@@ -0,0 +1,4 @@
+sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,1,0,0,190,55,190,55,100,256,256,87
+geometry=188,31,640,256,720,280,1,2,1,2,16000000,1024,5000,310,4,6,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode4_525_6BPP+C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode4_525_6BPP+C.txt
new file mode 100644
index 00000000..801c5c8f
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode4_525_6BPP+C.txt
@@ -0,0 +1,5 @@
+sampling=5,5,5,5,5,5,5,0,1,0,6,0,0,0,0,0,0,7,1,0,55,16,55,16,100,34,34,34
+geometry=112,30,640,204,736,234,2,5,1,2,14312500,912,4500,262,5,6,0
+palette=RrGgBb_(EGA)
+palette_control=2
+ntsc_phase=3
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode5_CGA_(IBM_New)-C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode5_CGA_(IBM_New)-C.txt
new file mode 100644
index 00000000..e1989bde
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Mode5_CGA_(IBM_New)-C.txt
@@ -0,0 +1,8 @@
+sampling2=7,7,7,7,7,7,7,0,1,0,6,0,0,0,0,0,0,7,1,0,55,16,55,16,100,34,34,34
+geometry2=112,30,640,204,736,234,2,5,1,2,14318181,912,4500,262,4,6,0
+sampling=5,5,5,5,5,5,5,0,1,0,6,0,0,0,0,0,0,7,1,0,47,11,47,11,100,29,29,29
+geometry=112,30,640,204,736,234,2,5,1,2,14318181,912,4500,262,4,6,0
+palette=RGBI_(CGA)
+palette_control=2
+ntsc_colour=1
+ntsc_phase=2
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt
new file mode 100644
index 00000000..e86d319c
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt
@@ -0,0 +1,4 @@
+sampling=4,4,4,4,4,4,4,0,1,0,4,0,0,0,0,3,0,7,0,0,227,53,192,18,100,157,124,88
+geometry=92,29,320,256,384,288,1,1,3,1,9545454,512,5000,312,4,6,0
+palette=Mono_(8_level_RGB)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt
new file mode 100644
index 00000000..936a5849
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt
@@ -0,0 +1,4 @@
+sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,3,0,7,0,0,227,53,192,18,100,157,124,88
+geometry=124,32,480,256,584,288,3,4,1,1,14318181,768,5000,312,5,6,0
+palette=Mono_(8_level_RGB)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeE_Atari_ST_Mono.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeE_Atari_ST_Mono.txt
new file mode 100644
index 00000000..6543e935
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeE_Atari_ST_Mono.txt
@@ -0,0 +1,5 @@
+sampling2=3,3,3,3,3,3,3,0,7,0,7,0,0,0,0,0,0,0,0,0,28,256,28,256,100,256,256,34
+geometry2=140,34,640,402,672,480,2,2,0,0,32150436,896,15000,501,0,6,0
+sampling=2,2,2,2,2,2,2,0,7,0,7,0,0,0,0,0,0,0,1,0,28,256,28,256,100,256,256,34
+geometry=140,34,640,402,672,480,2,2,0,0,32150436,896,15000,501,5,6,0
+scanline_level=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeF_864x1024_64Mhz-C.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeF_864x1024_64Mhz-C.txt
new file mode 100644
index 00000000..1dc219b1
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/ModeF_864x1024_64Mhz-C.txt
@@ -0,0 +1,8 @@
+sampling2=0,0,0,0,0,0,0,0,6,0,3,0,0,0,0,0,0,0,1,0,28,256,28,256,100,256,256,34
+geometry2=88,17,864,1024,872,1028,1,1,0,0,64000000,1024,5000,1056,4,6,0
+sampling=0,0,0,0,0,0,0,0,6,0,6,0,0,0,0,0,0,0,1,0,28,256,28,256,100,256,256,34
+geometry=96,17,864,1024,872,1028,1,1,0,0,64000000,1024,5000,1056,4,6,0
+scanline_level=0
+overclock_cpu=50
+overclock_core=50
+powerup_message=0
diff --git a/src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_3LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_NoTerm.txt
similarity index 63%
rename from src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_3LVL_NoTerm.txt
rename to src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_NoTerm.txt
index 20df7c7a..6d3dd648 100644
--- a/src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_3LVL_NoTerm.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_NoTerm.txt
@@ -1,4 +1,4 @@
 sampling=7,7,7,7,7,7,7,0,1,0,4,0,0,0,0,0,0,1,0,0,190,55,190,55,100,256,256,87
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RGBrgb_(Amstrad)
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term+Clamp.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term+Clamp.txt
new file mode 100644
index 00000000..d4bd7f08
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term+Clamp.txt
@@ -0,0 +1,4 @@
+sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,1,1,1,65,26,55,16,100,256,10,17
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_3LVL_Term.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term.txt
similarity index 62%
rename from src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_3LVL_Term.txt
rename to src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term.txt
index 6ad69fa0..95e2df67 100644
--- a/src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_3LVL_Term.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term.txt
@@ -1,4 +1,4 @@
 sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,1,1,0,55,16,55,16,100,256,256,17
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RGBrgb_(Amstrad)
 powerup_message=0
diff --git a/src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_4LVL_Term.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_4LVL_Term.txt
similarity index 61%
rename from src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_4LVL_Term.txt
rename to src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_4LVL_Term.txt
index c6e634cc..a3fc4807 100644
--- a/src/scripts/Profiles/3-12_BIT_BBC_Analog/_Test/Test_4LVL_Term.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/Unused/Test_4LVL_Term.txt
@@ -1,4 +1,4 @@
 sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,7,1,0,55,16,55,16,100,34,34,34
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RrGgBb_(EGA)
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/modeD_192Mhz_Test.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/modeD_192Mhz_Test.txt
new file mode 100644
index 00000000..6c7ff07c
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Multi_Test/modeD_192Mhz_Test.txt
@@ -0,0 +1,6 @@
+sampling2=1,1,1,1,1,1,1,0,5,0,8,0,0,0,0,0,0,1,1,0,34,34,34,34,100,256,256,256
+geometry2=128,32,480,256,576,288,3,4,1,0,12000000,768,5000,314,5,0,0
+sampling=1,1,1,1,1,1,1,0,5,0,8,0,0,0,0,0,0,7,1,0,55,16,55,16,100,34,34,34
+geometry=128,32,480,256,576,288,3,4,1,1,12000000,768,5000,314,5,6,0
+palette=RrGgBb_(EGA)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_NoTerm.txt
index 20df7c7a..6d3dd648 100644
--- a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_NoTerm.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_NoTerm.txt
@@ -1,4 +1,4 @@
 sampling=7,7,7,7,7,7,7,0,1,0,4,0,0,0,0,0,0,1,0,0,190,55,190,55,100,256,256,87
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RGBrgb_(Amstrad)
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term+Clamp.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term+Clamp.txt
index 8b46bab9..d4bd7f08 100644
--- a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term+Clamp.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term+Clamp.txt
@@ -1,4 +1,4 @@
 sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,1,1,1,65,26,55,16,100,256,10,17
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RGBrgb_(Amstrad)
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term.txt
index 6ad69fa0..95e2df67 100644
--- a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_3LVL_Term.txt
@@ -1,4 +1,4 @@
 sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,1,1,0,55,16,55,16,100,256,256,17
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RGBrgb_(Amstrad)
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_4LVL_Term.txt b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_4LVL_Term.txt
index c6e634cc..a3fc4807 100644
--- a/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_4LVL_Term.txt
+++ b/src/scripts/Profiles/6-12_BIT_RGB_Analog/_Test/Test_4LVL_Term.txt
@@ -1,4 +1,4 @@
 sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,7,1,0,55,16,55,16,100,34,34,34
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,0,0
 palette=RrGgBb_(EGA)
 powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV/_Test/Test_4BPP-Comp(S).txt b/src/scripts/Profiles/6-12_BIT_YUV/_Test/Test_4BPP-Comp(S).txt
deleted file mode 100644
index f2bef79e..00000000
--- a/src/scripts/Profiles/6-12_BIT_YUV/_Test/Test_4BPP-Comp(S).txt
+++ /dev/null
@@ -1,4 +0,0 @@
-sampling=6,6,6,6,6,6,6,0,1,0,4,0,0,0,0,0,0,1,0,0,100,256,100,256,100,256,0,256
-geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
-palette=RGBrgb_(Spectrum)
-powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Other/TS9347_40_COL.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Other/TS9347_40_COL.txt
new file mode 100644
index 00000000..2ed68296
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Other/TS9347_40_COL.txt
@@ -0,0 +1,3 @@
+sampling=5,5,5,5,5,5,5,0,1,0,8,0,0,0,0,3,1,2,0,0,111,102,93,84,23,76,67,50
+geometry=32,33,360,256,440,280,1,1,3,1,9545454,512,5000,312,4,0,0
+palette=Mono_(8_level_YUV)
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Other/TS9347_80_COL.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Other/TS9347_80_COL.txt
new file mode 100644
index 00000000..b27f882a
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Other/TS9347_80_COL.txt
@@ -0,0 +1,3 @@
+sampling=5,5,5,5,5,5,5,0,1,0,8,0,0,0,0,3,1,2,0,0,111,102,93,84,23,76,67,50
+geometry=32,33,512,256,696,280,1,2,1,1,14318181,768,5000,312,4,0,0
+palette=Mono_(8_level_YUV)
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode0_4LVL_Term-C.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode0_4LVL_Term-C.txt
new file mode 100644
index 00000000..41f3d6e7
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode0_4LVL_Term-C.txt
@@ -0,0 +1,4 @@
+sampling=3,3,3,3,3,3,3,0,1,0,4,0,0,0,0,4,0,2,1,0,55,34,55,34,100,16,16,16
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,4,6,0
+palette=RrGgBb_(EGA)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode1_3LVL_Term+C.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode1_3LVL_Term+C.txt
new file mode 100644
index 00000000..e78c3734
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode1_3LVL_Term+C.txt
@@ -0,0 +1,4 @@
+sampling=3,3,3,3,3,3,3,0,1,0,4,0,0,0,0,0,0,1,1,0,55,16,55,16,100,256,256,17
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,310,5,6,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode2_3LVL_Clamp+Term+C.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode2_3LVL_Clamp+Term+C.txt
new file mode 100644
index 00000000..d2cfcfeb
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode2_3LVL_Clamp+Term+C.txt
@@ -0,0 +1,4 @@
+sampling=3,3,3,3,3,3,3,0,1,0,4,0,0,0,0,0,0,1,1,1,65,26,55,16,100,256,10,17
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,312,5,6,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode3_3LVL_NoTerm-C.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode3_3LVL_NoTerm-C.txt
new file mode 100644
index 00000000..211b14a8
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode3_3LVL_NoTerm-C.txt
@@ -0,0 +1,4 @@
+sampling=3,3,3,3,3,3,3,0,1,0,4,0,0,0,0,0,0,1,0,0,190,55,190,55,100,256,256,87
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,5000,310,4,6,0
+palette=RGBrgb_(Amstrad)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode4_525_6BPP+C.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode4_525_6BPP+C.txt
new file mode 100644
index 00000000..ef9c1cb3
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode4_525_6BPP+C.txt
@@ -0,0 +1,5 @@
+sampling=2,2,2,2,2,2,2,0,1,0,6,0,0,0,0,4,0,2,1,0,55,34,55,34,100,16,16,16
+geometry=112,30,640,204,736,234,2,5,1,2,14312500,912,4500,262,5,6,0
+palette=RrGgBb_(EGA)
+palette_control=2
+ntsc_phase=3
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode5_CGA_(IBM_New)-C.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode5_CGA_(IBM_New)-C.txt
new file mode 100644
index 00000000..01e8f3a2
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Mode5_CGA_(IBM_New)-C.txt
@@ -0,0 +1,6 @@
+sampling=7,7,7,7,7,7,7,0,1,0,6,0,0,0,0,4,0,2,1,0,55,34,55,34,100,16,16,16
+geometry=112,30,640,204,736,234,2,5,1,2,14318181,912,4500,262,4,6,0
+palette=RGBI
+palette_control=2
+ntsc_colour=1
+ntsc_phase=2
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt
new file mode 100644
index 00000000..dffc92e5
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/ModeB_TS9347_40-8LVL_NoTerm.txt
@@ -0,0 +1,4 @@
+sampling=0,0,0,0,0,0,0,0,1,0,4,0,0,0,0,3,0,2,0,0,227,192,157,124,100,88,53,18
+geometry=92,29,320,256,384,288,1,1,3,1,9545454,512,5000,312,4,6,0
+palette=Mono_(8_level_YUV)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt
new file mode 100644
index 00000000..51a2b961
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/ModeC_TS9347_80-8LVL_NoTerm.txt
@@ -0,0 +1,4 @@
+sampling=3,3,3,3,3,3,3,0,1,0,4,0,0,0,0,3,0,2,0,0,227,192,157,124,100,88,53,18
+geometry=124,32,480,256,584,288,3,4,1,1,14318181,768,15000,312,5,6,0
+palette=Mono_(8_level_YUV)
+powerup_message=0
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_3LVL_NoTerm.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_3LVL_NoTerm.txt
similarity index 100%
rename from src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_3LVL_NoTerm.txt
rename to src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_3LVL_NoTerm.txt
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_3LVL_Term+Clamp.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term+Clamp.txt
similarity index 100%
rename from src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_3LVL_Term+Clamp.txt
rename to src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term+Clamp.txt
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_3LVL_Term.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term.txt
similarity index 100%
rename from src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_3LVL_Term.txt
rename to src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_3LVL_Term.txt
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_4LVL_Term.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_4LVL_Term.txt
similarity index 100%
rename from src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Test_4LVL_Term.txt
rename to src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_4LVL_Term.txt
diff --git a/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_8LVL_Mono_Term.txt b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_8LVL_Mono_Term.txt
new file mode 100644
index 00000000..e94701ed
--- /dev/null
+++ b/src/scripts/Profiles/6-12_BIT_YUV_Analog/_Test/Multi_Test/Unused/Test_8LVL_Mono_Term.txt
@@ -0,0 +1,4 @@
+sampling=5,5,5,5,5,5,5,0,1,0,4,0,0,0,0,3,0,2,1,0,25,22,18,14,100,10,5,2
+geometry=188,33,640,256,720,280,1,2,1,2,16000000,1024,15000,312,4,0,0
+palette=Mono_(8_level_YUV)
+powerup_message=0
diff --git a/src/scripts/Use_ARM_Capture.bat b/src/scripts/Use_ARM_Capture.bat
index 5e2b0e62..3d50183f 100644
--- a/src/scripts/Use_ARM_Capture.bat
+++ b/src/scripts/Use_ARM_Capture.bat
@@ -1,2 +1,5 @@
+@echo Switching to ARM capture
+@echo Warning: GPU capture is preferred
+@pause
 ren config.txt configG.txt
 ren configA.txt config.txt
diff --git a/src/scripts/Use_GPU_Capture.bat b/src/scripts/Use_GPU_Capture.bat
index 5b12d882..9c057e60 100644
--- a/src/scripts/Use_GPU_Capture.bat
+++ b/src/scripts/Use_GPU_Capture.bat
@@ -1,2 +1,4 @@
+@echo Switching to GPU capture
+@pause
 ren config.txt configA.txt
 ren configG.txt config.txt
diff --git a/src/videocore.asm b/src/videocore.asm
index ffc8d92d..41e15a31 100644
Binary files a/src/videocore.asm and b/src/videocore.asm differ
diff --git a/src/videocore.c b/src/videocore.c
index 92d3ab0f..82fd5b3c 100644
--- a/src/videocore.c
+++ b/src/videocore.c
@@ -11,93 +11,103 @@ unsigned char ___videocore_asm[] = {
   0x52, 0x23, 0x53, 0x25, 0x59, 0x26, 0x5a, 0x27, 0x5c, 0x30, 0x5c, 0x34,
   0xf0, 0x71, 0xf1, 0x71, 0xf2, 0x71, 0xf3, 0x71, 0xf9, 0x71, 0xfa, 0x71,
   0x50, 0x31, 0x51, 0x32, 0x52, 0x33, 0x53, 0x35, 0x59, 0x36, 0x5a, 0x37,
-  0x82, 0x40, 0x53, 0x20, 0x03, 0x6a, 0x7e, 0x18, 0xf3, 0x6c, 0x00, 0x90,
-  0x64, 0x00, 0x31, 0x40, 0x01, 0x7b, 0x01, 0x6a, 0x39, 0x18, 0x11, 0x6a,
-  0x27, 0x18, 0x12, 0x73, 0x21, 0x6a, 0x34, 0x18, 0x31, 0x6a, 0x22, 0x18,
-  0x41, 0x6a, 0x0e, 0x18, 0x51, 0x6a, 0xd7, 0x18, 0x40, 0x08, 0x20, 0x45,
-  0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0xf9, 0x18,
-  0x58, 0x34, 0x00, 0x9e, 0x41, 0x00, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d,
+  0x82, 0x40, 0x01, 0x00, 0x53, 0x20, 0x01, 0x00, 0x03, 0x6a, 0x01, 0x00,
+  0x7b, 0x18, 0xf3, 0x6d, 0xe4, 0x18, 0xf3, 0x6c, 0x00, 0x90, 0x65, 0x00,
+  0x31, 0x40, 0x01, 0x7b, 0x01, 0x6a, 0x39, 0x18, 0x11, 0x6a, 0x27, 0x18,
+  0x12, 0x73, 0x21, 0x6a, 0x34, 0x18, 0x31, 0x6a, 0x22, 0x18, 0x41, 0x6a,
+  0x0e, 0x18, 0x51, 0x6a, 0xd2, 0x18, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d,
   0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0xf9, 0x18, 0x58, 0x34,
+  0x00, 0x9e, 0x41, 0x00, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18,
+  0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0xf9, 0x18, 0x58, 0x34, 0x40, 0x08,
+  0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x70, 0x6d,
+  0x79, 0x18, 0x2e, 0x1f, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18,
+  0x20, 0x45, 0x12, 0x75, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18,
+  0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0xf3, 0x18, 0x58, 0x34, 0x1e, 0x1f,
   0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45, 0x12, 0x75,
-  0x70, 0x6d, 0x79, 0x18, 0x2e, 0x1f, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d,
+  0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45, 0x12, 0x75,
+  0x70, 0x6d, 0xf3, 0x18, 0x58, 0x34, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d,
   0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d,
-  0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0xf3, 0x18, 0x58, 0x34,
-  0x1e, 0x1f, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45,
-  0x12, 0x75, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45,
-  0x12, 0x75, 0x70, 0x6d, 0xf3, 0x18, 0x58, 0x34, 0x40, 0x08, 0x20, 0x45,
-  0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x40, 0x08, 0x20, 0x45,
-  0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0x73, 0x18,
-  0x12, 0x6d, 0x87, 0x18, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18,
-  0x20, 0x45, 0x12, 0x75, 0x82, 0x40, 0xe3, 0x6c, 0x00, 0x91, 0x25, 0x01,
-  0xd3, 0x6c, 0x00, 0x91, 0x8c, 0x00, 0x73, 0x47, 0x13, 0x62, 0x13, 0x7a,
+  0xfd, 0x18, 0x20, 0x45, 0x12, 0x75, 0x70, 0x6d, 0x73, 0x18, 0x12, 0x6d,
+  0x87, 0x18, 0x40, 0x08, 0x20, 0x45, 0x10, 0x6d, 0xfd, 0x18, 0x20, 0x45,
+  0x12, 0x75, 0x82, 0x40, 0x12, 0x1f, 0xd3, 0x6c, 0x00, 0x91, 0x9d, 0x00,
+  0x50, 0x20, 0xf0, 0x6d, 0x8c, 0x18, 0x40, 0x08, 0x70, 0x6d, 0xfb, 0x18,
+  0x03, 0x6d, 0x87, 0x18, 0x50, 0x20, 0xf0, 0x6d, 0x84, 0x18, 0x40, 0x08,
+  0x70, 0x6d, 0x7b, 0x18, 0xe3, 0x6c, 0x00, 0x91, 0x48, 0x01, 0x73, 0x47,
+  0x13, 0x62, 0x13, 0x7a, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d,
+  0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08,
+  0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
+  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x31, 0x7f, 0x90, 0x52, 0xff,
   0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2,
   0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18,
   0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
-  0x10, 0x4d, 0x50, 0x31, 0x7f, 0x90, 0x66, 0xff, 0x40, 0x08, 0x10, 0x6d,
+  0x10, 0x4d, 0x50, 0x32, 0x7f, 0x90, 0x3c, 0xff, 0x40, 0x08, 0x10, 0x6d,
   0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x13, 0x66,
   0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47,
-  0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x32,
-  0x7f, 0x90, 0x50, 0xff, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d,
+  0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x33,
+  0x7f, 0x90, 0x26, 0xff, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d,
   0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08,
   0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x33, 0x7f, 0x90, 0x3a, 0xff,
+  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x35, 0x7f, 0x90, 0x10, 0xff,
   0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2,
   0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18,
   0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
-  0x10, 0x4d, 0x50, 0x35, 0x7f, 0x90, 0x24, 0xff, 0x40, 0x08, 0x10, 0x6d,
+  0x10, 0x4d, 0x50, 0x36, 0x7f, 0x90, 0xfa, 0xfe, 0x40, 0x08, 0x10, 0x6d,
   0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x13, 0x66,
-  0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47,
-  0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x36,
-  0x7f, 0x90, 0x0e, 0xff, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d,
-  0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x12, 0x75,
+  0x20, 0x4d, 0x12, 0x75, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d,
+  0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d,
+  0x50, 0x37, 0x7f, 0x90, 0xe3, 0xfe, 0x7f, 0x9e, 0x7b, 0xff, 0x50, 0x20,
+  0xf0, 0x6d, 0xa4, 0x18, 0x40, 0x08, 0x70, 0x6d, 0xfb, 0x18, 0x40, 0x08,
+  0x70, 0x6d, 0xf8, 0x18, 0x40, 0x08, 0x70, 0x6d, 0xf5, 0x18, 0x40, 0x08,
+  0x70, 0x6d, 0xf2, 0x18, 0x40, 0x08, 0x70, 0x6d, 0xef, 0x18, 0x03, 0x6d,
+  0x93, 0x18, 0x50, 0x20, 0xf0, 0x6d, 0x90, 0x18, 0x40, 0x08, 0x70, 0x6d,
+  0x7b, 0x18, 0x40, 0x08, 0x70, 0x6d, 0x78, 0x18, 0x40, 0x08, 0x70, 0x6d,
+  0x75, 0x18, 0x40, 0x08, 0x70, 0x6d, 0x72, 0x18, 0x40, 0x08, 0x70, 0x6d,
+  0x6f, 0x18, 0x73, 0x47, 0x13, 0x62, 0x13, 0x7a, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x41, 0x08,
+  0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
+  0x10, 0x4d, 0x50, 0x31, 0x7f, 0x90, 0xa0, 0xfe, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x41, 0x08,
+  0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
+  0x10, 0x4d, 0x50, 0x32, 0x7f, 0x90, 0x88, 0xfe, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x41, 0x08,
+  0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
+  0x10, 0x4d, 0x50, 0x33, 0x7f, 0x90, 0x70, 0xfe, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x41, 0x08,
+  0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
+  0x10, 0x4d, 0x50, 0x35, 0x7f, 0x90, 0x58, 0xfe, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x41, 0x08,
+  0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a,
+  0x10, 0x4d, 0x50, 0x36, 0x7f, 0x90, 0x40, 0xfe, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x12, 0x75, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18,
+  0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d,
+  0x03, 0x6a, 0x10, 0x4d, 0x50, 0x37, 0x7f, 0x90, 0x27, 0xfe, 0x7f, 0x9e,
+  0x6f, 0xff, 0x73, 0x47, 0x30, 0x40, 0xb0, 0x62, 0xc1, 0x60, 0xe3, 0xc4,
+  0x01, 0x07, 0x12, 0x75, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d,
+  0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x12, 0x75, 0x20, 0x4d, 0x41, 0x08,
+  0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
+  0x01, 0x7d, 0x10, 0x4d, 0x10, 0x4d, 0x50, 0x31, 0x40, 0x08, 0x10, 0x6d,
+  0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x20, 0x4d,
   0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2,
-  0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x37, 0x7f, 0x90,
-  0xf7, 0xfe, 0x7f, 0x9e, 0x7b, 0xff, 0x73, 0x47, 0x13, 0x62, 0x13, 0x7a,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
-  0x7e, 0x18, 0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x31, 0x7f, 0x90, 0xda, 0xfe,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
-  0x7e, 0x18, 0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x32, 0x7f, 0x90, 0xc2, 0xfe,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
-  0x7e, 0x18, 0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x33, 0x7f, 0x90, 0xaa, 0xfe,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
-  0x7e, 0x18, 0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x35, 0x7f, 0x90, 0x92, 0xfe,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
-  0x7e, 0x18, 0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x36, 0x7f, 0x90, 0x7a, 0xfe,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x40, 0x08, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x12, 0x75, 0x41, 0x08,
-  0x11, 0x6d, 0x7e, 0x18, 0x41, 0x08, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2,
-  0xce, 0x08, 0x01, 0x7d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x37, 0x7f, 0x90,
-  0x61, 0xfe, 0x7f, 0x9e, 0x6f, 0xff, 0x73, 0x47, 0x30, 0x40, 0xb0, 0x62,
-  0xc1, 0x60, 0xe3, 0xc4, 0x01, 0x07, 0x12, 0x75, 0x40, 0x08, 0x10, 0x6d,
-  0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x12, 0x75,
-  0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47,
-  0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x10, 0x4d, 0x10, 0x4d, 0x50, 0x31,
-  0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2,
-  0xce, 0x00, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d,
+  0xce, 0x08, 0x01, 0x7d, 0x10, 0x4d, 0x10, 0x4d, 0x50, 0x32, 0x40, 0x08,
+  0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
+  0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d,
   0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x10, 0x4d, 0x10, 0x4d,
-  0x50, 0x32, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47,
-  0x00, 0xc2, 0xce, 0x00, 0x13, 0x66, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
+  0x50, 0x33, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47,
+  0x00, 0xc2, 0xce, 0x00, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18,
+  0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x10, 0x4d,
+  0x10, 0x4d, 0x50, 0x35, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d,
+  0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d,
   0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d,
-  0x10, 0x4d, 0x10, 0x4d, 0x50, 0x33, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18,
+  0x10, 0x4d, 0x10, 0x4d, 0x50, 0x36, 0x40, 0x08, 0x10, 0x6d, 0xfe, 0x18,
   0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x20, 0x4d, 0x41, 0x08,
   0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2, 0xce, 0x08,
-  0x01, 0x7d, 0x10, 0x4d, 0x10, 0x4d, 0x50, 0x35, 0x40, 0x08, 0x10, 0x6d,
-  0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00, 0x20, 0x4d,
-  0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47, 0x01, 0xc2,
-  0xce, 0x08, 0x01, 0x7d, 0x10, 0x4d, 0x10, 0x4d, 0x50, 0x36, 0x40, 0x08,
-  0x10, 0x6d, 0xfe, 0x18, 0x80, 0x6d, 0x60, 0x47, 0x00, 0xc2, 0xce, 0x00,
-  0x20, 0x4d, 0x41, 0x08, 0x11, 0x6d, 0x7e, 0x18, 0x81, 0x6d, 0x61, 0x47,
-  0x01, 0xc2, 0xce, 0x08, 0x01, 0x7d, 0x10, 0x4d, 0x03, 0x6a, 0x10, 0x4d,
-  0x50, 0x37, 0x7f, 0x91, 0x8b, 0xff, 0x7f, 0x9e, 0xdf, 0xfd
+  0x01, 0x7d, 0x10, 0x4d, 0x03, 0x6a, 0x10, 0x4d, 0x50, 0x37, 0x7f, 0x91,
+  0x8b, 0xff, 0x7f, 0x9e, 0xa5, 0xfd
 };
-unsigned int ___videocore_asm_len = 1198;
+unsigned int ___videocore_asm_len = 1314;
diff --git a/src/videocore.lst b/src/videocore.lst
index 220e0dcc..fe7cf48d 100644
--- a/src/videocore.lst
+++ b/src/videocore.lst
@@ -1,5 +1,5 @@
 Sections:
-00: ".text" (0-4AE)
+00: ".text" (0-522)
 
 
 Source: "videocore.s"
@@ -39,807 +39,880 @@ Source: "videocore.s"
                             	    34: .equ ALT_MUX_BIT,          14             #moved version of MUX bit
                             	    35: .equ SYNC_BIT,             23             #sync input
                             	    36: .equ VIDEO_MASK,           0x3ffc         #12bit GPIO mask
-                            	    37: .equ COMMAND_MASK,         0x00000fff     #masks out command bits that trigger sync detection
-                            	    38: .equ SIMPLE_SYNC_FLAG,     15
-                            	    39: .equ HIGH_LATENCY_FLAG,    14
+                            	    37: 
+                            	    38: .equ COMMAND_MASK,         0x00000fff     #masks out command bits that trigger sync detection
+                            	    39: #command bits
                             	    40: .equ OLD_FIRMWARE_FLAG,    13
-                            	    41: 
-                            	    42: #macros
-                            	    43: 
-                            	    44: .macro LO_PSYNC_CAPTURE
-                            	    45: wait_psync_lo\@:
-                            	    46:    ld     r0, (r4)
-                            	    47:    btst   r0, PSYNC_BIT
-                            	    48:    bne    wait_psync_lo\@
-                            	    49:    btst   r0, MUX_BIT
-                            	    50:    and    r0, r6
-                            	    51:    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	    52:    sub    r3, 1
-                            	    53:    or     r0, r2           #merge bit state
-                            	    54: .endm
-                            	    55: 
-                            	    56: .macro HI_PSYNC_CAPTURE
-                            	    57: wait_psync_hi\@:
-                            	    58:    ld     r1, (r4)
-                            	    59:    btst   r1, PSYNC_BIT
-                            	    60:    beq    wait_psync_hi\@
-                            	    61:    btst   r1, MUX_BIT
-                            	    62:    and    r1, r6
-                            	    63:    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	    64:    lsl    r1, 16           #merge lo and hi samples
-                            	    65:    cmp    r3, 0
-                            	    66:    or     r0, r1
-                            	    67: .endm
-                            	    68: 
-                            	    69: 
-                            	    70: .macro OFW_LO_PSYNC_CAPTURE
-                            	    71: wait_psync_lo\@:
-                            	    72:    ld     r0, (r4)
-                            	    73:    btst   r0, PSYNC_BIT
-                            	    74:    bne    wait_psync_lo\@
-                            	    75:    ld     r0, (r4)
-                            	    76:    btst   r0, MUX_BIT
-                            	    77:    and    r0, r6
-                            	    78:    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	    79:    sub    r3, 1
-                            	    80:    or     r0, r2           #merge bit state
-                            	    81: .endm
-                            	    82: 
-                            	    83: .macro OFW_HI_PSYNC_CAPTURE
-                            	    84: wait_psync_hi\@:
-                            	    85:    ld     r1, (r4)
-                            	    86:    btst   r1, PSYNC_BIT
-                            	    87:    beq    wait_psync_hi\@
-                            	    88:    ld     r1, (r4)
-                            	    89:    btst   r1, MUX_BIT
-                            	    90:    and    r1, r6
-                            	    91:    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	    92:    lsl    r1, 16           #merge lo and hi samples
-                            	    93:    cmp    r3, 0
-                            	    94:    or     r0, r1
-                            	    95: .endm
-                            	    96: 
-                            	    97: 
-                            	    98: .macro HL_LO_PSYNC_CAPTURE
-                            	    99: wait_psync_lo\@:
-                            	   100:    ld     r0, (r4)
-                            	   101:    btst   r0, PSYNC_BIT
-                            	   102:    bne    wait_psync_lo\@
-                            	   103:    btst   r0, MUX_BIT
-                            	   104:    and    r0, r6
-                            	   105:    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	   106: 
-                            	   107: .endm
-                            	   108: 
-                            	   109: .macro HL_HI_PSYNC_CAPTURE
-                            	   110: wait_psync_hi\@:
-                            	   111:    ld     r1, (r4)
-                            	   112:    btst   r1, PSYNC_BIT
-                            	   113:    beq    wait_psync_hi\@
-                            	   114:    btst   r1, MUX_BIT
-                            	   115:    and    r1, r6
-                            	   116:    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	   117:    lsl    r1, 16           #merge lo and hi samples
-                            	   118:    or     r0, r1
-                            	   119: .endm
-                            	   120: 
-                            	   121: 
-                            	   122: .macro EDGE_DETECT
-                            	   123: waitPSE\@:
-                            	   124:    ld     r0, (r4)
-                            	   125:    eor    r0, r2
-                            	   126:    btst   r0, PSYNC_BIT
-                            	   127:    bne    waitPSE\@
-                            	   128:    eor    r0, r2       #restore r0 value
-                            	   129:    bchg   r2, PSYNC_BIT
-                            	   130: .endm
-                            	   131: 
-                            	   132: 
-                            	   133: # main code entry point
-00:00000000 0500            	   134:    di
-00:00000002 106A            	   135:    cmp    r0, 1
-00:00000004 8D18            	   136:    bne    not_gpio_read_benchmark
-00:00000006 02E8A0860100    	   137:    mov    r2, 100000
-00:0000000C 01E83400207E    	   138:    mov    r1, GPLEV0
-                            	   139: read_bench_loop:
-00:00000012 1308            	   140:    ld     r3, (r1)  #read gpio
-00:00000014 1266            	   141:    sub    r2, 1
-00:00000016 026A            	   142:    cmp    r2, 0
-00:00000018 FD18            	   143:    bne    read_bench_loop
-00:0000001A 0400            	   144:    ei
-00:0000001C 5A00            	   145:    rts
-                            	   146: 
-                            	   147: not_gpio_read_benchmark:
-00:0000001E 206A            	   148:    cmp    r0, 2
-00:00000020 8E18            	   149:    bne    not_mbox_write_benchmark
-00:00000022 02E8A0860100    	   150:    mov    r2, 100000
-00:00000028 01E8BC00007E    	   151:    mov    r1, GPU_DATA_BUFFER_5
-00:0000002E 0360            	   152:    mov    r3, 0
-                            	   153: write_bench_loop:
-00:00000030 1309            	   154:    st     r3, (r1)  #write to mbox
-00:00000032 1266            	   155:    sub    r2, 1
-00:00000034 026A            	   156:    cmp    r2, 0
-00:00000036 FD18            	   157:    bne    write_bench_loop
-00:00000038 0400            	   158:    ei
-00:0000003A 5A00            	   159:    rts
-                            	   160: 
-                            	   161: not_mbox_write_benchmark:
-00:0000003C 04E83400207E    	   162:    mov    r4, GPLEV0
-00:00000042 05E8A000007E    	   163:    mov    r5, GPU_COMMAND
-00:00000048 06E8FC3F0000    	   164:    mov    r6, VIDEO_MASK
-00:0000004E 07E8FF0F0000    	   165:    mov    r7, COMMAND_MASK
-00:00000054 08E801000200    	   166:    mov    r8, DEFAULT_BIT_STATE
-00:0000005A 0C60            	   167:    mov    r12, 0                       # remains at zero for rest of the code
-00:0000005C 5C31            	   168:    st     r12, DATA_BUFFER_0_offset(r5)
-00:0000005E 5C32            	   169:    st     r12, DATA_BUFFER_1_offset(r5)
-00:00000060 5C33            	   170:    st     r12, DATA_BUFFER_2_offset(r5)
-00:00000062 5C35            	   171:    st     r12, DATA_BUFFER_3_offset(r5)
-00:00000064 5C36            	   172:    st     r12, DATA_BUFFER_4_offset(r5)
-00:00000066 5C37            	   173:    st     r12, DATA_BUFFER_5_offset(r5)
-                            	   174: 
-                            	   175: wait_for_command:
-00:00000068 5021            	   176:    ld     r0, DATA_BUFFER_0_offset(r5)
-00:0000006A 5122            	   177:    ld     r1, DATA_BUFFER_1_offset(r5)
-00:0000006C 5223            	   178:    ld     r2, DATA_BUFFER_2_offset(r5)
-00:0000006E 5325            	   179:    ld     r3, DATA_BUFFER_3_offset(r5)
-00:00000070 5926            	   180:    ld     r9, DATA_BUFFER_4_offset(r5)
-00:00000072 5A27            	   181:    ld     r10, DATA_BUFFER_5_offset(r5)
-00:00000074 5C30            	   182:    st     r12, GPU_COMMAND_offset(r5)    #set command register to 0
-00:00000076 5C34            	   183:    st     r12, GPU_SYNC_offset(r5)       #set sync register to 0
-00:00000078 F071            	   184:    bset   r0, FINAL_BIT
-00:0000007A F171            	   185:    bset   r1, FINAL_BIT
-00:0000007C F271            	   186:    bset   r2, FINAL_BIT
-00:0000007E F371            	   187:    bset   r3, FINAL_BIT
-00:00000080 F971            	   188:    bset   r9, FINAL_BIT
-00:00000082 FA71            	   189:    bset   r10, FINAL_BIT
-                            	   190: 
-00:00000084 5031            	   191:    st     r0, DATA_BUFFER_0_offset(r5)
-00:00000086 5132            	   192:    st     r1, DATA_BUFFER_1_offset(r5)
-00:00000088 5233            	   193:    st     r2, DATA_BUFFER_2_offset(r5)
-00:0000008A 5335            	   194:    st     r3, DATA_BUFFER_3_offset(r5)
-00:0000008C 5936            	   195:    st     r9, DATA_BUFFER_4_offset(r5)
-00:0000008E 5A37            	   196:    st     r10, DATA_BUFFER_5_offset(r5)
-                            	   197: 
-00:00000090 8240            	   198:    mov    r2, r8                        #set the default state of the control bits
-                            	   199: 
-                            	   200: wait_for_command_loop:
-00:00000092 5320            	   201:    ld     r3, GPU_COMMAND_offset(r5)
-00:00000094 036A            	   202:    cmp    r3, 0
-00:00000096 7E18            	   203:    beq    wait_for_command_loop
-00:00000098 F36C            	   204:    btst   r3, SIMPLE_SYNC_FLAG                   #bit signals upper 16 bits is a sync command
-00:0000009A 00906400        	   205:    beq    do_capture
-00:0000009E 3140            	   206:    mov    r1, r3
-00:000000A0 017B            	   207:    lsr    r1, 16
-                            	   208: 
-                            	   209:    #simple mode sync detection, enters with PSYNC_BIT set in r2
-00:000000A2 016A            	   210:    cmp    r1, 0
-00:000000A4 3918            	   211:    beq    edge_trail_neg
-00:000000A6 116A            	   212:    cmp    r1, 1
-00:000000A8 2718            	   213:    beq    edge_lead_neg
-00:000000AA 1273            	   214:    bclr   r2, PSYNC_BIT             #only +ve edge (inverted later)
-00:000000AC 216A            	   215:    cmp    r1, 2
-00:000000AE 3418            	   216:    beq    edge_trail_pos
-00:000000B0 316A            	   217:    cmp    r1, 3
-00:000000B2 2218            	   218:    beq    edge_lead_pos
-00:000000B4 416A            	   219:    cmp    r1, 4
-00:000000B6 0E18            	   220:    beq    edge_trail_both
-00:000000B8 516A            	   221:    cmp    r1, 5
-00:000000BA D718            	   222:    bne    wait_for_command
-                            	   223:    #if here then edge_lead_both
-                            	   224: 
-                            	   225: edge_lead_both:
-                            	   226:    EDGE_DETECT
+                            	    41: .equ HIGH_LATENCY_FLAG,    14
+                            	    42: .equ SIMPLE_SYNC_FLAG,     15
+                            	    43: .equ LEADING_SYNC_FLAG,    16
+                            	    44: .equ SYNC_ABORT_FLAG,      31
+                            	    45: 
+                            	    46: #macros
+                            	    47: 
+                            	    48: .macro LO_PSYNC_CAPTURE
+                            	    49: wait_psync_lo\@:
+                            	    50:    ld     r0, (r4)
+                            	    51:    btst   r0, PSYNC_BIT
+                            	    52:    bne    wait_psync_lo\@
+                            	    53:    btst   r0, MUX_BIT
+                            	    54:    and    r0, r6
+                            	    55:    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	    56:    sub    r3, 1
+                            	    57:    or     r0, r2           #merge bit state
+                            	    58: .endm
+                            	    59: 
+                            	    60: .macro HI_PSYNC_CAPTURE
+                            	    61: wait_psync_hi\@:
+                            	    62:    ld     r1, (r4)
+                            	    63:    btst   r1, PSYNC_BIT
+                            	    64:    beq    wait_psync_hi\@
+                            	    65:    btst   r1, MUX_BIT
+                            	    66:    and    r1, r6
+                            	    67:    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	    68:    lsl    r1, 16           #merge lo and hi samples
+                            	    69:    cmp    r3, 0
+                            	    70:    or     r0, r1
+                            	    71: .endm
+                            	    72: 
+                            	    73: 
+                            	    74: .macro OFW_LO_PSYNC_CAPTURE
+                            	    75: wait_psync_lo\@:
+                            	    76:    ld     r0, (r4)
+                            	    77:    btst   r0, PSYNC_BIT
+                            	    78:    bne    wait_psync_lo\@
+                            	    79:    ld     r0, (r4)
+                            	    80:    btst   r0, MUX_BIT
+                            	    81:    and    r0, r6
+                            	    82:    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	    83:    sub    r3, 1
+                            	    84:    or     r0, r2           #merge bit state
+                            	    85: .endm
+                            	    86: 
+                            	    87: .macro OFW_HI_PSYNC_CAPTURE
+                            	    88: wait_psync_hi\@:
+                            	    89:    ld     r1, (r4)
+                            	    90:    btst   r1, PSYNC_BIT
+                            	    91:    beq    wait_psync_hi\@
+                            	    92:    ld     r1, (r4)
+                            	    93:    btst   r1, MUX_BIT
+                            	    94:    and    r1, r6
+                            	    95:    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	    96:    lsl    r1, 16           #merge lo and hi samples
+                            	    97:    cmp    r3, 0
+                            	    98:    or     r0, r1
+                            	    99: .endm
+                            	   100: 
+                            	   101: 
+                            	   102: .macro HL_LO_PSYNC_CAPTURE
+                            	   103: wait_psync_lo\@:
+                            	   104:    ld     r0, (r4)
+                            	   105:    btst   r0, PSYNC_BIT
+                            	   106:    bne    wait_psync_lo\@
+                            	   107:    btst   r0, MUX_BIT
+                            	   108:    and    r0, r6
+                            	   109:    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	   110: 
+                            	   111: .endm
+                            	   112: 
+                            	   113: .macro HL_HI_PSYNC_CAPTURE
+                            	   114: wait_psync_hi\@:
+                            	   115:    ld     r1, (r4)
+                            	   116:    btst   r1, PSYNC_BIT
+                            	   117:    beq    wait_psync_hi\@
+                            	   118:    btst   r1, MUX_BIT
+                            	   119:    and    r1, r6
+                            	   120:    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	   121:    lsl    r1, 16           #merge lo and hi samples
+                            	   122:    or     r0, r1
+                            	   123: .endm
+                            	   124: 
+                            	   125: 
+                            	   126: .macro EDGE_DETECT
+                            	   127: waitPSE\@:
+                            	   128:    ld     r0, (r4)
+                            	   129:    eor    r0, r2
+                            	   130:    btst   r0, PSYNC_BIT
+                            	   131:    bne    waitPSE\@
+                            	   132:    eor    r0, r2       #restore r0 value
+                            	   133:    bchg   r2, PSYNC_BIT
+                            	   134: .endm
+                            	   135: 
+                            	   136: 
+                            	   137: # main code entry point
+00:00000000 0500            	   138:    di
+00:00000002 106A            	   139:    cmp    r0, 1
+00:00000004 8D18            	   140:    bne    not_gpio_read_benchmark
+00:00000006 02E8A0860100    	   141:    mov    r2, 100000
+00:0000000C 01E83400207E    	   142:    mov    r1, GPLEV0
+                            	   143: read_bench_loop:
+00:00000012 1308            	   144:    ld     r3, (r1)  #read gpio
+00:00000014 1266            	   145:    sub    r2, 1
+00:00000016 026A            	   146:    cmp    r2, 0
+00:00000018 FD18            	   147:    bne    read_bench_loop
+00:0000001A 0400            	   148:    ei
+00:0000001C 5A00            	   149:    rts
+                            	   150: 
+                            	   151: not_gpio_read_benchmark:
+00:0000001E 206A            	   152:    cmp    r0, 2
+00:00000020 8E18            	   153:    bne    not_mbox_write_benchmark
+00:00000022 02E8A0860100    	   154:    mov    r2, 100000
+00:00000028 01E8BC00007E    	   155:    mov    r1, GPU_DATA_BUFFER_5
+00:0000002E 0360            	   156:    mov    r3, 0
+                            	   157: write_bench_loop:
+00:00000030 1309            	   158:    st     r3, (r1)  #write to mbox
+00:00000032 1266            	   159:    sub    r2, 1
+00:00000034 026A            	   160:    cmp    r2, 0
+00:00000036 FD18            	   161:    bne    write_bench_loop
+00:00000038 0400            	   162:    ei
+00:0000003A 5A00            	   163:    rts
+                            	   164: 
+                            	   165: not_mbox_write_benchmark:
+00:0000003C 04E83400207E    	   166:    mov    r4, GPLEV0
+00:00000042 05E8A000007E    	   167:    mov    r5, GPU_COMMAND
+00:00000048 06E8FC3F0000    	   168:    mov    r6, VIDEO_MASK
+00:0000004E 07E8FF0F0000    	   169:    mov    r7, COMMAND_MASK
+00:00000054 08E801000200    	   170:    mov    r8, DEFAULT_BIT_STATE
+00:0000005A 0C60            	   171:    mov    r12, 0                       # remains at zero for rest of the code
+00:0000005C 5C31            	   172:    st     r12, DATA_BUFFER_0_offset(r5)
+00:0000005E 5C32            	   173:    st     r12, DATA_BUFFER_1_offset(r5)
+00:00000060 5C33            	   174:    st     r12, DATA_BUFFER_2_offset(r5)
+00:00000062 5C35            	   175:    st     r12, DATA_BUFFER_3_offset(r5)
+00:00000064 5C36            	   176:    st     r12, DATA_BUFFER_4_offset(r5)
+00:00000066 5C37            	   177:    st     r12, DATA_BUFFER_5_offset(r5)
+                            	   178: 
+                            	   179: wait_for_command:
+00:00000068 5021            	   180:    ld     r0, DATA_BUFFER_0_offset(r5)
+00:0000006A 5122            	   181:    ld     r1, DATA_BUFFER_1_offset(r5)
+00:0000006C 5223            	   182:    ld     r2, DATA_BUFFER_2_offset(r5)
+00:0000006E 5325            	   183:    ld     r3, DATA_BUFFER_3_offset(r5)
+00:00000070 5926            	   184:    ld     r9, DATA_BUFFER_4_offset(r5)
+00:00000072 5A27            	   185:    ld     r10, DATA_BUFFER_5_offset(r5)
+00:00000074 5C30            	   186:    st     r12, GPU_COMMAND_offset(r5)    #set command register to 0
+00:00000076 5C34            	   187:    st     r12, GPU_SYNC_offset(r5)       #set sync register to 0
+00:00000078 F071            	   188:    bset   r0, FINAL_BIT
+00:0000007A F171            	   189:    bset   r1, FINAL_BIT
+00:0000007C F271            	   190:    bset   r2, FINAL_BIT
+00:0000007E F371            	   191:    bset   r3, FINAL_BIT
+00:00000080 F971            	   192:    bset   r9, FINAL_BIT
+00:00000082 FA71            	   193:    bset   r10, FINAL_BIT
+                            	   194: 
+00:00000084 5031            	   195:    st     r0, DATA_BUFFER_0_offset(r5)
+00:00000086 5132            	   196:    st     r1, DATA_BUFFER_1_offset(r5)
+00:00000088 5233            	   197:    st     r2, DATA_BUFFER_2_offset(r5)
+00:0000008A 5335            	   198:    st     r3, DATA_BUFFER_3_offset(r5)
+00:0000008C 5936            	   199:    st     r9, DATA_BUFFER_4_offset(r5)
+00:0000008E 5A37            	   200:    st     r10, DATA_BUFFER_5_offset(r5)
+                            	   201: 
+00:00000090 8240            	   202:    mov    r2, r8                        #set the default state of the control bits
+                            	   203: 
+                            	   204: wait_for_command_loop:
+00:00000092 0100            	   205:    nop    #some idle time to reduce continuous polling of register
+00:00000094 5320            	   206:    ld     r3, GPU_COMMAND_offset(r5)
+00:00000096 0100            	   207:    nop
+00:00000098 036A            	   208:    cmp    r3, 0
+00:0000009A 0100            	   209:    nop
+00:0000009C 7B18            	   210:    beq    wait_for_command_loop
+00:0000009E F36D            	   211:    btst   r3, SYNC_ABORT_FLAG
+00:000000A0 E418            	   212:    bne    wait_for_command
+00:000000A2 F36C            	   213:    btst   r3, SIMPLE_SYNC_FLAG                   #bit signals upper 16 bits is a sync command
+00:000000A4 00906500        	   214:    beq    do_capture
+00:000000A8 3140            	   215:    mov    r1, r3
+00:000000AA 017B            	   216:    lsr    r1, 16
+                            	   217: 
+                            	   218:    #simple mode sync detection, enters with PSYNC_BIT set in r2
+00:000000AC 016A            	   219:    cmp    r1, 0
+00:000000AE 3918            	   220:    beq    edge_trail_neg
+00:000000B0 116A            	   221:    cmp    r1, 1
+00:000000B2 2718            	   222:    beq    edge_lead_neg
+00:000000B4 1273            	   223:    bclr   r2, PSYNC_BIT             #only +ve edge (inverted later)
+00:000000B6 216A            	   224:    cmp    r1, 2
+00:000000B8 3418            	   225:    beq    edge_trail_pos
+00:000000BA 316A            	   226:    cmp    r1, 3
+00:000000BC 2218            	   227:    beq    edge_lead_pos
+00:000000BE 416A            	   228:    cmp    r1, 4
+00:000000C0 0E18            	   229:    beq    edge_trail_both
+00:000000C2 516A            	   230:    cmp    r1, 5
+00:000000C4 D218            	   231:    bne    wait_for_command
+                            	   232:    #if here then edge_lead_both
+                            	   233: 
+                            	   234: edge_lead_both:
+                            	   235:    EDGE_DETECT
                             	     1M waitPSE1:
-00:000000BC 4008            	     2M    ld     r0, (r4)
-00:000000BE 2045            	     3M    eor    r0, r2
-00:000000C0 106D            	     4M    btst   r0, PSYNC_BIT
-00:000000C2 FD18            	     5M    bne    waitPSE1
-00:000000C4 2045            	     6M    eor    r0, r2       #restore r0 value
-00:000000C6 1275            	     7M    bchg   r2, PSYNC_BIT
-00:000000C8 706D            	   227:    btst   r0, SYNC_BIT
-00:000000CA F918            	   228:    bne    edge_lead_both
-00:000000CC 5834            	   229:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
-00:000000CE 009E4100        	   230:    b      done_simple_sync
-                            	   231: 
-                            	   232: edge_trail_both:
-                            	   233:    EDGE_DETECT
+00:000000C6 4008            	     2M    ld     r0, (r4)
+00:000000C8 2045            	     3M    eor    r0, r2
+00:000000CA 106D            	     4M    btst   r0, PSYNC_BIT
+00:000000CC FD18            	     5M    bne    waitPSE1
+00:000000CE 2045            	     6M    eor    r0, r2       #restore r0 value
+00:000000D0 1275            	     7M    bchg   r2, PSYNC_BIT
+00:000000D2 706D            	   236:    btst   r0, SYNC_BIT
+00:000000D4 F918            	   237:    bne    edge_lead_both
+00:000000D6 5834            	   238:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
+00:000000D8 009E4100        	   239:    b      done_simple_sync
+                            	   240: 
+                            	   241: edge_trail_both:
+                            	   242:    EDGE_DETECT
                             	     1M waitPSE2:
-00:000000D2 4008            	     2M    ld     r0, (r4)
-00:000000D4 2045            	     3M    eor    r0, r2
-00:000000D6 106D            	     4M    btst   r0, PSYNC_BIT
-00:000000D8 FD18            	     5M    bne    waitPSE2
-00:000000DA 2045            	     6M    eor    r0, r2       #restore r0 value
-00:000000DC 1275            	     7M    bchg   r2, PSYNC_BIT
-00:000000DE 706D            	   234:    btst   r0, SYNC_BIT
-00:000000E0 F918            	   235:    bne    edge_trail_both
-00:000000E2 5834            	   236:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
-                            	   237: edge_trail_both_hi:
-                            	   238:    EDGE_DETECT
-                            	     1M waitPSE3:
-00:000000E4 4008            	     2M    ld     r0, (r4)
-00:000000E6 2045            	     3M    eor    r0, r2
-00:000000E8 106D            	     4M    btst   r0, PSYNC_BIT
-00:000000EA FD18            	     5M    bne    waitPSE3
-00:000000EC 2045            	     6M    eor    r0, r2       #restore r0 value
-00:000000EE 1275            	     7M    bchg   r2, PSYNC_BIT
-00:000000F0 706D            	   239:    btst   r0, SYNC_BIT
-00:000000F2 7918            	   240:    beq    edge_trail_both_hi
-00:000000F4 2E1F            	   241:    b      done_simple_sync
-                            	   242: 
-                            	   243: edge_lead_neg:
-                            	   244: edge_lead_pos:
-                            	   245:    #incoming psync state controls edge
-                            	   246: wait_csync_lo2:
+00:000000DC 4008            	     2M    ld     r0, (r4)
+00:000000DE 2045            	     3M    eor    r0, r2
+00:000000E0 106D            	     4M    btst   r0, PSYNC_BIT
+00:000000E2 FD18            	     5M    bne    waitPSE2
+00:000000E4 2045            	     6M    eor    r0, r2       #restore r0 value
+00:000000E6 1275            	     7M    bchg   r2, PSYNC_BIT
+00:000000E8 706D            	   243:    btst   r0, SYNC_BIT
+00:000000EA F918            	   244:    bne    edge_trail_both
+00:000000EC 5834            	   245:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
+                            	   246: edge_trail_both_hi:
                             	   247:    EDGE_DETECT
+                            	     1M waitPSE3:
+00:000000EE 4008            	     2M    ld     r0, (r4)
+00:000000F0 2045            	     3M    eor    r0, r2
+00:000000F2 106D            	     4M    btst   r0, PSYNC_BIT
+00:000000F4 FD18            	     5M    bne    waitPSE3
+00:000000F6 2045            	     6M    eor    r0, r2       #restore r0 value
+00:000000F8 1275            	     7M    bchg   r2, PSYNC_BIT
+00:000000FA 706D            	   248:    btst   r0, SYNC_BIT
+00:000000FC 7918            	   249:    beq    edge_trail_both_hi
+00:000000FE 2E1F            	   250:    b      done_simple_sync
+                            	   251: 
+                            	   252: edge_lead_neg:
+                            	   253: edge_lead_pos:
+                            	   254:    #incoming psync state controls edge
+                            	   255: wait_csync_lo2:
+                            	   256:    EDGE_DETECT
                             	     1M waitPSE4:
-00:000000F6 4008            	     2M    ld     r0, (r4)
-00:000000F8 2045            	     3M    eor    r0, r2
-00:000000FA 106D            	     4M    btst   r0, PSYNC_BIT
-00:000000FC FD18            	     5M    bne    waitPSE4
-00:000000FE 2045            	     6M    eor    r0, r2       #restore r0 value
-00:00000100 1275            	     7M    bchg   r2, PSYNC_BIT
-                            	   248:    EDGE_DETECT
+00:00000100 4008            	     2M    ld     r0, (r4)
+00:00000102 2045            	     3M    eor    r0, r2
+00:00000104 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000106 FD18            	     5M    bne    waitPSE4
+00:00000108 2045            	     6M    eor    r0, r2       #restore r0 value
+00:0000010A 1275            	     7M    bchg   r2, PSYNC_BIT
+                            	   257:    EDGE_DETECT
                             	     1M waitPSE5:
-00:00000102 4008            	     2M    ld     r0, (r4)
-00:00000104 2045            	     3M    eor    r0, r2
-00:00000106 106D            	     4M    btst   r0, PSYNC_BIT
-00:00000108 FD18            	     5M    bne    waitPSE5
-00:0000010A 2045            	     6M    eor    r0, r2       #restore r0 value
-00:0000010C 1275            	     7M    bchg   r2, PSYNC_BIT
-00:0000010E 706D            	   249:    btst   r0, SYNC_BIT
-00:00000110 F318            	   250:    bne    wait_csync_lo2
-00:00000112 5834            	   251:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
-00:00000114 1E1F            	   252:    b      done_simple_sync
-                            	   253: 
-                            	   254: edge_trail_neg:
-                            	   255: edge_trail_pos:
-                            	   256:    #incoming psync state controls edge *** this one used by amiga
-                            	   257: wait_csync_lo:
-                            	   258:    EDGE_DETECT
+00:0000010C 4008            	     2M    ld     r0, (r4)
+00:0000010E 2045            	     3M    eor    r0, r2
+00:00000110 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000112 FD18            	     5M    bne    waitPSE5
+00:00000114 2045            	     6M    eor    r0, r2       #restore r0 value
+00:00000116 1275            	     7M    bchg   r2, PSYNC_BIT
+00:00000118 706D            	   258:    btst   r0, SYNC_BIT
+00:0000011A F318            	   259:    bne    wait_csync_lo2
+00:0000011C 5834            	   260:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
+00:0000011E 1E1F            	   261:    b      done_simple_sync
+                            	   262: 
+                            	   263: edge_trail_neg:
+                            	   264: edge_trail_pos:
+                            	   265:    #incoming psync state controls edge *** this one used by amiga
+                            	   266: wait_csync_lo:
+                            	   267:    EDGE_DETECT
                             	     1M waitPSE6:
-00:00000116 4008            	     2M    ld     r0, (r4)
-00:00000118 2045            	     3M    eor    r0, r2
-00:0000011A 106D            	     4M    btst   r0, PSYNC_BIT
-00:0000011C FD18            	     5M    bne    waitPSE6
-00:0000011E 2045            	     6M    eor    r0, r2       #restore r0 value
-00:00000120 1275            	     7M    bchg   r2, PSYNC_BIT
-                            	   259:    EDGE_DETECT
+00:00000120 4008            	     2M    ld     r0, (r4)
+00:00000122 2045            	     3M    eor    r0, r2
+00:00000124 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000126 FD18            	     5M    bne    waitPSE6
+00:00000128 2045            	     6M    eor    r0, r2       #restore r0 value
+00:0000012A 1275            	     7M    bchg   r2, PSYNC_BIT
+                            	   268:    EDGE_DETECT
                             	     1M waitPSE7:
-00:00000122 4008            	     2M    ld     r0, (r4)
-00:00000124 2045            	     3M    eor    r0, r2
-00:00000126 106D            	     4M    btst   r0, PSYNC_BIT
-00:00000128 FD18            	     5M    bne    waitPSE7
-00:0000012A 2045            	     6M    eor    r0, r2       #restore r0 value
-00:0000012C 1275            	     7M    bchg   r2, PSYNC_BIT
-00:0000012E 706D            	   260:    btst   r0, SYNC_BIT
-00:00000130 F318            	   261:    bne    wait_csync_lo
-00:00000132 5834            	   262:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
-                            	   263: wait_csync_hi:
-                            	   264:    EDGE_DETECT
+00:0000012C 4008            	     2M    ld     r0, (r4)
+00:0000012E 2045            	     3M    eor    r0, r2
+00:00000130 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000132 FD18            	     5M    bne    waitPSE7
+00:00000134 2045            	     6M    eor    r0, r2       #restore r0 value
+00:00000136 1275            	     7M    bchg   r2, PSYNC_BIT
+00:00000138 706D            	   269:    btst   r0, SYNC_BIT
+00:0000013A F318            	   270:    bne    wait_csync_lo
+00:0000013C 5834            	   271:    st     r8, GPU_SYNC_offset(r5)   #lsbit flags sync detected
+                            	   272: wait_csync_hi:
+                            	   273:    EDGE_DETECT
                             	     1M waitPSE8:
-00:00000134 4008            	     2M    ld     r0, (r4)
-00:00000136 2045            	     3M    eor    r0, r2
-00:00000138 106D            	     4M    btst   r0, PSYNC_BIT
-00:0000013A FD18            	     5M    bne    waitPSE8
-00:0000013C 2045            	     6M    eor    r0, r2       #restore r0 value
-00:0000013E 1275            	     7M    bchg   r2, PSYNC_BIT
-                            	   265:    EDGE_DETECT
+00:0000013E 4008            	     2M    ld     r0, (r4)
+00:00000140 2045            	     3M    eor    r0, r2
+00:00000142 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000144 FD18            	     5M    bne    waitPSE8
+00:00000146 2045            	     6M    eor    r0, r2       #restore r0 value
+00:00000148 1275            	     7M    bchg   r2, PSYNC_BIT
+                            	   274:    EDGE_DETECT
                             	     1M waitPSE9:
-00:00000140 4008            	     2M    ld     r0, (r4)
-00:00000142 2045            	     3M    eor    r0, r2
-00:00000144 106D            	     4M    btst   r0, PSYNC_BIT
-00:00000146 FD18            	     5M    bne    waitPSE9
-00:00000148 2045            	     6M    eor    r0, r2       #restore r0 value
-00:0000014A 1275            	     7M    bchg   r2, PSYNC_BIT
-00:0000014C 706D            	   266:    btst   r0, SYNC_BIT
-00:0000014E 7318            	   267:    beq    wait_csync_hi
-                            	   268: 
-                            	   269: done_simple_sync:
-00:00000150 126D            	   270:    btst   r2, PSYNC_BIT
-00:00000152 8718            	   271:    bne    no_compensate_psync
-                            	   272:    EDGE_DETECT           #have to compensate because capture hard coded to always start on same edge
+00:0000014A 4008            	     2M    ld     r0, (r4)
+00:0000014C 2045            	     3M    eor    r0, r2
+00:0000014E 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000150 FD18            	     5M    bne    waitPSE9
+00:00000152 2045            	     6M    eor    r0, r2       #restore r0 value
+00:00000154 1275            	     7M    bchg   r2, PSYNC_BIT
+00:00000156 706D            	   275:    btst   r0, SYNC_BIT
+00:00000158 7318            	   276:    beq    wait_csync_hi
+                            	   277: 
+                            	   278: done_simple_sync:
+00:0000015A 126D            	   279:    btst   r2, PSYNC_BIT
+00:0000015C 8718            	   280:    bne    no_compensate_psync
+                            	   281:    EDGE_DETECT           #have to compensate because capture hard coded to always start on same edge
                             	     1M waitPSE10:
-00:00000154 4008            	     2M    ld     r0, (r4)
-00:00000156 2045            	     3M    eor    r0, r2
-00:00000158 106D            	     4M    btst   r0, PSYNC_BIT
-00:0000015A FD18            	     5M    bne    waitPSE10
-00:0000015C 2045            	     6M    eor    r0, r2       #restore r0 value
-00:0000015E 1275            	     7M    bchg   r2, PSYNC_BIT
-                            	   273: no_compensate_psync:
-                            	   274: 
-00:00000160 8240            	   275:    mov    r2, r8         #set the default state of the control bits
-                            	   276: 
-                            	   277: do_capture:
-00:00000162 E36C            	   278:    btst   r3, HIGH_LATENCY_FLAG         #bit signals high latency capture, only suitable for 9/12bpp modes
-00:00000164 00912501        	   279:    bne    hl_capture
-                            	   280: 
-00:00000168 D36C            	   281:    btst   r3, OLD_FIRMWARE_FLAG         #bit signals old firmware capture, requires double reads as psync not pipelined
-00:0000016A 00918C00        	   282:    bne    ofw_capture
-                            	   283: 
-00:0000016E 7347            	   284:    and    r3, r7         #mask off any command bits (max capture is 4095 psync cycles)
-00:00000170 1362            	   285:    add    r3, 1          #round up to multiple of 2
-00:00000172 137A            	   286:    lsr    r3, 1          #divide by 2 as capturing 2 samples per cycle
-                            	   287: 
-                            	   288: capture_loop:
-                            	   289:    LO_PSYNC_CAPTURE
+00:0000015E 4008            	     2M    ld     r0, (r4)
+00:00000160 2045            	     3M    eor    r0, r2
+00:00000162 106D            	     4M    btst   r0, PSYNC_BIT
+00:00000164 FD18            	     5M    bne    waitPSE10
+00:00000166 2045            	     6M    eor    r0, r2       #restore r0 value
+00:00000168 1275            	     7M    bchg   r2, PSYNC_BIT
+                            	   282: no_compensate_psync:
+00:0000016A 8240            	   283:    mov    r2, r8         #set the default state of the control bits
+00:0000016C 121F            	   284:    b      capture_rest
+                            	   285: 
+                            	   286: do_capture:
+00:0000016E D36C            	   287:    btst   r3, OLD_FIRMWARE_FLAG         #bit signals old firmware capture, requires double reads as psync not pipelined
+00:00000170 00919D00        	   288:    bne    ofw_capture
+                            	   289: 
+                            	   290: wait_csync_lo_cpld:
+00:00000174 5020            	   291:    ld     r0, GPU_COMMAND_offset(r5)
+00:00000176 F06D            	   292:    btst   r0, SYNC_ABORT_FLAG
+00:00000178 8C18            	   293:    bne    capture_rest
+00:0000017A 4008            	   294:    ld     r0, (r4)
+00:0000017C 706D            	   295:    btst   r0, SYNC_BIT
+00:0000017E FB18            	   296:    bne    wait_csync_lo_cpld
+                            	   297: 
+00:00000180 036D            	   298:    btst   r3, LEADING_SYNC_FLAG
+00:00000182 8718            	   299:    bne    capture_rest
+                            	   300: 
+                            	   301: wait_csync_hi_cpld:
+00:00000184 5020            	   302:    ld     r0, GPU_COMMAND_offset(r5)
+00:00000186 F06D            	   303:    btst   r0, SYNC_ABORT_FLAG
+00:00000188 8418            	   304:    bne    capture_rest
+00:0000018A 4008            	   305:    ld     r0, (r4)
+00:0000018C 706D            	   306:    btst   r0, SYNC_BIT
+00:0000018E 7B18            	   307:    beq    wait_csync_hi_cpld
+                            	   308: 
+                            	   309: capture_rest:
+00:00000190 E36C            	   310:    btst   r3, HIGH_LATENCY_FLAG         #bit signals high latency capture, only suitable for 9/12bpp modes
+00:00000192 00914801        	   311:    bne    hl_capture
+                            	   312: 
+00:00000196 7347            	   313:    and    r3, r7         #mask off any command bits (max capture is 4095 psync cycles)
+00:00000198 1362            	   314:    add    r3, 1          #round up to multiple of 2
+00:0000019A 137A            	   315:    lsr    r3, 1          #divide by 2 as capturing 2 samples per cycle
+                            	   316: 
+                            	   317: capture_loop:
+                            	   318:    LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo11:
-00:00000174 4008            	     2M    ld     r0, (r4)
-00:00000176 106D            	     3M    btst   r0, PSYNC_BIT
-00:00000178 FE18            	     4M    bne    wait_psync_lo11
-00:0000017A 806D            	     5M    btst   r0, MUX_BIT
-00:0000017C 6047            	     6M    and    r0, r6
-00:0000017E 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000182 1366            	     8M    sub    r3, 1
-00:00000184 204D            	     9M    or     r0, r2           #merge bit state
-                            	   290:    HI_PSYNC_CAPTURE
+00:0000019C 4008            	     2M    ld     r0, (r4)
+00:0000019E 106D            	     3M    btst   r0, PSYNC_BIT
+00:000001A0 FE18            	     4M    bne    wait_psync_lo11
+00:000001A2 806D            	     5M    btst   r0, MUX_BIT
+00:000001A4 6047            	     6M    and    r0, r6
+00:000001A6 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000001AA 1366            	     8M    sub    r3, 1
+00:000001AC 204D            	     9M    or     r0, r2           #merge bit state
+                            	   319:    HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi12:
-00:00000186 4108            	     2M    ld     r1, (r4)
-00:00000188 116D            	     3M    btst   r1, PSYNC_BIT
-00:0000018A 7E18            	     4M    beq    wait_psync_hi12
-00:0000018C 816D            	     5M    btst   r1, MUX_BIT
-00:0000018E 6147            	     6M    and    r1, r6
-00:00000190 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000194 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:00000196 036A            	     9M    cmp    r3, 0
-00:00000198 104D            	    10M    or     r0, r1
-                            	   291: 
-00:0000019A 5031            	   292:    st     r0, DATA_BUFFER_0_offset(r5)
-00:0000019C 7F9066FF        	   293:    beq    wait_for_command
-                            	   294: 
-                            	   295:    LO_PSYNC_CAPTURE
+00:000001AE 4108            	     2M    ld     r1, (r4)
+00:000001B0 116D            	     3M    btst   r1, PSYNC_BIT
+00:000001B2 7E18            	     4M    beq    wait_psync_hi12
+00:000001B4 816D            	     5M    btst   r1, MUX_BIT
+00:000001B6 6147            	     6M    and    r1, r6
+00:000001B8 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000001BC 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:000001BE 036A            	     9M    cmp    r3, 0
+00:000001C0 104D            	    10M    or     r0, r1
+                            	   320: 
+00:000001C2 5031            	   321:    st     r0, DATA_BUFFER_0_offset(r5)
+00:000001C4 7F9052FF        	   322:    beq    wait_for_command
+                            	   323: 
+                            	   324:    LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo13:
-00:000001A0 4008            	     2M    ld     r0, (r4)
-00:000001A2 106D            	     3M    btst   r0, PSYNC_BIT
-00:000001A4 FE18            	     4M    bne    wait_psync_lo13
-00:000001A6 806D            	     5M    btst   r0, MUX_BIT
-00:000001A8 6047            	     6M    and    r0, r6
-00:000001AA 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000001AE 1366            	     8M    sub    r3, 1
-00:000001B0 204D            	     9M    or     r0, r2           #merge bit state
-                            	   296:    HI_PSYNC_CAPTURE
+00:000001C8 4008            	     2M    ld     r0, (r4)
+00:000001CA 106D            	     3M    btst   r0, PSYNC_BIT
+00:000001CC FE18            	     4M    bne    wait_psync_lo13
+00:000001CE 806D            	     5M    btst   r0, MUX_BIT
+00:000001D0 6047            	     6M    and    r0, r6
+00:000001D2 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000001D6 1366            	     8M    sub    r3, 1
+00:000001D8 204D            	     9M    or     r0, r2           #merge bit state
+                            	   325:    HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi14:
-00:000001B2 4108            	     2M    ld     r1, (r4)
-00:000001B4 116D            	     3M    btst   r1, PSYNC_BIT
-00:000001B6 7E18            	     4M    beq    wait_psync_hi14
-00:000001B8 816D            	     5M    btst   r1, MUX_BIT
-00:000001BA 6147            	     6M    and    r1, r6
-00:000001BC 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000001C0 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:000001C2 036A            	     9M    cmp    r3, 0
-00:000001C4 104D            	    10M    or     r0, r1
-                            	   297: 
-00:000001C6 5032            	   298:    st     r0, DATA_BUFFER_1_offset(r5)
-00:000001C8 7F9050FF        	   299:    beq    wait_for_command
-                            	   300: 
-                            	   301:    LO_PSYNC_CAPTURE
+00:000001DA 4108            	     2M    ld     r1, (r4)
+00:000001DC 116D            	     3M    btst   r1, PSYNC_BIT
+00:000001DE 7E18            	     4M    beq    wait_psync_hi14
+00:000001E0 816D            	     5M    btst   r1, MUX_BIT
+00:000001E2 6147            	     6M    and    r1, r6
+00:000001E4 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000001E8 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:000001EA 036A            	     9M    cmp    r3, 0
+00:000001EC 104D            	    10M    or     r0, r1
+                            	   326: 
+00:000001EE 5032            	   327:    st     r0, DATA_BUFFER_1_offset(r5)
+00:000001F0 7F903CFF        	   328:    beq    wait_for_command
+                            	   329: 
+                            	   330:    LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo15:
-00:000001CC 4008            	     2M    ld     r0, (r4)
-00:000001CE 106D            	     3M    btst   r0, PSYNC_BIT
-00:000001D0 FE18            	     4M    bne    wait_psync_lo15
-00:000001D2 806D            	     5M    btst   r0, MUX_BIT
-00:000001D4 6047            	     6M    and    r0, r6
-00:000001D6 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000001DA 1366            	     8M    sub    r3, 1
-00:000001DC 204D            	     9M    or     r0, r2           #merge bit state
-                            	   302:    HI_PSYNC_CAPTURE
+00:000001F4 4008            	     2M    ld     r0, (r4)
+00:000001F6 106D            	     3M    btst   r0, PSYNC_BIT
+00:000001F8 FE18            	     4M    bne    wait_psync_lo15
+00:000001FA 806D            	     5M    btst   r0, MUX_BIT
+00:000001FC 6047            	     6M    and    r0, r6
+00:000001FE 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000202 1366            	     8M    sub    r3, 1
+00:00000204 204D            	     9M    or     r0, r2           #merge bit state
+                            	   331:    HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi16:
-00:000001DE 4108            	     2M    ld     r1, (r4)
-00:000001E0 116D            	     3M    btst   r1, PSYNC_BIT
-00:000001E2 7E18            	     4M    beq    wait_psync_hi16
-00:000001E4 816D            	     5M    btst   r1, MUX_BIT
-00:000001E6 6147            	     6M    and    r1, r6
-00:000001E8 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000001EC 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:000001EE 036A            	     9M    cmp    r3, 0
-00:000001F0 104D            	    10M    or     r0, r1
-                            	   303: 
-00:000001F2 5033            	   304:    st     r0, DATA_BUFFER_2_offset(r5)
-00:000001F4 7F903AFF        	   305:    beq    wait_for_command
-                            	   306: 
-                            	   307:    LO_PSYNC_CAPTURE
+00:00000206 4108            	     2M    ld     r1, (r4)
+00:00000208 116D            	     3M    btst   r1, PSYNC_BIT
+00:0000020A 7E18            	     4M    beq    wait_psync_hi16
+00:0000020C 816D            	     5M    btst   r1, MUX_BIT
+00:0000020E 6147            	     6M    and    r1, r6
+00:00000210 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000214 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:00000216 036A            	     9M    cmp    r3, 0
+00:00000218 104D            	    10M    or     r0, r1
+                            	   332: 
+00:0000021A 5033            	   333:    st     r0, DATA_BUFFER_2_offset(r5)
+00:0000021C 7F9026FF        	   334:    beq    wait_for_command
+                            	   335: 
+                            	   336:    LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo17:
-00:000001F8 4008            	     2M    ld     r0, (r4)
-00:000001FA 106D            	     3M    btst   r0, PSYNC_BIT
-00:000001FC FE18            	     4M    bne    wait_psync_lo17
-00:000001FE 806D            	     5M    btst   r0, MUX_BIT
-00:00000200 6047            	     6M    and    r0, r6
-00:00000202 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000206 1366            	     8M    sub    r3, 1
-00:00000208 204D            	     9M    or     r0, r2           #merge bit state
-                            	   308:    HI_PSYNC_CAPTURE
+00:00000220 4008            	     2M    ld     r0, (r4)
+00:00000222 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000224 FE18            	     4M    bne    wait_psync_lo17
+00:00000226 806D            	     5M    btst   r0, MUX_BIT
+00:00000228 6047            	     6M    and    r0, r6
+00:0000022A 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000022E 1366            	     8M    sub    r3, 1
+00:00000230 204D            	     9M    or     r0, r2           #merge bit state
+                            	   337:    HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi18:
-00:0000020A 4108            	     2M    ld     r1, (r4)
-00:0000020C 116D            	     3M    btst   r1, PSYNC_BIT
-00:0000020E 7E18            	     4M    beq    wait_psync_hi18
-00:00000210 816D            	     5M    btst   r1, MUX_BIT
-00:00000212 6147            	     6M    and    r1, r6
-00:00000214 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000218 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:0000021A 036A            	     9M    cmp    r3, 0
-00:0000021C 104D            	    10M    or     r0, r1
-                            	   309: 
-00:0000021E 5035            	   310:    st     r0, DATA_BUFFER_3_offset(r5)
-00:00000220 7F9024FF        	   311:    beq    wait_for_command
-                            	   312: 
-                            	   313:    LO_PSYNC_CAPTURE
+00:00000232 4108            	     2M    ld     r1, (r4)
+00:00000234 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000236 7E18            	     4M    beq    wait_psync_hi18
+00:00000238 816D            	     5M    btst   r1, MUX_BIT
+00:0000023A 6147            	     6M    and    r1, r6
+00:0000023C 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000240 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:00000242 036A            	     9M    cmp    r3, 0
+00:00000244 104D            	    10M    or     r0, r1
+                            	   338: 
+00:00000246 5035            	   339:    st     r0, DATA_BUFFER_3_offset(r5)
+00:00000248 7F9010FF        	   340:    beq    wait_for_command
+                            	   341: 
+                            	   342:    LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo19:
-00:00000224 4008            	     2M    ld     r0, (r4)
-00:00000226 106D            	     3M    btst   r0, PSYNC_BIT
-00:00000228 FE18            	     4M    bne    wait_psync_lo19
-00:0000022A 806D            	     5M    btst   r0, MUX_BIT
-00:0000022C 6047            	     6M    and    r0, r6
-00:0000022E 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000232 1366            	     8M    sub    r3, 1
-00:00000234 204D            	     9M    or     r0, r2           #merge bit state
-                            	   314:    HI_PSYNC_CAPTURE
+00:0000024C 4008            	     2M    ld     r0, (r4)
+00:0000024E 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000250 FE18            	     4M    bne    wait_psync_lo19
+00:00000252 806D            	     5M    btst   r0, MUX_BIT
+00:00000254 6047            	     6M    and    r0, r6
+00:00000256 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000025A 1366            	     8M    sub    r3, 1
+00:0000025C 204D            	     9M    or     r0, r2           #merge bit state
+                            	   343:    HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi20:
-00:00000236 4108            	     2M    ld     r1, (r4)
-00:00000238 116D            	     3M    btst   r1, PSYNC_BIT
-00:0000023A 7E18            	     4M    beq    wait_psync_hi20
-00:0000023C 816D            	     5M    btst   r1, MUX_BIT
-00:0000023E 6147            	     6M    and    r1, r6
-00:00000240 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000244 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:00000246 036A            	     9M    cmp    r3, 0
-00:00000248 104D            	    10M    or     r0, r1
-                            	   315: 
-00:0000024A 5036            	   316:    st     r0, DATA_BUFFER_4_offset(r5)
-00:0000024C 7F900EFF        	   317:    beq    wait_for_command
-                            	   318: 
-                            	   319:    LO_PSYNC_CAPTURE
+00:0000025E 4108            	     2M    ld     r1, (r4)
+00:00000260 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000262 7E18            	     4M    beq    wait_psync_hi20
+00:00000264 816D            	     5M    btst   r1, MUX_BIT
+00:00000266 6147            	     6M    and    r1, r6
+00:00000268 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000026C 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:0000026E 036A            	     9M    cmp    r3, 0
+00:00000270 104D            	    10M    or     r0, r1
+                            	   344: 
+00:00000272 5036            	   345:    st     r0, DATA_BUFFER_4_offset(r5)
+00:00000274 7F90FAFE        	   346:    beq    wait_for_command
+                            	   347: 
+                            	   348:    LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo21:
-00:00000250 4008            	     2M    ld     r0, (r4)
-00:00000252 106D            	     3M    btst   r0, PSYNC_BIT
-00:00000254 FE18            	     4M    bne    wait_psync_lo21
-00:00000256 806D            	     5M    btst   r0, MUX_BIT
-00:00000258 6047            	     6M    and    r0, r6
-00:0000025A 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000025E 1366            	     8M    sub    r3, 1
-00:00000260 204D            	     9M    or     r0, r2           #merge bit state
-00:00000262 1275            	   320:    bchg   r2, PSYNC_BIT        #invert the software psync bit every 12 samples / 6 words
-                            	   321:    HI_PSYNC_CAPTURE
+00:00000278 4008            	     2M    ld     r0, (r4)
+00:0000027A 106D            	     3M    btst   r0, PSYNC_BIT
+00:0000027C FE18            	     4M    bne    wait_psync_lo21
+00:0000027E 806D            	     5M    btst   r0, MUX_BIT
+00:00000280 6047            	     6M    and    r0, r6
+00:00000282 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000286 1366            	     8M    sub    r3, 1
+00:00000288 204D            	     9M    or     r0, r2           #merge bit state
+00:0000028A 1275            	   349:    bchg   r2, PSYNC_BIT        #invert the software psync bit every 12 samples / 6 words
+                            	   350:    HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi22:
-00:00000264 4108            	     2M    ld     r1, (r4)
-00:00000266 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000268 7E18            	     4M    beq    wait_psync_hi22
-00:0000026A 816D            	     5M    btst   r1, MUX_BIT
-00:0000026C 6147            	     6M    and    r1, r6
-00:0000026E 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000272 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:00000274 036A            	     9M    cmp    r3, 0
-00:00000276 104D            	    10M    or     r0, r1
-                            	   322: 
-00:00000278 5037            	   323:    st     r0, DATA_BUFFER_5_offset(r5)
-00:0000027A 7F90F7FE        	   324:    beq    wait_for_command
-                            	   325: 
-00:0000027E 7F9E7BFF        	   326:    b      capture_loop
-                            	   327: 
-                            	   328: ofw_capture:
-00:00000282 7347            	   329:    and    r3, r7         #mask off any command bits (max capture is 4095 psync cycles)
-00:00000284 1362            	   330:    add    r3, 1          #round up to multiple of 2
-00:00000286 137A            	   331:    lsr    r3, 1          #divide by 2 as capturing 2 samples per cycle
-                            	   332: 
-                            	   333: old_firmware_capture_loop:
-                            	   334:    OFW_LO_PSYNC_CAPTURE
+00:0000028C 4108            	     2M    ld     r1, (r4)
+00:0000028E 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000290 7E18            	     4M    beq    wait_psync_hi22
+00:00000292 816D            	     5M    btst   r1, MUX_BIT
+00:00000294 6147            	     6M    and    r1, r6
+00:00000296 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000029A 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:0000029C 036A            	     9M    cmp    r3, 0
+00:0000029E 104D            	    10M    or     r0, r1
+                            	   351: 
+00:000002A0 5037            	   352:    st     r0, DATA_BUFFER_5_offset(r5)
+00:000002A2 7F90E3FE        	   353:    beq    wait_for_command
+                            	   354: 
+00:000002A6 7F9E7BFF        	   355:    b      capture_loop
+                            	   356: 
+                            	   357: ofw_capture:
+                            	   358: ofw_wait_csync_lo_cpld:
+00:000002AA 5020            	   359:    ld     r0, GPU_COMMAND_offset(r5)
+00:000002AC F06D            	   360:    btst   r0, SYNC_ABORT_FLAG
+00:000002AE A418            	   361:    bne    ofw_capture_rest
+00:000002B0 4008            	   362:    ld     r0, (r4)
+00:000002B2 706D            	   363:    btst   r0, SYNC_BIT
+00:000002B4 FB18            	   364:    bne    ofw_wait_csync_lo_cpld
+00:000002B6 4008            	   365:    ld     r0, (r4)
+00:000002B8 706D            	   366:    btst   r0, SYNC_BIT
+00:000002BA F818            	   367:    bne    ofw_wait_csync_lo_cpld
+00:000002BC 4008            	   368:    ld     r0, (r4)
+00:000002BE 706D            	   369:    btst   r0, SYNC_BIT
+00:000002C0 F518            	   370:    bne    ofw_wait_csync_lo_cpld
+00:000002C2 4008            	   371:    ld     r0, (r4)
+00:000002C4 706D            	   372:    btst   r0, SYNC_BIT
+00:000002C6 F218            	   373:    bne    ofw_wait_csync_lo_cpld
+00:000002C8 4008            	   374:    ld     r0, (r4)
+00:000002CA 706D            	   375:    btst   r0, SYNC_BIT
+00:000002CC EF18            	   376:    bne    ofw_wait_csync_lo_cpld
+                            	   377: 
+00:000002CE 036D            	   378:    btst   r3, LEADING_SYNC_FLAG
+00:000002D0 9318            	   379:    bne    ofw_capture_rest
+                            	   380: 
+                            	   381: ofw_wait_csync_hi_cpld:
+00:000002D2 5020            	   382:    ld     r0, GPU_COMMAND_offset(r5)
+00:000002D4 F06D            	   383:    btst   r0, SYNC_ABORT_FLAG
+00:000002D6 9018            	   384:    bne    ofw_capture_rest
+00:000002D8 4008            	   385:    ld     r0, (r4)
+00:000002DA 706D            	   386:    btst   r0, SYNC_BIT
+00:000002DC 7B18            	   387:    beq    ofw_wait_csync_hi_cpld
+00:000002DE 4008            	   388:    ld     r0, (r4)
+00:000002E0 706D            	   389:    btst   r0, SYNC_BIT
+00:000002E2 7818            	   390:    beq    ofw_wait_csync_hi_cpld
+00:000002E4 4008            	   391:    ld     r0, (r4)
+00:000002E6 706D            	   392:    btst   r0, SYNC_BIT
+00:000002E8 7518            	   393:    beq    ofw_wait_csync_hi_cpld
+00:000002EA 4008            	   394:    ld     r0, (r4)
+00:000002EC 706D            	   395:    btst   r0, SYNC_BIT
+00:000002EE 7218            	   396:    beq    ofw_wait_csync_hi_cpld
+00:000002F0 4008            	   397:    ld     r0, (r4)
+00:000002F2 706D            	   398:    btst   r0, SYNC_BIT
+00:000002F4 6F18            	   399:    beq    ofw_wait_csync_hi_cpld
+                            	   400: 
+                            	   401: ofw_capture_rest:
+00:000002F6 7347            	   402:    and    r3, r7         #mask off any command bits (max capture is 4095 psync cycles)
+00:000002F8 1362            	   403:    add    r3, 1          #round up to multiple of 2
+00:000002FA 137A            	   404:    lsr    r3, 1          #divide by 2 as capturing 2 samples per cycle
+                            	   405: 
+                            	   406: old_firmware_capture_loop:
+                            	   407:    OFW_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo23:
-00:00000288 4008            	     2M    ld     r0, (r4)
-00:0000028A 106D            	     3M    btst   r0, PSYNC_BIT
-00:0000028C FE18            	     4M    bne    wait_psync_lo23
-00:0000028E 4008            	     5M    ld     r0, (r4)
-00:00000290 806D            	     6M    btst   r0, MUX_BIT
-00:00000292 6047            	     7M    and    r0, r6
-00:00000294 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000298 1366            	     9M    sub    r3, 1
-00:0000029A 204D            	    10M    or     r0, r2           #merge bit state
-                            	   335:    OFW_HI_PSYNC_CAPTURE
+00:000002FC 4008            	     2M    ld     r0, (r4)
+00:000002FE 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000300 FE18            	     4M    bne    wait_psync_lo23
+00:00000302 4008            	     5M    ld     r0, (r4)
+00:00000304 806D            	     6M    btst   r0, MUX_BIT
+00:00000306 6047            	     7M    and    r0, r6
+00:00000308 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000030C 1366            	     9M    sub    r3, 1
+00:0000030E 204D            	    10M    or     r0, r2           #merge bit state
+                            	   408:    OFW_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi24:
-00:0000029C 4108            	     2M    ld     r1, (r4)
-00:0000029E 116D            	     3M    btst   r1, PSYNC_BIT
-00:000002A0 7E18            	     4M    beq    wait_psync_hi24
-00:000002A2 4108            	     5M    ld     r1, (r4)
-00:000002A4 816D            	     6M    btst   r1, MUX_BIT
-00:000002A6 6147            	     7M    and    r1, r6
-00:000002A8 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000002AC 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
-00:000002AE 036A            	    10M    cmp    r3, 0
-00:000002B0 104D            	    11M    or     r0, r1
-                            	   336: 
-00:000002B2 5031            	   337:    st     r0, DATA_BUFFER_0_offset(r5)
-00:000002B4 7F90DAFE        	   338:    beq    wait_for_command
-                            	   339: 
-                            	   340:    OFW_LO_PSYNC_CAPTURE
+00:00000310 4108            	     2M    ld     r1, (r4)
+00:00000312 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000314 7E18            	     4M    beq    wait_psync_hi24
+00:00000316 4108            	     5M    ld     r1, (r4)
+00:00000318 816D            	     6M    btst   r1, MUX_BIT
+00:0000031A 6147            	     7M    and    r1, r6
+00:0000031C 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000320 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
+00:00000322 036A            	    10M    cmp    r3, 0
+00:00000324 104D            	    11M    or     r0, r1
+                            	   409: 
+00:00000326 5031            	   410:    st     r0, DATA_BUFFER_0_offset(r5)
+00:00000328 7F90A0FE        	   411:    beq    wait_for_command
+                            	   412: 
+                            	   413:    OFW_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo25:
-00:000002B8 4008            	     2M    ld     r0, (r4)
-00:000002BA 106D            	     3M    btst   r0, PSYNC_BIT
-00:000002BC FE18            	     4M    bne    wait_psync_lo25
-00:000002BE 4008            	     5M    ld     r0, (r4)
-00:000002C0 806D            	     6M    btst   r0, MUX_BIT
-00:000002C2 6047            	     7M    and    r0, r6
-00:000002C4 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000002C8 1366            	     9M    sub    r3, 1
-00:000002CA 204D            	    10M    or     r0, r2           #merge bit state
-                            	   341:    OFW_HI_PSYNC_CAPTURE
+00:0000032C 4008            	     2M    ld     r0, (r4)
+00:0000032E 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000330 FE18            	     4M    bne    wait_psync_lo25
+00:00000332 4008            	     5M    ld     r0, (r4)
+00:00000334 806D            	     6M    btst   r0, MUX_BIT
+00:00000336 6047            	     7M    and    r0, r6
+00:00000338 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000033C 1366            	     9M    sub    r3, 1
+00:0000033E 204D            	    10M    or     r0, r2           #merge bit state
+                            	   414:    OFW_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi26:
-00:000002CC 4108            	     2M    ld     r1, (r4)
-00:000002CE 116D            	     3M    btst   r1, PSYNC_BIT
-00:000002D0 7E18            	     4M    beq    wait_psync_hi26
-00:000002D2 4108            	     5M    ld     r1, (r4)
-00:000002D4 816D            	     6M    btst   r1, MUX_BIT
-00:000002D6 6147            	     7M    and    r1, r6
-00:000002D8 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000002DC 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
-00:000002DE 036A            	    10M    cmp    r3, 0
-00:000002E0 104D            	    11M    or     r0, r1
-                            	   342: 
-00:000002E2 5032            	   343:    st     r0, DATA_BUFFER_1_offset(r5)
-00:000002E4 7F90C2FE        	   344:    beq    wait_for_command
-                            	   345: 
-                            	   346:    OFW_LO_PSYNC_CAPTURE
+00:00000340 4108            	     2M    ld     r1, (r4)
+00:00000342 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000344 7E18            	     4M    beq    wait_psync_hi26
+00:00000346 4108            	     5M    ld     r1, (r4)
+00:00000348 816D            	     6M    btst   r1, MUX_BIT
+00:0000034A 6147            	     7M    and    r1, r6
+00:0000034C 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000350 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
+00:00000352 036A            	    10M    cmp    r3, 0
+00:00000354 104D            	    11M    or     r0, r1
+                            	   415: 
+00:00000356 5032            	   416:    st     r0, DATA_BUFFER_1_offset(r5)
+00:00000358 7F9088FE        	   417:    beq    wait_for_command
+                            	   418: 
+                            	   419:    OFW_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo27:
-00:000002E8 4008            	     2M    ld     r0, (r4)
-00:000002EA 106D            	     3M    btst   r0, PSYNC_BIT
-00:000002EC FE18            	     4M    bne    wait_psync_lo27
-00:000002EE 4008            	     5M    ld     r0, (r4)
-00:000002F0 806D            	     6M    btst   r0, MUX_BIT
-00:000002F2 6047            	     7M    and    r0, r6
-00:000002F4 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000002F8 1366            	     9M    sub    r3, 1
-00:000002FA 204D            	    10M    or     r0, r2           #merge bit state
-                            	   347:    OFW_HI_PSYNC_CAPTURE
+00:0000035C 4008            	     2M    ld     r0, (r4)
+00:0000035E 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000360 FE18            	     4M    bne    wait_psync_lo27
+00:00000362 4008            	     5M    ld     r0, (r4)
+00:00000364 806D            	     6M    btst   r0, MUX_BIT
+00:00000366 6047            	     7M    and    r0, r6
+00:00000368 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000036C 1366            	     9M    sub    r3, 1
+00:0000036E 204D            	    10M    or     r0, r2           #merge bit state
+                            	   420:    OFW_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi28:
-00:000002FC 4108            	     2M    ld     r1, (r4)
-00:000002FE 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000300 7E18            	     4M    beq    wait_psync_hi28
-00:00000302 4108            	     5M    ld     r1, (r4)
-00:00000304 816D            	     6M    btst   r1, MUX_BIT
-00:00000306 6147            	     7M    and    r1, r6
-00:00000308 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000030C 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
-00:0000030E 036A            	    10M    cmp    r3, 0
-00:00000310 104D            	    11M    or     r0, r1
-                            	   348: 
-00:00000312 5033            	   349:    st     r0, DATA_BUFFER_2_offset(r5)
-00:00000314 7F90AAFE        	   350:    beq    wait_for_command
-                            	   351: 
-                            	   352:    OFW_LO_PSYNC_CAPTURE
+00:00000370 4108            	     2M    ld     r1, (r4)
+00:00000372 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000374 7E18            	     4M    beq    wait_psync_hi28
+00:00000376 4108            	     5M    ld     r1, (r4)
+00:00000378 816D            	     6M    btst   r1, MUX_BIT
+00:0000037A 6147            	     7M    and    r1, r6
+00:0000037C 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000380 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
+00:00000382 036A            	    10M    cmp    r3, 0
+00:00000384 104D            	    11M    or     r0, r1
+                            	   421: 
+00:00000386 5033            	   422:    st     r0, DATA_BUFFER_2_offset(r5)
+00:00000388 7F9070FE        	   423:    beq    wait_for_command
+                            	   424: 
+                            	   425:    OFW_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo29:
-00:00000318 4008            	     2M    ld     r0, (r4)
-00:0000031A 106D            	     3M    btst   r0, PSYNC_BIT
-00:0000031C FE18            	     4M    bne    wait_psync_lo29
-00:0000031E 4008            	     5M    ld     r0, (r4)
-00:00000320 806D            	     6M    btst   r0, MUX_BIT
-00:00000322 6047            	     7M    and    r0, r6
-00:00000324 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000328 1366            	     9M    sub    r3, 1
-00:0000032A 204D            	    10M    or     r0, r2           #merge bit state
-                            	   353:    OFW_HI_PSYNC_CAPTURE
+00:0000038C 4008            	     2M    ld     r0, (r4)
+00:0000038E 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000390 FE18            	     4M    bne    wait_psync_lo29
+00:00000392 4008            	     5M    ld     r0, (r4)
+00:00000394 806D            	     6M    btst   r0, MUX_BIT
+00:00000396 6047            	     7M    and    r0, r6
+00:00000398 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000039C 1366            	     9M    sub    r3, 1
+00:0000039E 204D            	    10M    or     r0, r2           #merge bit state
+                            	   426:    OFW_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi30:
-00:0000032C 4108            	     2M    ld     r1, (r4)
-00:0000032E 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000330 7E18            	     4M    beq    wait_psync_hi30
-00:00000332 4108            	     5M    ld     r1, (r4)
-00:00000334 816D            	     6M    btst   r1, MUX_BIT
-00:00000336 6147            	     7M    and    r1, r6
-00:00000338 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000033C 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
-00:0000033E 036A            	    10M    cmp    r3, 0
-00:00000340 104D            	    11M    or     r0, r1
-                            	   354: 
-00:00000342 5035            	   355:    st     r0, DATA_BUFFER_3_offset(r5)
-00:00000344 7F9092FE        	   356:    beq    wait_for_command
-                            	   357: 
-                            	   358:    OFW_LO_PSYNC_CAPTURE
+00:000003A0 4108            	     2M    ld     r1, (r4)
+00:000003A2 116D            	     3M    btst   r1, PSYNC_BIT
+00:000003A4 7E18            	     4M    beq    wait_psync_hi30
+00:000003A6 4108            	     5M    ld     r1, (r4)
+00:000003A8 816D            	     6M    btst   r1, MUX_BIT
+00:000003AA 6147            	     7M    and    r1, r6
+00:000003AC 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000003B0 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
+00:000003B2 036A            	    10M    cmp    r3, 0
+00:000003B4 104D            	    11M    or     r0, r1
+                            	   427: 
+00:000003B6 5035            	   428:    st     r0, DATA_BUFFER_3_offset(r5)
+00:000003B8 7F9058FE        	   429:    beq    wait_for_command
+                            	   430: 
+                            	   431:    OFW_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo31:
-00:00000348 4008            	     2M    ld     r0, (r4)
-00:0000034A 106D            	     3M    btst   r0, PSYNC_BIT
-00:0000034C FE18            	     4M    bne    wait_psync_lo31
-00:0000034E 4008            	     5M    ld     r0, (r4)
-00:00000350 806D            	     6M    btst   r0, MUX_BIT
-00:00000352 6047            	     7M    and    r0, r6
-00:00000354 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000358 1366            	     9M    sub    r3, 1
-00:0000035A 204D            	    10M    or     r0, r2           #merge bit state
-                            	   359:    OFW_HI_PSYNC_CAPTURE
+00:000003BC 4008            	     2M    ld     r0, (r4)
+00:000003BE 106D            	     3M    btst   r0, PSYNC_BIT
+00:000003C0 FE18            	     4M    bne    wait_psync_lo31
+00:000003C2 4008            	     5M    ld     r0, (r4)
+00:000003C4 806D            	     6M    btst   r0, MUX_BIT
+00:000003C6 6047            	     7M    and    r0, r6
+00:000003C8 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000003CC 1366            	     9M    sub    r3, 1
+00:000003CE 204D            	    10M    or     r0, r2           #merge bit state
+                            	   432:    OFW_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi32:
-00:0000035C 4108            	     2M    ld     r1, (r4)
-00:0000035E 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000360 7E18            	     4M    beq    wait_psync_hi32
-00:00000362 4108            	     5M    ld     r1, (r4)
-00:00000364 816D            	     6M    btst   r1, MUX_BIT
-00:00000366 6147            	     7M    and    r1, r6
-00:00000368 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000036C 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
-00:0000036E 036A            	    10M    cmp    r3, 0
-00:00000370 104D            	    11M    or     r0, r1
-                            	   360: 
-00:00000372 5036            	   361:    st     r0, DATA_BUFFER_4_offset(r5)
-00:00000374 7F907AFE        	   362:    beq    wait_for_command
-                            	   363: 
-                            	   364:    OFW_LO_PSYNC_CAPTURE
+00:000003D0 4108            	     2M    ld     r1, (r4)
+00:000003D2 116D            	     3M    btst   r1, PSYNC_BIT
+00:000003D4 7E18            	     4M    beq    wait_psync_hi32
+00:000003D6 4108            	     5M    ld     r1, (r4)
+00:000003D8 816D            	     6M    btst   r1, MUX_BIT
+00:000003DA 6147            	     7M    and    r1, r6
+00:000003DC 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000003E0 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
+00:000003E2 036A            	    10M    cmp    r3, 0
+00:000003E4 104D            	    11M    or     r0, r1
+                            	   433: 
+00:000003E6 5036            	   434:    st     r0, DATA_BUFFER_4_offset(r5)
+00:000003E8 7F9040FE        	   435:    beq    wait_for_command
+                            	   436: 
+                            	   437:    OFW_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo33:
-00:00000378 4008            	     2M    ld     r0, (r4)
-00:0000037A 106D            	     3M    btst   r0, PSYNC_BIT
-00:0000037C FE18            	     4M    bne    wait_psync_lo33
-00:0000037E 4008            	     5M    ld     r0, (r4)
-00:00000380 806D            	     6M    btst   r0, MUX_BIT
-00:00000382 6047            	     7M    and    r0, r6
-00:00000384 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000388 1366            	     9M    sub    r3, 1
-00:0000038A 204D            	    10M    or     r0, r2           #merge bit state
-00:0000038C 1275            	   365:    bchg   r2, PSYNC_BIT        #invert the software psync bit every 12 samples / 6 words
-                            	   366:    OFW_HI_PSYNC_CAPTURE
+00:000003EC 4008            	     2M    ld     r0, (r4)
+00:000003EE 106D            	     3M    btst   r0, PSYNC_BIT
+00:000003F0 FE18            	     4M    bne    wait_psync_lo33
+00:000003F2 4008            	     5M    ld     r0, (r4)
+00:000003F4 806D            	     6M    btst   r0, MUX_BIT
+00:000003F6 6047            	     7M    and    r0, r6
+00:000003F8 00C2CE00        	     8M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000003FC 1366            	     9M    sub    r3, 1
+00:000003FE 204D            	    10M    or     r0, r2           #merge bit state
+00:00000400 1275            	   438:    bchg   r2, PSYNC_BIT        #invert the software psync bit every 12 samples / 6 words
+                            	   439:    OFW_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi34:
-00:0000038E 4108            	     2M    ld     r1, (r4)
-00:00000390 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000392 7E18            	     4M    beq    wait_psync_hi34
-00:00000394 4108            	     5M    ld     r1, (r4)
-00:00000396 816D            	     6M    btst   r1, MUX_BIT
-00:00000398 6147            	     7M    and    r1, r6
-00:0000039A 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000039E 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
-00:000003A0 036A            	    10M    cmp    r3, 0
-00:000003A2 104D            	    11M    or     r0, r1
-                            	   367: 
-00:000003A4 5037            	   368:    st     r0, DATA_BUFFER_5_offset(r5)
-00:000003A6 7F9061FE        	   369:    beq    wait_for_command
-                            	   370: 
-00:000003AA 7F9E6FFF        	   371:    b      old_firmware_capture_loop
-                            	   372: 
-                            	   373: hl_capture:
-00:000003AE 7347            	   374:    and    r3, r7           #mask off any command bits (max capture is 4095 psync cycles)
-00:000003B0 3040            	   375:    mov    r0, r3
-00:000003B2 B062            	   376:    add    r0, 11           #round up to multiple of 12
-00:000003B4 C160            	   377:    mov    r1, 12
-00:000003B6 E3C40107        	   378:    divu   r3, r0, r1       #divide by 12 as capturing 12 samples per cycle
-00:000003BA 1275            	   379:    bchg   r2, PSYNC_BIT    #pre invert the software psync bit
-                            	   380: 
-                            	   381: high_latency_capture_loop:
-                            	   382:    HL_LO_PSYNC_CAPTURE
+00:00000402 4108            	     2M    ld     r1, (r4)
+00:00000404 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000406 7E18            	     4M    beq    wait_psync_hi34
+00:00000408 4108            	     5M    ld     r1, (r4)
+00:0000040A 816D            	     6M    btst   r1, MUX_BIT
+00:0000040C 6147            	     7M    and    r1, r6
+00:0000040E 01C2CE08        	     8M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000412 017D            	     9M    lsl    r1, 16           #merge lo and hi samples
+00:00000414 036A            	    10M    cmp    r3, 0
+00:00000416 104D            	    11M    or     r0, r1
+                            	   440: 
+00:00000418 5037            	   441:    st     r0, DATA_BUFFER_5_offset(r5)
+00:0000041A 7F9027FE        	   442:    beq    wait_for_command
+                            	   443: 
+00:0000041E 7F9E6FFF        	   444:    b      old_firmware_capture_loop
+                            	   445: 
+                            	   446: hl_capture:
+00:00000422 7347            	   447:    and    r3, r7           #mask off any command bits (max capture is 4095 psync cycles)
+00:00000424 3040            	   448:    mov    r0, r3
+00:00000426 B062            	   449:    add    r0, 11           #round up to multiple of 12
+00:00000428 C160            	   450:    mov    r1, 12
+00:0000042A E3C40107        	   451:    divu   r3, r0, r1       #divide by 12 as capturing 12 samples per cycle
+00:0000042E 1275            	   452:    bchg   r2, PSYNC_BIT    #pre invert the software psync bit
+                            	   453: 
+                            	   454: high_latency_capture_loop:
+                            	   455:    HL_LO_PSYNC_CAPTURE
                             	     1M wait_psync_lo35:
-00:000003BC 4008            	     2M    ld     r0, (r4)
-00:000003BE 106D            	     3M    btst   r0, PSYNC_BIT
-00:000003C0 FE18            	     4M    bne    wait_psync_lo35
-00:000003C2 806D            	     5M    btst   r0, MUX_BIT
-00:000003C4 6047            	     6M    and    r0, r6
-00:000003C6 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000430 4008            	     2M    ld     r0, (r4)
+00:00000432 106D            	     3M    btst   r0, PSYNC_BIT
+00:00000434 FE18            	     4M    bne    wait_psync_lo35
+00:00000436 806D            	     5M    btst   r0, MUX_BIT
+00:00000438 6047            	     6M    and    r0, r6
+00:0000043A 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
                             	     8M 
-00:000003CA 1275            	   383:    bchg   r2, PSYNC_BIT    #invert the software psync bit every 12 samples / 6 words
-00:000003CC 204D            	   384:    or     r0, r2           #merge bit state
-                            	   385:    HL_HI_PSYNC_CAPTURE
+00:0000043E 1275            	   456:    bchg   r2, PSYNC_BIT    #invert the software psync bit every 12 samples / 6 words
+00:00000440 204D            	   457:    or     r0, r2           #merge bit state
+                            	   458:    HL_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi36:
-00:000003CE 4108            	     2M    ld     r1, (r4)
-00:000003D0 116D            	     3M    btst   r1, PSYNC_BIT
-00:000003D2 7E18            	     4M    beq    wait_psync_hi36
-00:000003D4 816D            	     5M    btst   r1, MUX_BIT
-00:000003D6 6147            	     6M    and    r1, r6
-00:000003D8 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:000003DC 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:000003DE 104D            	     9M    or     r0, r1
-00:000003E0 104D            	   386:    or     r0, r1
-00:000003E2 5031            	   387:    st     r0, DATA_BUFFER_0_offset(r5)
-                            	   388: 
-                            	   389:    HL_LO_PSYNC_CAPTURE
-                            	     1M wait_psync_lo37:
-00:000003E4 4008            	     2M    ld     r0, (r4)
-00:000003E6 106D            	     3M    btst   r0, PSYNC_BIT
-00:000003E8 FE18            	     4M    bne    wait_psync_lo37
-00:000003EA 806D            	     5M    btst   r0, MUX_BIT
-00:000003EC 6047            	     6M    and    r0, r6
-00:000003EE 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	     8M 
-00:000003F2 204D            	   390:    or     r0, r2           #merge bit state
-                            	   391:    HL_HI_PSYNC_CAPTURE
-                            	     1M wait_psync_hi38:
-00:000003F4 4108            	     2M    ld     r1, (r4)
-00:000003F6 116D            	     3M    btst   r1, PSYNC_BIT
-00:000003F8 7E18            	     4M    beq    wait_psync_hi38
-00:000003FA 816D            	     5M    btst   r1, MUX_BIT
-00:000003FC 6147            	     6M    and    r1, r6
-00:000003FE 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:00000402 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:00000404 104D            	     9M    or     r0, r1
-00:00000406 104D            	   392:    or     r0, r1
-00:00000408 5032            	   393:    st     r0, DATA_BUFFER_1_offset(r5)
-                            	   394: 
-                            	   395:    HL_LO_PSYNC_CAPTURE
-                            	     1M wait_psync_lo39:
-00:0000040A 4008            	     2M    ld     r0, (r4)
-00:0000040C 106D            	     3M    btst   r0, PSYNC_BIT
-00:0000040E FE18            	     4M    bne    wait_psync_lo39
-00:00000410 806D            	     5M    btst   r0, MUX_BIT
-00:00000412 6047            	     6M    and    r0, r6
-00:00000414 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	     8M 
-00:00000418 1366            	   396:    sub    r3, 1
-00:0000041A 204D            	   397:    or     r0, r2           #merge bit state
-                            	   398:    HL_HI_PSYNC_CAPTURE
-                            	     1M wait_psync_hi40:
-00:0000041C 4108            	     2M    ld     r1, (r4)
-00:0000041E 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000420 7E18            	     4M    beq    wait_psync_hi40
-00:00000422 816D            	     5M    btst   r1, MUX_BIT
-00:00000424 6147            	     6M    and    r1, r6
-00:00000426 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000042A 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:0000042C 104D            	     9M    or     r0, r1
-00:0000042E 104D            	   399:    or     r0, r1
-00:00000430 5033            	   400:    st     r0, DATA_BUFFER_2_offset(r5)
-                            	   401: 
-                            	   402:    HL_LO_PSYNC_CAPTURE
-                            	     1M wait_psync_lo41:
-00:00000432 4008            	     2M    ld     r0, (r4)
-00:00000434 106D            	     3M    btst   r0, PSYNC_BIT
-00:00000436 FE18            	     4M    bne    wait_psync_lo41
-00:00000438 806D            	     5M    btst   r0, MUX_BIT
-00:0000043A 6047            	     6M    and    r0, r6
-00:0000043C 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-                            	     8M 
-00:00000440 204D            	   403:    or     r0, r2           #merge bit state
-                            	   404:    HL_HI_PSYNC_CAPTURE
-                            	     1M wait_psync_hi42:
 00:00000442 4108            	     2M    ld     r1, (r4)
 00:00000444 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000446 7E18            	     4M    beq    wait_psync_hi42
+00:00000446 7E18            	     4M    beq    wait_psync_hi36
 00:00000448 816D            	     5M    btst   r1, MUX_BIT
 00:0000044A 6147            	     6M    and    r1, r6
 00:0000044C 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
 00:00000450 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
 00:00000452 104D            	     9M    or     r0, r1
-00:00000454 104D            	   405:    or     r0, r1
-00:00000456 5035            	   406:    st     r0, DATA_BUFFER_3_offset(r5)
-                            	   407: 
-                            	   408:    HL_LO_PSYNC_CAPTURE
-                            	     1M wait_psync_lo43:
+00:00000454 104D            	   459:    or     r0, r1
+00:00000456 5031            	   460:    st     r0, DATA_BUFFER_0_offset(r5)
+                            	   461: 
+                            	   462:    HL_LO_PSYNC_CAPTURE
+                            	     1M wait_psync_lo37:
 00:00000458 4008            	     2M    ld     r0, (r4)
 00:0000045A 106D            	     3M    btst   r0, PSYNC_BIT
-00:0000045C FE18            	     4M    bne    wait_psync_lo43
+00:0000045C FE18            	     4M    bne    wait_psync_lo37
 00:0000045E 806D            	     5M    btst   r0, MUX_BIT
 00:00000460 6047            	     6M    and    r0, r6
 00:00000462 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
                             	     8M 
-00:00000466 204D            	   409:    or     r0, r2           #merge bit state
-                            	   410:    HL_HI_PSYNC_CAPTURE
-                            	     1M wait_psync_hi44:
+00:00000466 204D            	   463:    or     r0, r2           #merge bit state
+                            	   464:    HL_HI_PSYNC_CAPTURE
+                            	     1M wait_psync_hi38:
 00:00000468 4108            	     2M    ld     r1, (r4)
 00:0000046A 116D            	     3M    btst   r1, PSYNC_BIT
-00:0000046C 7E18            	     4M    beq    wait_psync_hi44
+00:0000046C 7E18            	     4M    beq    wait_psync_hi38
 00:0000046E 816D            	     5M    btst   r1, MUX_BIT
 00:00000470 6147            	     6M    and    r1, r6
 00:00000472 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
 00:00000476 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
 00:00000478 104D            	     9M    or     r0, r1
-00:0000047A 104D            	   411:    or     r0, r1
-00:0000047C 5036            	   412:    st     r0, DATA_BUFFER_4_offset(r5)
-                            	   413: 
-                            	   414:    HL_LO_PSYNC_CAPTURE
-                            	     1M wait_psync_lo45:
+00:0000047A 104D            	   465:    or     r0, r1
+00:0000047C 5032            	   466:    st     r0, DATA_BUFFER_1_offset(r5)
+                            	   467: 
+                            	   468:    HL_LO_PSYNC_CAPTURE
+                            	     1M wait_psync_lo39:
 00:0000047E 4008            	     2M    ld     r0, (r4)
 00:00000480 106D            	     3M    btst   r0, PSYNC_BIT
-00:00000482 FE18            	     4M    bne    wait_psync_lo45
+00:00000482 FE18            	     4M    bne    wait_psync_lo39
 00:00000484 806D            	     5M    btst   r0, MUX_BIT
 00:00000486 6047            	     6M    and    r0, r6
 00:00000488 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
                             	     8M 
-00:0000048C 204D            	   415:    or     r0, r2           #merge bit state
-                            	   416:    HL_HI_PSYNC_CAPTURE
+00:0000048C 1366            	   469:    sub    r3, 1
+00:0000048E 204D            	   470:    or     r0, r2           #merge bit state
+                            	   471:    HL_HI_PSYNC_CAPTURE
+                            	     1M wait_psync_hi40:
+00:00000490 4108            	     2M    ld     r1, (r4)
+00:00000492 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000494 7E18            	     4M    beq    wait_psync_hi40
+00:00000496 816D            	     5M    btst   r1, MUX_BIT
+00:00000498 6147            	     6M    and    r1, r6
+00:0000049A 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:0000049E 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:000004A0 104D            	     9M    or     r0, r1
+00:000004A2 104D            	   472:    or     r0, r1
+00:000004A4 5033            	   473:    st     r0, DATA_BUFFER_2_offset(r5)
+                            	   474: 
+                            	   475:    HL_LO_PSYNC_CAPTURE
+                            	     1M wait_psync_lo41:
+00:000004A6 4008            	     2M    ld     r0, (r4)
+00:000004A8 106D            	     3M    btst   r0, PSYNC_BIT
+00:000004AA FE18            	     4M    bne    wait_psync_lo41
+00:000004AC 806D            	     5M    btst   r0, MUX_BIT
+00:000004AE 6047            	     6M    and    r0, r6
+00:000004B0 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	     8M 
+00:000004B4 204D            	   476:    or     r0, r2           #merge bit state
+                            	   477:    HL_HI_PSYNC_CAPTURE
+                            	     1M wait_psync_hi42:
+00:000004B6 4108            	     2M    ld     r1, (r4)
+00:000004B8 116D            	     3M    btst   r1, PSYNC_BIT
+00:000004BA 7E18            	     4M    beq    wait_psync_hi42
+00:000004BC 816D            	     5M    btst   r1, MUX_BIT
+00:000004BE 6147            	     6M    and    r1, r6
+00:000004C0 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000004C4 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:000004C6 104D            	     9M    or     r0, r1
+00:000004C8 104D            	   478:    or     r0, r1
+00:000004CA 5035            	   479:    st     r0, DATA_BUFFER_3_offset(r5)
+                            	   480: 
+                            	   481:    HL_LO_PSYNC_CAPTURE
+                            	     1M wait_psync_lo43:
+00:000004CC 4008            	     2M    ld     r0, (r4)
+00:000004CE 106D            	     3M    btst   r0, PSYNC_BIT
+00:000004D0 FE18            	     4M    bne    wait_psync_lo43
+00:000004D2 806D            	     5M    btst   r0, MUX_BIT
+00:000004D4 6047            	     6M    and    r0, r6
+00:000004D6 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	     8M 
+00:000004DA 204D            	   482:    or     r0, r2           #merge bit state
+                            	   483:    HL_HI_PSYNC_CAPTURE
+                            	     1M wait_psync_hi44:
+00:000004DC 4108            	     2M    ld     r1, (r4)
+00:000004DE 116D            	     3M    btst   r1, PSYNC_BIT
+00:000004E0 7E18            	     4M    beq    wait_psync_hi44
+00:000004E2 816D            	     5M    btst   r1, MUX_BIT
+00:000004E4 6147            	     6M    and    r1, r6
+00:000004E6 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:000004EA 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:000004EC 104D            	     9M    or     r0, r1
+00:000004EE 104D            	   484:    or     r0, r1
+00:000004F0 5036            	   485:    st     r0, DATA_BUFFER_4_offset(r5)
+                            	   486: 
+                            	   487:    HL_LO_PSYNC_CAPTURE
+                            	     1M wait_psync_lo45:
+00:000004F2 4008            	     2M    ld     r0, (r4)
+00:000004F4 106D            	     3M    btst   r0, PSYNC_BIT
+00:000004F6 FE18            	     4M    bne    wait_psync_lo45
+00:000004F8 806D            	     5M    btst   r0, MUX_BIT
+00:000004FA 6047            	     6M    and    r0, r6
+00:000004FC 00C2CE00        	     7M    bsetne r0, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+                            	     8M 
+00:00000500 204D            	   488:    or     r0, r2           #merge bit state
+                            	   489:    HL_HI_PSYNC_CAPTURE
                             	     1M wait_psync_hi46:
-00:0000048E 4108            	     2M    ld     r1, (r4)
-00:00000490 116D            	     3M    btst   r1, PSYNC_BIT
-00:00000492 7E18            	     4M    beq    wait_psync_hi46
-00:00000494 816D            	     5M    btst   r1, MUX_BIT
-00:00000496 6147            	     6M    and    r1, r6
-00:00000498 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
-00:0000049C 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
-00:0000049E 104D            	     9M    or     r0, r1
-00:000004A0 036A            	   417:    cmp    r3, 0
-00:000004A2 104D            	   418:    or     r0, r1
-00:000004A4 5037            	   419:    st     r0, DATA_BUFFER_5_offset(r5)
-                            	   420: 
-00:000004A6 7F918BFF        	   421:    bne    high_latency_capture_loop
-                            	   422: 
-00:000004AA 7F9EDFFD        	   423:    b      wait_for_command
-                            	   424: 
-                            	   425: 
+00:00000502 4108            	     2M    ld     r1, (r4)
+00:00000504 116D            	     3M    btst   r1, PSYNC_BIT
+00:00000506 7E18            	     4M    beq    wait_psync_hi46
+00:00000508 816D            	     5M    btst   r1, MUX_BIT
+00:0000050A 6147            	     6M    and    r1, r6
+00:0000050C 01C2CE08        	     7M    bsetne r1, ALT_MUX_BIT  #move mux bit to position in 16 bit sample
+00:00000510 017D            	     8M    lsl    r1, 16           #merge lo and hi samples
+00:00000512 104D            	     9M    or     r0, r1
+00:00000514 036A            	   490:    cmp    r3, 0
+00:00000516 104D            	   491:    or     r0, r1
+00:00000518 5037            	   492:    st     r0, DATA_BUFFER_5_offset(r5)
+                            	   493: 
+00:0000051A 7F918BFF        	   494:    bne    high_latency_capture_loop
+                            	   495: 
+00:0000051E 7F9EA5FD        	   496:    b      wait_for_command
+                            	   497: 
+                            	   498: 
 
 
 Symbols by name:
@@ -859,81 +932,89 @@ GPU_COMMAND_offset               S:00000000
 GPU_DATA_BUFFER_5                S:7E0000BC
 GPU_SYNC_offset                  S:00000010
 HIGH_LATENCY_FLAG                S:0000000E
+LEADING_SYNC_FLAG                S:00000010
 MUX_BIT                          S:00000018
 OLD_FIRMWARE_FLAG                S:0000000D
 PSYNC_BIT                        S:00000011
 SIMPLE_SYNC_FLAG                 S:0000000F
+SYNC_ABORT_FLAG                  S:0000001F
 SYNC_BIT                         S:00000017
 VIDEO_MASK                       S:00003FFC
-capture_loop                    00:00000174
-do_capture                      00:00000162
-done_simple_sync                00:00000150
-edge_lead_both                  00:000000BC
-edge_lead_neg                   00:000000F6
-edge_lead_pos                   00:000000F6
-edge_trail_both                 00:000000D2
-edge_trail_both_hi              00:000000E4
-edge_trail_neg                  00:00000116
-edge_trail_pos                  00:00000116
-high_latency_capture_loop       00:000003BC
-hl_capture                      00:000003AE
-no_compensate_psync             00:00000160
+capture_loop                    00:0000019C
+capture_rest                    00:00000190
+do_capture                      00:0000016E
+done_simple_sync                00:0000015A
+edge_lead_both                  00:000000C6
+edge_lead_neg                   00:00000100
+edge_lead_pos                   00:00000100
+edge_trail_both                 00:000000DC
+edge_trail_both_hi              00:000000EE
+edge_trail_neg                  00:00000120
+edge_trail_pos                  00:00000120
+high_latency_capture_loop       00:00000430
+hl_capture                      00:00000422
+no_compensate_psync             00:0000016A
 not_gpio_read_benchmark         00:0000001E
 not_mbox_write_benchmark        00:0000003C
-ofw_capture                     00:00000282
-old_firmware_capture_loop       00:00000288
+ofw_capture                     00:000002AA
+ofw_capture_rest                00:000002F6
+ofw_wait_csync_hi_cpld          00:000002D2
+ofw_wait_csync_lo_cpld          00:000002AA
+old_firmware_capture_loop       00:000002FC
 read_bench_loop                 00:00000012
-waitPSE1                        00:000000BC
-waitPSE10                       00:00000154
-waitPSE2                        00:000000D2
-waitPSE3                        00:000000E4
-waitPSE4                        00:000000F6
-waitPSE5                        00:00000102
-waitPSE6                        00:00000116
-waitPSE7                        00:00000122
-waitPSE8                        00:00000134
-waitPSE9                        00:00000140
-wait_csync_hi                   00:00000134
-wait_csync_lo                   00:00000116
-wait_csync_lo2                  00:000000F6
+waitPSE1                        00:000000C6
+waitPSE10                       00:0000015E
+waitPSE2                        00:000000DC
+waitPSE3                        00:000000EE
+waitPSE4                        00:00000100
+waitPSE5                        00:0000010C
+waitPSE6                        00:00000120
+waitPSE7                        00:0000012C
+waitPSE8                        00:0000013E
+waitPSE9                        00:0000014A
+wait_csync_hi                   00:0000013E
+wait_csync_hi_cpld              00:00000184
+wait_csync_lo                   00:00000120
+wait_csync_lo2                  00:00000100
+wait_csync_lo_cpld              00:00000174
 wait_for_command                00:00000068
 wait_for_command_loop           00:00000092
-wait_psync_hi12                 00:00000186
-wait_psync_hi14                 00:000001B2
-wait_psync_hi16                 00:000001DE
-wait_psync_hi18                 00:0000020A
-wait_psync_hi20                 00:00000236
-wait_psync_hi22                 00:00000264
-wait_psync_hi24                 00:0000029C
-wait_psync_hi26                 00:000002CC
-wait_psync_hi28                 00:000002FC
-wait_psync_hi30                 00:0000032C
-wait_psync_hi32                 00:0000035C
-wait_psync_hi34                 00:0000038E
-wait_psync_hi36                 00:000003CE
-wait_psync_hi38                 00:000003F4
-wait_psync_hi40                 00:0000041C
-wait_psync_hi42                 00:00000442
-wait_psync_hi44                 00:00000468
-wait_psync_hi46                 00:0000048E
-wait_psync_lo11                 00:00000174
-wait_psync_lo13                 00:000001A0
-wait_psync_lo15                 00:000001CC
-wait_psync_lo17                 00:000001F8
-wait_psync_lo19                 00:00000224
-wait_psync_lo21                 00:00000250
-wait_psync_lo23                 00:00000288
-wait_psync_lo25                 00:000002B8
-wait_psync_lo27                 00:000002E8
-wait_psync_lo29                 00:00000318
-wait_psync_lo31                 00:00000348
-wait_psync_lo33                 00:00000378
-wait_psync_lo35                 00:000003BC
-wait_psync_lo37                 00:000003E4
-wait_psync_lo39                 00:0000040A
-wait_psync_lo41                 00:00000432
-wait_psync_lo43                 00:00000458
-wait_psync_lo45                 00:0000047E
+wait_psync_hi12                 00:000001AE
+wait_psync_hi14                 00:000001DA
+wait_psync_hi16                 00:00000206
+wait_psync_hi18                 00:00000232
+wait_psync_hi20                 00:0000025E
+wait_psync_hi22                 00:0000028C
+wait_psync_hi24                 00:00000310
+wait_psync_hi26                 00:00000340
+wait_psync_hi28                 00:00000370
+wait_psync_hi30                 00:000003A0
+wait_psync_hi32                 00:000003D0
+wait_psync_hi34                 00:00000402
+wait_psync_hi36                 00:00000442
+wait_psync_hi38                 00:00000468
+wait_psync_hi40                 00:00000490
+wait_psync_hi42                 00:000004B6
+wait_psync_hi44                 00:000004DC
+wait_psync_hi46                 00:00000502
+wait_psync_lo11                 00:0000019C
+wait_psync_lo13                 00:000001C8
+wait_psync_lo15                 00:000001F4
+wait_psync_lo17                 00:00000220
+wait_psync_lo19                 00:0000024C
+wait_psync_lo21                 00:00000278
+wait_psync_lo23                 00:000002FC
+wait_psync_lo25                 00:0000032C
+wait_psync_lo27                 00:0000035C
+wait_psync_lo29                 00:0000038C
+wait_psync_lo31                 00:000003BC
+wait_psync_lo33                 00:000003EC
+wait_psync_lo35                 00:00000430
+wait_psync_lo37                 00:00000458
+wait_psync_lo39                 00:0000047E
+wait_psync_lo41                 00:000004A6
+wait_psync_lo43                 00:000004CC
+wait_psync_lo45                 00:000004F2
 write_bench_loop                00:00000030
 
 Symbols by value:
@@ -946,6 +1027,7 @@ Symbols by value:
 0000000E HIGH_LATENCY_FLAG
 0000000F SIMPLE_SYNC_FLAG
 00000010 GPU_SYNC_offset
+00000010 LEADING_SYNC_FLAG
 00000011 PSYNC_BIT
 00000012 read_bench_loop
 00000014 DATA_BUFFER_3_offset
@@ -955,74 +1037,81 @@ Symbols by value:
 0000001C DATA_BUFFER_5_offset
 0000001E not_gpio_read_benchmark
 0000001F FINAL_BIT
+0000001F SYNC_ABORT_FLAG
 00000030 write_bench_loop
 0000003C not_mbox_write_benchmark
 00000068 wait_for_command
 00000092 wait_for_command_loop
-000000BC edge_lead_both
-000000BC waitPSE1
-000000D2 edge_trail_both
-000000D2 waitPSE2
-000000E4 edge_trail_both_hi
-000000E4 waitPSE3
-000000F6 edge_lead_neg
-000000F6 edge_lead_pos
-000000F6 waitPSE4
-000000F6 wait_csync_lo2
-00000102 waitPSE5
-00000116 edge_trail_neg
-00000116 edge_trail_pos
-00000116 waitPSE6
-00000116 wait_csync_lo
-00000122 waitPSE7
-00000134 waitPSE8
-00000134 wait_csync_hi
-00000140 waitPSE9
-00000150 done_simple_sync
-00000154 waitPSE10
-00000160 no_compensate_psync
-00000162 do_capture
-00000174 capture_loop
-00000174 wait_psync_lo11
-00000186 wait_psync_hi12
-000001A0 wait_psync_lo13
-000001B2 wait_psync_hi14
-000001CC wait_psync_lo15
-000001DE wait_psync_hi16
-000001F8 wait_psync_lo17
-0000020A wait_psync_hi18
-00000224 wait_psync_lo19
-00000236 wait_psync_hi20
-00000250 wait_psync_lo21
-00000264 wait_psync_hi22
-00000282 ofw_capture
-00000288 old_firmware_capture_loop
-00000288 wait_psync_lo23
-0000029C wait_psync_hi24
-000002B8 wait_psync_lo25
-000002CC wait_psync_hi26
-000002E8 wait_psync_lo27
-000002FC wait_psync_hi28
-00000318 wait_psync_lo29
-0000032C wait_psync_hi30
-00000348 wait_psync_lo31
-0000035C wait_psync_hi32
-00000378 wait_psync_lo33
-0000038E wait_psync_hi34
-000003AE hl_capture
-000003BC high_latency_capture_loop
-000003BC wait_psync_lo35
-000003CE wait_psync_hi36
-000003E4 wait_psync_lo37
-000003F4 wait_psync_hi38
-0000040A wait_psync_lo39
-0000041C wait_psync_hi40
-00000432 wait_psync_lo41
-00000442 wait_psync_hi42
-00000458 wait_psync_lo43
-00000468 wait_psync_hi44
-0000047E wait_psync_lo45
-0000048E wait_psync_hi46
+000000C6 edge_lead_both
+000000C6 waitPSE1
+000000DC edge_trail_both
+000000DC waitPSE2
+000000EE edge_trail_both_hi
+000000EE waitPSE3
+00000100 edge_lead_neg
+00000100 edge_lead_pos
+00000100 waitPSE4
+00000100 wait_csync_lo2
+0000010C waitPSE5
+00000120 edge_trail_neg
+00000120 edge_trail_pos
+00000120 waitPSE6
+00000120 wait_csync_lo
+0000012C waitPSE7
+0000013E waitPSE8
+0000013E wait_csync_hi
+0000014A waitPSE9
+0000015A done_simple_sync
+0000015E waitPSE10
+0000016A no_compensate_psync
+0000016E do_capture
+00000174 wait_csync_lo_cpld
+00000184 wait_csync_hi_cpld
+00000190 capture_rest
+0000019C capture_loop
+0000019C wait_psync_lo11
+000001AE wait_psync_hi12
+000001C8 wait_psync_lo13
+000001DA wait_psync_hi14
+000001F4 wait_psync_lo15
+00000206 wait_psync_hi16
+00000220 wait_psync_lo17
+00000232 wait_psync_hi18
+0000024C wait_psync_lo19
+0000025E wait_psync_hi20
+00000278 wait_psync_lo21
+0000028C wait_psync_hi22
+000002AA ofw_capture
+000002AA ofw_wait_csync_lo_cpld
+000002D2 ofw_wait_csync_hi_cpld
+000002F6 ofw_capture_rest
+000002FC old_firmware_capture_loop
+000002FC wait_psync_lo23
+00000310 wait_psync_hi24
+0000032C wait_psync_lo25
+00000340 wait_psync_hi26
+0000035C wait_psync_lo27
+00000370 wait_psync_hi28
+0000038C wait_psync_lo29
+000003A0 wait_psync_hi30
+000003BC wait_psync_lo31
+000003D0 wait_psync_hi32
+000003EC wait_psync_lo33
+00000402 wait_psync_hi34
+00000422 hl_capture
+00000430 high_latency_capture_loop
+00000430 wait_psync_lo35
+00000442 wait_psync_hi36
+00000458 wait_psync_lo37
+00000468 wait_psync_hi38
+0000047E wait_psync_lo39
+00000490 wait_psync_hi40
+000004A6 wait_psync_lo41
+000004B6 wait_psync_hi42
+000004CC wait_psync_lo43
+000004DC wait_psync_hi44
+000004F2 wait_psync_lo45
+00000502 wait_psync_hi46
 00000FFF COMMAND_MASK
 00003FFC VIDEO_MASK
 00020001 DEFAULT_BIT_STATE
diff --git a/src/videocore.s b/src/videocore.s
index fd3fba56..bd864d4f 100644
--- a/src/videocore.s
+++ b/src/videocore.s
@@ -34,10 +34,14 @@
 .equ ALT_MUX_BIT,          14             #moved version of MUX bit
 .equ SYNC_BIT,             23             #sync input
 .equ VIDEO_MASK,           0x3ffc         #12bit GPIO mask
+
 .equ COMMAND_MASK,         0x00000fff     #masks out command bits that trigger sync detection
-.equ SIMPLE_SYNC_FLAG,     15
-.equ HIGH_LATENCY_FLAG,    14
+#command bits
 .equ OLD_FIRMWARE_FLAG,    13
+.equ HIGH_LATENCY_FLAG,    14
+.equ SIMPLE_SYNC_FLAG,     15
+.equ LEADING_SYNC_FLAG,    16
+.equ SYNC_ABORT_FLAG,      31
 
 #macros
 
@@ -198,9 +202,14 @@ wait_for_command:
    mov    r2, r8                        #set the default state of the control bits
 
 wait_for_command_loop:
+   nop    #some idle time to reduce continuous polling of register
    ld     r3, GPU_COMMAND_offset(r5)
+   nop
    cmp    r3, 0
+   nop
    beq    wait_for_command_loop
+   btst   r3, SYNC_ABORT_FLAG
+   bne    wait_for_command
    btst   r3, SIMPLE_SYNC_FLAG                   #bit signals upper 16 bits is a sync command
    beq    do_capture
    mov    r1, r3
@@ -271,16 +280,36 @@ done_simple_sync:
    bne    no_compensate_psync
    EDGE_DETECT           #have to compensate because capture hard coded to always start on same edge
 no_compensate_psync:
-
    mov    r2, r8         #set the default state of the control bits
+   b      capture_rest
 
 do_capture:
-   btst   r3, HIGH_LATENCY_FLAG         #bit signals high latency capture, only suitable for 9/12bpp modes
-   bne    hl_capture
-
    btst   r3, OLD_FIRMWARE_FLAG         #bit signals old firmware capture, requires double reads as psync not pipelined
    bne    ofw_capture
 
+wait_csync_lo_cpld:
+   ld     r0, GPU_COMMAND_offset(r5)
+   btst   r0, SYNC_ABORT_FLAG
+   bne    capture_rest
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   bne    wait_csync_lo_cpld
+
+   btst   r3, LEADING_SYNC_FLAG
+   bne    capture_rest
+
+wait_csync_hi_cpld:
+   ld     r0, GPU_COMMAND_offset(r5)
+   btst   r0, SYNC_ABORT_FLAG
+   bne    capture_rest
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   beq    wait_csync_hi_cpld
+
+capture_rest:
+   btst   r3, HIGH_LATENCY_FLAG         #bit signals high latency capture, only suitable for 9/12bpp modes
+   bne    hl_capture
+
    and    r3, r7         #mask off any command bits (max capture is 4095 psync cycles)
    add    r3, 1          #round up to multiple of 2
    lsr    r3, 1          #divide by 2 as capturing 2 samples per cycle
@@ -326,6 +355,50 @@ capture_loop:
    b      capture_loop
 
 ofw_capture:
+ofw_wait_csync_lo_cpld:
+   ld     r0, GPU_COMMAND_offset(r5)
+   btst   r0, SYNC_ABORT_FLAG
+   bne    ofw_capture_rest
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   bne    ofw_wait_csync_lo_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   bne    ofw_wait_csync_lo_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   bne    ofw_wait_csync_lo_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   bne    ofw_wait_csync_lo_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   bne    ofw_wait_csync_lo_cpld
+
+   btst   r3, LEADING_SYNC_FLAG
+   bne    ofw_capture_rest
+
+ofw_wait_csync_hi_cpld:
+   ld     r0, GPU_COMMAND_offset(r5)
+   btst   r0, SYNC_ABORT_FLAG
+   bne    ofw_capture_rest
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   beq    ofw_wait_csync_hi_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   beq    ofw_wait_csync_hi_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   beq    ofw_wait_csync_hi_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   beq    ofw_wait_csync_hi_cpld
+   ld     r0, (r4)
+   btst   r0, SYNC_BIT
+   beq    ofw_wait_csync_hi_cpld
+
+ofw_capture_rest:
    and    r3, r7         #mask off any command bits (max capture is 4095 psync cycles)
    add    r3, 1          #round up to multiple of 2
    lsr    r3, 1          #divide by 2 as capturing 2 samples per cycle