diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt deleted file mode 100644 index cc60b3d423f309..00000000000000 --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt +++ /dev/null @@ -1,50 +0,0 @@ -* HiSilicon Clock and Reset Generator(CRG) - -The CRG module provides clock and reset signals to various -modules within the SoC. - -This binding uses the following bindings: - Documentation/devicetree/bindings/clock/clock-bindings.txt - Documentation/devicetree/bindings/reset/reset.txt - -Required Properties: - -- compatible: should be one of the following. - - "hisilicon,hi3516cv300-crg" - - "hisilicon,hi3516cv300-sysctrl" - - "hisilicon,hi3519-crg" - - "hisilicon,hi3798cv200-crg" - - "hisilicon,hi3798cv200-sysctrl" - -- reg: physical base address of the controller and length of memory mapped - region. - -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifier could be found in . - -- #reset-cells: should be 2. - -A reset signal can be controlled by writing a bit register in the CRG module. -The reset specifier consists of two cells. The first cell represents the -register offset relative to the base address. The second cell represents the -bit index in the register. - -Example: CRG nodes -CRG: clock-reset-controller@12010000 { - compatible = "hisilicon,hi3519-crg"; - reg = <0x12010000 0x10000>; - #clock-cells = <1>; - #reset-cells = <2>; -}; - -Example: consumer nodes -i2c0: i2c@12110000 { - compatible = "hisilicon,hi3519-i2c"; - reg = <0x12110000 0x1000>; - clocks = <&CRG HI3519_I2C0_RST>; - resets = <&CRG 0xe4 0>; -}; diff --git a/Documentation/devicetree/bindings/clock/hisilicon,hisi-crg.yaml b/Documentation/devicetree/bindings/clock/hisilicon,hisi-crg.yaml new file mode 100644 index 00000000000000..3f3e3333be226d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hisilicon,hisi-crg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/hisilicon,hisi-crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon SOC Clock and Reset Generator (CRG) module + +maintainers: + - Yang Xiwen + +description: | + Hisilicon SOC clock control module which supports the clocks, resets and + power domains on various SoCs. + +properties: + compatible: + oneOf: + - const: hisilicon,hi3519-crg + - items: + - enum: + - hisilicon,hi3516cv300-crg + - hisilicon,hi3516cv300-sysctrl + - hisilicon,hi3798cv200-crg + - hisilicon,hi3798cv200-sysctrl + - hisilicon,hi3798mv200-crg + - hisilicon,hi3798mv200-sysctrl + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 2 + description: | + First cell is reset request register offset. + Second cell is bit offset in reset request register. + + reset-controller: + type: object + description: | + Reset controller for Hi3798CV200 GMAC module + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi3798cv200-crg + then: + required: + - reset-controller + else: + properties: + reset-controller: false + +additionalProperties: false + +examples: + - | + clock-reset-controller@12010000 { + compatible = "hisilicon,hi3519-crg"; + reg = <0x12010000 0x10000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a606786..1e6a8a8829b160 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -5,7 +5,8 @@ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. */ -#include +#include +#include #include #include #include diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index c1ec75aa4ccdf8..fab8059240b76d 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -45,6 +45,14 @@ config COMMON_CLK_HI3798CV200 help Build the clock driver for hi3798cv200. +config COMMON_CLK_HI3798MV200 + tristate "Hi3798MV200 Clock Driver" + depends on ARCH_HISI || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3798mv200. + config COMMON_CLK_HI6220 bool "Hi6220 Clock Driver" depends on ARCH_HISI || COMPILE_TEST diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 2978e56cb876b8..b9ef6372705f7d 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -3,7 +3,7 @@ # Hisilicon Clock specific Makefile # -obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o +obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o clk-pll.o obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o @@ -14,6 +14,7 @@ obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o +obj-$(CONFIG_COMMON_CLK_HI3798MV200) += crg-hi3798mv200.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index ff4ca0edce06a3..77fa4203a428d6 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, +static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, int nums, struct hisi_clock_data *data, struct device *dev) { void __iomem *base = data->base; @@ -517,7 +517,7 @@ static struct hisi_clock_data *hi3559av100_clk_register( if (ret) return ERR_PTR(ret); - hisi_clk_register_pll(hi3559av100_pll_clks, + _hisi_clk_register_pll(hi3559av100_pll_clks, ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev); ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg, diff --git a/drivers/clk/hisilicon/clk-pll.c b/drivers/clk/hisilicon/clk-pll.c new file mode 100644 index 00000000000000..c5c07a65fcf46f --- /dev/null +++ b/drivers/clk/hisilicon/clk-pll.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * PLL driver for HiSilicon SoCs + * + * Copyright 2024 (c) Yang Xiwen + */ + +#include +#include +#include +#include + +#include "clk.h" + +/* PLL has two conf regs in total */ +#define HISI_PLL_CFG(n) ((n) * 4) + +/* reg 0 definitions */ +#define HISI_PLL_FRAC GENMASK(23, 0) +#define HISI_PLL_POSTDIV1 GENMASK(26, 24) +#define HISI_PLL_POSTDIV2 GENMASK(30, 28) + +/* reg 1 definitions */ +#define HISI_PLL_FBDIV GENMASK(11, 0) +#define HISI_PLL_REFDIV GENMASK(17, 12) +#define HISI_PLL_PD BIT(20) +#define HISI_PLL_FOUTVCOPD BIT(21) +#define HISI_PLL_FOUT4PHASEPD BIT(22) +#define HISI_PLL_FOUTPOSTDIVPD BIT(23) +#define HISI_PLL_DACPD BIT(24) +#define HISI_PLL_DSMPD BIT(25) +#define HISI_PLL_BYPASS BIT(26) + +/* + * Datasheet said the maximum is 3.2GHz, + * but tests show it can be very high + * + * Leave some margin here (8 GHz should be fine) + */ +#define HISI_PLL_FOUTVCO_MAX_RATE 8000000000 +/* 800 MHz */ +#define HISI_PLL_FOUTVCO_MIN_RATE 800000000 + +struct hisi_pll { + struct clk_hw hw; + void __iomem *base; + u8 postdiv1, postdiv2, refdiv; + u32 divisor; +}; + +#define to_hisi_pll(_hw) container_of(_hw, struct hisi_pll, hw) + +static int hisi_pll_prepare(struct clk_hw *hw) +{ + struct hisi_pll *pll = to_hisi_pll(hw); + u32 reg; + + reg = readl(pll->base + HISI_PLL_CFG(0)); + pll->postdiv1 = FIELD_GET(HISI_PLL_POSTDIV1, reg); + pll->postdiv2 = FIELD_GET(HISI_PLL_POSTDIV2, reg); + // We don't use frac, clear it + reg &= ~HISI_PLL_FRAC; + writel(reg, pll->base + HISI_PLL_CFG(0)); + + reg = readl(pll->base + HISI_PLL_CFG(1)); + pll->refdiv = FIELD_GET(HISI_PLL_REFDIV, reg); + + pll->divisor = pll->refdiv * pll->postdiv1 * pll->postdiv2; + + // return -EINVAL if boot loader does not init PLL correctly + if (pll->divisor == 0) { + pr_err("%s: PLLs are not initialized by boot loader correctly!\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int hisi_pll_set_rate(struct clk_hw *hw, ulong rate, ulong parent_rate) +{ + struct hisi_pll *pll = to_hisi_pll(hw); + u64 fbdiv = rate * pll->divisor; + u32 reg; + + do_div(fbdiv, parent_rate); + + reg = readl(pll->base + HISI_PLL_CFG(1)); + reg &= ~HISI_PLL_FBDIV; + reg |= FIELD_PREP(HISI_PLL_FBDIV, fbdiv); + writel(reg, pll->base + HISI_PLL_CFG(1)); + + /* TODO: wait for PLL lock? */ + + return 0; +} + +static int hisi_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) +{ + struct hisi_pll *pll = to_hisi_pll(hw); + u64 vco, ref_rate = req->best_parent_rate; + + if (ref_rate == 0) + return -EINVAL; + + do_div(ref_rate, pll->refdiv); + vco = clamp(req->rate * (pll->postdiv1 * pll->postdiv2), + HISI_PLL_FOUTVCO_MIN_RATE, HISI_PLL_FOUTVCO_MAX_RATE); + vco = rounddown(vco, ref_rate); + if (vco < HISI_PLL_FOUTVCO_MIN_RATE) + vco += ref_rate; + + do_div(vco, pll->postdiv1 * pll->postdiv2); + req->rate = vco; + + return 0; +} + +static ulong hisi_pll_recalc_rate(struct clk_hw *hw, ulong parent_rate) +{ + struct hisi_pll *pll = to_hisi_pll(hw); + u32 reg, fbdiv; + + reg = readl(pll->base + HISI_PLL_CFG(1)); + fbdiv = FIELD_GET(HISI_PLL_FBDIV, reg); + parent_rate *= fbdiv; + do_div(parent_rate, pll->divisor); + + return parent_rate; +} + +static const struct clk_ops hisi_pll_ops = { + .prepare = hisi_pll_prepare, + .set_rate = hisi_pll_set_rate, + .determine_rate = hisi_pll_determine_rate, + .recalc_rate = hisi_pll_recalc_rate, +}; + +/* + * devm_hisi_pll_register - register a HiSilicon PLL + * + * @dev: clk provider + * @name: clock name + * @parent_name: parent clock, usually 24MHz OSC + * #flags: CCF common flags + * @reg: register address + */ +struct clk *devm_clk_register_hisi_pll(struct device *dev, const char *name, const char *parent, + unsigned int flags, void __iomem *reg) +{ + struct hisi_pll *pll; + struct clk_init_data init; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + if (!parent) + return ERR_PTR(-EINVAL); + + init.name = name; + init.ops = &hisi_pll_ops; + init.flags = flags; + init.parent_names = &parent; + init.num_parents = 1; + + pll->base = reg; + pll->hw.init = &init; + + return devm_clk_register(dev, &pll->hw); +} +EXPORT_SYMBOL_GPL(devm_clk_register_hisi_pll); diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 09368fd32befb3..0e9b0f13b49444 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -341,3 +341,27 @@ void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, data->clk_data.clks[clks[i].id] = clk; } } + +int hisi_clk_register_pll(struct device *dev, const struct hisi_pll_clock *clks, + int nums, struct hisi_clock_data *data) +{ + struct clk *clk; + void __iomem *base = data->base; + int i; + + for (i = 0; i < nums; i++) { + clk = devm_clk_register_hisi_pll(dev, clks[i].name, clks[i].parent_name, + clks[i].flags, base + clks[i].offset); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + return PTR_ERR(clk); + } + + + data->clk_data.clks[clks[i].id] = clk; + } + + return 0; +} +EXPORT_SYMBOL_GPL(hisi_clk_register_pll); diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 7a9b42e1b0272f..8c59f3927152fc 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -103,6 +103,14 @@ struct hisi_gate_clock { const char *alias; }; +struct hisi_pll_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; +}; + struct clk *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, @@ -122,6 +130,8 @@ int hisi_clk_register_mux(const struct hisi_mux_clock *, int, struct clk *clk_register_hisi_phase(struct device *dev, const struct hisi_phase_clock *clks, void __iomem *base, spinlock_t *lock); +struct clk *devm_clk_register_hisi_pll(struct device *dev, const char *name, const char *parent, + unsigned int flags, void __iomem *reg); int hisi_clk_register_phase(struct device *dev, const struct hisi_phase_clock *clks, int nums, struct hisi_clock_data *data); @@ -133,6 +143,8 @@ void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, int, struct hisi_clock_data *); void hi6220_clk_register_divider(const struct hi6220_divider_clock *, int, struct hisi_clock_data *); +int hisi_clk_register_pll(struct device *dev, const struct hisi_pll_clock *clks, + int nums, struct hisi_clock_data *data); #define hisi_clk_unregister(type) \ static inline \ diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index f651b197e45abe..3e26a8f6df3641 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -5,7 +5,8 @@ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. */ -#include +#include +#include #include #include #include diff --git a/drivers/clk/hisilicon/crg-hi3798mv200.c b/drivers/clk/hisilicon/crg-hi3798mv200.c new file mode 100644 index 00000000000000..5a2410d0a0b956 --- /dev/null +++ b/drivers/clk/hisilicon/crg-hi3798mv200.c @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Hi3798MV200 Clock and Reset Generator Driver + * + * Copyright (c) 2024 Yang Xiwen + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include "clk.h" +#include "crg.h" +#include "reset.h" + +/* hi3798MV200 core CRG */ +enum hi3798mv200_crg_inner_clk { + HI3798MV200_FIXED_3M = HI3798MV200_CRG_CLK_COUNT, + HI3798MV200_FIXED_12M, + HI3798MV200_FIXED_24M, + HI3798MV200_FIXED_25M, + HI3798MV200_FIXED_27M, + HI3798MV200_FIXED_48M, + HI3798MV200_FIXED_50M, + HI3798MV200_FIXED_54M, + HI3798MV200_FIXED_60M, + HI3798MV200_FIXED_75M, + HI3798MV200_FIXED_100M, + HI3798MV200_FIXED_125M, + HI3798MV200_FIXED_150M, + HI3798MV200_FIXED_200M, + HI3798MV200_FIXED_400M, + HI3798MV200_FIXED_600M, + HI3798MV200_FIXED_800M, + HI3798MV200_FIXED_1200M, + HI3798MV200_FIXED_1350M, + HI3798MV200_MMC_MUX, + HI3798MV200_SDIO0_MUX, + HI3798MV200_SDIO1_MUX, + HI3798MV200_COMBPHY_MUX, + HI3798MV200_FEMAC_MUX, + HI3798MV200_GMAC_MUX, + HI3798MV200_CRG_NR_CLKS, +}; + +static const struct hisi_fixed_rate_clock hi3798mv200_fixed_rate_clks[] = { + { HI3798MV200_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, + { HI3798MV200_APB_CLK, "clk_apb", NULL, 0, 100000000, }, + { HI3798MV200_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798MV200_FIXED_3M, "3m", NULL, 0, 3000000, }, + { HI3798MV200_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798MV200_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3798MV200_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3798MV200_FIXED_27M, "27m", NULL, 0, 27000000, }, + { HI3798MV200_FIXED_48M, "48m", NULL, 0, 48000000, }, + { HI3798MV200_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3798MV200_FIXED_54M, "54m", NULL, 0, 54000000, }, + { HI3798MV200_FIXED_60M, "60m", NULL, 0, 60000000, }, + { HI3798MV200_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798MV200_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3798MV200_FIXED_125M, "125m", NULL, 0, 125000000, }, + { HI3798MV200_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3798MV200_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3798MV200_FIXED_400M, "400m", NULL, 0, 400000000, }, + { HI3798MV200_FIXED_600M, "600m", NULL, 0, 600000000, }, + { HI3798MV200_FIXED_800M, "800m", NULL, 0, 800000000, }, + { HI3798MV200_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, + { HI3798MV200_FIXED_1350M, "1350m", NULL, 0, 1350000000, }, +}; + +static const char *const sdio_mux_p[] = { "100m", "50m", "150m", "25m" }; +static u32 sdio_mux_table[] = {0, 1, 2, 3}; + +static const char *const mmc_mux_p[] = { "100m", "50m", "25m", "200m", "150m" }; +static u32 mmc_mux_table[] = {0, 1, 2, 3, 6}; + +static const char *const cpu_mux_p[] = { "apll", "200m", "800m", "1350m", + "24m", "1200m", "400m", "600m" }; +static u32 cpu_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; + +static const char *const comphy_mux_p[] = { "25m", "100m"}; +static const char *const femac_mux_p[] = { "54m", "27m" }; +static const char *const gmac_mux_p[] = { "125m", "75m" }; +static const char *const ext_netphy_mux_p[] = { "25m", "50m" }; +static const char *const mde1_bus_mux_p[] = { "24m", "200m" }; +static const char *const mde3_bus_mux_p[] = { "24m", "400m" }; +static u32 mux_table_1bit[] = {0, 1}; + +static const char *const core_bus_mux_p[] = { "24m", "200m", "250m" }; +static const char *const mde0_bus_mux_p[] = { "24m", "300m", "400m" }; +static const char *const mde2_bus_mux_p[] = { "24m", "400m", "450m" }; +static u32 mux_table_2bit_pattern1[] = {0, 1, 2}; + +static struct hisi_mux_clock hi3798mv200_mux_clks[] = { + { HI3798MV200_CORE_BUS_CLK, "clk_core_bus", core_bus_mux_p, ARRAY_SIZE(core_bus_mux_p), + 0, 0x58, 0, 2, 0, mux_table_2bit_pattern1, }, + { HI3798MV200_MDE0_BUS_CLK, "clk_mde0_bus", mde0_bus_mux_p, ARRAY_SIZE(mde0_bus_mux_p), + 0, 0x58, 2, 2, 0, mux_table_2bit_pattern1, }, + { HI3798MV200_MDE1_BUS_CLK, "clk_mde1_bus", mde1_bus_mux_p, ARRAY_SIZE(mde1_bus_mux_p), + 0, 0x58, 4, 1, 0, mux_table_1bit, }, + { HI3798MV200_MDE2_BUS_CLK, "clk_mde2_bus", mde2_bus_mux_p, ARRAY_SIZE(mde2_bus_mux_p), + 0, 0x58, 8, 2, 0, mux_table_2bit_pattern1, }, + { HI3798MV200_MDE3_BUS_CLK, "clk_mde3_bus", mde3_bus_mux_p, ARRAY_SIZE(mde3_bus_mux_p), + 0, 0x58, 10, 1, 0, mux_table_1bit, }, + { HI3798MV200_CPU_CLK, "clk_cpu", cpu_mux_p, ARRAY_SIZE(cpu_mux_p), + CLK_SET_RATE_PARENT, 0x48, 0, 3, CLK_MUX_ROUND_CLOSEST, cpu_mux_table }, + { HI3798MV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + 0, 0xa0, 8, 3, CLK_MUX_ROUND_CLOSEST, mmc_mux_table, }, + { HI3798MV200_COMBPHY_MUX, "combphy_mux", comphy_mux_p, + ARRAY_SIZE(comphy_mux_p), 0, 0x188, 3, 1, 0, mux_table_1bit, }, + { HI3798MV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), + 0, 0x9c, 8, 2, CLK_MUX_ROUND_CLOSEST, sdio_mux_table, }, + { HI3798MV200_SDIO1_MUX, "sdio1_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), + 0, 0x28c, 8, 2, CLK_MUX_ROUND_CLOSEST, sdio_mux_table, }, + { HI3798MV200_FEMAC_MUX, "femac_mux", femac_mux_p, ARRAY_SIZE(femac_mux_p), + 0, 0xd0, 2, 1, 0, mux_table_1bit, }, + { HI3798MV200_GMAC_MUX, "gmac_mux", gmac_mux_p, ARRAY_SIZE(gmac_mux_p), + 0, 0xcc, 7, 1, 0, mux_table_1bit, }, + { HI3798MV200_EXT_NETPHY_CLK, "ext_netphy_mux", ext_netphy_mux_p, ARRAY_SIZE(ext_netphy_mux_p), + 0, 0xcc, 6, 1, 0, mux_table_1bit, }, +}; + +static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7}; +static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315}; + +static struct hisi_phase_clock hi3798mv200_phase_clks[] = { + { HI3798MV200_SDIO0_SAMPLE_CLK, "sdio0_sample", "clk_sdio0_ciu", + 0, 0x9c, 12, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HI3798MV200_SDIO0_DRV_CLK, "sdio0_drive", "clk_sdio0_ciu", + 0, 0x9c, 16, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HI3798MV200_SDIO1_SAMPLE_CLK, "sdio1_sample", "clk_sdio1_ciu", + 0, 0x28c, 12, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HI3798MV200_SDIO1_DRV_CLK, "sdio1_drive", "clk_sdio1_ciu", + 0, 0x28c, 16, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HI3798MV200_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", + 0, 0xa0, 12, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HI3798MV200_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", + 0, 0xa0, 16, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, +}; + +static const struct hisi_gate_clock hi3798mv200_gate_clks[] = { + /* UART */ + { HI3798MV200_UART2_CLK, "clk_uart2", "75m", + CLK_SET_RATE_PARENT, 0x68, 4, 0, }, + { HI3798MV200_UART3_CLK, "clk_uart3", "75m", + CLK_SET_RATE_PARENT, 0x68, 6, 0, }, + /* I2C */ + { HI3798MV200_I2C0_CLK, "clk_i2c0", "clk_apb", + CLK_SET_RATE_PARENT, 0x6c, 4, 0, }, + { HI3798MV200_I2C1_CLK, "clk_i2c1", "clk_apb", + CLK_SET_RATE_PARENT, 0x6c, 8, 0, }, + { HI3798MV200_I2C2_CLK, "clk_i2c2", "clk_apb", + CLK_SET_RATE_PARENT, 0x6c, 12, 0, }, + /* SPI */ + { HI3798MV200_SPI0_CLK, "clk_spi0", "clk_apb", + CLK_SET_RATE_PARENT, 0x70, 0, 0, }, + /* SCI */ + { HI3798MV200_SCI0_CLK, "clk_sci0", "clk_apb", + CLK_SET_RATE_PARENT, 0x74, 0, 0, }, + { HI3798MV200_SCI1_CLK, "clk_sci1", "clk_apb", + CLK_SET_RATE_PARENT, 0x74, 2, 0, }, + /* SDIO */ + { HI3798MV200_SDIO0_BIU_CLK, "clk_sdio0_biu", "clk_ahb", + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + { HI3798MV200_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", + CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, + { HI3798MV200_SDIO1_BIU_CLK, "clk_sdio1_biu", "clk_ahb", + CLK_SET_RATE_PARENT, 0x28c, 0, 0, }, + { HI3798MV200_SDIO1_CIU_CLK, "clk_sdio1_ciu", "sdio1_mux", + CLK_SET_RATE_PARENT, 0x28c, 1, 0, }, + /* EMMC */ + { HI3798MV200_MMC_BIU_CLK, "clk_mmc_biu", "clk_ahb", + CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, + { HI3798MV200_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", + CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, + /* Ethernet */ + { HI3798MV200_GMAC_CLK, "clk_gmac", "gmac_mux", + CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, + { HI3798MV200_GSF_CLK, "clk_gmacif", "clk_ahb", + CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, + { HI3798MV200_ETH_CLK, "clk_femac", "femac_mux", + CLK_SET_RATE_PARENT, 0xd0, 1, 0, }, + { HI3798MV200_ETH_BUS_CLK, "clk_femacif", "clk_ahb", + CLK_SET_RATE_PARENT, 0xd0, 0, 0, }, + { HI3798MV200_FEPHY_CLK, "clk_fephy", "25m", + CLK_SET_RATE_PARENT, 0x388, 0, 0, }, + /* COMBPHY */ + { HI3798MV200_COMBPHY_CLK, "clk_combphy", "combphy_mux", + CLK_SET_RATE_PARENT, 0x188, 0, 0, }, + /* USB2 */ + { HI3798MV200_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, + { HI3798MV200_USB2_HST_PHY_CLK, "clk_u2_phy", "60m", + CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, + { HI3798MV200_USB2_12M_CLK, "clk_u2_12m", "12m", + CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, + { HI3798MV200_USB2_48M_CLK, "clk_u2_48m", "48m", + CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, + { HI3798MV200_USB2_UTMI0_CLK, "clk_u2_utmi0", "60m", + CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, + { HI3798MV200_USB2_UTMI1_CLK, "clk_u2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0xb8, 6, 0 }, + { HI3798MV200_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 3, 0 }, + { HI3798MV200_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, + { HI3798MV200_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB3 bus */ + { HI3798MV200_USB3_GM_CLK, "clk_u3_gm", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb0, 6, 0 }, + { HI3798MV200_USB3_GS_CLK, "clk_u3_gs", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb0, 5, 0 }, + { HI3798MV200_USB3_BUS_CLK, "clk_u3_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + /* USB3 ctrl */ + { HI3798MV200_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, + { HI3798MV200_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HI3798MV200_USB3_REF_CLK, "clk_u3_ref", "125m", + CLK_SET_RATE_PARENT, 0xb0, 1, 0 }, + { HI3798MV200_USB3_UTMI_CLK, "clk_u3_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + /* Watchdog */ + { HI3798MV200_WDG0_CLK, "clk_wdg0", "clk_osc", + CLK_SET_RATE_PARENT, 0x178, 0, 0 }, +}; + +static const struct hisi_pll_clock hi3798mv200_plls[] = { + { HI3798MV200_APLL_CLK, "apll", "clk_osc", CLK_IS_CRITICAL, 0x0 }, + { HI3798MV200_BPLL_CLK, "bpll", "clk_osc", CLK_IS_CRITICAL, 0x8 }, + { HI3798MV200_DPLL_CLK, "dpll", "clk_osc", CLK_IS_CRITICAL, 0x10 }, + { HI3798MV200_VPLL_CLK, "vpll", "clk_osc", CLK_IS_CRITICAL, 0x20 }, + { HI3798MV200_HPLL_CLK, "hpll", "clk_osc", CLK_IS_CRITICAL, 0x28 }, + { HI3798MV200_EPLL_CLK, "epll", "clk_osc", CLK_IS_CRITICAL, 0x30 }, + { HI3798MV200_QPLL_CLK, "qpll", "clk_osc", CLK_IS_CRITICAL, 0x38 }, +}; + +static struct hisi_clock_data *hi3798mv200_clk_register( + struct platform_device *pdev) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data = hisi_clk_alloc(pdev, HI3798MV200_CRG_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + /* hisi_phase_clock is resource managed */ + ret = hisi_clk_register_phase(&pdev->dev, + hi3798mv200_phase_clks, + ARRAY_SIZE(hi3798mv200_phase_clks), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_pll(&pdev->dev, + hi3798mv200_plls, + ARRAY_SIZE(hi3798mv200_plls), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_fixed_rate(hi3798mv200_fixed_rate_clks, + ARRAY_SIZE(hi3798mv200_fixed_rate_clks), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_mux(hi3798mv200_mux_clks, + ARRAY_SIZE(hi3798mv200_mux_clks), + clk_data); + if (ret) + goto unregister_fixed_rate; + + ret = hisi_clk_register_gate(hi3798mv200_gate_clks, + ARRAY_SIZE(hi3798mv200_gate_clks), + clk_data); + if (ret) + goto unregister_mux; + + ret = of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(hi3798mv200_gate_clks, + ARRAY_SIZE(hi3798mv200_gate_clks), + clk_data); +unregister_mux: + hisi_clk_unregister_mux(hi3798mv200_mux_clks, + ARRAY_SIZE(hi3798mv200_mux_clks), + clk_data); +unregister_fixed_rate: + hisi_clk_unregister_fixed_rate(hi3798mv200_fixed_rate_clks, + ARRAY_SIZE(hi3798mv200_fixed_rate_clks), + clk_data); + return ERR_PTR(ret); +} + +static void hi3798mv200_clk_unregister(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(hi3798mv200_gate_clks, + ARRAY_SIZE(hi3798mv200_gate_clks), + crg->clk_data); + hisi_clk_unregister_mux(hi3798mv200_mux_clks, + ARRAY_SIZE(hi3798mv200_mux_clks), + crg->clk_data); + hisi_clk_unregister_fixed_rate(hi3798mv200_fixed_rate_clks, + ARRAY_SIZE(hi3798mv200_fixed_rate_clks), + crg->clk_data); +} + +static const struct hisi_crg_funcs hi3798mv200_crg_funcs = { + .register_clks = hi3798mv200_clk_register, + .unregister_clks = hi3798mv200_clk_unregister, +}; + +/* hi3798MV200 sysctrl CRG */ + +enum hi3798mv200_sysctrl_inner_clk { + HI3798MV200_UART0_MUX = HI3798MV200_SYSCTRL_CLK_COUNT, + + HI3798MV200_SYSCTRL_NR_CLKS +}; + +static const char *const uart0_mux_p[] = { "3m", "75m" }; + +static const char *const mcu_bus_mux_p[] = { "24m", "200m", "6m" }; + +static const struct hisi_mux_clock hi3798mv200_sysctrl_mux_clks[] = { + { HI3798MV200_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), + CLK_SET_RATE_PARENT, 0x48, 29, 1, 0, mux_table_1bit, }, + { HI3798MV200_MCU_BUS_CLK, "mcu_bus_mux", mcu_bus_mux_p, ARRAY_SIZE(mcu_bus_mux_p), + CLK_SET_RATE_PARENT, 0x0, 0, 2, 0, mux_table_2bit_pattern1, }, +}; + +static const struct hisi_gate_clock hi3798mv200_sysctrl_gate_clks[] = { + { HI3798MV200_MCE_CLK, "clk_mce", "mcu_bus_mux", + CLK_SET_RATE_PARENT, 0x48, 0, 0, }, + { HI3798MV200_IR_CLK, "clk_ir", "clk_osc", + CLK_SET_RATE_PARENT, 0x48, 4, 0, }, + { HI3798MV200_TIMER01_CLK, "clk_timer01", "clk_osc", + CLK_SET_RATE_PARENT, 0x48, 6, 0, }, + { HI3798MV200_UART0_CLK, "clk_uart0", "uart0_mux", + CLK_SET_RATE_PARENT, 0x48, 12, 0, }, +}; + +static struct hisi_clock_data *hi3798mv200_sysctrl_clk_register( + struct platform_device *pdev) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data = hisi_clk_alloc(pdev, HI3798MV200_SYSCTRL_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + ret = hisi_clk_register_mux(hi3798mv200_sysctrl_mux_clks, + ARRAY_SIZE(hi3798mv200_sysctrl_mux_clks), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_gate(hi3798mv200_sysctrl_gate_clks, + ARRAY_SIZE(hi3798mv200_sysctrl_gate_clks), + clk_data); + if (ret) + goto unregister_mux; + + ret = of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(hi3798mv200_sysctrl_gate_clks, + ARRAY_SIZE(hi3798mv200_sysctrl_gate_clks), + clk_data); +unregister_mux: + hisi_clk_unregister_mux(hi3798mv200_sysctrl_mux_clks, + ARRAY_SIZE(hi3798mv200_sysctrl_mux_clks), + clk_data); + return ERR_PTR(ret); +} + +static void hi3798mv200_sysctrl_clk_unregister(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(hi3798mv200_sysctrl_gate_clks, + ARRAY_SIZE(hi3798mv200_sysctrl_gate_clks), + crg->clk_data); + hisi_clk_unregister_mux(hi3798mv200_sysctrl_mux_clks, + ARRAY_SIZE(hi3798mv200_sysctrl_mux_clks), + crg->clk_data); +} + +static const struct hisi_crg_funcs hi3798mv200_sysctrl_funcs = { + .register_clks = hi3798mv200_sysctrl_clk_register, + .unregister_clks = hi3798mv200_sysctrl_clk_unregister, +}; + +static const struct of_device_id hi3798mv200_crg_match_table[] = { + { .compatible = "hisilicon,hi3798mv200-crg", + .data = &hi3798mv200_crg_funcs }, + { .compatible = "hisilicon,hi3798mv200-sysctrl", + .data = &hi3798mv200_sysctrl_funcs }, + { } +}; +MODULE_DEVICE_TABLE(of, hi3798mv200_crg_match_table); + +static int hi3798mv200_crg_probe(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg; + + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); + if (!crg) + return -ENOMEM; + + crg->funcs = of_device_get_match_data(&pdev->dev); + if (!crg->funcs) + return -ENOENT; + + crg->rstc = hisi_reset_init(pdev); + if (!crg->rstc) + return -ENOMEM; + + crg->clk_data = crg->funcs->register_clks(pdev); + if (IS_ERR(crg->clk_data)) { + hisi_reset_exit(crg->rstc); + return PTR_ERR(crg->clk_data); + } + + platform_set_drvdata(pdev, crg); + return 0; +} + +static int hi3798mv200_crg_remove(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + hisi_reset_exit(crg->rstc); + crg->funcs->unregister_clks(pdev); + return 0; +} + +static struct platform_driver hi3798mv200_crg_driver = { + .probe = hi3798mv200_crg_probe, + .remove = hi3798mv200_crg_remove, + .driver = { + .name = "hi3798mv200-crg", + .of_match_table = hi3798mv200_crg_match_table, + }, +}; + +static int __init hi3798mv200_crg_init(void) +{ + return platform_driver_register(&hi3798mv200_crg_driver); +} +core_initcall(hi3798mv200_crg_init); + +static void __exit hi3798mv200_crg_exit(void) +{ + platform_driver_unregister(&hi3798mv200_crg_driver); +} +module_exit(hi3798mv200_crg_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HiSilicon Hi3798MV200 CRG Driver"); diff --git a/include/dt-bindings/clock/hisilicon,hi3798cv200-crg.h b/include/dt-bindings/clock/hisilicon,hi3798cv200-crg.h new file mode 100644 index 00000000000000..7cd8b5d053de35 --- /dev/null +++ b/include/dt-bindings/clock/hisilicon,hi3798cv200-crg.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI3798CV200_CRG_H +#define __DT_BINDINGS_CLOCK_HI3798CV200_CRG_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 +#define HISTB_USB2_BUS_CLK 34 +#define HISTB_USB2_PHY_CLK 35 +#define HISTB_USB2_UTMI_CLK 36 +#define HISTB_USB2_12M_CLK 37 +#define HISTB_USB2_48M_CLK 38 +#define HISTB_USB2_OTG_UTMI_CLK 39 +#define HISTB_USB2_PHY1_REF_CLK 40 +#define HISTB_USB2_PHY2_REF_CLK 41 +#define HISTB_COMBPHY0_CLK 42 +#define HISTB_USB3_BUS_CLK 43 +#define HISTB_USB3_UTMI_CLK 44 +#define HISTB_USB3_PIPE_CLK 45 +#define HISTB_USB3_SUSPEND_CLK 46 +#define HISTB_USB3_BUS_CLK1 47 +#define HISTB_USB3_UTMI_CLK1 48 +#define HISTB_USB3_PIPE_CLK1 49 +#define HISTB_USB3_SUSPEND_CLK1 50 + +#endif /* __DT_BINDINGS_CLOCK_HI3798CV200_CRG_H */ diff --git a/include/dt-bindings/clock/hisilicon,hi3798cv200-sysctrl.h b/include/dt-bindings/clock/hisilicon,hi3798cv200-sysctrl.h new file mode 100644 index 00000000000000..e908b30bb8cee3 --- /dev/null +++ b/include/dt-bindings/clock/hisilicon,hi3798cv200-sysctrl.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI3798CV200_SYSCTRL_H +#define __DT_BINDINGS_CLOCK_HI3798CV200_SYSCTRL_H + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DT_BINDINGS_CLOCK_HI3798CV200_SYSCTRL_H */ diff --git a/include/dt-bindings/clock/hisilicon,hi3798mv200-crg.h b/include/dt-bindings/clock/hisilicon,hi3798mv200-crg.h new file mode 100644 index 00000000000000..c860940142bd3e --- /dev/null +++ b/include/dt-bindings/clock/hisilicon,hi3798mv200-crg.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Yang Xiwen + */ + +#ifndef __DT_BINDINGS_CLOCK_HI3798MV200_CRG_H +#define __DT_BINDINGS_CLOCK_HI3798MV200_CRG_H + +/* clocks provided by core CRG */ +#define HI3798MV200_OSC_CLK 0 +#define HI3798MV200_APB_CLK 1 +#define HI3798MV200_AHB_CLK 2 +#define HI3798MV200_APLL_CLK 3 +#define HI3798MV200_BPLL_CLK 4 +#define HI3798MV200_DPLL_CLK 5 +#define HI3798MV200_VPLL_CLK 6 +#define HI3798MV200_HPLL_CLK 7 +#define HI3798MV200_EPLL_CLK 8 +#define HI3798MV200_QPLL_CLK 9 +#define HI3798MV200_PERI_DIV_CLK 10 +#define HI3798MV200_CORE_BUS_CLK 11 +#define HI3798MV200_MDE0_BUS_CLK 12 +#define HI3798MV200_MDE1_BUS_CLK 13 +#define HI3798MV200_MDE2_BUS_CLK 14 +#define HI3798MV200_MDE3_BUS_CLK 15 +#define HI3798MV200_CPU_CLK 16 +/* UART1 does not exist */ +#define HI3798MV200_UART2_CLK 17 +#define HI3798MV200_UART3_CLK 18 +#define HI3798MV200_I2C0_CLK 19 +#define HI3798MV200_I2C1_CLK 20 +#define HI3798MV200_I2C2_CLK 21 +#define HI3798MV200_SPI0_CLK 22 +#define HI3798MV200_SCI0_CLK 23 +#define HI3798MV200_SCI1_CLK 24 +#define HI3798MV200_VDH_CLK 25 +#define HI3798MV200_VDH_DSP_CLK 26 +#define HI3798MV200_JPGD_CLK 27 +#define HI3798MV200_PGD_CLK 28 +#define HI3798MV200_BPD_CLK 29 +#define HI3798MV200_VENV_CLK 30 +#define HI3798MV200_VENV_AXI_CLK 31 +#define HI3798MV200_JPGE_CLK 32 +#define HI3798MV200_TDE_CLK 33 +#define HI3798MV200_SDIO0_BIU_CLK 34 +#define HI3798MV200_SDIO0_CIU_CLK 35 +#define HI3798MV200_SDIO0_DRV_CLK 36 +#define HI3798MV200_SDIO0_SAMPLE_CLK 37 +#define HI3798MV200_MMC_BIU_CLK 38 +#define HI3798MV200_MMC_CIU_CLK 39 +#define HI3798MV200_MMC_DRV_CLK 40 +#define HI3798MV200_MMC_SAMPLE_CLK 41 +#define HI3798MV200_SATA_CLK 42 +#define HI3798MV200_SATA_RX_CLK 43 +#define HI3798MV200_SATA_CKO_ALIVE_CLK 44 +#define HI3798MV200_SATA_TX_CLK 45 +#define HI3798MV200_USB3_BUS_CLK 46 +#define HI3798MV200_USB3_REF_CLK 47 +#define HI3798MV200_USB3_SUSPEND_CLK 48 +#define HI3798MV200_USB3_PIPE_CLK 49 +#define HI3798MV200_USB3_UTMI_CLK 50 +#define HI3798MV200_USB3_GS_CLK 51 +#define HI3798MV200_USB3_GM_CLK 52 +#define HI3798MV200_USB2_BUS_CLK 53 +#define HI3798MV200_USB2_48M_CLK 54 +#define HI3798MV200_USB2_12M_CLK 55 +#define HI3798MV200_USB2_OTG_UTMI_CLK 56 +#define HI3798MV200_USB2_HST_PHY_CLK 57 +#define HI3798MV200_USB2_UTMI0_CLK 58 +#define HI3798MV200_USB2_UTMI1_CLK 59 +#define HI3798MV200_USB2_PHY1_REF_CLK 60 +#define HI3798MV200_USB2_PHY2_REF_CLK 61 +#define HI3798MV200_SHA0_CLK 62 +#define HI3798MV200_SHA1_CLK 63 +#define HI3798MV200_PMC_CLK 64 +#define HI3798MV200_GSF_CLK 65 +#define HI3798MV200_GMAC_CLK 66 +#define HI3798MV200_EXT_NETPHY_CLK 67 +#define HI3798MV200_ETH_BUS_CLK 68 +#define HI3798MV200_ETH_CLK 69 +#define HI3798MV200_GPU_CLK 70 +#define HI3798MV200_VO_BUS 71 +#define HI3798MV200_VO_SD 72 +#define HI3798MV200_VO_SDATE 73 +#define HI3798MV200_VDAC_CH0_CLK 74 +#define HI3798MV200_VO_HD 75 +#define HI3798MV200_VDP_CLK 76 +#define HI3798MV200_VDP_CFG_CLK 77 +#define HI3798MV200_VPSS_CLK 78 +#define HI3798MV200_PVR_BUS_CLK 79 +#define HI3798MV200_PVR_DMX_CLK 80 +#define HI3798MV200_PVR_27M_CLK 81 +#define HI3798MV200_PVR_TSI1_CLK 82 +#define HI3798MV200_PVR_TSI2_CLK 83 +#define HI3798MV200_PVR_TSI3_CLK 84 +#define HI3798MV200_PVR_TSI4_CLK 85 +#define HI3798MV200_PVR_TS0_CLK 86 +#define HI3798MV200_PVR_TSOUT0_CLK 87 +#define HI3798MV200_HDMITX_SSC_CLK 88 +#define HI3798MV200_HDMITX_SSC_BYPASS_CLK 89 +#define HI3798MV200_HDMITX_CTRL_24M_CLK 90 +#define HI3798MV200_HDMITX_CTRL_CEC_CLK 91 +#define HI3798MV200_HDMITX_CTRL_60M_CLK 92 +#define HI3798MV200_HDMITX_CTRL_AS_CLK 93 +#define HI3798MV200_HDMITX_PHY_TMDS_CLK 94 +#define HI3798MV200_ADAC_CLK 95 +#define HI3798MV200_AIAO_CLK 96 +#define HI3798MV200_VDAC_CHOP_CLK 97 +#define HI3798MV200_WDG0_CLK 98 +#define HI3798MV200_COMBPHY_CLK 99 +#define HI3798MV200_PCIE_BUS_CLK 100 +#define HI3798MV200_PCIE_SYS_CLK 101 +#define HI3798MV200_PCIE_PIPE_CLK 102 +#define HI3798MV200_PCIE_AUX_CLK 103 +#define HI3798MV200_SDIO1_BIU_CLK 104 +#define HI3798MV200_SDIO1_CIU_CLK 105 +#define HI3798MV200_SDIO1_DRV_CLK 106 +#define HI3798MV200_SDIO1_SAMPLE_CLK 107 +#define HI3798MV200_VENC_SMMU_CLK 108 +#define HI3798MV200_TDE_SMMU_CLK 109 +#define HI3798MV200_JPGD_SMMU_CLK 110 +#define HI3798MV200_VDH_SMMU_CLK 111 +#define HI3798MV200_VDP_SMMU_CLK 112 +#define HI3798MV200_VPSS_SMMU_CLK 113 +#define HI3798MV200_PGD_SMMU_CLK 114 +#define HI3798MV200_VO_BP_CLK 115 +#define HI3798MV200_VDP_G4_CLK 116 +#define HI3798MV200_VDP_V3_CLK 117 +#define HI3798MV200_VDP_SD_CLK 118 +#define HI3798MV200_VDP_WBC_CP_CLK 119 +#define HI3798MV200_VDP_WBC_GP_CLK 120 +#define HI3798MV200_VDP_WBC_HD_CLK 121 +#define HI3798MV200_VDP_G3_CLK 122 +#define HI3798MV200_VDP_G1_CLK 123 +#define HI3798MV200_VDP_G0_CLK 124 +#define HI3798MV200_VDP_V1_CLK 125 +#define HI3798MV200_VDP_V0_CLK 126 +#define HI3798MV200_VDP_HD_CLK 127 +#define HI3798MV200_CIPHER_SMMU_CLK 128 +#define HI3798MV200_FMC_CLK 129 +#define HI3798MV200_FEPHY_CLK 130 +#define HI3798MV200_DMAC_CLK 131 +#define HI3798MV200_GZIP_CLK 132 +#define HI3798MV200_GZIP_AXI_CLK 133 +#define HI3798MV200_GZIP_APB_CLK 134 +#define HI3798MV200_PM_CLK 135 +#define HI3798MV200_FRACDIV_CLK 136 + +#define HI3798MV200_CRG_CLK_COUNT 137 + +#endif /* __DT_BINDINGS_CLOCK_HI3798MV200_CRG_H */ diff --git a/include/dt-bindings/clock/hisilicon,hi3798mv200-sysctrl.h b/include/dt-bindings/clock/hisilicon,hi3798mv200-sysctrl.h new file mode 100644 index 00000000000000..185e4b701e234e --- /dev/null +++ b/include/dt-bindings/clock/hisilicon,hi3798mv200-sysctrl.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Yang Xiwen + */ + +#ifndef __DT_BINDINGS_CLOCK_HI3798MV200_SYSCTRL_H +#define __DT_BINDINGS_CLOCK_HI3798MV200_SYSCTRL_H + +/* clocks provided by mcu CRG */ +#define HI3798MV200_MCU_BUS_CLK 0 +#define HI3798MV200_MCE_CLK 1 +#define HI3798MV200_IR_CLK 2 +#define HI3798MV200_TIMER01_CLK 3 +#define HI3798MV200_LEDC_CLK 4 +#define HI3798MV200_UART0_CLK 5 +#define HI3798MV200_WIFI_CLK 6 +#define HI3798MV200_LSADC_CLK 7 + +#define HI3798MV200_SYSCTRL_CLK_COUNT 8 + +#endif /* __DT_BINDINGS_CLOCK_HI3798MV200_SYSCTRL_H */ diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index e64e5770ada643..def617ebe85294 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -1,70 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * DEPRECATED + * + * Each CRG driver should have its own clock number definitions header file. + * This file is only reserved for backward compatibility for Hi3798CV200 */ #ifndef __DTS_HISTB_CLOCK_H #define __DTS_HISTB_CLOCK_H -/* clocks provided by core CRG */ -#define HISTB_OSC_CLK 0 -#define HISTB_APB_CLK 1 -#define HISTB_AHB_CLK 2 -#define HISTB_UART1_CLK 3 -#define HISTB_UART2_CLK 4 -#define HISTB_UART3_CLK 5 -#define HISTB_I2C0_CLK 6 -#define HISTB_I2C1_CLK 7 -#define HISTB_I2C2_CLK 8 -#define HISTB_I2C3_CLK 9 -#define HISTB_I2C4_CLK 10 -#define HISTB_I2C5_CLK 11 -#define HISTB_SPI0_CLK 12 -#define HISTB_SPI1_CLK 13 -#define HISTB_SPI2_CLK 14 -#define HISTB_SCI_CLK 15 -#define HISTB_FMC_CLK 16 -#define HISTB_MMC_BIU_CLK 17 -#define HISTB_MMC_CIU_CLK 18 -#define HISTB_MMC_DRV_CLK 19 -#define HISTB_MMC_SAMPLE_CLK 20 -#define HISTB_SDIO0_BIU_CLK 21 -#define HISTB_SDIO0_CIU_CLK 22 -#define HISTB_SDIO0_DRV_CLK 23 -#define HISTB_SDIO0_SAMPLE_CLK 24 -#define HISTB_PCIE_AUX_CLK 25 -#define HISTB_PCIE_PIPE_CLK 26 -#define HISTB_PCIE_SYS_CLK 27 -#define HISTB_PCIE_BUS_CLK 28 -#define HISTB_ETH0_MAC_CLK 29 -#define HISTB_ETH0_MACIF_CLK 30 -#define HISTB_ETH1_MAC_CLK 31 -#define HISTB_ETH1_MACIF_CLK 32 -#define HISTB_COMBPHY1_CLK 33 -#define HISTB_USB2_BUS_CLK 34 -#define HISTB_USB2_PHY_CLK 35 -#define HISTB_USB2_UTMI_CLK 36 -#define HISTB_USB2_12M_CLK 37 -#define HISTB_USB2_48M_CLK 38 -#define HISTB_USB2_OTG_UTMI_CLK 39 -#define HISTB_USB2_PHY1_REF_CLK 40 -#define HISTB_USB2_PHY2_REF_CLK 41 -#define HISTB_COMBPHY0_CLK 42 -#define HISTB_USB3_BUS_CLK 43 -#define HISTB_USB3_UTMI_CLK 44 -#define HISTB_USB3_PIPE_CLK 45 -#define HISTB_USB3_SUSPEND_CLK 46 -#define HISTB_USB3_BUS_CLK1 47 -#define HISTB_USB3_UTMI_CLK1 48 -#define HISTB_USB3_PIPE_CLK1 49 -#define HISTB_USB3_SUSPEND_CLK1 50 +#warning "This header file is deprecated, include hisilicon,hi3798cv200-crg.h \ +and hisilicon,hi3798cv200-sysctrl.h directly instead" -/* clocks provided by mcu CRG */ -#define HISTB_MCE_CLK 1 -#define HISTB_IR_CLK 2 -#define HISTB_TIMER01_CLK 3 -#define HISTB_LEDC_CLK 4 -#define HISTB_UART0_CLK 5 -#define HISTB_LSADC_CLK 6 +#include "hisilicon,hi3798cv200-crg.h" +#include "hisilicon,hi3798cv200-sysctrl.h" -#endif /* __DTS_HISTB_CLOCK_H */ +#endif /* __DTS_HISTB_CLOCK_H */