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main.h
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main.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#ifndef __RTK_MAIN_H_
#define __RTK_MAIN_H_
#include <linux/version.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0)
#include "compiler.h"
#endif
#include <net/mac80211.h>
#include <linux/vmalloc.h>
#include <linux/firmware.h>
#include <linux/average.h>
#include <linux/bitops.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
#include <linux/bitfield.h>
#else
#include "bitfield.h"
#endif
#include <linux/iopoll.h>
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include "util.h"
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)
#include <linux/etherdevice.h>
#endif
#if !defined(RHEL_RELEASE_CODE)
#define RHEL_RELEASE_CODE 0
#define RHEL_RELEASE_VERSION(a, b) a<<8 & b
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0)
/**
* cfg80211_ssid_eq - compare two SSIDs
* @a: first SSID
* @b: second SSID
*
* Return: %true if SSIDs are equal, %false otherwise.
*/
static inline bool
cfg80211_ssid_eq(struct cfg80211_ssid *a, struct cfg80211_ssid *b)
{
if (WARN_ON(!a || !b))
return false;
if (a->ssid_len != b->ssid_len)
return false;
return memcmp(a->ssid, b->ssid, a->ssid_len) ? false : true;
}
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) || defined(RHEL_RELEASE) && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(8,0))
/* see Documentation/timers/timers-howto.rst for the thresholds */
static inline void fsleep(unsigned long usecs)
{
if (usecs <= 10)
udelay(usecs);
else if (usecs <= 20000)
usleep_range(usecs, 2 * usecs);
else
msleep(DIV_ROUND_UP(usecs, 1000));
}
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)
#define NUM_NL80211_BANDS IEEE80211_NUM_BANDS
#endif
#define RTW_MAX_MAC_ID_NUM 32
#define RTW_MAX_SEC_CAM_NUM 32
#define MAX_PG_CAM_BACKUP_NUM 8
#define RTW_SCAN_MAX_SSIDS 4
#define RTW_MAX_PATTERN_NUM 12
#define RTW_MAX_PATTERN_MASK_SIZE 16
#define RTW_MAX_PATTERN_SIZE 128
#define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
#define RFREG_MASK 0xfffff
#define INV_RF_DATA 0xffffffff
#define TX_PAGE_SIZE_SHIFT 7
#define TX_PAGE_SIZE (1 << TX_PAGE_SIZE_SHIFT)
#define RTW_CHANNEL_WIDTH_MAX 3
#define RTW_RF_PATH_MAX 4
#define HW_FEATURE_LEN 13
#define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
extern bool rtw_bf_support;
extern bool rtw_disable_lps_deep_mode;
extern unsigned int rtw_debug_mask;
extern bool rtw_edcca_enabled;
extern const struct ieee80211_ops rtw_ops;
#define RTW_MAX_CHANNEL_NUM_2G 14
#define RTW_MAX_CHANNEL_NUM_5G 49
struct rtw_dev;
struct rtw_debugfs;
enum rtw_hci_type {
RTW_HCI_TYPE_PCIE,
RTW_HCI_TYPE_USB,
RTW_HCI_TYPE_SDIO,
RTW_HCI_TYPE_UNDEFINE,
};
struct rtw_hci {
struct rtw_hci_ops *ops;
enum rtw_hci_type type;
u32 rpwm_addr;
u32 cpwm_addr;
u8 bulkout_num;
};
#define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
#define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
#define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
#define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
#define IS_CH_5G_BAND_MID(channel) \
(IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
#define IS_CH_2G_BAND(channel) ((channel) <= 14)
#define IS_CH_5G_BAND(channel) \
(IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
enum rtw_supported_band {
RTW_BAND_2G = BIT(NL80211_BAND_2GHZ),
RTW_BAND_5G = BIT(NL80211_BAND_5GHZ),
RTW_BAND_60G = BIT(NL80211_BAND_60GHZ),
};
/* now, support up to 80M bw */
#define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
enum rtw_bandwidth {
RTW_CHANNEL_WIDTH_20 = 0,
RTW_CHANNEL_WIDTH_40 = 1,
RTW_CHANNEL_WIDTH_80 = 2,
RTW_CHANNEL_WIDTH_160 = 3,
RTW_CHANNEL_WIDTH_80_80 = 4,
RTW_CHANNEL_WIDTH_5 = 5,
RTW_CHANNEL_WIDTH_10 = 6,
};
enum rtw_sc_offset {
RTW_SC_DONT_CARE = 0,
RTW_SC_20_UPPER = 1,
RTW_SC_20_LOWER = 2,
RTW_SC_20_UPMOST = 3,
RTW_SC_20_LOWEST = 4,
RTW_SC_40_UPPER = 9,
RTW_SC_40_LOWER = 10,
};
enum rtw_net_type {
RTW_NET_NO_LINK = 0,
RTW_NET_AD_HOC = 1,
RTW_NET_MGD_LINKED = 2,
RTW_NET_AP_MODE = 3,
};
enum rtw_rf_type {
RF_1T1R = 0,
RF_1T2R = 1,
RF_2T2R = 2,
RF_2T3R = 3,
RF_2T4R = 4,
RF_3T3R = 5,
RF_3T4R = 6,
RF_4T4R = 7,
RF_TYPE_MAX,
};
enum rtw_rf_path {
RF_PATH_A = 0,
RF_PATH_B = 1,
RF_PATH_C = 2,
RF_PATH_D = 3,
};
enum rtw_bb_path {
BB_PATH_A = BIT(0),
BB_PATH_B = BIT(1),
BB_PATH_C = BIT(2),
BB_PATH_D = BIT(3),
BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
};
enum rtw_rate_section {
RTW_RATE_SECTION_CCK = 0,
RTW_RATE_SECTION_OFDM,
RTW_RATE_SECTION_HT_1S,
RTW_RATE_SECTION_HT_2S,
RTW_RATE_SECTION_VHT_1S,
RTW_RATE_SECTION_VHT_2S,
/* keep last */
RTW_RATE_SECTION_MAX,
};
enum rtw_wireless_set {
WIRELESS_CCK = 0x00000001,
WIRELESS_OFDM = 0x00000002,
WIRELESS_HT = 0x00000004,
WIRELESS_VHT = 0x00000008,
};
#define HT_STBC_EN BIT(0)
#define VHT_STBC_EN BIT(1)
#define HT_LDPC_EN BIT(0)
#define VHT_LDPC_EN BIT(1)
enum rtw_chip_type {
RTW_CHIP_TYPE_8822B,
RTW_CHIP_TYPE_8822C,
RTW_CHIP_TYPE_8723D,
RTW_CHIP_TYPE_8821C,
RTW_CHIP_TYPE_8703B,
};
enum rtw_tx_queue_type {
/* the order of AC queues matters */
RTW_TX_QUEUE_BK = 0x0,
RTW_TX_QUEUE_BE = 0x1,
RTW_TX_QUEUE_VI = 0x2,
RTW_TX_QUEUE_VO = 0x3,
RTW_TX_QUEUE_BCN = 0x4,
RTW_TX_QUEUE_MGMT = 0x5,
RTW_TX_QUEUE_HI0 = 0x6,
RTW_TX_QUEUE_H2C = 0x7,
/* keep it last */
RTK_MAX_TX_QUEUE_NUM
};
enum rtw_rx_queue_type {
RTW_RX_QUEUE_MPDU = 0x0,
RTW_RX_QUEUE_C2H = 0x1,
/* keep it last */
RTK_MAX_RX_QUEUE_NUM
};
enum rtw_fw_type {
RTW_NORMAL_FW = 0x0,
RTW_WOWLAN_FW = 0x1,
};
enum rtw_rate_index {
RTW_RATEID_BGN_40M_2SS = 0,
RTW_RATEID_BGN_40M_1SS = 1,
RTW_RATEID_BGN_20M_2SS = 2,
RTW_RATEID_BGN_20M_1SS = 3,
RTW_RATEID_GN_N2SS = 4,
RTW_RATEID_GN_N1SS = 5,
RTW_RATEID_BG = 6,
RTW_RATEID_G = 7,
RTW_RATEID_B_20M = 8,
RTW_RATEID_ARFR0_AC_2SS = 9,
RTW_RATEID_ARFR1_AC_1SS = 10,
RTW_RATEID_ARFR2_AC_2G_1SS = 11,
RTW_RATEID_ARFR3_AC_2G_2SS = 12,
RTW_RATEID_ARFR4_AC_3SS = 13,
RTW_RATEID_ARFR5_N_3SS = 14,
RTW_RATEID_ARFR7_N_4SS = 15,
RTW_RATEID_ARFR6_AC_4SS = 16
};
enum rtw_trx_desc_rate {
DESC_RATE1M = 0x00,
DESC_RATE2M = 0x01,
DESC_RATE5_5M = 0x02,
DESC_RATE11M = 0x03,
DESC_RATE6M = 0x04,
DESC_RATE9M = 0x05,
DESC_RATE12M = 0x06,
DESC_RATE18M = 0x07,
DESC_RATE24M = 0x08,
DESC_RATE36M = 0x09,
DESC_RATE48M = 0x0a,
DESC_RATE54M = 0x0b,
DESC_RATEMCS0 = 0x0c,
DESC_RATEMCS1 = 0x0d,
DESC_RATEMCS2 = 0x0e,
DESC_RATEMCS3 = 0x0f,
DESC_RATEMCS4 = 0x10,
DESC_RATEMCS5 = 0x11,
DESC_RATEMCS6 = 0x12,
DESC_RATEMCS7 = 0x13,
DESC_RATEMCS8 = 0x14,
DESC_RATEMCS9 = 0x15,
DESC_RATEMCS10 = 0x16,
DESC_RATEMCS11 = 0x17,
DESC_RATEMCS12 = 0x18,
DESC_RATEMCS13 = 0x19,
DESC_RATEMCS14 = 0x1a,
DESC_RATEMCS15 = 0x1b,
DESC_RATEMCS16 = 0x1c,
DESC_RATEMCS17 = 0x1d,
DESC_RATEMCS18 = 0x1e,
DESC_RATEMCS19 = 0x1f,
DESC_RATEMCS20 = 0x20,
DESC_RATEMCS21 = 0x21,
DESC_RATEMCS22 = 0x22,
DESC_RATEMCS23 = 0x23,
DESC_RATEMCS24 = 0x24,
DESC_RATEMCS25 = 0x25,
DESC_RATEMCS26 = 0x26,
DESC_RATEMCS27 = 0x27,
DESC_RATEMCS28 = 0x28,
DESC_RATEMCS29 = 0x29,
DESC_RATEMCS30 = 0x2a,
DESC_RATEMCS31 = 0x2b,
DESC_RATEVHT1SS_MCS0 = 0x2c,
DESC_RATEVHT1SS_MCS1 = 0x2d,
DESC_RATEVHT1SS_MCS2 = 0x2e,
DESC_RATEVHT1SS_MCS3 = 0x2f,
DESC_RATEVHT1SS_MCS4 = 0x30,
DESC_RATEVHT1SS_MCS5 = 0x31,
DESC_RATEVHT1SS_MCS6 = 0x32,
DESC_RATEVHT1SS_MCS7 = 0x33,
DESC_RATEVHT1SS_MCS8 = 0x34,
DESC_RATEVHT1SS_MCS9 = 0x35,
DESC_RATEVHT2SS_MCS0 = 0x36,
DESC_RATEVHT2SS_MCS1 = 0x37,
DESC_RATEVHT2SS_MCS2 = 0x38,
DESC_RATEVHT2SS_MCS3 = 0x39,
DESC_RATEVHT2SS_MCS4 = 0x3a,
DESC_RATEVHT2SS_MCS5 = 0x3b,
DESC_RATEVHT2SS_MCS6 = 0x3c,
DESC_RATEVHT2SS_MCS7 = 0x3d,
DESC_RATEVHT2SS_MCS8 = 0x3e,
DESC_RATEVHT2SS_MCS9 = 0x3f,
DESC_RATEVHT3SS_MCS0 = 0x40,
DESC_RATEVHT3SS_MCS1 = 0x41,
DESC_RATEVHT3SS_MCS2 = 0x42,
DESC_RATEVHT3SS_MCS3 = 0x43,
DESC_RATEVHT3SS_MCS4 = 0x44,
DESC_RATEVHT3SS_MCS5 = 0x45,
DESC_RATEVHT3SS_MCS6 = 0x46,
DESC_RATEVHT3SS_MCS7 = 0x47,
DESC_RATEVHT3SS_MCS8 = 0x48,
DESC_RATEVHT3SS_MCS9 = 0x49,
DESC_RATEVHT4SS_MCS0 = 0x4a,
DESC_RATEVHT4SS_MCS1 = 0x4b,
DESC_RATEVHT4SS_MCS2 = 0x4c,
DESC_RATEVHT4SS_MCS3 = 0x4d,
DESC_RATEVHT4SS_MCS4 = 0x4e,
DESC_RATEVHT4SS_MCS5 = 0x4f,
DESC_RATEVHT4SS_MCS6 = 0x50,
DESC_RATEVHT4SS_MCS7 = 0x51,
DESC_RATEVHT4SS_MCS8 = 0x52,
DESC_RATEVHT4SS_MCS9 = 0x53,
DESC_RATE_MAX,
};
enum rtw_regulatory_domains {
RTW_REGD_FCC = 0,
RTW_REGD_MKK = 1,
RTW_REGD_ETSI = 2,
RTW_REGD_IC = 3,
RTW_REGD_KCC = 4,
RTW_REGD_ACMA = 5,
RTW_REGD_CHILE = 6,
RTW_REGD_UKRAINE = 7,
RTW_REGD_MEXICO = 8,
RTW_REGD_CN = 9,
RTW_REGD_QATAR = 10,
RTW_REGD_UK = 11,
RTW_REGD_WW,
RTW_REGD_MAX
};
enum rtw_txq_flags {
RTW_TXQ_AMPDU,
RTW_TXQ_BLOCK_BA,
};
enum rtw_flags {
RTW_FLAG_RUNNING,
RTW_FLAG_FW_RUNNING,
RTW_FLAG_SCANNING,
RTW_FLAG_POWERON,
RTW_FLAG_LEISURE_PS,
RTW_FLAG_LEISURE_PS_DEEP,
RTW_FLAG_DIG_DISABLE,
RTW_FLAG_BUSY_TRAFFIC,
RTW_FLAG_WOWLAN,
RTW_FLAG_RESTARTING,
RTW_FLAG_RESTART_TRIGGERING,
RTW_FLAG_FORCE_LOWEST_RATE,
NUM_OF_RTW_FLAGS,
};
enum rtw_evm {
RTW_EVM_OFDM = 0,
RTW_EVM_1SS,
RTW_EVM_2SS_A,
RTW_EVM_2SS_B,
/* keep it last */
RTW_EVM_NUM
};
enum rtw_snr {
RTW_SNR_OFDM_A = 0,
RTW_SNR_OFDM_B,
RTW_SNR_OFDM_C,
RTW_SNR_OFDM_D,
RTW_SNR_1SS_A,
RTW_SNR_1SS_B,
RTW_SNR_1SS_C,
RTW_SNR_1SS_D,
RTW_SNR_2SS_A,
RTW_SNR_2SS_B,
RTW_SNR_2SS_C,
RTW_SNR_2SS_D,
/* keep it last */
RTW_SNR_NUM
};
enum rtw_port {
RTW_PORT_0 = 0,
RTW_PORT_1 = 1,
RTW_PORT_2 = 2,
RTW_PORT_3 = 3,
RTW_PORT_4 = 4,
RTW_PORT_NUM
};
enum rtw_wow_flags {
RTW_WOW_FLAG_EN_MAGIC_PKT,
RTW_WOW_FLAG_EN_REKEY_PKT,
RTW_WOW_FLAG_EN_DISCONNECT,
/* keep it last */
RTW_WOW_FLAG_MAX,
};
/* the power index is represented by differences, which cck-1s & ht40-1s are
* the base values, so for 1s's differences, there are only ht20 & ofdm
*/
struct rtw_2g_1s_pwr_idx_diff {
#ifdef __LITTLE_ENDIAN
s8 ofdm:4;
s8 bw20:4;
#else
s8 bw20:4;
s8 ofdm:4;
#endif
} __packed;
struct rtw_2g_ns_pwr_idx_diff {
#ifdef __LITTLE_ENDIAN
s8 bw20:4;
s8 bw40:4;
s8 cck:4;
s8 ofdm:4;
#else
s8 ofdm:4;
s8 cck:4;
s8 bw40:4;
s8 bw20:4;
#endif
} __packed;
struct rtw_2g_txpwr_idx {
u8 cck_base[6];
u8 bw40_base[5];
struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
};
struct rtw_5g_ht_1s_pwr_idx_diff {
#ifdef __LITTLE_ENDIAN
s8 ofdm:4;
s8 bw20:4;
#else
s8 bw20:4;
s8 ofdm:4;
#endif
} __packed;
struct rtw_5g_ht_ns_pwr_idx_diff {
#ifdef __LITTLE_ENDIAN
s8 bw20:4;
s8 bw40:4;
#else
s8 bw40:4;
s8 bw20:4;
#endif
} __packed;
struct rtw_5g_ofdm_ns_pwr_idx_diff {
#ifdef __LITTLE_ENDIAN
s8 ofdm_3s:4;
s8 ofdm_2s:4;
s8 ofdm_4s:4;
s8 res:4;
#else
s8 res:4;
s8 ofdm_4s:4;
s8 ofdm_2s:4;
s8 ofdm_3s:4;
#endif
} __packed;
struct rtw_5g_vht_ns_pwr_idx_diff {
#ifdef __LITTLE_ENDIAN
s8 bw160:4;
s8 bw80:4;
#else
s8 bw80:4;
s8 bw160:4;
#endif
} __packed;
struct rtw_5g_txpwr_idx {
u8 bw40_base[14];
struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
};
struct rtw_txpwr_idx {
struct rtw_2g_txpwr_idx pwr_idx_2g;
struct rtw_5g_txpwr_idx pwr_idx_5g;
};
struct rtw_channel_params {
u8 center_chan;
u8 primary_chan;
u8 bandwidth;
};
struct rtw_hw_reg {
u32 addr;
u32 mask;
};
struct rtw_hw_reg_desc {
u32 addr;
u32 mask;
const char *desc;
};
struct rtw_ltecoex_addr {
u32 ctrl;
u32 wdata;
u32 rdata;
};
struct rtw_reg_domain {
u32 addr;
u32 mask;
#define RTW_REG_DOMAIN_MAC32 0
#define RTW_REG_DOMAIN_MAC16 1
#define RTW_REG_DOMAIN_MAC8 2
#define RTW_REG_DOMAIN_RF_A 3
#define RTW_REG_DOMAIN_RF_B 4
#define RTW_REG_DOMAIN_NL 0xFF
u8 domain;
};
struct rtw_rf_sipi_addr {
u32 hssi_1;
u32 hssi_2;
u32 lssi_read;
u32 lssi_read_pi;
};
struct rtw_hw_reg_offset {
struct rtw_hw_reg hw_reg;
u8 offset;
};
struct rtw_backup_info {
u8 len;
u32 reg;
u32 val;
};
enum rtw_vif_port_set {
PORT_SET_MAC_ADDR = BIT(0),
PORT_SET_BSSID = BIT(1),
PORT_SET_NET_TYPE = BIT(2),
PORT_SET_AID = BIT(3),
PORT_SET_BCN_CTRL = BIT(4),
};
struct rtw_vif_port {
struct rtw_hw_reg mac_addr;
struct rtw_hw_reg bssid;
struct rtw_hw_reg net_type;
struct rtw_hw_reg aid;
struct rtw_hw_reg bcn_ctrl;
};
struct rtw_tx_pkt_info {
u32 tx_pkt_size;
u8 offset;
u8 pkt_offset;
u8 tim_offset;
u8 mac_id;
u8 rate_id;
u8 rate;
u8 qsel;
u8 bw;
u8 sec_type;
u8 sn;
bool ampdu_en;
u8 ampdu_factor;
u8 ampdu_density;
u16 seq;
bool stbc;
bool ldpc;
bool dis_rate_fallback;
bool bmc;
bool use_rate;
bool ls;
bool fs;
bool short_gi;
bool report;
bool rts;
bool dis_qselseq;
bool en_hwseq;
u8 hw_ssn_sel;
bool nav_use_hdr;
bool bt_null;
};
struct rtw_rx_pkt_stat {
bool phy_status;
bool icv_err;
bool crc_err;
bool decrypted;
bool is_c2h;
bool channel_invalid;
s32 signal_power;
u16 pkt_len;
u8 bw;
u8 drv_info_sz;
u8 shift;
u8 rate;
u8 mac_id;
u8 cam_id;
u8 ppdu_cnt;
u32 tsf_low;
s8 rx_power[RTW_RF_PATH_MAX];
u8 rssi;
u8 rxsc;
s8 rx_snr[RTW_RF_PATH_MAX];
u8 rx_evm[RTW_RF_PATH_MAX];
s8 cfo_tail[RTW_RF_PATH_MAX];
u16 freq;
u8 band;
struct rtw_sta_info *si;
struct ieee80211_vif *vif;
struct ieee80211_hdr *hdr;
};
DECLARE_EWMA(tp, 10, 2);
struct rtw_traffic_stats {
/* units in bytes */
u64 tx_unicast;
u64 rx_unicast;
/* count for packets */
u64 tx_cnt;
u64 rx_cnt;
/* units in Mbps */
u32 tx_throughput;
u32 rx_throughput;
struct ewma_tp tx_ewma_tp;
struct ewma_tp rx_ewma_tp;
};
enum rtw_lps_mode {
RTW_MODE_ACTIVE = 0,
RTW_MODE_LPS = 1,
RTW_MODE_WMM_PS = 2,
};
enum rtw_lps_deep_mode {
LPS_DEEP_MODE_NONE = 0,
LPS_DEEP_MODE_LCLK = 1,
LPS_DEEP_MODE_PG = 2,
};
enum rtw_pwr_state {
RTW_RF_OFF = 0x0,
RTW_RF_ON = 0x4,
RTW_ALL_ON = 0xc,
};
struct rtw_lps_conf {
enum rtw_lps_mode mode;
enum rtw_lps_deep_mode deep_mode;
enum rtw_lps_deep_mode wow_deep_mode;
enum rtw_pwr_state state;
u8 awake_interval;
u8 rlbm;
u8 smart_ps;
u8 port_id;
bool sec_cam_backup;
bool pattern_cam_backup;
};
enum rtw_hw_key_type {
RTW_CAM_NONE = 0,
RTW_CAM_WEP40 = 1,
RTW_CAM_TKIP = 2,
RTW_CAM_AES = 4,
RTW_CAM_WEP104 = 5,
};
struct rtw_cam_entry {
bool valid;
bool group;
u8 addr[ETH_ALEN];
u8 hw_key_type;
struct ieee80211_key_conf *key;
};
struct rtw_sec_desc {
/* search strategy */
bool default_key_search;
u32 total_cam_num;
struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
};
struct rtw_tx_report {
/* protect the tx report queue */
spinlock_t q_lock;
struct sk_buff_head queue;
atomic_t sn;
struct timer_list purge_timer;
};
struct rtw_ra_report {
struct rate_info txrate;
u32 bit_rate;
u8 desc_rate;
};
struct rtw_txq {
struct list_head list;
unsigned long flags;
};
DECLARE_EWMA(rssi, 10, 16);
struct rtw_sta_info {
struct rtw_dev *rtwdev;
struct ieee80211_sta *sta;
struct ieee80211_vif *vif;
struct ewma_rssi avg_rssi;
u8 rssi_level;
u8 mac_id;
u8 rate_id;
enum rtw_bandwidth bw_mode;
enum rtw_rf_type rf_type;
u8 stbc_en:2;
u8 ldpc_en:2;
bool sgi_enable;
bool vht_enable;
u8 init_ra_lv;
u64 ra_mask;
DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
struct rtw_ra_report ra_report;
bool use_cfg_mask;
struct cfg80211_bitrate_mask *mask;
struct work_struct rc_work;
};
enum rtw_bfee_role {
RTW_BFEE_NONE,
RTW_BFEE_SU,
RTW_BFEE_MU
};
struct rtw_bfee {
enum rtw_bfee_role role;
u16 p_aid;
u8 g_id;
u8 mac_addr[ETH_ALEN];
u8 sound_dim;
/* SU-MIMO */
u8 su_reg_index;
/* MU-MIMO */
u16 aid;
};
struct rtw_bf_info {
u8 bfer_mu_cnt;
u8 bfer_su_cnt;
DECLARE_BITMAP(bfer_su_reg_maping, 2);
u8 cur_csi_rpt_rate;
};
struct rtw_vif {
enum rtw_net_type net_type;
u16 aid;
u8 mac_id;
u8 mac_addr[ETH_ALEN];
u8 bssid[ETH_ALEN];
u8 port;
u8 bcn_ctrl;
struct list_head rsvd_page_list;
struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
const struct rtw_vif_port *conf;
struct cfg80211_scan_request *scan_req;
struct ieee80211_scan_ies *scan_ies;
struct rtw_traffic_stats stats;
struct rtw_bfee bfee;
};
struct rtw_regulatory {
char alpha2[2];
u8 txpwr_regd_2g;
u8 txpwr_regd_5g;
};
enum rtw_regd_state {
RTW_REGD_STATE_WORLDWIDE,
RTW_REGD_STATE_PROGRAMMED,
RTW_REGD_STATE_SETTING,
RTW_REGD_STATE_NR,
};
struct rtw_regd {
enum rtw_regd_state state;
const struct rtw_regulatory *regulatory;
enum nl80211_dfs_regions dfs_region;
};
struct rtw_chip_ops {
int (*mac_init)(struct rtw_dev *rtwdev);
int (*dump_fw_crash)(struct rtw_dev *rtwdev);
void (*shutdown)(struct rtw_dev *rtwdev);
int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
void (*phy_set_param)(struct rtw_dev *rtwdev);
void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
u8 bandwidth, u8 primary_chan_idx);
void (*query_phy_status)(struct rtw_dev *rtwdev, u8 *phy_status,
struct rtw_rx_pkt_stat *pkt_stat);
u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
u32 addr, u32 mask);
bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
u32 addr, u32 mask, u32 data);
void (*set_tx_power_index)(struct rtw_dev *rtwdev);
int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
u32 size);
int (*set_antenna)(struct rtw_dev *rtwdev,
u32 antenna_tx,
u32 antenna_rx);
void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
void (*phy_calibration)(struct rtw_dev *rtwdev);
void (*dpk_track)(struct rtw_dev *rtwdev);
void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
void (*pwr_track)(struct rtw_dev *rtwdev);
void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
struct rtw_bfee *bfee, bool enable);
void (*set_gid_table)(struct rtw_dev *rtwdev,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *conf);
void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
u8 fixrate_en, u8 *new_rate);
void (*adaptivity_init)(struct rtw_dev *rtwdev);
void (*adaptivity)(struct rtw_dev *rtwdev);
void (*cfo_init)(struct rtw_dev *rtwdev);
void (*cfo_track)(struct rtw_dev *rtwdev);
void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
enum rtw_bb_path tx_path_1ss,
enum rtw_bb_path tx_path_cck,
bool is_tx2_path);
void (*config_txrx_mode)(struct rtw_dev *rtwdev, u8 tx_path,
u8 rx_path, bool is_tx2_path);
/* for USB/SDIO only */
void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,
struct rtw_tx_pkt_info *pkt_info,
u8 *txdesc);
/* for coex */
void (*coex_set_init)(struct rtw_dev *rtwdev);
void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
u8 ctrl_type, u8 pos_type);
void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
};
#define RTW_PWR_POLLING_CNT 20000
#define RTW_PWR_CMD_READ 0x00
#define RTW_PWR_CMD_WRITE 0x01
#define RTW_PWR_CMD_POLLING 0x02
#define RTW_PWR_CMD_DELAY 0x03
#define RTW_PWR_CMD_END 0x04
/* define the base address of each block */
#define RTW_PWR_ADDR_MAC 0x00
#define RTW_PWR_ADDR_USB 0x01
#define RTW_PWR_ADDR_PCIE 0x02
#define RTW_PWR_ADDR_SDIO 0x03
#define RTW_PWR_INTF_SDIO_MSK BIT(0)
#define RTW_PWR_INTF_USB_MSK BIT(1)
#define RTW_PWR_INTF_PCI_MSK BIT(2)
#define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
#define RTW_PWR_CUT_TEST_MSK BIT(0)
#define RTW_PWR_CUT_A_MSK BIT(1)
#define RTW_PWR_CUT_B_MSK BIT(2)
#define RTW_PWR_CUT_C_MSK BIT(3)
#define RTW_PWR_CUT_D_MSK BIT(4)
#define RTW_PWR_CUT_E_MSK BIT(5)
#define RTW_PWR_CUT_F_MSK BIT(6)
#define RTW_PWR_CUT_G_MSK BIT(7)
#define RTW_PWR_CUT_ALL_MSK 0xFF
enum rtw_pwr_seq_cmd_delay_unit {
RTW_PWR_DELAY_US,
RTW_PWR_DELAY_MS,
};
struct rtw_pwr_seq_cmd {
u16 offset;
u8 cut_mask;
u8 intf_mask;
u8 base:4;
u8 cmd:4;
u8 mask;
u8 value;
};