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Add defs.bzl for //synthesis package
1 parent 81bfab8 commit 0fc3a88

19 files changed

+66
-36
lines changed

‎README.md

+1-1
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@@ -66,7 +66,7 @@ This is the `BUILD` file. Every thing in bazel needs a rule description of what
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to build. The rules use yosys and OpenROAD to place and route your design.
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```python
69-
load("@rules_hdl//synthesis:build_defs.bzl", "synthesize_rtl")
69+
load("@rules_hdl//synthesis:defs.bzl", "synthesize_rtl")
7070
load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route")
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load("@rules_hdl//verilog:defs.bzl", "verilog_library")
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‎flows/basic_asic.bzl

+1-1
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@@ -18,7 +18,7 @@ load("@bazel_skylib//rules:build_test.bzl", "build_test")
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load("//gds_write:build_defs.bzl", "gds_write")
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load("//place_and_route:build_defs.bzl", "place_and_route")
2020
load("//static_timing:build_defs.bzl", "run_opensta")
21-
load("//synthesis:build_defs.bzl", "synthesize_rtl")
21+
load("//synthesis:defs.bzl", "synthesize_rtl")
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2323
def _get_with_defaults(target_name, extra_args, defaults):
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target_extra_args = dict(**extra_args.pop(target_name, {}))

‎gds_write/build_defs.bzl

+1-1
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@@ -16,7 +16,7 @@
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load("@rules_hdl//pdk:open_road_configuration.bzl", "assert_has_open_road_configuration", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
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2121
def _gds_write_impl(ctx):
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# Throws an error if there is no OpenROAD configuration

‎place_and_route/build_defs.bzl

+1-1
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@@ -27,7 +27,7 @@ load("//place_and_route:private/pdn_gen.bzl", "pdn_gen")
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load("//place_and_route:private/place_pins.bzl", "place_pins")
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load("//place_and_route:private/repair.bzl", "repair")
2929
load("//place_and_route:private/resize.bzl", "resize")
30-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
30+
load("//synthesis:defs.bzl", "SynthesisInfo")
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3232
PLACE_AND_ROUTE_STEPS = [
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("init_floor_plan", init_floor_plan, "pre_pnr"),

‎place_and_route/open_road.bzl

+2-2
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@@ -14,8 +14,8 @@
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"""File encapsulating the open road command"""
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17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
18-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
18+
load("//synthesis:defs.bzl", "SynthesisInfo")
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2020
OpenRoadInfo = provider(
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"Provider to support running openroad outside of bazel",

‎place_and_route/private/clock_tree_synthesis.bzl

+2-2
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@
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"""Clock Tree Synthesis openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "format_openroad_do_not_use_list", "merge_open_road_info", "openroad_command", "placement_padding_commands", "timing_setup_commands")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
2020

2121
def clock_tree_synthesis(ctx, open_road_info):
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"""Performs clock tree synthesis.

‎place_and_route/private/detailed_routing.bzl

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@@ -14,9 +14,9 @@
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"""Detailed Routing openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "DetailedRoutingInfo", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "DetailedRoutingInfo", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
2020

2121
def detailed_routing(ctx, open_road_info):
2222
"""Performs detailed routing.

‎place_and_route/private/floorplan.bzl

+2-2
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@@ -14,11 +14,11 @@
1414

1515
"""Floorplaning openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "openroad_command", "timing_setup_commands")
1919
load("//place_and_route:private/report_area.bzl", "generate_area_results")
2020
load("//place_and_route:private/report_power.bzl", "generate_power_results")
21-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
21+
load("//synthesis:defs.bzl", "SynthesisInfo")
2222

2323
def _initialize_floorplan_command(ctx):
2424
open_road_configuration = get_open_road_configuration(ctx.attr.synthesized_rtl[SynthesisInfo])

‎place_and_route/private/global_placement.bzl

+2-2
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@@ -14,9 +14,9 @@
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"""Global placement openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
2020

2121
def global_placement(ctx, open_road_info):
2222
"""Performs the global placement of the standard cells.

‎place_and_route/private/global_routing.bzl

+2-2
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@@ -14,11 +14,11 @@
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"""Global Routing openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
1919
load("//place_and_route:private/report_area.bzl", "generate_area_results")
2020
load("//place_and_route:private/report_power.bzl", "generate_power_results")
21-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
21+
load("//synthesis:defs.bzl", "SynthesisInfo")
2222

2323
def _global_routing_layer_adjustments(adjustments):
2424
adjustment_command = "{"

‎place_and_route/private/pdn_gen.bzl

+2-2
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@@ -14,9 +14,9 @@
1414

1515
"""PDN openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
2020

2121
def pdn_gen(ctx, open_road_info):
2222
"""Generates the power delivery network for the ASIC.

‎place_and_route/private/place_pins.bzl

+2-2
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@@ -14,9 +14,9 @@
1414

1515
"""Pin Placement openROAD commands"""
1616

17-
load("@rules_hdl//pdk:open_road_configuration.bzl", "get_open_road_configuration")
17+
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "merge_open_road_info", "openroad_command", "timing_setup_commands")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
2020

2121
def place_pins(ctx, open_road_info):
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"""Places pins around the die area.

‎place_and_route/private/repair.bzl

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@@ -16,7 +16,7 @@
1616

1717
load("//pdk:open_road_configuration.bzl", "get_open_road_configuration")
1818
load("//place_and_route:open_road.bzl", "OpenRoadInfo", "format_openroad_do_not_use_list", "merge_open_road_info", "openroad_command", "timing_setup_commands")
19-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
19+
load("//synthesis:defs.bzl", "SynthesisInfo")
2020

2121
def repair(ctx, open_road_info):
2222
"""Performs several repair operations on a placed design.

‎place_and_route/private/report_power.bzl

+1-1
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@@ -14,7 +14,7 @@
1414

1515
"""Report Power Commands"""
1616

17-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
17+
load("//synthesis:defs.bzl", "SynthesisInfo")
1818

1919
def generate_power_results(ctx, output_file):
2020
netlist_target = ctx.attr.synthesized_rtl

‎static_timing/build_defs.bzl

+1-1
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@@ -14,7 +14,7 @@
1414

1515
"""Rules for running openSTA on synthesized Verilog."""
1616

17-
load("//synthesis:build_defs.bzl", "SynthesisInfo")
17+
load("//synthesis:defs.bzl", "SynthesisInfo")
1818

1919
def _run_opensta_impl(ctx):
2020
"""Implementation of the 'run_opensta' rule.

‎synthesis/BUILD renamed to ‎synthesis/BUILD.bazel

File renamed without changes.

‎synthesis/build_defs.bzl

+24-12
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@@ -37,14 +37,14 @@ ExternalSynthesisInfo = provider(
3737
},
3838
)
3939

40-
# Args:
41-
# standard_cell_info: The StandardCellInfo provider this target was synthesized against.
42-
# synthesized_netlist: The structural verilog syntheized with standard_cell_info
43-
# top_module: The name of the top level module of the synthesized netlist
44-
# log_file: Log output file from the synthesis step.
4540
SynthesisInfo = provider(
4641
"Information about the synthesis target",
47-
fields = ["standard_cell_info", "synthesized_netlist", "top_module", "log_file"],
42+
fields = {
43+
"log_file": "Log output file from the synthesis step.",
44+
"standard_cell_info": "The StandardCellInfo provider this target was synthesized against.",
45+
"synthesized_netlist": "he structural verilog syntheized with standard_cell_info",
46+
"top_module": "The name of the top level module of the synthesized netlist",
47+
},
4848
)
4949

5050
def _transitive_srcs(deps):
@@ -294,7 +294,9 @@ def _synthesize_binary_impl(ctx):
294294
synthesis_binary = rule(
295295
implementation = _synthesize_binary_impl,
296296
attrs = {
297-
"synthesize_rtl_rule": attr.label(providers = [ExternalSynthesisInfo]),
297+
"synthesize_rtl_rule": attr.label(
298+
providers = [ExternalSynthesisInfo],
299+
),
298300
"yosys_tool": attr.label(
299301
default = Label("@at_clifford_yosys//:yosys"),
300302
executable = True,
@@ -316,9 +318,15 @@ synthesize_rtl = rule(
316318
allow_single_file = True,
317319
doc = "Verilog file that maps yosys adder to PDK adders.",
318320
),
319-
"deps": attr.label_list(providers = [[VerilogInfo], [UhdmInfo]]),
320-
"output_file_name": attr.string(doc = "The output file name."),
321-
"srcs": attr.label_list(allow_files = True),
321+
"deps": attr.label_list(
322+
providers = [[VerilogInfo], [UhdmInfo]],
323+
),
324+
"output_file_name": attr.string(
325+
doc = "The output file name.",
326+
),
327+
"srcs": attr.label_list(
328+
allow_files = True,
329+
),
322330
"standard_cells": attr.label(
323331
providers = [StandardCellInfo],
324332
default = "@com_google_skywater_pdk_sky130_fd_sc_hd//:sky130_fd_sc_hd",
@@ -328,8 +336,12 @@ synthesize_rtl = rule(
328336
allow_single_file = True,
329337
doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl",
330338
),
331-
"target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"),
332-
"top_module": attr.string(default = "top"),
339+
"target_clock_period_pico_seconds": attr.int(
340+
doc = "target clock period in picoseconds",
341+
),
342+
"top_module": attr.string(
343+
default = "top",
344+
),
333345
"yosys_tool": attr.label(
334346
default = Label("@at_clifford_yosys//:yosys"),
335347
executable = True,

‎synthesis/defs.bzl

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@@ -0,0 +1,18 @@
1+
"""Rules for synthesizing (System)Verilog code."""
2+
3+
load(
4+
":build_defs.bzl",
5+
_ExternalSynthesisInfo = "ExternalSynthesisInfo",
6+
_SynthesisInfo = "SynthesisInfo",
7+
_UhdmInfo = "UhdmInfo",
8+
_benchmark_synth = "benchmark_synth",
9+
_synthesis_binary = "synthesis_binary",
10+
_synthesize_rtl = "synthesize_rtl",
11+
)
12+
13+
benchmark_synth = _benchmark_synth
14+
ExternalSynthesisInfo = _ExternalSynthesisInfo
15+
synthesis_binary = _synthesis_binary
16+
SynthesisInfo = _SynthesisInfo
17+
synthesize_rtl = _synthesize_rtl
18+
UhdmInfo = _UhdmInfo

‎tests/BUILD

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@@ -19,7 +19,7 @@ load("//flows:basic_asic.bzl", "basic_asic_flow")
1919
load("//gds_write:build_defs.bzl", "gds_write")
2020
load("//place_and_route:build_defs.bzl", "place_and_route")
2121
load("//static_timing:build_defs.bzl", "run_opensta")
22-
load("//synthesis:build_defs.bzl", "synthesize_rtl")
22+
load("//synthesis:defs.bzl", "synthesize_rtl")
2323
load("//verilog:defs.bzl", "verilog_library")
2424

2525
package(

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