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half_adder
115 lines (115 loc) · 1.33 KB
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half_adder
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$date
Thu Sep 6 16:18:05 2018
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module half_adder_tb $end
$var wire 1 ! carry $end
$var wire 1 " sum $end
$var reg 1 # a1 $end
$var reg 1 $ b1 $end
$scope module ha $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 ! c $end
$var wire 1 " s $end
$scope module or1 $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 " y $end
$var wire 1 ' y1 $end
$scope module nr $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 ( gnd $end
$var wire 1 ) vcc $end
$var wire 1 * w $end
$var wire 1 ' y $end
$upscope $end
$scope module nt $end
$var wire 1 ' a $end
$var wire 1 + gnd $end
$var wire 1 , vcc $end
$var wire 1 " y $end
$upscope $end
$upscope $end
$scope module an $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 ! y $end
$var wire 1 - y1 $end
$scope module n $end
$var wire 1 % a $end
$var wire 1 & b $end
$var wire 1 . gnd $end
$var wire 1 / vdd $end
$var wire 1 0 w $end
$var wire 1 - y $end
$upscope $end
$scope module nt $end
$var wire 1 - a $end
$var wire 1 1 gnd $end
$var wire 1 2 vcc $end
$var wire 1 ! y $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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