full_adder

$date
	Thu Sep  6 16:18:08 2018
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module full_adder_tb $end
$var wire 1 ! cout $end
$var wire 1 " sum $end
$var reg 1 # a1 $end
$var reg 1 $ b1 $end
$var reg 1 % cin $end
$scope module fa $end
$var wire 1 & a $end
$var wire 1 ' b $end
$var wire 1 ( c1 $end
$var wire 1 ) c2 $end
$var wire 1 * cin $end
$var wire 1 ! cout $end
$var wire 1 " s $end
$var wire 1 + s1 $end
$scope module ha1 $end
$var wire 1 & a $end
$var wire 1 ' b $end
$var wire 1 ( c $end
$var wire 1 + s $end
$scope module or1 $end
$var wire 1 & a $end
$var wire 1 ' b $end
$var wire 1 + y $end
$var wire 1 , y1 $end
$scope module nr $end
$var wire 1 & a $end
$var wire 1 ' b $end
$var wire 1 - gnd $end
$var wire 1 . vcc $end
$var wire 1 / w $end
$var wire 1 , y $end
$upscope $end
$scope module nt $end
$var wire 1 , a $end
$var wire 1 0 gnd $end
$var wire 1 1 vcc $end
$var wire 1 + y $end
$upscope $end
$upscope $end
$scope module an $end
$var wire 1 & a $end
$var wire 1 ' b $end
$var wire 1 ( y $end
$var wire 1 2 y1 $end
$scope module n $end
$var wire 1 & a $end
$var wire 1 ' b $end
$var wire 1 3 gnd $end
$var wire 1 4 vdd $end
$var wire 1 5 w $end
$var wire 1 2 y $end
$upscope $end
$scope module nt $end
$var wire 1 2 a $end
$var wire 1 6 gnd $end
$var wire 1 7 vcc $end
$var wire 1 ( y $end
$upscope $end
$upscope $end
$upscope $end
$scope module ha2 $end
$var wire 1 + a $end
$var wire 1 * b $end
$var wire 1 ) c $end
$var wire 1 " s $end
$scope module or1 $end
$var wire 1 + a $end
$var wire 1 * b $end
$var wire 1 " y $end
$var wire 1 8 y1 $end
$scope module nr $end
$var wire 1 + a $end
$var wire 1 * b $end
$var wire 1 9 gnd $end
$var wire 1 : vcc $end
$var wire 1 ; w $end
$var wire 1 8 y $end
$upscope $end
$scope module nt $end
$var wire 1 8 a $end
$var wire 1 < gnd $end
$var wire 1 = vcc $end
$var wire 1 " y $end
$upscope $end
$upscope $end
$scope module an $end
$var wire 1 + a $end
$var wire 1 * b $end
$var wire 1 ) y $end
$var wire 1 > y1 $end
$scope module n $end
$var wire 1 + a $end
$var wire 1 * b $end
$var wire 1 ? gnd $end
$var wire 1 @ vdd $end
$var wire 1 A w $end
$var wire 1 > y $end
$upscope $end
$scope module nt $end
$var wire 1 > a $end
$var wire 1 B gnd $end
$var wire 1 C vcc $end
$var wire 1 ) y $end
$upscope $end
$upscope $end
$upscope $end
$scope module orfa $end
$var wire 1 ( a $end
$var wire 1 ) b $end
$var wire 1 ! y $end
$var wire 1 D y1 $end
$scope module nr $end
$var wire 1 ( a $end
$var wire 1 ) b $end
$var wire 1 E gnd $end
$var wire 1 F vcc $end
$var wire 1 G w $end
$var wire 1 D y $end
$upscope $end
$scope module nt $end
$var wire 1 D a $end
$var wire 1 H gnd $end
$var wire 1 I vcc $end
$var wire 1 ! y $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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