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ODROID-N2L: Introduce new SBC board 'ODROID-N2L'
 N2L U-Boot build : # make odroidn2l_defconfig # make Signed-off-by: ckkim <[email protected]> Change-Id: I49a43777cfb083965e7efc9fa8dd4b357777ec28
1 parent 545adf4 commit 2a3baa5

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8 files changed

+150
-4
lines changed

8 files changed

+150
-4
lines changed

‎board/amlogic/Kconfig

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,11 @@ config ODROID_N2
274274
select ODROID_COMMON
275275
default n
276276

277+
config ODROID_N2L
278+
bool "Support Hardkernel ODROID-N2L board"
279+
select ODROID_COMMON
280+
default n
281+
277282
config ODROID_C4
278283
bool "Support Hardkernel ODROID-C4 board"
279284
select ODROID_COMMON
@@ -540,6 +545,10 @@ if ODROID_N2
540545
source "board/hardkernel/odroidn2/Kconfig"
541546
endif
542547

548+
if ODROID_N2L
549+
source "board/hardkernel/odroidn2/Kconfig"
550+
endif
551+
543552
if ODROID_C4
544553
source "board/hardkernel/odroidc4/Kconfig"
545554
endif

‎board/hardkernel/odroid-common/board.c

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,13 @@ static unsigned int get_hw_revision(void)
7272
} else if (IS_RANGE(adc, 500, 520)) {
7373
hwrev = BOARD_REVISION(2021, 1, 21);
7474
}
75+
#elif defined(CONFIG_ODROID_N2L)
76+
/* ODROID-N2lite rev_0.1 */
77+
if (IS_RANGE(adc, 410, 430)) { /* avg : 419 */
78+
hwrev = BOARD_REVISION(2022, 2, 18);
79+
} else {
80+
hwrev = BOARD_REVISION(2022, 2, 18);
81+
}
7582
#elif defined(CONFIG_ODROID_C4)
7683
if (IS_RANGE(adc, 80, 100)) /* avg : 90 */
7784
hwrev = BOARD_REVISION(2020, 1, 29);
@@ -105,7 +112,7 @@ void board_set_dtbfile(const char *format)
105112
setenv("fdtfile", s);
106113
}
107114

108-
#if defined(CONFIG_ODROID_N2)
115+
#if defined(CONFIG_ODROID_N2) || defined(CONFIG_ODROID_N2L)
109116
int board_is_odroidn2(void)
110117
{
111118
int hwrev = board_revision();
@@ -120,6 +127,14 @@ int board_is_odroidn2plus(void)
120127
{
121128
return !board_is_odroidn2();
122129
}
130+
131+
int board_is_odroidn2l(void)
132+
{
133+
int hwrev = board_revision();
134+
135+
return ((hwrev >= BOARD_REVISION(2022, 2, 18)) ? 1 : 0);
136+
}
137+
123138
#elif defined(CONFIG_ODROID_C4)
124139
int board_is_odroidc4(void)
125140
{

‎board/hardkernel/odroid-common/odroid-common.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,10 @@ extern int get_adc_value(int channel);
3030
int board_revision(void);
3131
void board_set_dtbfile(const char *format);
3232

33-
#if defined(CONFIG_ODROID_N2)
33+
#if defined(CONFIG_ODROID_N2) || defined(CONFIG_ODROID_N2L)
3434
int board_is_odroidn2(void);
3535
int board_is_odroidn2plus(void);
36+
int board_is_odroidn2l(void);
3637
#elif defined(CONFIG_ODROID_C4)
3738
int board_is_odroidc4(void);
3839
int board_is_odroidhc4(void);

‎board/hardkernel/odroidn2/firmware/timing.c

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,84 @@
7676
#define CONFIG_DDR4_DEFAULT_CLK 1320
7777

7878
ddr_set_t __ddr_setting[] = {
79+
#if defined(CONFIG_ODROID_N2L)
80+
{
81+
/*odroid-n2-lite lpddr4x lpddr4 */
82+
.board_id = CONFIG_BOARD_ID_MASK,
83+
.version = 1,
84+
//.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
85+
.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
86+
.ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
87+
.DramType = CONFIG_DDR_TYPE_LPDDR4,
88+
.DRAMFreq = {1200, 0, 0, 0},
89+
.ddr_base_addr = CFG_DDR_BASE_ADDR,
90+
.ddr_start_offset = CFG_DDR_START_OFFSET,
91+
.imem_load_addr = 0xFFFC0000, //sram
92+
.dmem_load_size = 0x1000, //4K
93+
94+
.DisabledDbyte = 0xf0,
95+
.Is2Ttiming = 0,
96+
.HdtCtrl = 0xa,
97+
.dram_cs0_size_MB = 0xffff,//1024,
98+
.dram_cs1_size_MB = 0xffff,//1024,
99+
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
100+
.phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
101+
.dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
102+
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
103+
.ddr_rdbi_wr_enable = 0,
104+
.clk_drv_ohm = 40,
105+
.cs_drv_ohm = 40,
106+
.ac_drv_ohm = 40,
107+
.soc_data_drv_ohm_p = 40,
108+
.soc_data_drv_ohm_n = 40,
109+
.soc_data_odt_ohm_p = 0,
110+
.soc_data_odt_ohm_n = 120,
111+
.dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
112+
.dram_data_odt_ohm = 120,
113+
.dram_ac_odt_ohm = 120,
114+
.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
115+
.soc_clk_slew_rate = 0x3ff,//0x253,
116+
.soc_cs_slew_rate = 0x100,//0x253,
117+
.soc_ac_slew_rate = 0x100,//0x253,
118+
.soc_data_slew_rate = 0x1ff,
119+
.vref_output_permil = 350,//200,
120+
.vref_receiver_permil = 0,
121+
.vref_dram_permil = 0,
122+
//.vref_reverse = 0,
123+
.ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
124+
//.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
125+
.ac_pinmux = {00,00},
126+
.ddr_dmc_remap = {
127+
[0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
128+
[1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
129+
[2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
130+
[3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
131+
[4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
132+
},
133+
.ddr_lpddr34_ca_remap = {00,00},
134+
.ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
135+
.dram_rtt_nom_wr_park = {00,00},
136+
137+
/* pll ssc config:
138+
*
139+
* pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
140+
* ppm = strength * 500
141+
* mode: 0=center, 1=up, 2=down
142+
*
143+
* eg:
144+
* 1. config 1000ppm center ss. then mode=0, strength=2
145+
* .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
146+
* 2. config 3000ppm down ss. then mode=2, strength=6
147+
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
148+
*/
149+
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
150+
.ddr_func = DDR_FUNC,
151+
.magic = DRAM_CFG_MAGIC,
152+
.diagnose = CONFIG_DIAGNOSE_DISABLE,
153+
.bitTimeControl_2d = 1,
154+
.fast_boot[0] = 1,
155+
},
156+
#else
79157
{
80158
/* odroid-n2 ddr4 : (4Gbitx2)x2, (8Gbitx2)x2 */
81159
.board_id = CONFIG_BOARD_ID_MASK,
@@ -192,6 +270,7 @@ ddr_set_t __ddr_setting[] = {
192270
.ddr_func = DDR_FUNC,
193271
.magic = DRAM_CFG_MAGIC,
194272
},
273+
#endif
195274
};
196275

197276
pll_set_t __pll_setting = {
@@ -268,6 +347,10 @@ ddr_reg_t __ddr_reg[] = {
268347
#error "VCCK val out of range\n"
269348
#endif
270349

350+
#if defined(CONFIG_ODROID_N2L)
351+
#define VDDEE_VAL_REG0 0x0002000e
352+
#define VDDEE_VAL_REG1 0x0002000e
353+
#else
271354
/* VDDEE_VAL_REG0: VDDEE PWM table 0.69v-0.862v*/
272355
/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.863v*/
273356
#if (VDDEE_VAL == 800)
@@ -294,6 +377,7 @@ ddr_reg_t __ddr_reg[] = {
294377
#else
295378
#error "VDDEE val out of range\n"
296379
#endif
380+
#endif
297381

298382
/* for PWM use */
299383
/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */

‎board/hardkernel/odroidn2/odroidn2.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,8 +116,10 @@ int board_eth_init(bd_t *bis)
116116
dwmac_meson_cfg_drive_strength();
117117
setup_net_chip_ext();
118118
#endif
119+
#if !defined(CONFIG_ODROID_N2L)
119120
udelay(1000);
120121
designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
122+
#endif
121123
return 0;
122124
}
123125

@@ -278,9 +280,10 @@ static void gpio_set_vbus_power(char is_power_on)
278280
{
279281
int ret;
280282

283+
#if !defined(CONFIG_ODROID_N2L)
281284
/* USB Host power enable/disable */
282285
usbhost_set_power(is_power_on);
283-
286+
#endif
284287
/* usb otg power enable */
285288
ret = gpio_request(CONFIG_USB_GPIO_PWR,
286289
CONFIG_USB_GPIO_PWR_NAME);
@@ -416,9 +419,13 @@ int board_late_init(void)
416419
}
417420
#endif
418421

422+
#if defined(CONFIG_ODROID_N2L)
423+
setenv("variant", board_is_odroidn2l() ? "n2l" : "n2");
424+
board_set_dtbfile("meson64_odroid%s.dtb");
425+
#else
419426
setenv("variant", board_is_odroidn2plus() ? "n2_plus" : "n2");
420427
board_set_dtbfile("meson64_odroid%s.dtb");
421-
428+
#endif
422429
/* boot logo display - 1080p60hz */
423430
run_command("showlogo", 0);
424431

‎configs/odroidn2l_defconfig

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
CONFIG_ARM=y
2+
CONFIG_TARGET_MESON_G12B=y
3+
CONFIG_ODROID_N2L=y
4+
CONFIG_DM=y
5+
CONFIG_DM_GPIO=y
6+
CONFIG_AML_GPIO=y
7+
CONFIG_OF_LIBFDT_OVERLAY=y

‎fip/Makefile

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,19 @@ endif
128128
$(call encrypt_step, --bl2sig \
129129
--input $(buildtree)/fip/bl2_new.bin \
130130
--output $(buildtree)/fip/bl2.n.bin.sig)
131+
132+
ifeq ($(CONFIG_ODROID_N2L),y)
133+
$(call encrypt_step,--bootmk $(FIP_BL32_PROCESS) $(V3_PROCESS_FLAG) \
134+
--bl2 $(buildtree)/fip/bl2.n.bin.sig \
135+
--bl30 $(buildtree)/fip/bl30_new.bin.enc \
136+
--bl31 $(buildtree)/fip/bl31.$(BL3X_SUFFIX).enc \
137+
--bl33 $(buildtree)/fip/bl33.bin.enc \
138+
--ddrfw1 $(buildsrc)/fip/$(SOC)/lpddr4_1d.fw \
139+
--ddrfw2 $(buildsrc)/fip/$(SOC)/lpddr4_2d.fw \
140+
--ddrfw4 $(buildsrc)/fip/$(SOC)/piei.fw \
141+
--ddrfw8 $(buildsrc)/fip/$(SOC)/$(DDR_FW_NAME) \
142+
--output $(FUSING_FOLDER)/u-boot.bin)
143+
else
131144
$(call encrypt_step,--bootmk $(FIP_BL32_PROCESS) $(V3_PROCESS_FLAG) \
132145
--bl2 $(buildtree)/fip/bl2.n.bin.sig \
133146
--bl30 $(buildtree)/fip/bl30_new.bin.enc \
@@ -138,6 +151,8 @@ endif
138151
--ddrfw4 $(buildsrc)/fip/$(SOC)/piei.fw \
139152
--ddrfw8 $(buildsrc)/fip/$(SOC)/$(DDR_FW_NAME) \
140153
--output $(FUSING_FOLDER)/u-boot.bin)
154+
endif
155+
141156
ifeq ($(CONFIG_AML_CRYPTO_UBOOT),y)
142157
$(call encrypt_step, --efsgen --amluserkey $(AML_USER_KEY) \
143158
--output $(buildtree)/fip/u-boot.bin.encrypt.efuse $(V3_PROCESS_FLAG))

‎include/configs/odroidn2.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,4 +25,12 @@
2525
#define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
2626
#endif
2727

28+
#if defined(CONFIG_ODROID_N2L)
29+
#define CONFIG_ETHERNET_NONE
30+
#undef ETHERNET_EXTERNAL_PHY
31+
#undef ETHERNET_INTERNAL_PHY
32+
33+
#undef CONFIG_AML_CVBS
34+
#endif
35+
2836
#endif

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