From c8dcb4ca69ca6159ab27d7dd5db89c2523ab6a65 Mon Sep 17 00:00:00 2001
From: Steven Johnson <srj@google.com>
Date: Tue, 17 Sep 2024 08:37:41 -0700
Subject: [PATCH] Fix for top-of-tree LLVM (#8421)

* Fix for top-of-tree LLVM

* Update simd_op_check_sve2.cpp
---
 src/LLVM_Headers.h                      | 2 ++
 test/correctness/simd_op_check_sve2.cpp | 9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/LLVM_Headers.h b/src/LLVM_Headers.h
index bd76de8baae6..416a62cd7390 100644
--- a/src/LLVM_Headers.h
+++ b/src/LLVM_Headers.h
@@ -85,7 +85,9 @@
 #include <llvm/Transforms/IPO.h>
 #include <llvm/Transforms/IPO/AlwaysInliner.h>
 #include <llvm/Transforms/IPO/Inliner.h>
+#if LLVM_VERSION < 200
 #include <llvm/Transforms/Instrumentation.h>
+#endif
 #include <llvm/Transforms/Instrumentation/AddressSanitizer.h>
 #include <llvm/Transforms/Instrumentation/SanitizerCoverage.h>
 #include <llvm/Transforms/Instrumentation/ThreadSanitizer.h>
diff --git a/test/correctness/simd_op_check_sve2.cpp b/test/correctness/simd_op_check_sve2.cpp
index 9f6b958d6c2a..d0e614d657a2 100644
--- a/test/correctness/simd_op_check_sve2.cpp
+++ b/test/correctness/simd_op_check_sve2.cpp
@@ -643,8 +643,13 @@ class SimdOpCheckArmSve : public SimdOpCheckTest {
                 // No corresponding instructions exists for is_nan, is_inf, is_finite.
                 // The instructions expected to be generated depends on CodeGen_LLVM::visit(const Call *op)
                 add_arm64("nan", is_vector ? sel_op("", "fcmge", "fcmuo") : "fcmp", is_nan(f_1));
-                add_arm64("inf", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
-                add_arm64("finite", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
+                if (Halide::Internal::get_llvm_version() >= 200) {
+                    add_arm64("inf", is_vector ? sel_op("", "fcmge", "fcmeq") : "", is_inf(f_1));
+                    add_arm64("finite", is_vector ? sel_op("", "fcmge", "fcmeq") : "", is_inf(f_1));
+                } else {
+                    add_arm64("inf", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
+                    add_arm64("finite", {{"fabs", bits, force_vectorized_lanes}}, vf, is_inf(f_1));
+                }
             }
 
             if (bits == 16) {