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benchmark_1_stream_clean.log
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benchmark_1_stream_clean.log
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Accel-Sim [build accelsim-commit-2260456ea5e6a1420f5734f145a4b7d8ab1d4737_modified_1.0]
*** GPGPU-Sim Simulator Version 4.2.0 [build gpgpu-sim_git-commit-13c67115070dc2f0876254a790d0238073ca364a_modified_2.0] ***
GPGPU-Sim: Configuration options:
-save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
-gpgpu_occupancy_sm_number 70 # The SM number to pass to ptxas when getting register usage for computing GPU occupancy. This parameter is required in the config.
-ptx_opcode_latency_int 4,13,4,5,145,32 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>Default 1,1,19,25,145,32
-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
-ptx_opcode_latency_sfu 100 # Opcode latencies for SFU instructionsDefault 8
-ptx_opcode_latency_tesnor 64 # Opcode latencies for Tensor instructionsDefault 64
-ptx_opcode_initiation_int 2,2,2,2,8,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>Default 1,1,4,4,32,4
-ptx_opcode_initiation_fp 2,2,2,2,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
-ptx_opcode_initiation_dp 4,4,4,4,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
-ptx_opcode_initiation_sfu 8 # Opcode initiation intervals for sfu instructionsDefault 8
-ptx_opcode_initiation_tensor 64 # Opcode initiation intervals for tensor instructionsDefault 64
-cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-network_mode 2 # Interconnection network mode
-inter_config_file mesh # Interconnection network config file
-icnt_in_buffer_limit 512 # in_buffer_limit
-icnt_out_buffer_limit 512 # out_buffer_limit
-icnt_subnets 2 # subnets
-icnt_arbiter_algo 1 # arbiter_algo
-icnt_verbose 0 # inct_verbose
-icnt_grant_cycles 1 # grant_cycles
-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
-checkpoint_option 0 # checkpointing flag (0 = no checkpoint)
-checkpoint_kernel 1 # checkpointing during execution of which kernel (1- 1st kernel)
-checkpoint_CTA 0 # checkpointing after # of CTA (< less than total CTA)
-resume_option 0 # resume flag (0 = no resume)
-resume_kernel 0 # Resume from which kernel (1= 1st kernel)
-resume_CTA 0 # resume from which CTA
-checkpoint_CTA_t 0 # resume from which CTA
-checkpoint_insn_Y 0 # resume from which CTA
-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability
-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
-gpgpu_simd_model 1 # 1 = post-dominator
-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
-gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
-gpgpu_l1_cache_write_ratio 25 # L1D write ratio
-gpgpu_l1_banks 4 # The number of L1 cache banks
-gpgpu_l1_banks_byte_interleaving 32 # l1 banks byte interleaving granularity
-gpgpu_l1_banks_hashing_function 0 # l1 banks hashing function
-gpgpu_l1_latency 20 # L1 Hit Latency
-gpgpu_smem_latency 20 # smem Latency
-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
-gpgpu_cache:dl1PrefShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
-gpgpu_gmem_skip_L1D 0 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
-n_regfile_gating_group 4 # group of lanes that should be read/written together)
-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
-gpgpu_registers_per_block 65536 # Maximum number of registers per CTA. (default 8192)
-gpgpu_ignore_resources_limitation 0 # gpgpu_ignore_resources_limitation (default 0)
-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 32)
-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
-gpgpu_n_clusters 40 # number of processing clusters
-gpgpu_n_cores_per_cluster 2 # number of simd cores per cluster
-gpgpu_n_cluster_ejection_buffer_size 32 # number of packets in ejection buffer
-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
-gpgpu_shmem_per_block 65536 # Size of shared memory per thread block or CTA (default 48kB)
-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_option 0,8,16,32,64,96 # Option list of shared memory sizes
-gpgpu_unified_l1d_size 128 # Size of unified data cache(L1D + shared memory) in KB
-gpgpu_adaptive_cache_config 1 # adaptive_cache_config
-gpgpu_shmem_sizeDefault 98304 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
-gpgpu_mem_unit_ports 1 # The number of memory transactions allowed per core cycle
-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
-gpgpu_num_reg_banks 8 # Number of register banks (default = 8)
-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
-gpgpu_sub_core_model 1 # Sub Core Volta/Pascal model (default = off)
-gpgpu_enable_specialized_operand_collector 0 # enable_specialized_operand_collector
-gpgpu_operand_collector_num_units_sp 4 # number of collector units (default = 4)
-gpgpu_operand_collector_num_units_dp 0 # number of collector units (default = 0)
-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
-gpgpu_operand_collector_num_units_int 0 # number of collector units (default = 0)
-gpgpu_operand_collector_num_units_tensor_core 4 # number of collector units (default = 4)
-gpgpu_operand_collector_num_units_mem 2 # number of collector units (default = 2)
-gpgpu_operand_collector_num_units_gen 8 # number of collector units (default = 0)
-gpgpu_operand_collector_num_in_ports_sp 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_dp 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_int 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_in_ports_tensor_core 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_in_ports_gen 8 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_out_ports_sp 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_dp 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_int 0 # number of collector unit in ports (default = 0)
-gpgpu_operand_collector_num_out_ports_tensor_core 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
-gpgpu_operand_collector_num_out_ports_gen 8 # number of collector unit in ports (default = 0)
-gpgpu_coalesce_arch 60 # Coalescing arch (GT200 = 13, Fermi = 20)
-gpgpu_num_sched_per_core 4 # Number of warp schedulers per core
-gpgpu_max_insn_issue_per_warp 1 # Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)
-gpgpu_dual_issue_diff_exec_units 1 # should dual issue use two different execution unit resources (Default = 1)
-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 # Pipeline widths ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-gpgpu_tensor_core_avail 1 # Tensor Core Available (default=0)
-gpgpu_num_sp_units 4 # Number of SP units (default=1)
-gpgpu_num_dp_units 4 # Number of DP units (default=0)
-gpgpu_num_int_units 4 # Number of INT units (default=0)
-gpgpu_num_sfu_units 4 # Number of SF units (default=1)
-gpgpu_num_tensor_core_units 4 # Number of tensor_core units (default=1)
-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
-gpgpu_scheduler lrr # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
-gpgpu_concurrent_kernel_sm 1 # Support concurrent kernels on a SM (default = disabled)
-gpgpu_perfect_inst_const_cache 1 # perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)
-gpgpu_inst_fetch_throughput 4 # the number of fetched intruction per warp each cycle
-gpgpu_reg_file_port_throughput 2 # the number ports of the register file
-specialized_unit_1 1,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_2 1,4,200,4,4,TEX # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_3 1,4,8,4,4,TENSOR # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_4 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_5 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_6 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_7 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-specialized_unit_8 0,4,4,4,4,BRA # specialized unit config {<enabled>,<num_units>:<latency>:<initiation>,<ID_OC_SPEC>:<OC_EX_SPEC>,<NAME>}
-gpgpu_perf_sim_memcpy 1 # Fill the L2 cache on memcpy
-gpgpu_simple_dram_model 0 # simple_dram_model with fixed latency and BW
-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
-gpgpu_dram_partition_queues 64:64:64:64 # i2$:$2d:d2$:$2i
-l2_ideal 0 # Use a ideal L2 cache that always hit
-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
-gpgpu_n_mem 24 # number of memory modules (e.g. memory controllers) in gpu
-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
-gpgpu_dram_return_queue_size 192 # 0 = unlimited (default); # entries per chip
-gpgpu_dram_buswidth 16 # default = 4 bytes (8 bytes per cycle at DDR)
-gpgpu_dram_burst_length 2 # Burst length of each DRAM request (default = 4 data bus cycle)
-dram_data_command_freq_ratio 2 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
-gpgpu_dram_timing_opt nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
-gpgpu_l2_rop_latency 160 # ROP queue latency (default 85)
-dram_latency 100 # DRAM latency (default 30)
-dram_dual_bus_interface 257 # dual_bus_interface (default = 0)
-dram_bnk_indexing_policy 1 # dram_bnk_indexing_policy (0 = normal indexing, 1 = Xoring with the higher bits) (Default = 0)
-dram_bnkgrp_indexing_policy 1 # dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)
-dram_seperate_write_queue_enable 1 # Seperate_Write_Queue_Enable
-dram_write_queue_size 128:108:32 # Write_Queue_Size
-dram_elimnate_rw_turnaround 0 # elimnate_rw_turnaround i.e set tWTR and tRTW = 0
-icnt_flit_size 40 # icnt_flit_size
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
-gpgpu_memory_partition_indexing 2 # 0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing
-accelwattch_xml_file accelwattch_sass_sim.xml # AccelWattch XML file
-power_simulation_enabled 0 # Turn on power simulator (1=On, 0=Off)
-power_per_cycle_dump 0 # Dump detailed power output each cycle
-hw_perf_file_name hw_perf.csv # Hardware Performance Statistics file
-hw_perf_bench_name # Kernel Name in Hardware Performance Statistics file
-power_simulation_mode 0 # Switch performance counter input for power simulation (0=Sim, 1=HW, 2=HW-Sim Hybrid)
-dvfs_enabled 0 # Turn on DVFS for power model
-aggregate_power_stats 0 # Accumulate power across all kernels
-accelwattch_hybrid_perfsim_L1_RH 0 # Get L1 Read Hits for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L1_RM 0 # Get L1 Read Misses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L1_WH 0 # Get L1 Write Hits for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L1_WM 0 # Get L1 Write Misses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L2_RH 0 # Get L2 Read Hits for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L2_RM 0 # Get L2 Read Misses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L2_WH 0 # Get L2 Write Hits for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_L2_WM 0 # Get L2 Write Misses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_CC_ACC 0 # Get Constant Cache Acesses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_SHARED_ACC 0 # Get Shared Memory Acesses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_DRAM_RD 0 # Get DRAM Reads for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_DRAM_WR 0 # Get DRAM Writes for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_NOC 0 # Get Interconnect Acesses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_PIPE_DUTY 0 # Get Pipeline Duty Cycle Acesses for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_NUM_SM_IDLE 0 # Get Number of Idle SMs for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_CYCLES 0 # Get Executed Cycles for Accelwattch-Hybrid from Accel-Sim
-accelwattch_hybrid_perfsim_VOLTAGE 0 # Get Chip Voltage for Accelwattch-Hybrid from Accel-Sim
-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
-steady_state_definition 8:4 # allowed deviation:number of samples
-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_max_completed_cta 0 # terminates gpu simulation early (0 = no limit)
-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
-gpgpu_compute_capability_major 7 # Major compute capability version number
-gpgpu_compute_capability_minor 0 # Minor compute capability version number
-gpgpu_flush_l1_cache 1 # Flush L1 cache at the end of each kernel call
-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
-gpgpu_max_concurrent_kernel 128 # maximum kernels that can run concurrently on GPU, set this value according to max resident grids for your compute capability
-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
-visualizer_outputfile NULL # Specifies the output log file for visualizer
-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
-gpgpu_stack_size_limit 1024 # GPU thread stack size
-gpgpu_heap_size_limit 8388608 # GPU malloc heap size
-gpgpu_runtime_sync_depth_limit 2 # GPU device runtime synchronize depth
-gpgpu_runtime_pending_launch_count_limit 2048 # GPU device runtime pending launch count
-trace_enabled 0 # Turn on traces
-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
-gpgpu_cdp_enabled 0 # Turn on CDP
-gpgpu_TB_launch_latency 0 # thread block launch latency in cycles. Default: 0
-trace ./util/tracer_nvbit/traces/kernelslist.g # traces kernel filetraces kernel file directory
-trace_opcode_latency_initiation_int 2,2 # Opcode latencies and initiation for integers in trace driven mode <latency,initiation>
-trace_opcode_latency_initiation_sp 2,2 # Opcode latencies and initiation for sp in trace driven mode <latency,initiation>
-trace_opcode_latency_initiation_dp 8,4 # Opcode latencies and initiation for dp in trace driven mode <latency,initiation>
-trace_opcode_latency_initiation_sfu 20,8 # Opcode latencies and initiation for sfu in trace driven mode <latency,initiation>
-trace_opcode_latency_initiation_tensor 8,4 # Opcode latencies and initiation for tensor in trace driven mode <latency,initiation>
-trace_opcode_latency_initiation_spec_op_1 4,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_2 200,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_3 8,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_4 4,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_5 4,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_6 4,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_7 4,4 # specialized unit config <latency,initiation>
-trace_opcode_latency_initiation_spec_op_8 4,4 # specialized unit config <latency,initiation>
DRAM Timing Options:
nbk 16 # number of banks
CCD 1 # column to column delay
RRD 3 # minimal delay between activation of rows in different banks
RCD 12 # row to column delay
RAS 28 # time needed to activate row
RP 12 # time needed to precharge (deactivate) row
RC 40 # row cycle time
CDLR 3 # switching from write to read (changes tWTR)
WR 10 # last data-in to row precharge
CL 12 # CAS latency
WL 2 # Write latency
nbkgrp 4 # number of bank groups
CCDL 2 # column to column delay between accesses to different bank groups
RTPL 3 # read to precharge delay between accesses to different bank groups
Total number of memory sub partition = 48
addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
addr_dec_mask[BK] = 0000000000007100 high:15 low:8
addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
addr_dec_mask[COL] = 0000000000000eff high:12 low:0
addr_dec_mask[BURST] = 000000000000001f high:5 low:0
sub_partition_id_mask = 0000000000000100
GPGPU-Sim uArch: clock freqs: 1200000000.000000:1200000000.000000:1200000000.000000:850000000.000000
GPGPU-Sim uArch: clock periods: 0.00000000083333333333:0.00000000083333333333:0.00000000083333333333:0.00000000117647058824
*** Initializing Memory Statistics ***
GPGPU-Sim uArch: performance model initialization complete.
launching memcpy command : MemcpyHtoD,0x00007f2757100000,8192
launching memcpy command : MemcpyHtoD,0x00007f2757102000,8192
launching memcpy command : MemcpyHtoD,0x00007f2757104000,8192
launching memcpy command : MemcpyHtoD,0x00007f2757106000,8192
Processing kernel ./util/tracer_nvbit/traces/kernel-1.traceg
-kernel name = _Z5saxpyifPfS_
-kernel id = 1
-grid dim = (8,1,1)
-block dim = (256,1,1)
-shmem = 0
-nregs = 10
-binary version = 70
-cuda stream id = 0
-shmem base_addr = 0x00007f2790000000
-local mem base_addr = 0x00007f278e000000
-nvbit version = 1.5.3
-accelsim tracer version = 3
Header info loaded for kernel command : ./util/tracer_nvbit/traces/kernel-1.traceg
Processing kernel ./util/tracer_nvbit/traces/kernel-2.traceg
-kernel name = _Z5scaleifPf
-kernel id = 2
-grid dim = (8,1,1)
-block dim = (256,1,1)
-shmem = 0
-nregs = 8
-binary version = 70
-cuda stream id = 0
-shmem base_addr = 0x00007f2790000000
-local mem base_addr = 0x00007f278e000000
-nvbit version = 1.5.3
-accelsim tracer version = 3
Header info loaded for kernel command : ./util/tracer_nvbit/traces/kernel-2.traceg
Processing kernel ./util/tracer_nvbit/traces/kernel-3.traceg
-kernel name = _Z5saxpyifPfS_
-kernel id = 3
-grid dim = (8,1,1)
-block dim = (256,1,1)
-shmem = 0
-nregs = 10
-binary version = 70
-cuda stream id = 93932999106656
-shmem base_addr = 0x00007f2790000000
-local mem base_addr = 0x00007f278e000000
-nvbit version = 1.5.3
-accelsim tracer version = 3
Header info loaded for kernel command : ./util/tracer_nvbit/traces/kernel-3.traceg
Processing kernel ./util/tracer_nvbit/traces/kernel-4.traceg
-kernel name = _Z3addiPfS_
-kernel id = 4
-grid dim = (8,1,1)
-block dim = (256,1,1)
-shmem = 0
-nregs = 12
-binary version = 70
-cuda stream id = 0
-shmem base_addr = 0x00007f2790000000
-local mem base_addr = 0x00007f278e000000
-nvbit version = 1.5.3
-accelsim tracer version = 3
Header info loaded for kernel command : ./util/tracer_nvbit/traces/kernel-4.traceg
launching kernel name: _Z5saxpyifPfS_ uid: 1
launching kernel name: _Z5saxpyifPfS_ uid: 3
GPGPU-Sim uArch: CTA/core = 8, limited by: threads
GPGPU-Sim: Reconfigure L1 cache to 128KB
thread block = 0,0,0
thread block = 1,0,0
thread block = 2,0,0
thread block = 3,0,0
thread block = 4,0,0
thread block = 5,0,0
thread block = 6,0,0
thread block = 7,0,0
GPGPU-Sim uArch: CTA/core = 8, limited by: threads
GPGPU-Sim: Reconfigure L1 cache to 128KB
thread block = 0,0,0
thread block = 1,0,0
thread block = 2,0,0
thread block = 3,0,0
thread block = 4,0,0
thread block = 5,0,0
thread block = 6,0,0
thread block = 7,0,0
Destroy streams for kernel 3: size 0
kernel_name = _Z5saxpyifPfS_ _Z5saxpyifPfS_
kernel_launch_uid = 1 3
gpu_sim_cycle = 750
gpu_sim_insn = 53248
gpu_ipc = 70.9973
gpu_tot_sim_cycle = 750
gpu_tot_sim_insn = 53248
gpu_tot_ipc = 70.9973
gpu_tot_issued_cta = 16
gpu_occupancy = 12.0699%
gpu_tot_occupancy = 12.0699%
max_total_param_size = 0
gpu_stall_dramfull = 0
gpu_stall_icnt2sh = 0
partiton_level_parallism = 2.0480
partiton_level_parallism_total = 2.0480
partiton_level_parallism_util = 5.9767
partiton_level_parallism_util_total = 5.9767
L2_BW = 77.9264 GB/Sec
L2_BW_total = 77.9264 GB/Sec
gpu_total_sim_rate=53248
========= Core cache stats =========
L1I_cache:
L1I_total_cache_accesses = 0
L1I_total_cache_misses = 0
L1I_total_cache_pending_hits = 0
L1I_total_cache_reservation_fails = 0
L1D_cache:
L1D_cache_core[0]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[1]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[2]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[3]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[4]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[5]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[6]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[7]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[8]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[9]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[10]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[11]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[12]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 74
L1D_cache_core[13]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 74
L1D_cache_core[14]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[15]: Access = 96, Miss = 64, Miss_rate = 0.667, Pending_hits = 0, Reservation_fails = 67
L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[28]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[29]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[30]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[31]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[32]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[33]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[34]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[35]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[36]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[37]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[38]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_cache_core[39]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
L1D_total_cache_accesses = 1536
L1D_total_cache_misses = 1024
L1D_total_cache_miss_rate = 0.6667
L1D_total_cache_pending_hits = 0
L1D_total_cache_reservation_fails = 1086
L1D_cache_data_port_util = 0.044
L1D_cache_fill_port_util = 0.087
L1C_cache:
L1C_total_cache_accesses = 0
L1C_total_cache_misses = 0
L1C_total_cache_pending_hits = 0
L1C_total_cache_reservation_fails = 0
L1T_cache:
L1T_total_cache_accesses = 0
L1T_total_cache_misses = 0
L1T_total_cache_pending_hits = 0
L1T_total_cache_reservation_fails = 0
Total_core_cache_stats:
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 256
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][RESERVATION_FAIL] = 1072
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][SECTOR_MISS] = 768
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[CONST_ACC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[TEXTURE_ACC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][HIT] = 512
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][RESERVATION_FAIL] = 14
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][HIT] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[LOCAL_ACC_W][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][HIT] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][MISS] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L1_WRBK_ACC][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][HIT] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][MISS] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L2_WRBK_ACC][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[INST_ACC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][HIT] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][MISS] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L1_WR_ALLOC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][HIT] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][HIT_RESERVED] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][MISS] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][RESERVATION_FAIL] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][SECTOR_MISS] = 0
Total_core_cache_stats_breakdown[L2_WR_ALLOC_R][MSHR_HIT] = 0
Total_core_cache_stats_breakdown[GLOBAL_ACC_R][TOTAL_ACCESS] = 1024
Total_core_cache_stats_breakdown[GLOBAL_ACC_W][TOTAL_ACCESS] = 512
Total_core_cache_fail_stats:
Total_core_cache_fail_stats_breakdown[GLOBAL_ACC_R][MISS_QUEUE_FULL] = 1072
Total_core_cache_fail_stats_breakdown[GLOBAL_ACC_W][MISS_QUEUE_FULL] = 14
ctas_completed 12, Shader 0 warp_id issue ditsribution:
warp_id:
0, 1, 2, 3, 4, 5, 6, 7,
distro:
15, 15, 15, 15, 15, 15, 15, 15,
gpgpu_n_tot_thrd_icount = 61440
gpgpu_n_tot_w_icount = 1920
gpgpu_n_stall_shd_mem = 0
gpgpu_n_mem_read_local = 0
gpgpu_n_mem_write_local = 0
gpgpu_n_mem_read_global = 1024
gpgpu_n_mem_write_global = 512
gpgpu_n_mem_texture = 0
gpgpu_n_mem_const = 0
gpgpu_n_load_insn = 8192
gpgpu_n_store_insn = 4096
gpgpu_n_shmem_insn = 0
gpgpu_n_sstarr_insn = 0
gpgpu_n_tex_insn = 0
gpgpu_n_const_mem_insn = 0
gpgpu_n_param_mem_insn = 0
gpgpu_n_shmem_bkconflict = 0
gpgpu_n_cache_bkconflict = 0
gpgpu_n_intrawarp_mshr_merge = 0
gpgpu_n_cmem_portconflict = 0
gpgpu_stall_shd_mem[c_mem][resource_stall] = 0
gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
gpgpu_stall_shd_mem[gl_mem][resource_stall] = 0
gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
gpu_reg_bank_conflict_stalls = 0
Warp Occupancy Distribution:
Stall:336 W0_Idle:13914 W0_Scoreboard:30950 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:1664
single_issue_nums: WS0:480 WS1:480 WS2:480 WS3:480
dual_issue_nums: WS0:0 WS1:0 WS2:0 WS3:0
traffic_breakdown_coretomem[GLOBAL_ACC_R] = 8192 {8:1024,}
traffic_breakdown_coretomem[GLOBAL_ACC_W] = 20480 {40:512,}
traffic_breakdown_memtocore[GLOBAL_ACC_R] = 40960 {40:1024,}
traffic_breakdown_memtocore[GLOBAL_ACC_W] = 3936 {8:492,}
maxmflatency = 469
max_icnt2mem_latency = 149
maxmrqlatency = 50
max_icnt2sh_latency = 24
averagemflatency = 381
avg_icnt2mem_latency = 111
avg_mrq_latency = 16
avg_icnt2sh_latency = 6
mrq_lat_table:148 134 36 66 270 114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mf_lat_table:0 0 0 0 0 0 0 488 1024 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
icnt2mem_lat_table:0 0 0 0 334 528 582 92 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
icnt2sh_lat_table:0 1194 182 70 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
mf_lat_pw_table:0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
maximum concurrent accesses to same row:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
maximum service time to same row:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 353 368 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 339 368 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 361 368 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 377 339 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 353 368 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 339 368 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 361 368 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 377 339 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 370 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 368 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 377 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 372 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 370 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 368 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 377 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 372 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 353 401 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 339 399 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 361 411 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 372 406 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 353 401 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 339 399 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 361 411 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 372 406 0 0
average row accesses per activate:
dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 24.000000 40.000000 -nan -nan
dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[11]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[12]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[13]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[14]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[15]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 8.000000 -nan -nan -nan
dram[16]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[17]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[18]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[19]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[20]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[21]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[22]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
dram[23]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 16.000000 8.000000 -nan -nan
average row locality = 768/40 = 19.200001
number of total memory accesses made:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
total accesses: 0
min_bank_accesses = 0!
min_chip_accesses = 0!
number of total read accesses:
dram[0]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 24 40 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 16 8 0 0 0 0
total dram reads = 768
min_bank_accesses = 0!
chip skew: 64/8 = 8.00
number of total write accesses:
dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
total dram writes = 0
min_bank_accesses = 0!
min_chip_accesses = 0!
average mf latency per bank:
dram[0]: none none none none none none none none none none 611 696 none none none none
dram[1]: none none none none none none none none none none 629 698 none none none none
dram[2]: none none none none none none none none none none 642 672 none none none none
dram[3]: none none none none none none none none none none 633 634 none none none none
dram[4]: none none none none none none none none none none 611 696 none none none none
dram[5]: none none none none none none none none none none 629 698 none none none none
dram[6]: none none none none none none none none none none 642 672 none none none none
dram[7]: none none none none none none none none none none 633 634 none none none none
dram[8]: none none none none none none none none none none 566 none none none none none
dram[9]: none none none none none none none none none none 555 none none none none none
dram[10]: none none none none none none none none none none 574 none none none none none
dram[11]: none none none none none none none none none none 570 none none none none none
dram[12]: none none none none none none none none none none 566 none none none none none
dram[13]: none none none none none none none none none none 555 none none none none none
dram[14]: none none none none none none none none none none 574 none none none none none
dram[15]: none none none none none none none none none none 570 none none none none none
dram[16]: none none none none none none none none none none 644 588 none none none none
dram[17]: none none none none none none none none none none 630 583 none none none none
dram[18]: none none none none none none none none none none 652 595 none none none none
dram[19]: none none none none none none none none none none 676 602 none none none none
dram[20]: none none none none none none none none none none 644 588 none none none none
dram[21]: none none none none none none none none none none 630 583 none none none none
dram[22]: none none none none none none none none none none 652 595 none none none none
dram[23]: none none none none none none none none none none 676 602 none none none none
maximum mf latency per bank:
dram[0]: 0 0 0 0 0 0 0 0 0 0 446 465 0 0 0 0
dram[1]: 0 0 0 0 0 0 0 0 0 0 439 467 0 0 0 0
dram[2]: 0 0 0 0 0 0 0 0 0 0 443 469 0 0 0 0
dram[3]: 0 0 0 0 0 0 0 0 0 0 438 435 0 0 0 0
dram[4]: 0 0 0 0 0 0 0 0 0 0 446 465 0 0 0 0
dram[5]: 0 0 0 0 0 0 0 0 0 0 439 467 0 0 0 0
dram[6]: 0 0 0 0 0 0 0 0 0 0 443 469 0 0 0 0
dram[7]: 0 0 0 0 0 0 0 0 0 0 438 435 0 0 0 0
dram[8]: 0 0 0 0 0 0 0 0 0 0 393 0 0 0 0 0
dram[9]: 0 0 0 0 0 0 0 0 0 0 386 0 0 0 0 0
dram[10]: 0 0 0 0 0 0 0 0 0 0 389 0 0 0 0 0
dram[11]: 0 0 0 0 0 0 0 0 0 0 390 0 0 0 0 0
dram[12]: 0 0 0 0 0 0 0 0 0 0 393 0 0 0 0 0
dram[13]: 0 0 0 0 0 0 0 0 0 0 386 0 0 0 0 0
dram[14]: 0 0 0 0 0 0 0 0 0 0 389 0 0 0 0 0
dram[15]: 0 0 0 0 0 0 0 0 0 0 390 0 0 0 0 0
dram[16]: 0 0 0 0 0 0 0 0 0 0 419 413 0 0 0 0
dram[17]: 0 0 0 0 0 0 0 0 0 0 417 411 0 0 0 0
dram[18]: 0 0 0 0 0 0 0 0 0 0 422 419 0 0 0 0
dram[19]: 0 0 0 0 0 0 0 0 0 0 425 421 0 0 0 0
dram[20]: 0 0 0 0 0 0 0 0 0 0 419 413 0 0 0 0
dram[21]: 0 0 0 0 0 0 0 0 0 0 417 411 0 0 0 0
dram[22]: 0 0 0 0 0 0 0 0 0 0 422 419 0 0 0 0
dram[23]: 0 0 0 0 0 0 0 0 0 0 425 421 0 0 0 0
Memory Partition 0:
Cache L2_bank_000:
MSHR contents
Memory Sub Parition 1: pending memory requests:
mf: uid= 2553, sid00:w00, part=0, addr=0x7f2757102060, store, size=32, GLOBAL_W status = IN_PARTITION_ROP_DELAY (592), 0x00d0 w00[11111111111111111111111111111111]: <no instruction at address 0xd0>
mf: uid= 2554, sid00:w00, part=0, addr=0x7f2757102040, store, size=32, GLOBAL_W status = IN_PARTITION_ROP_DELAY (591), 0x00d0 w00[11111111111111111111111111111111]: <no instruction at address 0xd0>
mf: uid= 2555, sid00:w00, part=0, addr=0x7f2757102020, store, size=32, GLOBAL_W status = IN_PARTITION_ROP_DELAY (590), 0x00d0 w00[11111111111111111111111111111111]: <no instruction at address 0xd0>
mf: uid= 2556, sid00:w00, part=0, addr=0x7f2757102000, store, size=32, GLOBAL_W status = IN_PARTITION_ICNT_TO_L2_QUEUE (749), 0x00d0 w00[11111111111111111111111111111111]: <no instruction at address 0xd0>
Cache L2_bank_001:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[0]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=531 n_nop=465 n_act=2 n_pre=0 n_ref_event=0 n_req=64 n_rd=64 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0.1205
n_activity=119 dram_eff=0.5378
bk0: 0a 531i bk1: 0a 531i bk2: 0a 531i bk3: 0a 531i bk4: 0a 531i bk5: 0a 531i bk6: 0a 531i bk7: 0a 531i bk8: 0a 531i bk9: 0a 531i bk10: 0a 531i bk11: 0a 531i bk12: 24a 505i bk13: 40a 485i bk14: 0a 531i bk15: 0a 531i
------------------------------------------------------------------------
Row_Buffer_Locality = 0.968750
Row_Buffer_Locality_read = 0.968750
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = 1.271028
Bank_Level_Parallism_Col = 1.264151
Bank_Level_Parallism_Ready = 1.062500
write_to_read_ratio_blp_rw_average = 0.000000
GrpLevelPara = 1.264151
BW Util details:
bwutil = 0.120527
total_CMD = 531
util_bw = 64
Wasted_Col = 43
Wasted_Row = 0
Idle = 424
BW Util Bottlenecks:
RCDc_limit = 19
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 29
rwq = 0
CCDLc_limit_alone = 29
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 531
n_nop = 465
Read = 64
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 2
n_pre = 0
n_ref = 0
n_req = 64
total_req = 64
Dual Bus Interface Util:
issued_total_row = 2
issued_total_col = 64
Row_Bus_Util = 0.003766
CoL_Bus_Util = 0.120527
Either_Row_CoL_Bus_Util = 0.124294
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = 0.000000
queue_avg = 1.883239
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=16 avg=1.88324
Memory Partition 1:
Cache L2_bank_002:
MSHR contents
Cache L2_bank_003:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[1]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=531 n_nop=466 n_act=2 n_pre=0 n_ref_event=0 n_req=64 n_rd=64 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0.1205
n_activity=129 dram_eff=0.4961
bk0: 0a 531i bk1: 0a 531i bk2: 0a 531i bk3: 0a 531i bk4: 0a 531i bk5: 0a 531i bk6: 0a 531i bk7: 0a 531i bk8: 0a 531i bk9: 0a 531i bk10: 0a 531i bk11: 0a 531i bk12: 24a 507i bk13: 40a 482i bk14: 0a 531i bk15: 0a 531i
------------------------------------------------------------------------
Row_Buffer_Locality = 0.968750
Row_Buffer_Locality_read = 0.968750
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = 1.170940
Bank_Level_Parallism_Col = 1.163793
Bank_Level_Parallism_Ready = 1.078125
write_to_read_ratio_blp_rw_average = 0.000000
GrpLevelPara = 1.163793
BW Util details:
bwutil = 0.120527
total_CMD = 531
util_bw = 64
Wasted_Col = 53
Wasted_Row = 0
Idle = 414
BW Util Bottlenecks:
RCDc_limit = 20
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 36
rwq = 0
CCDLc_limit_alone = 36
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 531
n_nop = 466
Read = 64
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 2
n_pre = 0
n_ref = 0
n_req = 64
total_req = 64
Dual Bus Interface Util:
issued_total_row = 2
issued_total_col = 64
Row_Bus_Util = 0.003766
CoL_Bus_Util = 0.120527
Either_Row_CoL_Bus_Util = 0.122411
Issued_on_Two_Bus_Simul_Util = 0.001883
issued_two_Eff = 0.015385
queue_avg = 1.495292
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=12 avg=1.49529
Memory Partition 2:
Cache L2_bank_004:
MSHR contents
Memory Sub Parition 5: pending memory requests:
mf: uid= 2486, sid12:w07, part=2, addr=0x7f2757103bc0, store, size=32, GLOBAL_W status = IN_PARTITION_L2_TO_ICNT_QUEUE (749), 0x00d0 w07[11111111111111111111111111111111]: <no instruction at address 0xd0>
mf: uid= 2485, sid12:w07, part=2, addr=0x7f2757103be0, store, size=32, GLOBAL_W status = IN_PARTITION_ICNT_TO_L2_QUEUE (749), 0x00d0 w07[11111111111111111111111111111111]: <no instruction at address 0xd0>
Cache L2_bank_005:
MSHR contents
In Dram Latency Queue (total = 0):
DRAM[2]: 16 bks, busW=16 BL=2 CL=12, tRRD=3 tCCD=1, tRCD=12 tRAS=28 tRP=12 tRC=40
n_cmd=531 n_nop=465 n_act=2 n_pre=0 n_ref_event=0 n_req=64 n_rd=64 n_rd_L2_A=0 n_write=0 n_wr_bk=0 bw_util=0.1205
n_activity=117 dram_eff=0.547
bk0: 0a 531i bk1: 0a 531i bk2: 0a 531i bk3: 0a 531i bk4: 0a 531i bk5: 0a 531i bk6: 0a 531i bk7: 0a 531i bk8: 0a 531i bk9: 0a 531i bk10: 0a 531i bk11: 0a 531i bk12: 24a 504i bk13: 40a 476i bk14: 0a 531i bk15: 0a 531i
------------------------------------------------------------------------
Row_Buffer_Locality = 0.968750
Row_Buffer_Locality_read = 0.968750
Row_Buffer_Locality_write = -nan
Bank_Level_Parallism = 1.390476
Bank_Level_Parallism_Col = 1.384615
Bank_Level_Parallism_Ready = 1.125000
write_to_read_ratio_blp_rw_average = 0.000000
GrpLevelPara = 1.384615
BW Util details:
bwutil = 0.120527
total_CMD = 531
util_bw = 64
Wasted_Col = 41
Wasted_Row = 0
Idle = 426
BW Util Bottlenecks:
RCDc_limit = 21
RCDWRc_limit = 0
WTRc_limit = 0
RTWc_limit = 0
CCDLc_limit = 29
rwq = 0
CCDLc_limit_alone = 29
WTRc_limit_alone = 0
RTWc_limit_alone = 0
Commands details:
total_CMD = 531
n_nop = 465
Read = 64
Write = 0
L2_Alloc = 0
L2_WB = 0
n_act = 2
n_pre = 0
n_ref = 0
n_req = 64
total_req = 64
Dual Bus Interface Util:
issued_total_row = 2
issued_total_col = 64
Row_Bus_Util = 0.003766
CoL_Bus_Util = 0.120527
Either_Row_CoL_Bus_Util = 0.124294
Issued_on_Two_Bus_Simul_Util = 0.000000
issued_two_Eff = 0.000000
queue_avg = 1.777778
dram_util_bins: 0 0 0 0 0 0 0 0 0 0
dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
mrqq: max=15 avg=1.77778
Memory Partition 3:
Cache L2_bank_006:
MSHR contents
Memory Sub Parition 7: pending memory requests: