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Cadmium's CHIP 8 Quirks (WIP)

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gulrak edited this page Jun 11, 2023 · 4 revisions

Preamble: There are various lists of quirks and different emulators and documents and tutorials list quirks in different ways. While I am all in favor of standardizing these as far as it is practical, Cadmium uses a more fine grained control to try to emulate the various historical variants of CHIP-8 as close as I manage to do. This leads to more quirks than typically are listed in other sources. Also my approach on when a quirk is on or off is more based on the change of the root of CHIP 8, as I define for Cadmium that everything the original COSMAC VIP CHIP-8 interpreter did is what defines the base-line and every deviation from that is the quirk. That leads to every quirk flag being false by my definition for original 1979 CHIP-8 behavior. There are also "quirks" in this list that are feature switches, but I try to make the actual variants mainly be made up of these flags and reduce the code that depends on the concrete variant enum/name as much as possible. So all this does not mean this is the only correct way to do it, it is just the way I defined it in my own work, as I didn't want two only half orthogonal dimensions of Quirks and Flags and map everything to quirks, so please don't be mad at me. ;-)

List of Quirks and Description

This is a list of quirks that are supported by my current development version of Cadmium, the ones not in a release will be supported by a public version soon, alternative names often used in other source/emulators are given in parenthesis):

  1. 8xy6/8xyE just shift Vx ('shift' quirk)
    Originally CHIP-8 uses the value in Vy to shift it and store the result in Vx (not Vy), this quirk makes it ignore Vy and simply shift Vx.
  2. 8xy1/8xy2/8xy3 don't reset VF ('logic' quirk)
    The original interpreter sets VF to the carry/borrow result of every math operation, even the logic ones (8xy1, 8xy2 and 8xy3) where it is set to 0, but as this unnecessarily invalidates a usable register, modern variants have this quirk activated to keep that from happening.
  3. Fx55/Fx65 increment I only by x
    Originally the index register I was incremented while loading/storing registers from/to memory to the end value of I + x + 1, but the HP48 variants CHIP-48 and SCHIP1.0 introduced a change that resulted in I + x, only one or none of the Load/Store increment quirks can be enabled.
  4. Fx55/Fx65 don't increment I (load/store quirk)
    Originally the index register I was incremented while loading/storing registers from/to memory to the end value of I + x + 1, but the HP48 variant SCHIP1.1 introduced a change that resulted in leaving I unchanged, only one or none of the Load/Store increment quirks can be enabled.
  5. Wrap sprite pixels (inverse of more common 'clipping' quirk)
    While every variant wraps the start coordinates from Vx and Vy to stay in the screen and clip all other pixels of a sprite outside the right or bottom border, some variants (e.g. XO-CHIP) expect the pixels to be wrapped to the opposite side.
  6. Dxyn doesn't wait for vsync (inverse of the 'vblank' or 'display wait' quirk)
    The original COSMAC VIP waits for the start of the next frame before drawing sprite pixels to the actual screen, all HP48 based variants emulate this when not in extended (or hires) mode, limiting the draw rate to one sprite per frame at maximum.
  7. Lores Dxy0 draws 8 pixel width
    On the original interpreter setting the height to 0 doesn't draw anything at all, modern versions, starting from SCHIP1.1 use this to draw a sprite at the height of 16 pixels, this quirk enables it to draw 8x16 pixel sprites as the original SCHIP1.1 variant on the HP48SX, only one of Lores Dxy0 draws 8 pixel width or Lores Dxy0 draws 16 pixel width can be true.
  8. Lores Dxy0 draws 16 pixel width
    Same as Lores Dxy0 is 8x16 but drawing a 16x16 sprite, for example used in XO-CHIP, only one of Lores Dxy0 draws 8 pixel width or Lores Dxy0 draws 16 pixel width can be true.
  9. Dxyn uses SCHIP1.1 collision
    The SCHIP1.1 interpreter on the HP48SX doesn't return 0 or 1 based on the collision check, but instead in case of a collision the result is the number of rows a collision appeared in plus the number of rows clipped at the bottom border.
  10. HP SuperChip lores drawing
    Interpreters on the HP48 use an LCD with 131x64 pixel resolution, and draw always in 128x64 pixel physical resolution. In 64x32 modes the coordinates are doubled internally and the pixels drawn are 2x2 physical/hires pixel on the screen. To reduce overhead, the lores modes actually only draw and collision check on the even rows (starting to count rows at 0), and copy the affected part of the even row to the odd row on screen. This copy is done from x & 0x70 up to, but excluding (x & 0x70) + 32, where x is the doubled value of Vx.
  11. Half pixel lores scrolling
    This enables an SCHIP scroll behavior that scrolls half the pixels in lores than in hires mode (actually from the point of view of the calculator all scrolls are simply the same distance, but in hires pixels, leading to half the distance visually in lores pixels).
  12. Mode change clear
    Makes the 00FE and 00FF opcodes clear the screen, like on SCHPC or XO-CHIP, in contrast to SCHIP1.x on HP48SX.
  13. Bxnn/Jump0 uses Vx (jump quirk)
    On the HP48SX the variants CHIP-48, and SCHIP1.x had a different behavior for the Bnnn opcode making it in fact a Bxnn opcode where the jump is to XNN + Vx, instead of NNN + V0 making it even harder to use.
  14. 128x64 hires support
    This quirk enables support of the 128x64 mode and as such is needed by all other quirks that need that mode.
  15. Only 128x64 mode
    This enforces the emulator to start in 128x64 mode and not have an opcode that allows the program to change it. It is mainly used for the CHIP-10 mode.
  16. Multicolor support
    This enables color plane handling as used in XO-CHIP or HyperChip64.
  17. Cyclic stack
    This makes the stack pointer wrap around. It is a behavior of the Fish'n'Chips' emulator and some (very few like a Snake variant from 2014) games only work with it.
  18. Has 16 bit addresses
    By default the memory is limited to 4k, this quirk enables 64k address space like XO-CHIP supports it.
  19. XO-CHIP sound engine
    Enable XO-CHIP sound generation instead of the buzzer.
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