diff --git a/bin/params.in b/bin/params.in
index 45f3cfc..48cd213 100644
--- a/bin/params.in
+++ b/bin/params.in
@@ -65,11 +65,10 @@ l2_large_bypass 0
 memory_type igpu_network
 
 # LLC
-num_l3 1
-l3_num_set 16384 # 128 MB
-l3_assoc 64
-l3_line_size 128
-l3_latency 50
+llc_num_set 16384 # 128 MB
+llc_assoc 64
+llc_line_size 128
+llc_latency 50
 
 # DRAM
 dram_bus_width 4
@@ -93,6 +92,7 @@ pref_stream_on_large_core 1
 stream_length 64
 stream_buffer_n 256
 pref_acc_on 1
+pref_acc_study 1
 
 # ETC
 bug_detector_enable 1
@@ -111,7 +111,7 @@ debug_exec_stage 0
 debug_dcu_stage 0
 debug_retire_stage 0
 debug_map_stage 0
-debug_mem  1
+debug_mem  0
 debug_pref 1
 debug_trace_read 0
 debug_sim_thread_schedule 0
diff --git a/src/memory.cc b/src/memory.cc
index 21fd89c..d8156fc 100644
--- a/src/memory.cc
+++ b/src/memory.cc
@@ -57,6 +57,7 @@ POSSIBILITY OF SUCH DAMAGE.
 #include "statistics.h"
 
 #define DEBUG(args...) _DEBUG(*m_simBase->m_knobs->KNOB_DEBUG_MEM, ##args)
+#define DEBUG_PREF(args...) _DEBUG(*m_simBase->m_knobs->KNOB_DEBUG_PREF, ##args)
 #define DEBUG_CORE(m_core_id, args...)                        \
   if (m_core_id == *m_simBase->m_knobs->KNOB_DEBUG_CORE_ID) { \
     _DEBUG(*m_simBase->m_knobs->KNOB_DEBUG_MEM, ##args);      \
diff --git a/src/pref_common.cc b/src/pref_common.cc
index 421a07b..eaada5d 100644
--- a/src/pref_common.cc
+++ b/src/pref_common.cc
@@ -500,6 +500,7 @@ bool hwp_common_c::pref_addto_l1req_queue(Addr line_index, uns8 prefetcher_id) {
 
 // send a new request to l2 request queue
 bool hwp_common_c::pref_addto_l2req_queue(Addr line_index, uns8 prefetcher_id) {
+  DEBUG("l2 demand addr: %llx\n", line_index);
   return pref_addto_l2req_queue_set(line_index, prefetcher_id, false, false, 0,
                                     0);
 }
@@ -507,6 +508,7 @@ bool hwp_common_c::pref_addto_l2req_queue(Addr line_index, uns8 prefetcher_id) {
 // send a new request to l2 request queue
 bool hwp_common_c::pref_addto_l2req_queue(Addr line_index, uns8 prefetcher_id,
                                           Addr loadPC) {
+  DEBUG("l2 demand addr: %llx\n", line_index);
   return pref_addto_l2req_queue_set(line_index, prefetcher_id, false, false,
                                     loadPC, 0);
 }
@@ -514,6 +516,7 @@ bool hwp_common_c::pref_addto_l2req_queue(Addr line_index, uns8 prefetcher_id,
 // send a new request to l2 request queue
 bool hwp_common_c::pref_addto_l2req_queue(Addr line_index, uns8 prefetcher_id,
                                           Addr loadPC, int tid) {
+  DEBUG("l2 demand addr: %llx\n", line_index);
   return pref_addto_l2req_queue_set(line_index, prefetcher_id, false, false,
                                     loadPC, tid);
 }
@@ -522,6 +525,7 @@ bool hwp_common_c::pref_addto_l2req_queue(Addr line_index, uns8 prefetcher_id,
 bool hwp_common_c::pref_addto_l2req_queue_set(Addr line_index,
                                               uns8 prefetcher_id, bool Begin,
                                               bool End, Addr loadPC) {
+  DEBUG("l2 demand addr: %llx\n", line_index);
   return pref_addto_l2req_queue_set(line_index, prefetcher_id, Begin, End,
                                     loadPC, 0);
 }
@@ -535,7 +539,7 @@ bool hwp_common_c::pref_addto_l2req_queue_set(Addr line_index,
   Addr line_addr;
   if (!line_index)  // addr = 0
     return true;
-
+  DEBUG("l2 demand addr: %llx\n", line_index);
   line_addr = (line_index) << m_shift_bit;
 
   if (*m_simBase->m_knobs->KNOB_PREF_UPDATE_INTERVAL != 0 &&
@@ -674,6 +678,7 @@ bool hwp_common_c::pref_addto_l2req_queue_set(Addr line_index,
     for (ii = 0; ii < *m_simBase->m_knobs->KNOB_PREF_UL1REQ_QUEUE_SIZE; ++ii) {
       if (m_l2req_queue[ii].line_index == line_index) {
         STAT_EVENT(PREF_UL2REQ_QUEUE_MATCHED_REQ);
+        DEBUG("match prefetched address in queue: addr %llx\n", line_index);
         return true;  // Hit another request
       }
     }