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qsim-arm-regs.h
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qsim-arm-regs.h
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#ifndef __ARM_REGS_H
#define __ARM_REGS_H
//> ARM registers from Capstone
typedef enum qsim_arm_reg {
QSIM_ARM_INVALID = 0,
QSIM_ARM_APSR,
QSIM_ARM_APSR_NZCV,
QSIM_ARM_CPSR,
QSIM_ARM_FPEXC,
QSIM_ARM_FPINST,
QSIM_ARM_FPSCR,
QSIM_ARM_FPSCR_NZCV,
QSIM_ARM_FPSID,
QSIM_ARM_ITSTATE,
QSIM_ARM_LR,
QSIM_ARM_PC,
QSIM_ARM_SP,
QSIM_ARM_SPSR,
QSIM_ARM_D0,
QSIM_ARM_D1,
QSIM_ARM_D2,
QSIM_ARM_D3,
QSIM_ARM_D4,
QSIM_ARM_D5,
QSIM_ARM_D6,
QSIM_ARM_D7,
QSIM_ARM_D8,
QSIM_ARM_D9,
QSIM_ARM_D10,
QSIM_ARM_D11,
QSIM_ARM_D12,
QSIM_ARM_D13,
QSIM_ARM_D14,
QSIM_ARM_D15,
QSIM_ARM_D16,
QSIM_ARM_D17,
QSIM_ARM_D18,
QSIM_ARM_D19,
QSIM_ARM_D20,
QSIM_ARM_D21,
QSIM_ARM_D22,
QSIM_ARM_D23,
QSIM_ARM_D24,
QSIM_ARM_D25,
QSIM_ARM_D26,
QSIM_ARM_D27,
QSIM_ARM_D28,
QSIM_ARM_D29,
QSIM_ARM_D30,
QSIM_ARM_D31,
QSIM_ARM_FPINST2,
QSIM_ARM_MVFR0,
QSIM_ARM_MVFR1,
QSIM_ARM_MVFR2,
QSIM_ARM_Q0,
QSIM_ARM_Q1,
QSIM_ARM_Q2,
QSIM_ARM_Q3,
QSIM_ARM_Q4,
QSIM_ARM_Q5,
QSIM_ARM_Q6,
QSIM_ARM_Q7,
QSIM_ARM_Q8,
QSIM_ARM_Q9,
QSIM_ARM_Q10,
QSIM_ARM_Q11,
QSIM_ARM_Q12,
QSIM_ARM_Q13,
QSIM_ARM_Q14,
QSIM_ARM_Q15,
QSIM_ARM_R0,
QSIM_ARM_R1,
QSIM_ARM_R2,
QSIM_ARM_R3,
QSIM_ARM_R4,
QSIM_ARM_R5,
QSIM_ARM_R6,
QSIM_ARM_R7,
QSIM_ARM_R8,
QSIM_ARM_R9,
QSIM_ARM_R10,
QSIM_ARM_R11,
QSIM_ARM_R12,
QSIM_ARM_S0,
QSIM_ARM_S1,
QSIM_ARM_S2,
QSIM_ARM_S3,
QSIM_ARM_S4,
QSIM_ARM_S5,
QSIM_ARM_S6,
QSIM_ARM_S7,
QSIM_ARM_S8,
QSIM_ARM_S9,
QSIM_ARM_S10,
QSIM_ARM_S11,
QSIM_ARM_S12,
QSIM_ARM_S13,
QSIM_ARM_S14,
QSIM_ARM_S15,
QSIM_ARM_S16,
QSIM_ARM_S17,
QSIM_ARM_S18,
QSIM_ARM_S19,
QSIM_ARM_S20,
QSIM_ARM_S21,
QSIM_ARM_S22,
QSIM_ARM_S23,
QSIM_ARM_S24,
QSIM_ARM_S25,
QSIM_ARM_S26,
QSIM_ARM_S27,
QSIM_ARM_S28,
QSIM_ARM_S29,
QSIM_ARM_S30,
QSIM_ARM_S31,
QSIM_ARM_ENDING, // <-- mark the end of the list or registers
} qsim_arm_reg;
static const char *arm_regs_str[] __attribute__((unused)) = {
"r0", "r1", "r2", "r3",
"r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11",
"r12", "r13", "r14", "r15",
"cpsr",
NULL
};
uint64_t get_reg(int c, int r);
void set_reg(int c, int r, uint64_t val );
#endif