Nexys2Top.ucf

#
# Simple Brainfuck CPU in Verilog.
# Copyright (C) 2011  Sergey Gridasov <grindars@gmail.com>
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.
#

NET "CLK_IN" LOC = "B8" | IOSTANDARD = LVCMOS33 | TNM_NET = "CLK_IN";
TIMESPEC "TS_CLK_IN" = PERIOD "CLK_IN" 20ns HIGH 50%;

NET "RESET_IN" IOSTANDARD = LVCMOS33 | LOC = "B18";

NET "UART_RX" IOSTANDARD = LVCMOS33 | LOC = "U6";
NET "UART_TX" IOSTANDARD = LVCMOS33 | LOC = "P9";