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Issue with GF180 PDK and symbols import into Xschem and incompatibility with definitions in sm141064.spice #96
Issue with GF180 PDK and symbols import into Xschem and incompatibility with definitions in sm141064.spice #96
Comments
@msaligane did you have it for OpenFASoC? |
edit - to be clear, the error persists after deleting line blala from netlist. the issue is we cannot find symbols for devices example - pmos3p3 in our components-> /devices which is consistent with sm141064.spice |
Could this be related to #6 ? |
@proppy We do not use a schematic editor in the normal openfasoc flow. If it is regarding "blabla", yes, my student encountered this error before, but it was resolved. If there is a syntax error while specifying the ngspice model path this happens. |
@proppy - this is the path we use @msaligane - we cannot find pfet03v3 nfet03v3 under components ->/devices like you do in your designs. Did you do something specific in your PDK imports to xschem? |
Are you using an old version of the PDK? We are using the latest version installed by volare. This is the version of gf180pdk: @madhulikal @StanleyAlwaysLoveYou - can you please help? Thanks! |
@spnadig can you print the result of:
|
@spnadig - This syntax should help resolve the issue without manually deleting 'blabla' everytime. Also, can you check if the path of device models in xschemrc file is referencing to the correct pdk? |
I think the path to the model in
|
Removing xor script as it's not the right place to have it here.
Fixed with #91 |
Expected Behavior
ngspice needs to run with no errors
Actual Behavior
error:
##NETLIST
** sch_path: /usr/local/google/home/nigelcoburn/MixedSignal/Designs/TopLevel_oscillator.sch
**.subckt TopLevel_oscillator
X1 VDD GND Vout Vin Buffer
Vdd VDD GND 1.8
.save i(vdd)
Vin Vin GND pulse(0 1.8 1ns 1ns 1ns 4ns 10ns)
.save i(vin)
**** begin user architecture code
blabla
.tran 0.01n 1u
.saveall
name=TT_MODELS1 only_toplevel=false
.include /usr/local/google/home/nigelcoburn/MixedSignal/silicon-env/share/pdk/gf180mcuC/libs.tech/ngspice/design.ngspice
.lib /usr/local/google/home/nigelcoburn/MixedSignal/silicon-env/share/pdk/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical
**** end user architecture code
**.ends
expanding symbol: Designs/Buffer.sym # of pins=4
** sym_path: /usr/local/google/home/nigelcoburn/MixedSignal/Designs/Buffer.sym
** sch_path: /usr/local/google/home/nigelcoburn/MixedSignal/Designs/Buffer.sch
.subckt Buffer VP VN Y A
*.iopin VP
*.iopin VN
*.ipin A
*.opin Y
X1 VP VN net1 A Inverter
X2 VP VN Y net1 Inverter
.ends
expanding symbol: Designs/Inverter.sym # of pins=4
** sym_path: /usr/local/google/home/nigelcoburn/MixedSignal/Designs/Inverter.sym
** sch_path: /usr/local/google/home/nigelcoburn/MixedSignal/Designs/Inverter.sch
.subckt Inverter VP VN Y A
*.ipin A
*.iopin VP
*.iopin VN
*.opin Y
XM3 Y A VP VP pfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u'
XM4 Y A VN VN nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u'
.ends
.GLOBAL GND
.GLOBAL VDD
.end
Steps to Reproduce the Problem
Specifications
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