- 将
AddModulePrefix.scala加入scala源码, 并修改其中的yourpackage - 在生成verilog的源文件中添加
import yourpackage._ - 在
ChiselStage.execute方法的第二个参数AnnotationSeq中加入两个元素:
firrtl.stage.RunFirrtlTransformAnnotation(new AddModulePrefix())
ModulePrefixAnnotation("yourprefix")例如, 若使用https://github.com/OpenXiangShan/chisel-playground项目作为模板, 可进行如下修改:
--- chisel-playground/playground/src/Elaborate.scala
+++ chisel-playground/playground/src/Elaborate.scala
@@ -1,3 +1,8 @@
+package yourpackage
object Elaborate extends App {
- (new chisel3.stage.ChiselStage).execute(args, Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new GCD())))
+ (new chisel3.stage.ChiselStage).execute(args, Seq(
+ chisel3.stage.ChiselGeneratorAnnotation(() => new GCD()),
+ firrtl.stage.RunFirrtlTransformAnnotation(new AddModulePrefix()),
+ ModulePrefixAnnotation("ysyx_000000_")
+ ))
}感谢中科院计算所的蔺嘉炜同学提供firrtl transform源码.