Doc: update hrefs for 2022.2 docs

Author: Randy Hartgrove

Getting_Started/Vitis/Part3.md

@@ -52,7 +52,7 @@ Other than this, the functionality of the vector-add kernel is very easily recog
 
 The pragmas are used to map function parameters to distinct kernel ports. By mapping the two inputs parameters to different input ports, the kernel will be able to read both inputs in parallel. As a general rule, and without going into further details in this introductory tutorial, it is important to think about interface requirements of hardware accelerators and they will have a determining impact on maximum achievable performance.
 
-The Vitis online documentation provides comprehensive information on [C/C++ Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/C/C-Kernels) as well as a complete [HLS Pragmas](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/HLS-Pragmas) reference guide.
+The Vitis online documentation provides comprehensive information on [C/C++ Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C) as well as a complete [HLS Pragmas](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/HLS-Pragmas) reference guide.
 
 ### The Source Code for the Host Program
 

Getting_Started/Vitis/Part4-data_center.md

@@ -13,7 +13,7 @@
 
 ## Part 4 : Build and Run the Data Center Application
 
- In this fourth part of the Introduction to Vitis tutorial, you will compile and run the vector-add example using each of three build targets supported in the Vitis flow as described below. The overall flow is described in [Data Center Application Acceleration Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Data-Center-Application-Acceleration-Development-Flow), and includes the image flow diagram shown below. From the image you can see the standard G++ compilation process for the host application, and the use of the Vitis compiler (`v++`) for building the Xilinx device binary (`xclbin`). These are the steps you will be working through in this lab. 
+ In this fourth part of the Introduction to Vitis tutorial, you will compile and run the vector-add example using each of three build targets supported in the Vitis flow as described below. The overall flow is described in [Introduction to Data Center Acceleration for Software Programmers](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Introduction-to-Data-Center-Acceleration-for-Software-Programmers), and includes the image flow diagram shown below. From the image you can see the standard G++ compilation process for the host application, and the use of the Vitis compiler (`v++`) for building the Xilinx device binary (`xclbin`). These are the steps you will be working through in this lab. 
 
 ![img](./images/data_center_flow.png)
 
@@ -66,9 +66,9 @@ v++ -l -t sw_emu --platform xilinx_u200_gen3x16_xdma_2_202110_1 --config ../../s
 
 Here is a brief explanation of each of these four commands:
 
-1. `g++` compiles the host application using the standard GNU C compiler. Refer to [Building the Host Program](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Host-Program) for more information.
+1. `g++` compiles the host application using the standard GNU C compiler. Refer to [Building the Software Application](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Software-Application) for more information.
 2. `emconfigutil` generates an emulation configuration file which defines the device type and quantity of devices to emulate for the specified platform. Refer to [emconfigutil](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/emconfigutil-Utility) for more information.
-3. `v++ -c` compiles the source code for the vector-add accelerator into a compiled kernel object (.xo file). Refer to [Compiling Kernels with the Vitis Compiler](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Compiling-Kernels-with-the-Vitis-Compiler) for more information.
+3. `v++ -c` compiles the source code for the vector-add accelerator into a compiled kernel object (.xo file). Refer to [Compiling C/C++ PL Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Compiling-C/C-PL-Kernels) for more information.
 4. `v++ -l` links the compiled kernel with the target platform and generates the FPGA binary (.xclbin file). Refer to [Linking the Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-Kernels) for more information.
 
 The `-t` option of the `v++` command specifies the build target. Here it is set to `sw_emu` so we are building for software emulation.

Getting_Started/Vitis/Part4-embedded_platform.md

@@ -13,7 +13,7 @@
 
 ## Part 4 : Build and Run the Embedded Processor Application
 
- In this fourth part of the Introduction to Vitis tutorial, you will compile and run the vector-add example using each of three build targets supported in the Vitis flow as described below. The overall flow is described in [Embedded Processor Application Acceleration Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Embedded-Processor-Application-Acceleration-Development-Flow), and includes the image flow diagram shown below. From the image you can see the G++ cross-compiler  for building the host application for the Arm processor, and the use of the Vitis compiler (`v++`) for building the Xilinx device binary (`xclbin`). These are the steps you will be working through in this lab. 
+ In this fourth part of the Introduction to Vitis tutorial, you will compile and run the vector-add example using each of three build targets supported in the Vitis flow as described below. The overall flow is described in [Introduction to Vitis Tools for Embedded System Designers](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Introduction-to-Vitis-Tools-for-Embedded-System-Designers), and includes the image flow diagram shown below. From the image you can see the G++ cross-compiler  for building the host application for the Arm processor, and the use of the Vitis compiler (`v++`) for building the Xilinx device binary (`xclbin`). These are the steps you will be working through in this lab. 
 
 ![img](./images/embedded_processor_flow.png)
 
@@ -71,15 +71,15 @@ v++ -p -t sw_emu --platform xilinx_zcu102_base_202220_1 --config ../../src/zcu10
 
 Here is a brief explanation of each of these four commands:
 
-1. `$CXX` compiles the host application using the ARM cross-compiler. This variable contains the full compiler executable plus flags relevant to cross-compilation, and is set when you source the SDK environment setup script. Refer to [Building the Host Program](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Host-Program) for more information. This should resolve to `$XILINX_VITIS/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++`
-2. `v++ -c` compiles the source code for the vector-add accelerator into a compiled kernel object (.xo file). Refer to [Compiling Kernels with the Vitis Compiler](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Compiling-Kernels-with-the-Vitis-Compiler) for more information.
+1. `$CXX` compiles the host application using the ARM cross-compiler. This variable contains the full compiler executable plus flags relevant to cross-compilation, and is set when you source the SDK environment setup script. Refer to [Building the Software Application](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Building-the-Software-Application) for more information. This should resolve to `$XILINX_VITIS/gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-g++`
+2. `v++ -c` compiles the source code for the vector-add accelerator into a compiled kernel object (.xo file). Refer to [Compiling C/C++ PL Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Compiling-C/C-PL-Kernels) for more information.
 3. `v++ -l` links the compiled kernel with the target platform and generates the FPGA binary (.xclbin file). Refer to [Linking the Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Linking-the-Kernels) for more information.
 4. `v++ -p` packages the host executable, the rootfs, the FPGA binary and a few other files and generates a bootable image. Refer to [Packaging for Embedded Platforms](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Packaging-for-Embedded-Platforms) for more information. 
 
 There are two important differences to take note of here between building for Data Center accelerator cards and building for Embedded Platforms. 
 
 * The first is the use of the `v++ --package` command. This is a required step in the Embedded Processor platform flow, and is largely optional in the Data Center flow. The Data Center application runs in the X86 environment, and loads the xclbin from disk. However, in the Embedded Platform flow, generally the processor must be booted from an SD card, and the `--package` option gathers the files and generates the SD card.
-* The second is the `emconfigutil` command. This command is used in the Data Center flow to build an emulation version of the hardware platform. However, in the Embedded Platform flow, the embedded processor requires the use of an emulation environment (QEMU) as described in [Running Emulation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Running-Emulation). In this flow you will use a `launch_emulation` script rather than the emulation platform.
+* The second is the `emconfigutil` command. This command is used in the Data Center flow to build an emulation version of the hardware platform. However, in the Embedded Platform flow, the embedded processor requires the use of an emulation environment (QEMU) as described in [Simulating the Application with the Emulation Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Simulating-the-Application-with-the-Emulation-Flow). In this flow you will use a `launch_emulation` script rather than the emulation platform.
 
 The `-t` option of the `v++` command specifies the build target. Here it is set to `sw_emu` so we are building for software emulation.
 

Getting_Started/Vitis/README.md

@@ -18,7 +18,7 @@
 
 Welcome to the Vitis Getting Started tutorial. The Vitis tool provides a unified flow for developing FPGA accelerated application targeted to either Data Center accelerator cards or Embedded Processor platforms. If you are looking to learn more about the Vitis application acceleration development flow in order to get started with FPGA acceleration, you have come to the right place.
 
-This tutorial is divided into two separate flows: the [Data Center flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Data-Center-Application-Acceleration-Development-Flow), and the [Embedded Processor flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Embedded-Processor-Application-Acceleration-Development-Flow). These two flows are similar in that host applications and accelerated kernels written for one flow can be used in the other flow, and the build processes are similar. However, while similar the flows are also different in that the build and runtime environments of Data Center accelerator cards and Embedded Processor platforms have different requirements that must be met.
+This tutorial is divided into two separate flows: the [Data Center Acceleration flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Introduction-to-Data-Center-Acceleration-for-Software-Programmers), and the [Embedded System Design flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Introduction-to-Vitis-Tools-for-Embedded-System-Designers). These two flows are similar in that host applications and accelerated kernels written for one flow can be used in the other flow, and the build processes are similar. However, while similar the flows are also different in that the build and runtime environments of Data Center accelerator cards and Embedded Processor platforms have different requirements that must be met.
 
 This tutorial provides instructions for building and running on both the Alveo U200 Data Center accelerator card, and the Zynq Ultrascale MPSoC ZCU102 platform. These instructions can be easily adapted to other Xilinx cards. 
 
@@ -47,9 +47,9 @@ The Vitis unified software platform provides a framework for developing and deli
 
 A Vitis accelerated application consists of two distinct components: a software program running on a standard processor such as an X86 processor, or ARM embedded processor, and a Xilinx device binary (`xclbin`) containing hardware accelerated functions, or kernels.
 
-* The software program, or host application, is written in C/C++ and runs on a conventional CPU. The software program uses the [XRT native API](https://xilinx.github.io/XRT/master/html/index.html) implemented by the Xilinx Runtime library (XRT) to interact with the acceleration kernel in the Xilinx device. A description of the host application and required API calls can be found in the Vitis documentation under [Host Programming](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Host-Programming).
+* The software program, or host application, is written in C/C++ and runs on a conventional CPU. The software program uses the [XRT native API](https://xilinx.github.io/XRT/master/html/index.html) implemented by the Xilinx Runtime library (XRT) to interact with the acceleration kernel in the Xilinx device. A description of the host application and required API calls can be found in the Vitis documentation under [Writing the Software Application](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Writing-the-Software-Application).
 
-* The hardware accelerated kernels can be written in C/C++ or RTL (Verilog or VHDL) and run within the programmable logic part of the Xilinx device. Refer to [C/C++ Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/C/C-Kernels), or [RTL Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernels) in the Vitis documentation for coding requirements. The kernels are integrated with a Vitis hardware platform using standard AXI interfaces.
+* The hardware accelerated kernels can be written in C/C++ or RTL (Verilog or VHDL) and run within the programmable logic part of the Xilinx device. Refer to [Developing PL Kernels using C++](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Developing-PL-Kernels-using-C), or [Packaging RTL Kernels](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Packaging-RTL-Kernels) in the Vitis documentation for coding requirements. The kernels are integrated with a Vitis hardware platform using standard AXI interfaces.
 
 ![img](./images/part1_execution_model.png)
 
@@ -76,7 +76,7 @@ The Vitis build process follows a standard compilation and linking process for b
 
 * The host program is built using the GNU C++ compiler (g++) for Data Center applications or the GNU C++ Arm cross-compiler for Embedded Processor devices.
 
-* The FPGA binary is built using the Vitis compiler (v++). First the kernels are compiled into a Xilinx object (.xo) file. Then, the .xo files are linked with the hardware platform to generate the Xilinx device binary (.xclbin) file. As described in [Vitis Compiler Command](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Vitis-Compiler-Command), the Vitis compiler and linker accepts a wide range of options to tailor and optimize the results.
+* The FPGA binary is built using the Vitis compiler (v++). First the kernels are compiled into a Xilinx object (.xo) file. Then, the .xo files are linked with the hardware platform to generate the Xilinx device binary (.xclbin) file. As described in [V++ Command](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/v-Command), the Vitis compiler and linker accepts a wide range of options to tailor and optimize the results.
 
 ![img](./images/part1_build_flow.png)
 
@@ -90,7 +90,7 @@ The Vitis compiler provides three different build targets: two emulation targets
 
 * Hardware - The kernel code is compiled into a hardware description language (RTL), and then synthesized and implemented for a target Xilinx device, resulting in a binary (`xclbin`) file that will run on the actual FPGA.
 
->**TIP**: As described in [Running Emulation](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Running-Emulation), there are significant differences in the build and runtime environments between Data Center and Embedded Processor platforms. These two flows will be discussed in detail in the following sections.
+>**TIP**: As described in [Simulating the Application with the Emulation Flow](https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Simulating-the-Application-with-the-Emulation-Flow), there are significant differences in the build and runtime environments between Data Center and Embedded Processor platforms. These two flows will be discussed in detail in the following sections.
 
 ## Next Steps
 

Getting_Started/Vitis_HLS/README.md

@@ -36,7 +36,7 @@ Vitis High-Level Synthesis (HLS) is a key part of the Vitis application accelera
 
 > **TIP:** Vitis HLS can also be used to generate Vivado IP from C/C++ code, but that flow is not the subject of this tutorial. Although similar, there are some significant differences between producing Vitis XO kernels and Vivado RTL IP. However, you can use this tutorial as a general introduction to the Vitis HLS tool. 
 
-In this tutorial, you will work through the Vitis HLS tool GUI to build, analyze, and optimize a hardware kernel. You are working through the Vitis kernel flow in the Vitis tool. For more information, refer to [Enabling the Vitis Kernel Flow](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vitis-HLS-Process-Overview) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+In this tutorial, you will work through the Vitis HLS tool GUI to build, analyze, and optimize a hardware kernel. You are working through the Vitis kernel flow in the Vitis tool. For more information, refer to [Vitis HLS Flow Overview](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vitis-HLS-Flow-Overview) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
 ### Before You Begin
 

Getting_Started/Vitis_HLS/new_project.md

@@ -103,7 +103,7 @@ In this tutorial, you are working with a simple discrete cosine transform (DCT)
 
 8. In the Solution Configuration dialog box, select the **Vitis Kernel Flow Target** from the dropdown menu.
 
-   This enables the creation of a Vitis application acceleration hardware kernel (.xo) as an output for the project. For more information on how enabling the Vitis kernel flow configures the default behavior of the tool, refer to [Vitis HLS Process Overview](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vitis-HLS-Process-Overview) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
+   This enables the creation of a Vitis application acceleration hardware kernel (.xo) as an output for the project. For more information on how enabling the Vitis kernel flow configures the default behavior of the tool, refer to [Vitis HLS Flow Overview](https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Vitis-HLS-Flow-Overview) in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).
 
 9. With your project settings now configured, click **Finish**.
     Vitis HLS opens the new project in the default view.

Hardware_Acceleration/Design_Tutorials/10-get_moving_with_alveo/04-parallelizing-the-data-path.md

@@ -197,7 +197,7 @@ Some things to try to build on this experiment:
 
 - Play around with the buffer sizes again.  Can you find the inflection point where the CPU becomes faster?
 - Try to capture the Vitis Timeline Trace and view this for yourself.  The instructions for doing so are
-  found in the [Vitis Documentation](https://www.xilinx.com/html_docs/xilinx_2020_1/vitis_doc/index.html)
+  found in the [Vitis Documentation](https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation)
 
 ## Key Takeaways